1 //=======- ARMFrameLowering.cpp - ARM Frame Information --------*- C++ -*-====//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the ARM implementation of TargetFrameLowering class.
12 //===----------------------------------------------------------------------===//
14 #include "ARMFrameLowering.h"
15 #include "ARMAddressingModes.h"
16 #include "ARMBaseInstrInfo.h"
17 #include "ARMBaseRegisterInfo.h"
18 #include "ARMMachineFunctionInfo.h"
19 #include "llvm/CodeGen/MachineFrameInfo.h"
20 #include "llvm/CodeGen/MachineFunction.h"
21 #include "llvm/CodeGen/MachineInstrBuilder.h"
22 #include "llvm/CodeGen/MachineRegisterInfo.h"
23 #include "llvm/CodeGen/RegisterScavenging.h"
24 #include "llvm/Target/TargetOptions.h"
28 /// hasFP - Return true if the specified function should have a dedicated frame
29 /// pointer register. This is true if the function has variable sized allocas
30 /// or if frame pointer elimination is disabled.
32 bool ARMFrameLowering::hasFP(const MachineFunction &MF) const {
33 const TargetRegisterInfo *RegInfo = MF.getTarget().getRegisterInfo();
35 // Mac OS X requires FP not to be clobbered for backtracing purpose.
36 if (STI.isTargetDarwin())
39 const MachineFrameInfo *MFI = MF.getFrameInfo();
40 // Always eliminate non-leaf frame pointers.
41 return ((DisableFramePointerElim(MF) && MFI->hasCalls()) ||
42 RegInfo->needsStackRealignment(MF) ||
43 MFI->hasVarSizedObjects() ||
44 MFI->isFrameAddressTaken());
47 // hasReservedCallFrame - Under normal circumstances, when a frame pointer is
48 // not required, we reserve argument space for call sites in the function
49 // immediately on entry to the current function. This eliminates the need for
50 // add/sub sp brackets around call sites. Returns true if the call frame is
51 // included as part of the stack frame.
52 bool ARMFrameLowering::hasReservedCallFrame(const MachineFunction &MF) const {
53 const MachineFrameInfo *FFI = MF.getFrameInfo();
54 unsigned CFSize = FFI->getMaxCallFrameSize();
55 // It's not always a good idea to include the call frame as part of the
56 // stack frame. ARM (especially Thumb) has small immediate offset to
57 // address the stack frame. So a large call frame can cause poor codegen
58 // and may even makes it impossible to scavenge a register.
59 if (CFSize >= ((1 << 12) - 1) / 2) // Half of imm12
62 return !MF.getFrameInfo()->hasVarSizedObjects();
65 // canSimplifyCallFramePseudos - If there is a reserved call frame, the
66 // call frame pseudos can be simplified. Unlike most targets, having a FP
67 // is not sufficient here since we still may reference some objects via SP
68 // even when FP is available in Thumb2 mode.
69 bool ARMFrameLowering::canSimplifyCallFramePseudos(const MachineFunction &MF)const {
70 return hasReservedCallFrame(MF) || MF.getFrameInfo()->hasVarSizedObjects();
73 static bool isCalleeSavedRegister(unsigned Reg, const unsigned *CSRegs) {
74 for (unsigned i = 0; CSRegs[i]; ++i)
80 static bool isCSRestore(MachineInstr *MI,
81 const ARMBaseInstrInfo &TII,
82 const unsigned *CSRegs) {
83 // Integer spill area is handled with "pop".
84 if (MI->getOpcode() == ARM::LDMIA_RET ||
85 MI->getOpcode() == ARM::t2LDMIA_RET ||
86 MI->getOpcode() == ARM::LDMIA_UPD ||
87 MI->getOpcode() == ARM::t2LDMIA_UPD ||
88 MI->getOpcode() == ARM::VLDMDIA_UPD) {
89 // The first two operands are predicates. The last two are
90 // imp-def and imp-use of SP. Check everything in between.
91 for (int i = 5, e = MI->getNumOperands(); i != e; ++i)
92 if (!isCalleeSavedRegister(MI->getOperand(i).getReg(), CSRegs))
96 if ((MI->getOpcode() == ARM::LDR_POST ||
97 MI->getOpcode() == ARM::t2LDR_POST) &&
98 isCalleeSavedRegister(MI->getOperand(0).getReg(), CSRegs) &&
99 MI->getOperand(1).getReg() == ARM::SP)
106 emitSPUpdate(bool isARM,
107 MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,
108 DebugLoc dl, const ARMBaseInstrInfo &TII,
110 ARMCC::CondCodes Pred = ARMCC::AL, unsigned PredReg = 0) {
112 emitARMRegPlusImmediate(MBB, MBBI, dl, ARM::SP, ARM::SP, NumBytes,
115 emitT2RegPlusImmediate(MBB, MBBI, dl, ARM::SP, ARM::SP, NumBytes,
119 void ARMFrameLowering::emitPrologue(MachineFunction &MF) const {
120 MachineBasicBlock &MBB = MF.front();
121 MachineBasicBlock::iterator MBBI = MBB.begin();
122 MachineFrameInfo *MFI = MF.getFrameInfo();
123 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
124 const ARMBaseRegisterInfo *RegInfo =
125 static_cast<const ARMBaseRegisterInfo*>(MF.getTarget().getRegisterInfo());
126 const ARMBaseInstrInfo &TII =
127 *static_cast<const ARMBaseInstrInfo*>(MF.getTarget().getInstrInfo());
128 assert(!AFI->isThumb1OnlyFunction() &&
129 "This emitPrologue does not support Thumb1!");
130 bool isARM = !AFI->isThumbFunction();
131 unsigned VARegSaveSize = AFI->getVarArgsRegSaveSize();
132 unsigned NumBytes = MFI->getStackSize();
133 const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
134 DebugLoc dl = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
135 unsigned FramePtr = RegInfo->getFrameRegister(MF);
137 // Determine the sizes of each callee-save spill areas and record which frame
138 // belongs to which callee-save spill areas.
139 unsigned GPRCS1Size = 0, GPRCS2Size = 0, DPRCSSize = 0;
140 int FramePtrSpillFI = 0;
142 // Allocate the vararg register save area. This is not counted in NumBytes.
144 emitSPUpdate(isARM, MBB, MBBI, dl, TII, -VARegSaveSize);
146 if (!AFI->hasStackFrame()) {
148 emitSPUpdate(isARM, MBB, MBBI, dl, TII, -NumBytes);
152 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
153 unsigned Reg = CSI[i].getReg();
154 int FI = CSI[i].getFrameIdx();
162 FramePtrSpillFI = FI;
163 AFI->addGPRCalleeSavedArea1Frame(FI);
171 FramePtrSpillFI = FI;
172 if (STI.isTargetDarwin()) {
173 AFI->addGPRCalleeSavedArea2Frame(FI);
176 AFI->addGPRCalleeSavedArea1Frame(FI);
181 AFI->addDPRCalleeSavedAreaFrame(FI);
187 if (GPRCS1Size > 0) MBBI++;
189 // Set FP to point to the stack slot that contains the previous FP.
190 // For Darwin, FP is R7, which has now been stored in spill area 1.
191 // Otherwise, if this is not Darwin, all the callee-saved registers go
192 // into spill area 1, including the FP in R11. In either case, it is
193 // now safe to emit this assignment.
194 bool HasFP = hasFP(MF);
196 unsigned ADDriOpc = !AFI->isThumbFunction() ? ARM::ADDri : ARM::t2ADDri;
197 MachineInstrBuilder MIB =
198 BuildMI(MBB, MBBI, dl, TII.get(ADDriOpc), FramePtr)
199 .addFrameIndex(FramePtrSpillFI).addImm(0);
200 AddDefaultCC(AddDefaultPred(MIB));
204 if (GPRCS2Size > 0) MBBI++;
206 // Determine starting offsets of spill areas.
207 unsigned DPRCSOffset = NumBytes - (GPRCS1Size + GPRCS2Size + DPRCSSize);
208 unsigned GPRCS2Offset = DPRCSOffset + DPRCSSize;
209 unsigned GPRCS1Offset = GPRCS2Offset + GPRCS2Size;
211 AFI->setFramePtrSpillOffset(MFI->getObjectOffset(FramePtrSpillFI) +
213 AFI->setGPRCalleeSavedArea1Offset(GPRCS1Offset);
214 AFI->setGPRCalleeSavedArea2Offset(GPRCS2Offset);
215 AFI->setDPRCalleeSavedAreaOffset(DPRCSOffset);
218 if (DPRCSSize > 0) MBBI++;
220 NumBytes = DPRCSOffset;
222 // Adjust SP after all the callee-save spills.
223 emitSPUpdate(isARM, MBB, MBBI, dl, TII, -NumBytes);
225 // Restore from fp only in ARM mode: e.g. sub sp, r7, #24
226 // Note it's not safe to do this in Thumb2 mode because it would have
227 // taken two instructions:
230 // If an interrupt is taken between the two instructions, then sp is in
231 // an inconsistent state (pointing to the middle of callee-saved area).
232 // The interrupt handler can end up clobbering the registers.
233 AFI->setShouldRestoreSPFromFP(true);
236 if (STI.isTargetELF() && hasFP(MF))
237 MFI->setOffsetAdjustment(MFI->getOffsetAdjustment() -
238 AFI->getFramePtrSpillOffset());
240 AFI->setGPRCalleeSavedArea1Size(GPRCS1Size);
241 AFI->setGPRCalleeSavedArea2Size(GPRCS2Size);
242 AFI->setDPRCalleeSavedAreaSize(DPRCSSize);
244 // If we need dynamic stack realignment, do it here. Be paranoid and make
245 // sure if we also have VLAs, we have a base pointer for frame access.
246 if (RegInfo->needsStackRealignment(MF)) {
247 unsigned MaxAlign = MFI->getMaxAlignment();
248 assert (!AFI->isThumb1OnlyFunction());
249 if (!AFI->isThumbFunction()) {
250 // Emit bic sp, sp, MaxAlign
251 AddDefaultCC(AddDefaultPred(BuildMI(MBB, MBBI, dl,
252 TII.get(ARM::BICri), ARM::SP)
253 .addReg(ARM::SP, RegState::Kill)
254 .addImm(MaxAlign-1)));
256 // We cannot use sp as source/dest register here, thus we're emitting the
257 // following sequence:
259 // bic r4, r4, MaxAlign
261 // FIXME: It will be better just to find spare register here.
262 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVgpr2tgpr), ARM::R4)
263 .addReg(ARM::SP, RegState::Kill);
264 AddDefaultCC(AddDefaultPred(BuildMI(MBB, MBBI, dl,
265 TII.get(ARM::t2BICri), ARM::R4)
266 .addReg(ARM::R4, RegState::Kill)
267 .addImm(MaxAlign-1)));
268 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVtgpr2gpr), ARM::SP)
269 .addReg(ARM::R4, RegState::Kill);
272 AFI->setShouldRestoreSPFromFP(true);
275 // If we need a base pointer, set it up here. It's whatever the value
276 // of the stack pointer is at this point. Any variable size objects
277 // will be allocated after this, so we can still use the base pointer
278 // to reference locals.
279 if (RegInfo->hasBasePointer(MF)) {
281 BuildMI(MBB, MBBI, dl,
282 TII.get(ARM::MOVr), RegInfo->getBaseRegister())
284 .addImm((unsigned)ARMCC::AL).addReg(0).addReg(0);
286 BuildMI(MBB, MBBI, dl,
287 TII.get(ARM::tMOVgpr2gpr), RegInfo->getBaseRegister())
291 // If the frame has variable sized objects then the epilogue must restore
292 // the sp from fp. We can assume there's an FP here since hasFP already
293 // checks for hasVarSizedObjects.
294 if (MFI->hasVarSizedObjects())
295 AFI->setShouldRestoreSPFromFP(true);
298 void ARMFrameLowering::emitEpilogue(MachineFunction &MF,
299 MachineBasicBlock &MBB) const {
300 MachineBasicBlock::iterator MBBI = prior(MBB.end());
301 assert(MBBI->getDesc().isReturn() &&
302 "Can only insert epilog into returning blocks");
303 unsigned RetOpcode = MBBI->getOpcode();
304 DebugLoc dl = MBBI->getDebugLoc();
305 MachineFrameInfo *MFI = MF.getFrameInfo();
306 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
307 const TargetRegisterInfo *RegInfo = MF.getTarget().getRegisterInfo();
308 const ARMBaseInstrInfo &TII =
309 *static_cast<const ARMBaseInstrInfo*>(MF.getTarget().getInstrInfo());
310 assert(!AFI->isThumb1OnlyFunction() &&
311 "This emitEpilogue does not support Thumb1!");
312 bool isARM = !AFI->isThumbFunction();
314 unsigned VARegSaveSize = AFI->getVarArgsRegSaveSize();
315 int NumBytes = (int)MFI->getStackSize();
316 unsigned FramePtr = RegInfo->getFrameRegister(MF);
318 if (!AFI->hasStackFrame()) {
320 emitSPUpdate(isARM, MBB, MBBI, dl, TII, NumBytes);
322 // Unwind MBBI to point to first LDR / VLDRD.
323 const unsigned *CSRegs = RegInfo->getCalleeSavedRegs();
324 if (MBBI != MBB.begin()) {
327 while (MBBI != MBB.begin() && isCSRestore(MBBI, TII, CSRegs));
328 if (!isCSRestore(MBBI, TII, CSRegs))
332 // Move SP to start of FP callee save spill area.
333 NumBytes -= (AFI->getGPRCalleeSavedArea1Size() +
334 AFI->getGPRCalleeSavedArea2Size() +
335 AFI->getDPRCalleeSavedAreaSize());
337 // Reset SP based on frame pointer only if the stack frame extends beyond
338 // frame pointer stack slot or target is ELF and the function has FP.
339 if (AFI->shouldRestoreSPFromFP()) {
340 NumBytes = AFI->getFramePtrSpillOffset() - NumBytes;
343 emitARMRegPlusImmediate(MBB, MBBI, dl, ARM::SP, FramePtr, -NumBytes,
346 // It's not possible to restore SP from FP in a single instruction.
347 // For Darwin, this looks like:
350 // This is bad, if an interrupt is taken after the mov, sp is in an
351 // inconsistent state.
352 // Use the first callee-saved register as a scratch register.
353 assert(MF.getRegInfo().isPhysRegUsed(ARM::R4) &&
354 "No scratch register to restore SP from FP!");
355 emitT2RegPlusImmediate(MBB, MBBI, dl, ARM::R4, FramePtr, -NumBytes,
357 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVgpr2gpr), ARM::SP)
363 BuildMI(MBB, MBBI, dl, TII.get(ARM::MOVr), ARM::SP)
364 .addReg(FramePtr).addImm((unsigned)ARMCC::AL).addReg(0).addReg(0);
366 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVgpr2gpr), ARM::SP)
370 emitSPUpdate(isARM, MBB, MBBI, dl, TII, NumBytes);
372 // Increment past our save areas.
373 if (AFI->getDPRCalleeSavedAreaSize()) MBBI++;
374 if (AFI->getGPRCalleeSavedArea2Size()) MBBI++;
375 if (AFI->getGPRCalleeSavedArea1Size()) MBBI++;
378 if (RetOpcode == ARM::TCRETURNdi || RetOpcode == ARM::TCRETURNdiND ||
379 RetOpcode == ARM::TCRETURNri || RetOpcode == ARM::TCRETURNriND) {
380 // Tail call return: adjust the stack pointer and jump to callee.
381 MBBI = prior(MBB.end());
382 MachineOperand &JumpTarget = MBBI->getOperand(0);
384 // Jump to label or value in register.
385 if (RetOpcode == ARM::TCRETURNdi || RetOpcode == ARM::TCRETURNdiND) {
386 unsigned TCOpcode = (RetOpcode == ARM::TCRETURNdi)
387 ? (STI.isThumb() ? ARM::TAILJMPdt : ARM::TAILJMPd)
388 : (STI.isThumb() ? ARM::TAILJMPdNDt : ARM::TAILJMPdND);
389 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII.get(TCOpcode));
390 if (JumpTarget.isGlobal())
391 MIB.addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset(),
392 JumpTarget.getTargetFlags());
394 assert(JumpTarget.isSymbol());
395 MIB.addExternalSymbol(JumpTarget.getSymbolName(),
396 JumpTarget.getTargetFlags());
398 } else if (RetOpcode == ARM::TCRETURNri) {
399 BuildMI(MBB, MBBI, dl, TII.get(ARM::TAILJMPr)).
400 addReg(JumpTarget.getReg(), RegState::Kill);
401 } else if (RetOpcode == ARM::TCRETURNriND) {
402 BuildMI(MBB, MBBI, dl, TII.get(ARM::TAILJMPrND)).
403 addReg(JumpTarget.getReg(), RegState::Kill);
406 MachineInstr *NewMI = prior(MBBI);
407 for (unsigned i = 1, e = MBBI->getNumOperands(); i != e; ++i)
408 NewMI->addOperand(MBBI->getOperand(i));
410 // Delete the pseudo instruction TCRETURN.
415 emitSPUpdate(isARM, MBB, MBBI, dl, TII, VARegSaveSize);
418 // Provide a base+offset reference to an FI slot for debug info. It's the
419 // same as what we use for resolving the code-gen references for now.
420 // FIXME: This can go wrong when references are SP-relative and simple call
421 // frames aren't used.
423 ARMFrameLowering::getFrameIndexReference(const MachineFunction &MF, int FI,
424 unsigned &FrameReg) const {
425 return ResolveFrameIndexReference(MF, FI, FrameReg, 0);
429 ARMFrameLowering::ResolveFrameIndexReference(const MachineFunction &MF,
433 const MachineFrameInfo *MFI = MF.getFrameInfo();
434 const ARMBaseRegisterInfo *RegInfo =
435 static_cast<const ARMBaseRegisterInfo*>(MF.getTarget().getRegisterInfo());
436 const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
437 int Offset = MFI->getObjectOffset(FI) + MFI->getStackSize();
438 int FPOffset = Offset - AFI->getFramePtrSpillOffset();
439 bool isFixed = MFI->isFixedObjectIndex(FI);
443 if (AFI->isGPRCalleeSavedArea1Frame(FI))
444 return Offset - AFI->getGPRCalleeSavedArea1Offset();
445 else if (AFI->isGPRCalleeSavedArea2Frame(FI))
446 return Offset - AFI->getGPRCalleeSavedArea2Offset();
447 else if (AFI->isDPRCalleeSavedAreaFrame(FI))
448 return Offset - AFI->getDPRCalleeSavedAreaOffset();
450 // When dynamically realigning the stack, use the frame pointer for
451 // parameters, and the stack/base pointer for locals.
452 if (RegInfo->needsStackRealignment(MF)) {
453 assert (hasFP(MF) && "dynamic stack realignment without a FP!");
455 FrameReg = RegInfo->getFrameRegister(MF);
457 } else if (MFI->hasVarSizedObjects()) {
458 assert(RegInfo->hasBasePointer(MF) &&
459 "VLAs and dynamic stack alignment, but missing base pointer!");
460 FrameReg = RegInfo->getBaseRegister();
465 // If there is a frame pointer, use it when we can.
466 if (hasFP(MF) && AFI->hasStackFrame()) {
467 // Use frame pointer to reference fixed objects. Use it for locals if
468 // there are VLAs (and thus the SP isn't reliable as a base).
469 if (isFixed || (MFI->hasVarSizedObjects() &&
470 !RegInfo->hasBasePointer(MF))) {
471 FrameReg = RegInfo->getFrameRegister(MF);
473 } else if (MFI->hasVarSizedObjects()) {
474 assert(RegInfo->hasBasePointer(MF) && "missing base pointer!");
475 // Try to use the frame pointer if we can, else use the base pointer
476 // since it's available. This is handy for the emergency spill slot, in
478 if (AFI->isThumb2Function()) {
479 if (FPOffset >= -255 && FPOffset < 0) {
480 FrameReg = RegInfo->getFrameRegister(MF);
484 FrameReg = RegInfo->getBaseRegister();
485 } else if (AFI->isThumb2Function()) {
486 // In Thumb2 mode, the negative offset is very limited. Try to avoid
487 // out of range references.
488 if (FPOffset >= -255 && FPOffset < 0) {
489 FrameReg = RegInfo->getFrameRegister(MF);
492 } else if (Offset > (FPOffset < 0 ? -FPOffset : FPOffset)) {
493 // Otherwise, use SP or FP, whichever is closer to the stack slot.
494 FrameReg = RegInfo->getFrameRegister(MF);
498 // Use the base pointer if we have one.
499 if (RegInfo->hasBasePointer(MF))
500 FrameReg = RegInfo->getBaseRegister();
504 int ARMFrameLowering::getFrameIndexOffset(const MachineFunction &MF, int FI) const {
506 return getFrameIndexReference(MF, FI, FrameReg);
509 void ARMFrameLowering::emitPushInst(MachineBasicBlock &MBB,
510 MachineBasicBlock::iterator MI,
511 const std::vector<CalleeSavedInfo> &CSI,
512 unsigned StmOpc, unsigned StrOpc, bool NoGap,
513 bool(*Func)(unsigned, bool)) const {
514 MachineFunction &MF = *MBB.getParent();
515 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
518 if (MI != MBB.end()) DL = MI->getDebugLoc();
520 SmallVector<std::pair<unsigned,bool>, 4> Regs;
521 unsigned i = CSI.size();
523 unsigned LastReg = 0;
524 for (; i != 0; --i) {
525 unsigned Reg = CSI[i-1].getReg();
526 if (!(Func)(Reg, STI.isTargetDarwin())) continue;
528 // Add the callee-saved register as live-in unless it's LR and
529 // @llvm.returnaddress is called. If LR is returned for
530 // @llvm.returnaddress then it's already added to the function and
531 // entry block live-in sets.
533 if (Reg == ARM::LR) {
534 if (MF.getFrameInfo()->isReturnAddressTaken() &&
535 MF.getRegInfo().isLiveIn(Reg))
542 // If NoGap is true, push consecutive registers and then leave the rest
543 // for other instructions. e.g.
544 // vpush {d8, d10, d11} -> vpush {d8}, vpush {d10, d11}
545 if (NoGap && LastReg && LastReg != Reg-1)
548 Regs.push_back(std::make_pair(Reg, isKill));
553 if (Regs.size() > 1 || StrOpc== 0) {
554 MachineInstrBuilder MIB =
555 AddDefaultPred(BuildMI(MBB, MI, DL, TII.get(StmOpc), ARM::SP)
557 for (unsigned i = 0, e = Regs.size(); i < e; ++i)
558 MIB.addReg(Regs[i].first, getKillRegState(Regs[i].second));
559 } else if (Regs.size() == 1) {
560 MachineInstrBuilder MIB = BuildMI(MBB, MI, DL, TII.get(StrOpc),
562 .addReg(Regs[0].first, getKillRegState(Regs[0].second))
564 // ARM mode needs an extra reg0 here due to addrmode2. Will go away once
565 // that refactoring is complete (eventually).
566 if (StrOpc == ARM::STR_PRE) {
568 MIB.addImm(ARM_AM::getAM2Opc(ARM_AM::sub, 4, ARM_AM::no_shift));
577 void ARMFrameLowering::emitPopInst(MachineBasicBlock &MBB,
578 MachineBasicBlock::iterator MI,
579 const std::vector<CalleeSavedInfo> &CSI,
580 unsigned LdmOpc, unsigned LdrOpc,
581 bool isVarArg, bool NoGap,
582 bool(*Func)(unsigned, bool)) const {
583 MachineFunction &MF = *MBB.getParent();
584 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
585 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
586 DebugLoc DL = MI->getDebugLoc();
588 SmallVector<unsigned, 4> Regs;
589 unsigned i = CSI.size();
591 unsigned LastReg = 0;
592 bool DeleteRet = false;
593 for (; i != 0; --i) {
594 unsigned Reg = CSI[i-1].getReg();
595 if (!(Func)(Reg, STI.isTargetDarwin())) continue;
597 if (Reg == ARM::LR && !isVarArg && STI.hasV5TOps()) {
599 LdmOpc = AFI->isThumbFunction() ? ARM::t2LDMIA_RET : ARM::LDMIA_RET;
600 // Fold the return instruction into the LDM.
604 // If NoGap is true, pop consecutive registers and then leave the rest
605 // for other instructions. e.g.
606 // vpop {d8, d10, d11} -> vpop {d8}, vpop {d10, d11}
607 if (NoGap && LastReg && LastReg != Reg-1)
616 if (Regs.size() > 1 || LdrOpc == 0) {
617 MachineInstrBuilder MIB =
618 AddDefaultPred(BuildMI(MBB, MI, DL, TII.get(LdmOpc), ARM::SP)
620 for (unsigned i = 0, e = Regs.size(); i < e; ++i)
621 MIB.addReg(Regs[i], getDefRegState(true));
623 MI->eraseFromParent();
625 } else if (Regs.size() == 1) {
626 // If we adjusted the reg to PC from LR above, switch it back here. We
627 // only do that for LDM.
628 if (Regs[0] == ARM::PC)
630 MachineInstrBuilder MIB =
631 BuildMI(MBB, MI, DL, TII.get(LdrOpc), Regs[0])
632 .addReg(ARM::SP, RegState::Define)
634 // ARM mode needs an extra reg0 here due to addrmode2. Will go away once
635 // that refactoring is complete (eventually).
636 if (LdrOpc == ARM::LDR_POST) {
638 MIB.addImm(ARM_AM::getAM2Opc(ARM_AM::add, 4, ARM_AM::no_shift));
647 bool ARMFrameLowering::spillCalleeSavedRegisters(MachineBasicBlock &MBB,
648 MachineBasicBlock::iterator MI,
649 const std::vector<CalleeSavedInfo> &CSI,
650 const TargetRegisterInfo *TRI) const {
654 MachineFunction &MF = *MBB.getParent();
655 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
656 DebugLoc DL = MI->getDebugLoc();
658 unsigned PushOpc = AFI->isThumbFunction() ? ARM::t2STMDB_UPD : ARM::STMDB_UPD;
659 unsigned PushOneOpc = AFI->isThumbFunction() ? ARM::t2STR_PRE : ARM::STR_PRE;
660 unsigned FltOpc = ARM::VSTMDDB_UPD;
661 emitPushInst(MBB, MI, CSI, PushOpc, PushOneOpc, false, &isARMArea1Register);
662 emitPushInst(MBB, MI, CSI, PushOpc, PushOneOpc, false, &isARMArea2Register);
663 emitPushInst(MBB, MI, CSI, FltOpc, 0, true, &isARMArea3Register);
668 bool ARMFrameLowering::restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
669 MachineBasicBlock::iterator MI,
670 const std::vector<CalleeSavedInfo> &CSI,
671 const TargetRegisterInfo *TRI) const {
675 MachineFunction &MF = *MBB.getParent();
676 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
677 bool isVarArg = AFI->getVarArgsRegSaveSize() > 0;
678 DebugLoc DL = MI->getDebugLoc();
680 unsigned PopOpc = AFI->isThumbFunction() ? ARM::t2LDMIA_UPD : ARM::LDMIA_UPD;
681 unsigned LdrOpc = AFI->isThumbFunction() ? ARM::t2LDR_POST : ARM::LDR_POST;
682 unsigned FltOpc = ARM::VLDMDIA_UPD;
683 emitPopInst(MBB, MI, CSI, FltOpc, 0, isVarArg, true, &isARMArea3Register);
684 emitPopInst(MBB, MI, CSI, PopOpc, LdrOpc, isVarArg, false,
685 &isARMArea2Register);
686 emitPopInst(MBB, MI, CSI, PopOpc, LdrOpc, isVarArg, false,
687 &isARMArea1Register);
692 // FIXME: Make generic?
693 static unsigned GetFunctionSizeInBytes(const MachineFunction &MF,
694 const ARMBaseInstrInfo &TII) {
696 for (MachineFunction::const_iterator MBBI = MF.begin(), E = MF.end();
698 const MachineBasicBlock &MBB = *MBBI;
699 for (MachineBasicBlock::const_iterator I = MBB.begin(),E = MBB.end();
701 FnSize += TII.GetInstSizeInBytes(I);
706 /// estimateStackSize - Estimate and return the size of the frame.
707 /// FIXME: Make generic?
708 static unsigned estimateStackSize(MachineFunction &MF) {
709 const MachineFrameInfo *FFI = MF.getFrameInfo();
711 for (int i = FFI->getObjectIndexBegin(); i != 0; ++i) {
712 int FixedOff = -FFI->getObjectOffset(i);
713 if (FixedOff > Offset) Offset = FixedOff;
715 for (unsigned i = 0, e = FFI->getObjectIndexEnd(); i != e; ++i) {
716 if (FFI->isDeadObjectIndex(i))
718 Offset += FFI->getObjectSize(i);
719 unsigned Align = FFI->getObjectAlignment(i);
720 // Adjust to alignment boundary
721 Offset = (Offset+Align-1)/Align*Align;
723 return (unsigned)Offset;
726 /// estimateRSStackSizeLimit - Look at each instruction that references stack
727 /// frames and return the stack size limit beyond which some of these
728 /// instructions will require a scratch register during their expansion later.
729 // FIXME: Move to TII?
730 static unsigned estimateRSStackSizeLimit(MachineFunction &MF,
731 const TargetFrameLowering *TFI) {
732 const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
733 unsigned Limit = (1 << 12) - 1;
734 for (MachineFunction::iterator BB = MF.begin(),E = MF.end(); BB != E; ++BB) {
735 for (MachineBasicBlock::iterator I = BB->begin(), E = BB->end();
737 for (unsigned i = 0, e = I->getNumOperands(); i != e; ++i) {
738 if (!I->getOperand(i).isFI()) continue;
740 // When using ADDri to get the address of a stack object, 255 is the
741 // largest offset guaranteed to fit in the immediate offset.
742 if (I->getOpcode() == ARM::ADDri) {
743 Limit = std::min(Limit, (1U << 8) - 1);
747 // Otherwise check the addressing mode.
748 switch (I->getDesc().TSFlags & ARMII::AddrModeMask) {
749 case ARMII::AddrMode3:
750 case ARMII::AddrModeT2_i8:
751 Limit = std::min(Limit, (1U << 8) - 1);
753 case ARMII::AddrMode5:
754 case ARMII::AddrModeT2_i8s4:
755 Limit = std::min(Limit, ((1U << 8) - 1) * 4);
757 case ARMII::AddrModeT2_i12:
758 // i12 supports only positive offset so these will be converted to
759 // i8 opcodes. See llvm::rewriteT2FrameIndex.
760 if (TFI->hasFP(MF) && AFI->hasStackFrame())
761 Limit = std::min(Limit, (1U << 8) - 1);
763 case ARMII::AddrMode4:
764 case ARMII::AddrMode6:
765 // Addressing modes 4 & 6 (load/store) instructions can't encode an
766 // immediate offset for stack references.
771 break; // At most one FI per instruction
780 ARMFrameLowering::processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
781 RegScavenger *RS) const {
782 // This tells PEI to spill the FP as if it is any other callee-save register
783 // to take advantage the eliminateFrameIndex machinery. This also ensures it
784 // is spilled in the order specified by getCalleeSavedRegs() to make it easier
785 // to combine multiple loads / stores.
786 bool CanEliminateFrame = true;
787 bool CS1Spilled = false;
788 bool LRSpilled = false;
789 unsigned NumGPRSpills = 0;
790 SmallVector<unsigned, 4> UnspilledCS1GPRs;
791 SmallVector<unsigned, 4> UnspilledCS2GPRs;
792 const ARMBaseRegisterInfo *RegInfo =
793 static_cast<const ARMBaseRegisterInfo*>(MF.getTarget().getRegisterInfo());
794 const ARMBaseInstrInfo &TII =
795 *static_cast<const ARMBaseInstrInfo*>(MF.getTarget().getInstrInfo());
796 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
797 MachineFrameInfo *MFI = MF.getFrameInfo();
798 unsigned FramePtr = RegInfo->getFrameRegister(MF);
800 // Spill R4 if Thumb2 function requires stack realignment - it will be used as
801 // scratch register. Also spill R4 if Thumb2 function has varsized objects,
802 // since it's always posible to restore sp from fp in a single instruction.
803 // FIXME: It will be better just to find spare register here.
804 if (AFI->isThumb2Function() &&
805 (MFI->hasVarSizedObjects() || RegInfo->needsStackRealignment(MF)))
806 MF.getRegInfo().setPhysRegUsed(ARM::R4);
808 // Spill LR if Thumb1 function uses variable length argument lists.
809 if (AFI->isThumb1OnlyFunction() && AFI->getVarArgsRegSaveSize() > 0)
810 MF.getRegInfo().setPhysRegUsed(ARM::LR);
812 // Spill the BasePtr if it's used.
813 if (RegInfo->hasBasePointer(MF))
814 MF.getRegInfo().setPhysRegUsed(RegInfo->getBaseRegister());
816 // Don't spill FP if the frame can be eliminated. This is determined
817 // by scanning the callee-save registers to see if any is used.
818 const unsigned *CSRegs = RegInfo->getCalleeSavedRegs();
819 for (unsigned i = 0; CSRegs[i]; ++i) {
820 unsigned Reg = CSRegs[i];
821 bool Spilled = false;
822 if (MF.getRegInfo().isPhysRegUsed(Reg)) {
823 AFI->setCSRegisterIsSpilled(Reg);
825 CanEliminateFrame = false;
827 // Check alias registers too.
828 for (const unsigned *Aliases =
829 RegInfo->getAliasSet(Reg); *Aliases; ++Aliases) {
830 if (MF.getRegInfo().isPhysRegUsed(*Aliases)) {
832 CanEliminateFrame = false;
837 if (!ARM::GPRRegisterClass->contains(Reg))
843 if (!STI.isTargetDarwin()) {
850 // Keep track if LR and any of R4, R5, R6, and R7 is spilled.
855 case ARM::R4: case ARM::R5:
856 case ARM::R6: case ARM::R7:
863 if (!STI.isTargetDarwin()) {
864 UnspilledCS1GPRs.push_back(Reg);
869 case ARM::R4: case ARM::R5:
870 case ARM::R6: case ARM::R7:
872 UnspilledCS1GPRs.push_back(Reg);
875 UnspilledCS2GPRs.push_back(Reg);
881 bool ForceLRSpill = false;
882 if (!LRSpilled && AFI->isThumb1OnlyFunction()) {
883 unsigned FnSize = GetFunctionSizeInBytes(MF, TII);
884 // Force LR to be spilled if the Thumb function size is > 2048. This enables
885 // use of BL to implement far jump. If it turns out that it's not needed
886 // then the branch fix up path will undo it.
887 if (FnSize >= (1 << 11)) {
888 CanEliminateFrame = false;
893 // If any of the stack slot references may be out of range of an immediate
894 // offset, make sure a register (or a spill slot) is available for the
895 // register scavenger. Note that if we're indexing off the frame pointer, the
896 // effective stack size is 4 bytes larger since the FP points to the stack
897 // slot of the previous FP. Also, if we have variable sized objects in the
898 // function, stack slot references will often be negative, and some of
899 // our instructions are positive-offset only, so conservatively consider
900 // that case to want a spill slot (or register) as well. Similarly, if
901 // the function adjusts the stack pointer during execution and the
902 // adjustments aren't already part of our stack size estimate, our offset
903 // calculations may be off, so be conservative.
904 // FIXME: We could add logic to be more precise about negative offsets
905 // and which instructions will need a scratch register for them. Is it
906 // worth the effort and added fragility?
909 (estimateStackSize(MF) + ((hasFP(MF) && AFI->hasStackFrame()) ? 4:0) >=
910 estimateRSStackSizeLimit(MF, this)))
911 || MFI->hasVarSizedObjects()
912 || (MFI->adjustsStack() && !canSimplifyCallFramePseudos(MF));
914 bool ExtraCSSpill = false;
915 if (BigStack || !CanEliminateFrame || RegInfo->cannotEliminateFrame(MF)) {
916 AFI->setHasStackFrame(true);
918 // If LR is not spilled, but at least one of R4, R5, R6, and R7 is spilled.
919 // Spill LR as well so we can fold BX_RET to the registers restore (LDM).
920 if (!LRSpilled && CS1Spilled) {
921 MF.getRegInfo().setPhysRegUsed(ARM::LR);
922 AFI->setCSRegisterIsSpilled(ARM::LR);
924 UnspilledCS1GPRs.erase(std::find(UnspilledCS1GPRs.begin(),
925 UnspilledCS1GPRs.end(), (unsigned)ARM::LR));
926 ForceLRSpill = false;
931 MF.getRegInfo().setPhysRegUsed(FramePtr);
935 // If stack and double are 8-byte aligned and we are spilling an odd number
936 // of GPRs, spill one extra callee save GPR so we won't have to pad between
937 // the integer and double callee save areas.
938 unsigned TargetAlign = getStackAlignment();
939 if (TargetAlign == 8 && (NumGPRSpills & 1)) {
940 if (CS1Spilled && !UnspilledCS1GPRs.empty()) {
941 for (unsigned i = 0, e = UnspilledCS1GPRs.size(); i != e; ++i) {
942 unsigned Reg = UnspilledCS1GPRs[i];
943 // Don't spill high register if the function is thumb1
944 if (!AFI->isThumb1OnlyFunction() ||
945 isARMLowRegister(Reg) || Reg == ARM::LR) {
946 MF.getRegInfo().setPhysRegUsed(Reg);
947 AFI->setCSRegisterIsSpilled(Reg);
948 if (!RegInfo->isReservedReg(MF, Reg))
953 } else if (!UnspilledCS2GPRs.empty() && !AFI->isThumb1OnlyFunction()) {
954 unsigned Reg = UnspilledCS2GPRs.front();
955 MF.getRegInfo().setPhysRegUsed(Reg);
956 AFI->setCSRegisterIsSpilled(Reg);
957 if (!RegInfo->isReservedReg(MF, Reg))
962 // Estimate if we might need to scavenge a register at some point in order
963 // to materialize a stack offset. If so, either spill one additional
964 // callee-saved register or reserve a special spill slot to facilitate
965 // register scavenging. Thumb1 needs a spill slot for stack pointer
966 // adjustments also, even when the frame itself is small.
967 if (BigStack && !ExtraCSSpill) {
968 // If any non-reserved CS register isn't spilled, just spill one or two
969 // extra. That should take care of it!
970 unsigned NumExtras = TargetAlign / 4;
971 SmallVector<unsigned, 2> Extras;
972 while (NumExtras && !UnspilledCS1GPRs.empty()) {
973 unsigned Reg = UnspilledCS1GPRs.back();
974 UnspilledCS1GPRs.pop_back();
975 if (!RegInfo->isReservedReg(MF, Reg) &&
976 (!AFI->isThumb1OnlyFunction() || isARMLowRegister(Reg) ||
978 Extras.push_back(Reg);
982 // For non-Thumb1 functions, also check for hi-reg CS registers
983 if (!AFI->isThumb1OnlyFunction()) {
984 while (NumExtras && !UnspilledCS2GPRs.empty()) {
985 unsigned Reg = UnspilledCS2GPRs.back();
986 UnspilledCS2GPRs.pop_back();
987 if (!RegInfo->isReservedReg(MF, Reg)) {
988 Extras.push_back(Reg);
993 if (Extras.size() && NumExtras == 0) {
994 for (unsigned i = 0, e = Extras.size(); i != e; ++i) {
995 MF.getRegInfo().setPhysRegUsed(Extras[i]);
996 AFI->setCSRegisterIsSpilled(Extras[i]);
998 } else if (!AFI->isThumb1OnlyFunction()) {
999 // note: Thumb1 functions spill to R12, not the stack. Reserve a slot
1000 // closest to SP or frame pointer.
1001 const TargetRegisterClass *RC = ARM::GPRRegisterClass;
1002 RS->setScavengingFrameIndex(MFI->CreateStackObject(RC->getSize(),
1010 MF.getRegInfo().setPhysRegUsed(ARM::LR);
1011 AFI->setCSRegisterIsSpilled(ARM::LR);
1012 AFI->setLRIsSpilledForFarJump(true);