1 //===-- ARMFrameLowering.cpp - ARM Frame Information ----------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the ARM implementation of TargetFrameLowering class.
12 //===----------------------------------------------------------------------===//
14 #include "ARMFrameLowering.h"
15 #include "ARMBaseInstrInfo.h"
16 #include "ARMBaseRegisterInfo.h"
17 #include "ARMConstantPoolValue.h"
18 #include "ARMMachineFunctionInfo.h"
19 #include "MCTargetDesc/ARMAddressingModes.h"
20 #include "llvm/CodeGen/MachineFrameInfo.h"
21 #include "llvm/CodeGen/MachineFunction.h"
22 #include "llvm/CodeGen/MachineInstrBuilder.h"
23 #include "llvm/CodeGen/MachineModuleInfo.h"
24 #include "llvm/CodeGen/MachineRegisterInfo.h"
25 #include "llvm/CodeGen/RegisterScavenging.h"
26 #include "llvm/IR/CallingConv.h"
27 #include "llvm/IR/Function.h"
28 #include "llvm/MC/MCContext.h"
29 #include "llvm/Support/CommandLine.h"
30 #include "llvm/Target/TargetOptions.h"
35 SpillAlignedNEONRegs("align-neon-spills", cl::Hidden, cl::init(true),
36 cl::desc("Align ARM NEON spills in prolog and epilog"));
38 static MachineBasicBlock::iterator
39 skipAlignedDPRCS2Spills(MachineBasicBlock::iterator MI,
40 unsigned NumAlignedDPRCS2Regs);
42 ARMFrameLowering::ARMFrameLowering(const ARMSubtarget &sti)
43 : TargetFrameLowering(StackGrowsDown, sti.getStackAlignment(), 0, 4),
46 bool ARMFrameLowering::noFramePointerElim(const MachineFunction &MF) const {
47 // iOS always has a FP for backtracking, force other targets to keep their FP
48 // when doing FastISel. The emitted code is currently superior, and in cases
49 // like test-suite's lencod FastISel isn't quite correct when FP is eliminated.
50 return TargetFrameLowering::noFramePointerElim(MF) ||
51 MF.getSubtarget<ARMSubtarget>().useFastISel();
54 /// hasFP - Return true if the specified function should have a dedicated frame
55 /// pointer register. This is true if the function has variable sized allocas
56 /// or if frame pointer elimination is disabled.
57 bool ARMFrameLowering::hasFP(const MachineFunction &MF) const {
58 const TargetRegisterInfo *RegInfo = MF.getSubtarget().getRegisterInfo();
60 // iOS requires FP not to be clobbered for backtracing purpose.
61 if (STI.isTargetIOS())
64 const MachineFrameInfo *MFI = MF.getFrameInfo();
65 // Always eliminate non-leaf frame pointers.
66 return ((MF.getTarget().Options.DisableFramePointerElim(MF) &&
68 RegInfo->needsStackRealignment(MF) ||
69 MFI->hasVarSizedObjects() ||
70 MFI->isFrameAddressTaken());
73 /// hasReservedCallFrame - Under normal circumstances, when a frame pointer is
74 /// not required, we reserve argument space for call sites in the function
75 /// immediately on entry to the current function. This eliminates the need for
76 /// add/sub sp brackets around call sites. Returns true if the call frame is
77 /// included as part of the stack frame.
78 bool ARMFrameLowering::hasReservedCallFrame(const MachineFunction &MF) const {
79 const MachineFrameInfo *FFI = MF.getFrameInfo();
80 unsigned CFSize = FFI->getMaxCallFrameSize();
81 // It's not always a good idea to include the call frame as part of the
82 // stack frame. ARM (especially Thumb) has small immediate offset to
83 // address the stack frame. So a large call frame can cause poor codegen
84 // and may even makes it impossible to scavenge a register.
85 if (CFSize >= ((1 << 12) - 1) / 2) // Half of imm12
88 return !MF.getFrameInfo()->hasVarSizedObjects();
91 /// canSimplifyCallFramePseudos - If there is a reserved call frame, the
92 /// call frame pseudos can be simplified. Unlike most targets, having a FP
93 /// is not sufficient here since we still may reference some objects via SP
94 /// even when FP is available in Thumb2 mode.
96 ARMFrameLowering::canSimplifyCallFramePseudos(const MachineFunction &MF) const {
97 return hasReservedCallFrame(MF) || MF.getFrameInfo()->hasVarSizedObjects();
100 static bool isCSRestore(MachineInstr *MI,
101 const ARMBaseInstrInfo &TII,
102 const MCPhysReg *CSRegs) {
103 // Integer spill area is handled with "pop".
104 if (isPopOpcode(MI->getOpcode())) {
105 // The first two operands are predicates. The last two are
106 // imp-def and imp-use of SP. Check everything in between.
107 for (int i = 5, e = MI->getNumOperands(); i != e; ++i)
108 if (!isCalleeSavedRegister(MI->getOperand(i).getReg(), CSRegs))
112 if ((MI->getOpcode() == ARM::LDR_POST_IMM ||
113 MI->getOpcode() == ARM::LDR_POST_REG ||
114 MI->getOpcode() == ARM::t2LDR_POST) &&
115 isCalleeSavedRegister(MI->getOperand(0).getReg(), CSRegs) &&
116 MI->getOperand(1).getReg() == ARM::SP)
122 static void emitRegPlusImmediate(bool isARM, MachineBasicBlock &MBB,
123 MachineBasicBlock::iterator &MBBI, DebugLoc dl,
124 const ARMBaseInstrInfo &TII, unsigned DestReg,
125 unsigned SrcReg, int NumBytes,
126 unsigned MIFlags = MachineInstr::NoFlags,
127 ARMCC::CondCodes Pred = ARMCC::AL,
128 unsigned PredReg = 0) {
130 emitARMRegPlusImmediate(MBB, MBBI, dl, DestReg, SrcReg, NumBytes,
131 Pred, PredReg, TII, MIFlags);
133 emitT2RegPlusImmediate(MBB, MBBI, dl, DestReg, SrcReg, NumBytes,
134 Pred, PredReg, TII, MIFlags);
137 static void emitSPUpdate(bool isARM, MachineBasicBlock &MBB,
138 MachineBasicBlock::iterator &MBBI, DebugLoc dl,
139 const ARMBaseInstrInfo &TII, int NumBytes,
140 unsigned MIFlags = MachineInstr::NoFlags,
141 ARMCC::CondCodes Pred = ARMCC::AL,
142 unsigned PredReg = 0) {
143 emitRegPlusImmediate(isARM, MBB, MBBI, dl, TII, ARM::SP, ARM::SP, NumBytes,
144 MIFlags, Pred, PredReg);
147 static int sizeOfSPAdjustment(const MachineInstr *MI) {
149 switch (MI->getOpcode()) {
150 case ARM::VSTMDDB_UPD:
154 case ARM::t2STMDB_UPD:
158 case ARM::STR_PRE_IMM:
161 llvm_unreachable("Unknown push or pop like instruction");
165 // ARM and Thumb2 push/pop insts have explicit "sp, sp" operands (+
166 // pred) so the list starts at 4.
167 for (int i = MI->getNumOperands() - 1; i >= 4; --i)
172 static bool WindowsRequiresStackProbe(const MachineFunction &MF,
173 size_t StackSizeInBytes) {
174 const MachineFrameInfo *MFI = MF.getFrameInfo();
175 const Function *F = MF.getFunction();
176 unsigned StackProbeSize = (MFI->getStackProtectorIndex() > 0) ? 4080 : 4096;
177 if (F->hasFnAttribute("stack-probe-size"))
178 F->getFnAttribute("stack-probe-size")
180 .getAsInteger(0, StackProbeSize);
181 return StackSizeInBytes >= StackProbeSize;
185 struct StackAdjustingInsts {
187 MachineBasicBlock::iterator I;
192 SmallVector<InstInfo, 4> Insts;
194 void addInst(MachineBasicBlock::iterator I, unsigned SPAdjust,
195 bool BeforeFPSet = false) {
196 InstInfo Info = {I, SPAdjust, BeforeFPSet};
197 Insts.push_back(Info);
200 void addExtraBytes(const MachineBasicBlock::iterator I, unsigned ExtraBytes) {
201 auto Info = std::find_if(Insts.begin(), Insts.end(),
202 [&](InstInfo &Info) { return Info.I == I; });
203 assert(Info != Insts.end() && "invalid sp adjusting instruction");
204 Info->SPAdjust += ExtraBytes;
207 void emitDefCFAOffsets(MachineModuleInfo &MMI, MachineBasicBlock &MBB,
208 DebugLoc dl, const ARMBaseInstrInfo &TII, bool HasFP) {
209 unsigned CFAOffset = 0;
210 for (auto &Info : Insts) {
211 if (HasFP && !Info.BeforeFPSet)
214 CFAOffset -= Info.SPAdjust;
215 unsigned CFIIndex = MMI.addFrameInst(
216 MCCFIInstruction::createDefCfaOffset(nullptr, CFAOffset));
217 BuildMI(MBB, std::next(Info.I), dl,
218 TII.get(TargetOpcode::CFI_INSTRUCTION))
219 .addCFIIndex(CFIIndex)
220 .setMIFlags(MachineInstr::FrameSetup);
226 /// Emit an instruction sequence that will align the address in
227 /// register Reg by zero-ing out the lower bits. For versions of the
228 /// architecture that support Neon, this must be done in a single
229 /// instruction, since skipAlignedDPRCS2Spills assumes it is done in a
230 /// single instruction. That function only gets called when optimizing
231 /// spilling of D registers on a core with the Neon instruction set
233 static void emitAligningInstructions(MachineFunction &MF, ARMFunctionInfo *AFI,
234 const TargetInstrInfo &TII,
235 MachineBasicBlock &MBB,
236 MachineBasicBlock::iterator MBBI,
237 DebugLoc DL, const unsigned Reg,
238 const unsigned Alignment,
239 const bool MustBeSingleInstruction) {
240 const ARMSubtarget &AST =
241 static_cast<const ARMSubtarget &>(MF.getSubtarget());
242 const bool CanUseBFC = AST.hasV6T2Ops() || AST.hasV7Ops();
243 const unsigned AlignMask = Alignment - 1;
244 const unsigned NrBitsToZero = countTrailingZeros(Alignment);
245 assert(!AFI->isThumb1OnlyFunction() && "Thumb1 not supported");
246 if (!AFI->isThumbFunction()) {
247 // if the BFC instruction is available, use that to zero the lower
249 // bfc Reg, #0, log2(Alignment)
250 // otherwise use BIC, if the mask to zero the required number of bits
251 // can be encoded in the bic immediate field
252 // bic Reg, Reg, Alignment-1
254 // lsr Reg, Reg, log2(Alignment)
255 // lsl Reg, Reg, log2(Alignment)
257 AddDefaultPred(BuildMI(MBB, MBBI, DL, TII.get(ARM::BFC), Reg)
258 .addReg(Reg, RegState::Kill)
259 .addImm(~AlignMask));
260 } else if (AlignMask <= 255) {
262 AddDefaultPred(BuildMI(MBB, MBBI, DL, TII.get(ARM::BICri), Reg)
263 .addReg(Reg, RegState::Kill)
264 .addImm(AlignMask)));
266 assert(!MustBeSingleInstruction &&
267 "Shouldn't call emitAligningInstructions demanding a single "
268 "instruction to be emitted for large stack alignment for a target "
270 AddDefaultCC(AddDefaultPred(
271 BuildMI(MBB, MBBI, DL, TII.get(ARM::MOVsi), Reg)
272 .addReg(Reg, RegState::Kill)
273 .addImm(ARM_AM::getSORegOpc(ARM_AM::lsr, NrBitsToZero))));
274 AddDefaultCC(AddDefaultPred(
275 BuildMI(MBB, MBBI, DL, TII.get(ARM::MOVsi), Reg)
276 .addReg(Reg, RegState::Kill)
277 .addImm(ARM_AM::getSORegOpc(ARM_AM::lsl, NrBitsToZero))));
280 // Since this is only reached for Thumb-2 targets, the BFC instruction
281 // should always be available.
283 AddDefaultPred(BuildMI(MBB, MBBI, DL, TII.get(ARM::t2BFC), Reg)
284 .addReg(Reg, RegState::Kill)
285 .addImm(~AlignMask));
289 void ARMFrameLowering::emitPrologue(MachineFunction &MF,
290 MachineBasicBlock &MBB) const {
291 MachineBasicBlock::iterator MBBI = MBB.begin();
292 MachineFrameInfo *MFI = MF.getFrameInfo();
293 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
294 MachineModuleInfo &MMI = MF.getMMI();
295 MCContext &Context = MMI.getContext();
296 const TargetMachine &TM = MF.getTarget();
297 const MCRegisterInfo *MRI = Context.getRegisterInfo();
298 const ARMBaseRegisterInfo *RegInfo = STI.getRegisterInfo();
299 const ARMBaseInstrInfo &TII = *STI.getInstrInfo();
300 assert(!AFI->isThumb1OnlyFunction() &&
301 "This emitPrologue does not support Thumb1!");
302 bool isARM = !AFI->isThumbFunction();
303 unsigned Align = STI.getFrameLowering()->getStackAlignment();
304 unsigned ArgRegsSaveSize = AFI->getArgRegsSaveSize();
305 unsigned NumBytes = MFI->getStackSize();
306 const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
307 DebugLoc dl = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
308 unsigned FramePtr = RegInfo->getFrameRegister(MF);
310 // Determine the sizes of each callee-save spill areas and record which frame
311 // belongs to which callee-save spill areas.
312 unsigned GPRCS1Size = 0, GPRCS2Size = 0, DPRCSSize = 0;
313 int FramePtrSpillFI = 0;
316 // All calls are tail calls in GHC calling conv, and functions have no
317 // prologue/epilogue.
318 if (MF.getFunction()->getCallingConv() == CallingConv::GHC)
321 StackAdjustingInsts DefCFAOffsetCandidates;
322 bool HasFP = hasFP(MF);
324 // Allocate the vararg register save area.
325 if (ArgRegsSaveSize) {
326 emitSPUpdate(isARM, MBB, MBBI, dl, TII, -ArgRegsSaveSize,
327 MachineInstr::FrameSetup);
328 DefCFAOffsetCandidates.addInst(std::prev(MBBI), ArgRegsSaveSize, true);
331 if (!AFI->hasStackFrame() &&
332 (!STI.isTargetWindows() || !WindowsRequiresStackProbe(MF, NumBytes))) {
333 if (NumBytes - ArgRegsSaveSize != 0) {
334 emitSPUpdate(isARM, MBB, MBBI, dl, TII, -(NumBytes - ArgRegsSaveSize),
335 MachineInstr::FrameSetup);
336 DefCFAOffsetCandidates.addInst(std::prev(MBBI),
337 NumBytes - ArgRegsSaveSize, true);
339 DefCFAOffsetCandidates.emitDefCFAOffsets(MMI, MBB, dl, TII, HasFP);
343 // Determine spill area sizes.
344 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
345 unsigned Reg = CSI[i].getReg();
346 int FI = CSI[i].getFrameIdx();
353 if (STI.isTargetDarwin()) {
368 FramePtrSpillFI = FI;
372 // This is a DPR. Exclude the aligned DPRCS2 spills.
375 if (Reg < ARM::D8 || Reg >= ARM::D8 + AFI->getNumAlignedDPRCS2Regs())
381 MachineBasicBlock::iterator LastPush = MBB.end(), GPRCS1Push, GPRCS2Push;
382 if (GPRCS1Size > 0) {
383 GPRCS1Push = LastPush = MBBI++;
384 DefCFAOffsetCandidates.addInst(LastPush, GPRCS1Size, true);
387 // Determine starting offsets of spill areas.
388 unsigned GPRCS1Offset = NumBytes - ArgRegsSaveSize - GPRCS1Size;
389 unsigned GPRCS2Offset = GPRCS1Offset - GPRCS2Size;
390 unsigned DPRAlign = DPRCSSize ? std::min(8U, Align) : 4U;
391 unsigned DPRGapSize = (GPRCS1Size + GPRCS2Size + ArgRegsSaveSize) % DPRAlign;
392 unsigned DPRCSOffset = GPRCS2Offset - DPRGapSize - DPRCSSize;
393 int FramePtrOffsetInPush = 0;
395 FramePtrOffsetInPush =
396 MFI->getObjectOffset(FramePtrSpillFI) + ArgRegsSaveSize;
397 AFI->setFramePtrSpillOffset(MFI->getObjectOffset(FramePtrSpillFI) +
400 AFI->setGPRCalleeSavedArea1Offset(GPRCS1Offset);
401 AFI->setGPRCalleeSavedArea2Offset(GPRCS2Offset);
402 AFI->setDPRCalleeSavedAreaOffset(DPRCSOffset);
405 if (GPRCS2Size > 0) {
406 GPRCS2Push = LastPush = MBBI++;
407 DefCFAOffsetCandidates.addInst(LastPush, GPRCS2Size);
410 // Prolog/epilog inserter assumes we correctly align DPRs on the stack, so our
411 // .cfi_offset operations will reflect that.
413 assert(DPRGapSize == 4 && "unexpected alignment requirements for DPRs");
414 if (tryFoldSPUpdateIntoPushPop(STI, MF, LastPush, DPRGapSize))
415 DefCFAOffsetCandidates.addExtraBytes(LastPush, DPRGapSize);
417 emitSPUpdate(isARM, MBB, MBBI, dl, TII, -DPRGapSize,
418 MachineInstr::FrameSetup);
419 DefCFAOffsetCandidates.addInst(std::prev(MBBI), DPRGapSize);
425 // Since vpush register list cannot have gaps, there may be multiple vpush
426 // instructions in the prologue.
427 while (MBBI->getOpcode() == ARM::VSTMDDB_UPD) {
428 DefCFAOffsetCandidates.addInst(MBBI, sizeOfSPAdjustment(MBBI));
433 // Move past the aligned DPRCS2 area.
434 if (AFI->getNumAlignedDPRCS2Regs() > 0) {
435 MBBI = skipAlignedDPRCS2Spills(MBBI, AFI->getNumAlignedDPRCS2Regs());
436 // The code inserted by emitAlignedDPRCS2Spills realigns the stack, and
437 // leaves the stack pointer pointing to the DPRCS2 area.
439 // Adjust NumBytes to represent the stack slots below the DPRCS2 area.
440 NumBytes += MFI->getObjectOffset(D8SpillFI);
442 NumBytes = DPRCSOffset;
444 if (STI.isTargetWindows() && WindowsRequiresStackProbe(MF, NumBytes)) {
445 uint32_t NumWords = NumBytes >> 2;
447 if (NumWords < 65536)
448 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::t2MOVi16), ARM::R4)
450 .setMIFlags(MachineInstr::FrameSetup));
452 BuildMI(MBB, MBBI, dl, TII.get(ARM::t2MOVi32imm), ARM::R4)
454 .setMIFlags(MachineInstr::FrameSetup);
456 switch (TM.getCodeModel()) {
457 case CodeModel::Small:
458 case CodeModel::Medium:
459 case CodeModel::Default:
460 case CodeModel::Kernel:
461 BuildMI(MBB, MBBI, dl, TII.get(ARM::tBL))
462 .addImm((unsigned)ARMCC::AL).addReg(0)
463 .addExternalSymbol("__chkstk")
464 .addReg(ARM::R4, RegState::Implicit)
465 .setMIFlags(MachineInstr::FrameSetup);
467 case CodeModel::Large:
468 case CodeModel::JITDefault:
469 BuildMI(MBB, MBBI, dl, TII.get(ARM::t2MOVi32imm), ARM::R12)
470 .addExternalSymbol("__chkstk")
471 .setMIFlags(MachineInstr::FrameSetup);
473 BuildMI(MBB, MBBI, dl, TII.get(ARM::tBLXr))
474 .addImm((unsigned)ARMCC::AL).addReg(0)
475 .addReg(ARM::R12, RegState::Kill)
476 .addReg(ARM::R4, RegState::Implicit)
477 .setMIFlags(MachineInstr::FrameSetup);
481 AddDefaultCC(AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::t2SUBrr),
483 .addReg(ARM::SP, RegState::Define)
484 .addReg(ARM::R4, RegState::Kill)
485 .setMIFlags(MachineInstr::FrameSetup)));
490 // Adjust SP after all the callee-save spills.
491 if (AFI->getNumAlignedDPRCS2Regs() == 0 &&
492 tryFoldSPUpdateIntoPushPop(STI, MF, LastPush, NumBytes))
493 DefCFAOffsetCandidates.addExtraBytes(LastPush, NumBytes);
495 emitSPUpdate(isARM, MBB, MBBI, dl, TII, -NumBytes,
496 MachineInstr::FrameSetup);
497 DefCFAOffsetCandidates.addInst(std::prev(MBBI), NumBytes);
501 // Restore from fp only in ARM mode: e.g. sub sp, r7, #24
502 // Note it's not safe to do this in Thumb2 mode because it would have
503 // taken two instructions:
506 // If an interrupt is taken between the two instructions, then sp is in
507 // an inconsistent state (pointing to the middle of callee-saved area).
508 // The interrupt handler can end up clobbering the registers.
509 AFI->setShouldRestoreSPFromFP(true);
512 // Set FP to point to the stack slot that contains the previous FP.
513 // For iOS, FP is R7, which has now been stored in spill area 1.
514 // Otherwise, if this is not iOS, all the callee-saved registers go
515 // into spill area 1, including the FP in R11. In either case, it
516 // is in area one and the adjustment needs to take place just after
519 MachineBasicBlock::iterator AfterPush = std::next(GPRCS1Push);
520 unsigned PushSize = sizeOfSPAdjustment(GPRCS1Push);
521 emitRegPlusImmediate(!AFI->isThumbFunction(), MBB, AfterPush,
522 dl, TII, FramePtr, ARM::SP,
523 PushSize + FramePtrOffsetInPush,
524 MachineInstr::FrameSetup);
525 if (FramePtrOffsetInPush + PushSize != 0) {
526 unsigned CFIIndex = MMI.addFrameInst(MCCFIInstruction::createDefCfa(
527 nullptr, MRI->getDwarfRegNum(FramePtr, true),
528 -(ArgRegsSaveSize - FramePtrOffsetInPush)));
529 BuildMI(MBB, AfterPush, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
530 .addCFIIndex(CFIIndex)
531 .setMIFlags(MachineInstr::FrameSetup);
534 MMI.addFrameInst(MCCFIInstruction::createDefCfaRegister(
535 nullptr, MRI->getDwarfRegNum(FramePtr, true)));
536 BuildMI(MBB, AfterPush, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
537 .addCFIIndex(CFIIndex)
538 .setMIFlags(MachineInstr::FrameSetup);
542 // Now that the prologue's actual instructions are finalised, we can insert
543 // the necessary DWARF cf instructions to describe the situation. Start by
544 // recording where each register ended up:
545 if (GPRCS1Size > 0) {
546 MachineBasicBlock::iterator Pos = std::next(GPRCS1Push);
548 for (const auto &Entry : CSI) {
549 unsigned Reg = Entry.getReg();
550 int FI = Entry.getFrameIdx();
557 if (STI.isTargetDarwin())
569 CFIIndex = MMI.addFrameInst(MCCFIInstruction::createOffset(
570 nullptr, MRI->getDwarfRegNum(Reg, true), MFI->getObjectOffset(FI)));
571 BuildMI(MBB, Pos, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
572 .addCFIIndex(CFIIndex)
573 .setMIFlags(MachineInstr::FrameSetup);
579 if (GPRCS2Size > 0) {
580 MachineBasicBlock::iterator Pos = std::next(GPRCS2Push);
581 for (const auto &Entry : CSI) {
582 unsigned Reg = Entry.getReg();
583 int FI = Entry.getFrameIdx();
590 if (STI.isTargetDarwin()) {
591 unsigned DwarfReg = MRI->getDwarfRegNum(Reg, true);
592 unsigned Offset = MFI->getObjectOffset(FI);
593 unsigned CFIIndex = MMI.addFrameInst(
594 MCCFIInstruction::createOffset(nullptr, DwarfReg, Offset));
595 BuildMI(MBB, Pos, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
596 .addCFIIndex(CFIIndex)
597 .setMIFlags(MachineInstr::FrameSetup);
605 // Since vpush register list cannot have gaps, there may be multiple vpush
606 // instructions in the prologue.
607 MachineBasicBlock::iterator Pos = std::next(LastPush);
608 for (const auto &Entry : CSI) {
609 unsigned Reg = Entry.getReg();
610 int FI = Entry.getFrameIdx();
611 if ((Reg >= ARM::D0 && Reg <= ARM::D31) &&
612 (Reg < ARM::D8 || Reg >= ARM::D8 + AFI->getNumAlignedDPRCS2Regs())) {
613 unsigned DwarfReg = MRI->getDwarfRegNum(Reg, true);
614 unsigned Offset = MFI->getObjectOffset(FI);
615 unsigned CFIIndex = MMI.addFrameInst(
616 MCCFIInstruction::createOffset(nullptr, DwarfReg, Offset));
617 BuildMI(MBB, Pos, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
618 .addCFIIndex(CFIIndex)
619 .setMIFlags(MachineInstr::FrameSetup);
624 // Now we can emit descriptions of where the canonical frame address was
625 // throughout the process. If we have a frame pointer, it takes over the job
626 // half-way through, so only the first few .cfi_def_cfa_offset instructions
627 // actually get emitted.
628 DefCFAOffsetCandidates.emitDefCFAOffsets(MMI, MBB, dl, TII, HasFP);
630 if (STI.isTargetELF() && hasFP(MF))
631 MFI->setOffsetAdjustment(MFI->getOffsetAdjustment() -
632 AFI->getFramePtrSpillOffset());
634 AFI->setGPRCalleeSavedArea1Size(GPRCS1Size);
635 AFI->setGPRCalleeSavedArea2Size(GPRCS2Size);
636 AFI->setDPRCalleeSavedGapSize(DPRGapSize);
637 AFI->setDPRCalleeSavedAreaSize(DPRCSSize);
639 // If we need dynamic stack realignment, do it here. Be paranoid and make
640 // sure if we also have VLAs, we have a base pointer for frame access.
641 // If aligned NEON registers were spilled, the stack has already been
643 if (!AFI->getNumAlignedDPRCS2Regs() && RegInfo->needsStackRealignment(MF)) {
644 unsigned MaxAlign = MFI->getMaxAlignment();
645 assert(!AFI->isThumb1OnlyFunction());
646 if (!AFI->isThumbFunction()) {
647 emitAligningInstructions(MF, AFI, TII, MBB, MBBI, dl, ARM::SP, MaxAlign,
650 // We cannot use sp as source/dest register here, thus we're using r4 to
651 // perform the calculations. We're emitting the following sequence:
653 // -- use emitAligningInstructions to produce best sequence to zero
654 // -- out lower bits in r4
656 // FIXME: It will be better just to find spare register here.
657 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), ARM::R4)
658 .addReg(ARM::SP, RegState::Kill));
659 emitAligningInstructions(MF, AFI, TII, MBB, MBBI, dl, ARM::R4, MaxAlign,
661 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), ARM::SP)
662 .addReg(ARM::R4, RegState::Kill));
665 AFI->setShouldRestoreSPFromFP(true);
668 // If we need a base pointer, set it up here. It's whatever the value
669 // of the stack pointer is at this point. Any variable size objects
670 // will be allocated after this, so we can still use the base pointer
671 // to reference locals.
672 // FIXME: Clarify FrameSetup flags here.
673 if (RegInfo->hasBasePointer(MF)) {
675 BuildMI(MBB, MBBI, dl,
676 TII.get(ARM::MOVr), RegInfo->getBaseRegister())
678 .addImm((unsigned)ARMCC::AL).addReg(0).addReg(0);
680 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr),
681 RegInfo->getBaseRegister())
685 // If the frame has variable sized objects then the epilogue must restore
686 // the sp from fp. We can assume there's an FP here since hasFP already
687 // checks for hasVarSizedObjects.
688 if (MFI->hasVarSizedObjects())
689 AFI->setShouldRestoreSPFromFP(true);
692 void ARMFrameLowering::emitEpilogue(MachineFunction &MF,
693 MachineBasicBlock &MBB) const {
694 MachineFrameInfo *MFI = MF.getFrameInfo();
695 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
696 const TargetRegisterInfo *RegInfo = MF.getSubtarget().getRegisterInfo();
697 const ARMBaseInstrInfo &TII =
698 *static_cast<const ARMBaseInstrInfo *>(MF.getSubtarget().getInstrInfo());
699 assert(!AFI->isThumb1OnlyFunction() &&
700 "This emitEpilogue does not support Thumb1!");
701 bool isARM = !AFI->isThumbFunction();
703 unsigned ArgRegsSaveSize = AFI->getArgRegsSaveSize();
704 int NumBytes = (int)MFI->getStackSize();
705 unsigned FramePtr = RegInfo->getFrameRegister(MF);
707 // All calls are tail calls in GHC calling conv, and functions have no
708 // prologue/epilogue.
709 if (MF.getFunction()->getCallingConv() == CallingConv::GHC)
712 // First put ourselves on the first (from top) terminator instructions.
713 MachineBasicBlock::iterator MBBI = MBB.getFirstTerminator();
714 DebugLoc dl = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
716 if (!AFI->hasStackFrame()) {
717 if (NumBytes - ArgRegsSaveSize != 0)
718 emitSPUpdate(isARM, MBB, MBBI, dl, TII, NumBytes - ArgRegsSaveSize);
720 // Unwind MBBI to point to first LDR / VLDRD.
721 const MCPhysReg *CSRegs = RegInfo->getCalleeSavedRegs(&MF);
722 if (MBBI != MBB.begin()) {
725 } while (MBBI != MBB.begin() && isCSRestore(MBBI, TII, CSRegs));
726 if (!isCSRestore(MBBI, TII, CSRegs))
730 // Move SP to start of FP callee save spill area.
731 NumBytes -= (ArgRegsSaveSize +
732 AFI->getGPRCalleeSavedArea1Size() +
733 AFI->getGPRCalleeSavedArea2Size() +
734 AFI->getDPRCalleeSavedGapSize() +
735 AFI->getDPRCalleeSavedAreaSize());
737 // Reset SP based on frame pointer only if the stack frame extends beyond
738 // frame pointer stack slot or target is ELF and the function has FP.
739 if (AFI->shouldRestoreSPFromFP()) {
740 NumBytes = AFI->getFramePtrSpillOffset() - NumBytes;
743 emitARMRegPlusImmediate(MBB, MBBI, dl, ARM::SP, FramePtr, -NumBytes,
746 // It's not possible to restore SP from FP in a single instruction.
747 // For iOS, this looks like:
750 // This is bad, if an interrupt is taken after the mov, sp is in an
751 // inconsistent state.
752 // Use the first callee-saved register as a scratch register.
753 assert(!MFI->getPristineRegs(MF).test(ARM::R4) &&
754 "No scratch register to restore SP from FP!");
755 emitT2RegPlusImmediate(MBB, MBBI, dl, ARM::R4, FramePtr, -NumBytes,
757 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr),
764 BuildMI(MBB, MBBI, dl, TII.get(ARM::MOVr), ARM::SP)
765 .addReg(FramePtr).addImm((unsigned)ARMCC::AL).addReg(0).addReg(0);
767 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr),
771 } else if (NumBytes &&
772 !tryFoldSPUpdateIntoPushPop(STI, MF, MBBI, NumBytes))
773 emitSPUpdate(isARM, MBB, MBBI, dl, TII, NumBytes);
775 // Increment past our save areas.
776 if (AFI->getDPRCalleeSavedAreaSize()) {
778 // Since vpop register list cannot have gaps, there may be multiple vpop
779 // instructions in the epilogue.
780 while (MBBI->getOpcode() == ARM::VLDMDIA_UPD)
783 if (AFI->getDPRCalleeSavedGapSize()) {
784 assert(AFI->getDPRCalleeSavedGapSize() == 4 &&
785 "unexpected DPR alignment gap");
786 emitSPUpdate(isARM, MBB, MBBI, dl, TII, AFI->getDPRCalleeSavedGapSize());
789 if (AFI->getGPRCalleeSavedArea2Size()) MBBI++;
790 if (AFI->getGPRCalleeSavedArea1Size()) MBBI++;
794 emitSPUpdate(isARM, MBB, MBBI, dl, TII, ArgRegsSaveSize);
797 /// getFrameIndexReference - Provide a base+offset reference to an FI slot for
798 /// debug info. It's the same as what we use for resolving the code-gen
799 /// references for now. FIXME: This can go wrong when references are
800 /// SP-relative and simple call frames aren't used.
802 ARMFrameLowering::getFrameIndexReference(const MachineFunction &MF, int FI,
803 unsigned &FrameReg) const {
804 return ResolveFrameIndexReference(MF, FI, FrameReg, 0);
808 ARMFrameLowering::ResolveFrameIndexReference(const MachineFunction &MF,
809 int FI, unsigned &FrameReg,
811 const MachineFrameInfo *MFI = MF.getFrameInfo();
812 const ARMBaseRegisterInfo *RegInfo = static_cast<const ARMBaseRegisterInfo *>(
813 MF.getSubtarget().getRegisterInfo());
814 const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
815 int Offset = MFI->getObjectOffset(FI) + MFI->getStackSize();
816 int FPOffset = Offset - AFI->getFramePtrSpillOffset();
817 bool isFixed = MFI->isFixedObjectIndex(FI);
822 // SP can move around if there are allocas. We may also lose track of SP
823 // when emergency spilling inside a non-reserved call frame setup.
824 bool hasMovingSP = !hasReservedCallFrame(MF);
826 // When dynamically realigning the stack, use the frame pointer for
827 // parameters, and the stack/base pointer for locals.
828 if (RegInfo->needsStackRealignment(MF)) {
829 assert (hasFP(MF) && "dynamic stack realignment without a FP!");
831 FrameReg = RegInfo->getFrameRegister(MF);
833 } else if (hasMovingSP) {
834 assert(RegInfo->hasBasePointer(MF) &&
835 "VLAs and dynamic stack alignment, but missing base pointer!");
836 FrameReg = RegInfo->getBaseRegister();
841 // If there is a frame pointer, use it when we can.
842 if (hasFP(MF) && AFI->hasStackFrame()) {
843 // Use frame pointer to reference fixed objects. Use it for locals if
844 // there are VLAs (and thus the SP isn't reliable as a base).
845 if (isFixed || (hasMovingSP && !RegInfo->hasBasePointer(MF))) {
846 FrameReg = RegInfo->getFrameRegister(MF);
848 } else if (hasMovingSP) {
849 assert(RegInfo->hasBasePointer(MF) && "missing base pointer!");
850 if (AFI->isThumb2Function()) {
851 // Try to use the frame pointer if we can, else use the base pointer
852 // since it's available. This is handy for the emergency spill slot, in
854 if (FPOffset >= -255 && FPOffset < 0) {
855 FrameReg = RegInfo->getFrameRegister(MF);
859 } else if (AFI->isThumb2Function()) {
860 // Use add <rd>, sp, #<imm8>
861 // ldr <rd>, [sp, #<imm8>]
862 // if at all possible to save space.
863 if (Offset >= 0 && (Offset & 3) == 0 && Offset <= 1020)
865 // In Thumb2 mode, the negative offset is very limited. Try to avoid
866 // out of range references. ldr <rt>,[<rn>, #-<imm8>]
867 if (FPOffset >= -255 && FPOffset < 0) {
868 FrameReg = RegInfo->getFrameRegister(MF);
871 } else if (Offset > (FPOffset < 0 ? -FPOffset : FPOffset)) {
872 // Otherwise, use SP or FP, whichever is closer to the stack slot.
873 FrameReg = RegInfo->getFrameRegister(MF);
877 // Use the base pointer if we have one.
878 if (RegInfo->hasBasePointer(MF))
879 FrameReg = RegInfo->getBaseRegister();
883 void ARMFrameLowering::emitPushInst(MachineBasicBlock &MBB,
884 MachineBasicBlock::iterator MI,
885 const std::vector<CalleeSavedInfo> &CSI,
886 unsigned StmOpc, unsigned StrOpc,
888 bool(*Func)(unsigned, bool),
889 unsigned NumAlignedDPRCS2Regs,
890 unsigned MIFlags) const {
891 MachineFunction &MF = *MBB.getParent();
892 const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
895 if (MI != MBB.end()) DL = MI->getDebugLoc();
897 SmallVector<std::pair<unsigned,bool>, 4> Regs;
898 unsigned i = CSI.size();
900 unsigned LastReg = 0;
901 for (; i != 0; --i) {
902 unsigned Reg = CSI[i-1].getReg();
903 if (!(Func)(Reg, STI.isTargetDarwin())) continue;
905 // D-registers in the aligned area DPRCS2 are NOT spilled here.
906 if (Reg >= ARM::D8 && Reg < ARM::D8 + NumAlignedDPRCS2Regs)
909 // Add the callee-saved register as live-in unless it's LR and
910 // @llvm.returnaddress is called. If LR is returned for
911 // @llvm.returnaddress then it's already added to the function and
912 // entry block live-in sets.
914 if (Reg == ARM::LR) {
915 if (MF.getFrameInfo()->isReturnAddressTaken() &&
916 MF.getRegInfo().isLiveIn(Reg))
923 // If NoGap is true, push consecutive registers and then leave the rest
924 // for other instructions. e.g.
925 // vpush {d8, d10, d11} -> vpush {d8}, vpush {d10, d11}
926 if (NoGap && LastReg && LastReg != Reg-1)
929 Regs.push_back(std::make_pair(Reg, isKill));
934 if (Regs.size() > 1 || StrOpc== 0) {
935 MachineInstrBuilder MIB =
936 AddDefaultPred(BuildMI(MBB, MI, DL, TII.get(StmOpc), ARM::SP)
937 .addReg(ARM::SP).setMIFlags(MIFlags));
938 for (unsigned i = 0, e = Regs.size(); i < e; ++i)
939 MIB.addReg(Regs[i].first, getKillRegState(Regs[i].second));
940 } else if (Regs.size() == 1) {
941 MachineInstrBuilder MIB = BuildMI(MBB, MI, DL, TII.get(StrOpc),
943 .addReg(Regs[0].first, getKillRegState(Regs[0].second))
944 .addReg(ARM::SP).setMIFlags(MIFlags)
950 // Put any subsequent vpush instructions before this one: they will refer to
951 // higher register numbers so need to be pushed first in order to preserve
953 if (MI != MBB.begin())
958 void ARMFrameLowering::emitPopInst(MachineBasicBlock &MBB,
959 MachineBasicBlock::iterator MI,
960 const std::vector<CalleeSavedInfo> &CSI,
961 unsigned LdmOpc, unsigned LdrOpc,
962 bool isVarArg, bool NoGap,
963 bool(*Func)(unsigned, bool),
964 unsigned NumAlignedDPRCS2Regs) const {
965 MachineFunction &MF = *MBB.getParent();
966 const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
967 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
969 bool isTailCall = false;
970 bool isInterrupt = false;
971 if (MBB.end() != MI) {
972 DL = MI->getDebugLoc();
973 unsigned RetOpcode = MI->getOpcode();
974 isTailCall = (RetOpcode == ARM::TCRETURNdi || RetOpcode == ARM::TCRETURNri);
976 RetOpcode == ARM::SUBS_PC_LR || RetOpcode == ARM::t2SUBS_PC_LR;
979 SmallVector<unsigned, 4> Regs;
980 unsigned i = CSI.size();
982 unsigned LastReg = 0;
983 bool DeleteRet = false;
984 for (; i != 0; --i) {
985 unsigned Reg = CSI[i-1].getReg();
986 if (!(Func)(Reg, STI.isTargetDarwin())) continue;
988 // The aligned reloads from area DPRCS2 are not inserted here.
989 if (Reg >= ARM::D8 && Reg < ARM::D8 + NumAlignedDPRCS2Regs)
992 if (Reg == ARM::LR && !isTailCall && !isVarArg && !isInterrupt &&
994 if (MBB.succ_empty()) {
997 LdmOpc = AFI->isThumbFunction() ? ARM::t2LDMIA_RET : ARM::LDMIA_RET;
999 LdmOpc = AFI->isThumbFunction() ? ARM::t2LDMIA_UPD : ARM::LDMIA_UPD;
1000 // Fold the return instruction into the LDM.
1003 // If NoGap is true, pop consecutive registers and then leave the rest
1004 // for other instructions. e.g.
1005 // vpop {d8, d10, d11} -> vpop {d8}, vpop {d10, d11}
1006 if (NoGap && LastReg && LastReg != Reg-1)
1010 Regs.push_back(Reg);
1015 if (Regs.size() > 1 || LdrOpc == 0) {
1016 MachineInstrBuilder MIB =
1017 AddDefaultPred(BuildMI(MBB, MI, DL, TII.get(LdmOpc), ARM::SP)
1019 for (unsigned i = 0, e = Regs.size(); i < e; ++i)
1020 MIB.addReg(Regs[i], getDefRegState(true));
1021 if (DeleteRet && MI != MBB.end()) {
1022 MIB.copyImplicitOps(&*MI);
1023 MI->eraseFromParent();
1026 } else if (Regs.size() == 1) {
1027 // If we adjusted the reg to PC from LR above, switch it back here. We
1028 // only do that for LDM.
1029 if (Regs[0] == ARM::PC)
1031 MachineInstrBuilder MIB =
1032 BuildMI(MBB, MI, DL, TII.get(LdrOpc), Regs[0])
1033 .addReg(ARM::SP, RegState::Define)
1035 // ARM mode needs an extra reg0 here due to addrmode2. Will go away once
1036 // that refactoring is complete (eventually).
1037 if (LdrOpc == ARM::LDR_POST_REG || LdrOpc == ARM::LDR_POST_IMM) {
1039 MIB.addImm(ARM_AM::getAM2Opc(ARM_AM::add, 4, ARM_AM::no_shift));
1042 AddDefaultPred(MIB);
1046 // Put any subsequent vpop instructions after this one: they will refer to
1047 // higher register numbers so need to be popped afterwards.
1048 if (MI != MBB.end())
1053 /// Emit aligned spill instructions for NumAlignedDPRCS2Regs D-registers
1054 /// starting from d8. Also insert stack realignment code and leave the stack
1055 /// pointer pointing to the d8 spill slot.
1056 static void emitAlignedDPRCS2Spills(MachineBasicBlock &MBB,
1057 MachineBasicBlock::iterator MI,
1058 unsigned NumAlignedDPRCS2Regs,
1059 const std::vector<CalleeSavedInfo> &CSI,
1060 const TargetRegisterInfo *TRI) {
1061 MachineFunction &MF = *MBB.getParent();
1062 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1063 DebugLoc DL = MI != MBB.end() ? MI->getDebugLoc() : DebugLoc();
1064 const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
1065 MachineFrameInfo &MFI = *MF.getFrameInfo();
1067 // Mark the D-register spill slots as properly aligned. Since MFI computes
1068 // stack slot layout backwards, this can actually mean that the d-reg stack
1069 // slot offsets can be wrong. The offset for d8 will always be correct.
1070 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
1071 unsigned DNum = CSI[i].getReg() - ARM::D8;
1074 int FI = CSI[i].getFrameIdx();
1075 // The even-numbered registers will be 16-byte aligned, the odd-numbered
1076 // registers will be 8-byte aligned.
1077 MFI.setObjectAlignment(FI, DNum % 2 ? 8 : 16);
1079 // The stack slot for D8 needs to be maximally aligned because this is
1080 // actually the point where we align the stack pointer. MachineFrameInfo
1081 // computes all offsets relative to the incoming stack pointer which is a
1082 // bit weird when realigning the stack. Any extra padding for this
1083 // over-alignment is not realized because the code inserted below adjusts
1084 // the stack pointer by numregs * 8 before aligning the stack pointer.
1086 MFI.setObjectAlignment(FI, MFI.getMaxAlignment());
1089 // Move the stack pointer to the d8 spill slot, and align it at the same
1090 // time. Leave the stack slot address in the scratch register r4.
1092 // sub r4, sp, #numregs * 8
1093 // bic r4, r4, #align - 1
1096 bool isThumb = AFI->isThumbFunction();
1097 assert(!AFI->isThumb1OnlyFunction() && "Can't realign stack for thumb1");
1098 AFI->setShouldRestoreSPFromFP(true);
1100 // sub r4, sp, #numregs * 8
1101 // The immediate is <= 64, so it doesn't need any special encoding.
1102 unsigned Opc = isThumb ? ARM::t2SUBri : ARM::SUBri;
1103 AddDefaultCC(AddDefaultPred(BuildMI(MBB, MI, DL, TII.get(Opc), ARM::R4)
1105 .addImm(8 * NumAlignedDPRCS2Regs)));
1107 unsigned MaxAlign = MF.getFrameInfo()->getMaxAlignment();
1108 // We must set parameter MustBeSingleInstruction to true, since
1109 // skipAlignedDPRCS2Spills expects exactly 3 instructions to perform
1110 // stack alignment. Luckily, this can always be done since all ARM
1111 // architecture versions that support Neon also support the BFC
1113 emitAligningInstructions(MF, AFI, TII, MBB, MI, DL, ARM::R4, MaxAlign, true);
1116 // The stack pointer must be adjusted before spilling anything, otherwise
1117 // the stack slots could be clobbered by an interrupt handler.
1118 // Leave r4 live, it is used below.
1119 Opc = isThumb ? ARM::tMOVr : ARM::MOVr;
1120 MachineInstrBuilder MIB = BuildMI(MBB, MI, DL, TII.get(Opc), ARM::SP)
1122 MIB = AddDefaultPred(MIB);
1126 // Now spill NumAlignedDPRCS2Regs registers starting from d8.
1127 // r4 holds the stack slot address.
1128 unsigned NextReg = ARM::D8;
1130 // 16-byte aligned vst1.64 with 4 d-regs and address writeback.
1131 // The writeback is only needed when emitting two vst1.64 instructions.
1132 if (NumAlignedDPRCS2Regs >= 6) {
1133 unsigned SupReg = TRI->getMatchingSuperReg(NextReg, ARM::dsub_0,
1134 &ARM::QQPRRegClass);
1135 MBB.addLiveIn(SupReg);
1136 AddDefaultPred(BuildMI(MBB, MI, DL, TII.get(ARM::VST1d64Qwb_fixed),
1138 .addReg(ARM::R4, RegState::Kill).addImm(16)
1140 .addReg(SupReg, RegState::ImplicitKill));
1142 NumAlignedDPRCS2Regs -= 4;
1145 // We won't modify r4 beyond this point. It currently points to the next
1146 // register to be spilled.
1147 unsigned R4BaseReg = NextReg;
1149 // 16-byte aligned vst1.64 with 4 d-regs, no writeback.
1150 if (NumAlignedDPRCS2Regs >= 4) {
1151 unsigned SupReg = TRI->getMatchingSuperReg(NextReg, ARM::dsub_0,
1152 &ARM::QQPRRegClass);
1153 MBB.addLiveIn(SupReg);
1154 AddDefaultPred(BuildMI(MBB, MI, DL, TII.get(ARM::VST1d64Q))
1155 .addReg(ARM::R4).addImm(16).addReg(NextReg)
1156 .addReg(SupReg, RegState::ImplicitKill));
1158 NumAlignedDPRCS2Regs -= 4;
1161 // 16-byte aligned vst1.64 with 2 d-regs.
1162 if (NumAlignedDPRCS2Regs >= 2) {
1163 unsigned SupReg = TRI->getMatchingSuperReg(NextReg, ARM::dsub_0,
1165 MBB.addLiveIn(SupReg);
1166 AddDefaultPred(BuildMI(MBB, MI, DL, TII.get(ARM::VST1q64))
1167 .addReg(ARM::R4).addImm(16).addReg(SupReg));
1169 NumAlignedDPRCS2Regs -= 2;
1172 // Finally, use a vanilla vstr.64 for the odd last register.
1173 if (NumAlignedDPRCS2Regs) {
1174 MBB.addLiveIn(NextReg);
1175 // vstr.64 uses addrmode5 which has an offset scale of 4.
1176 AddDefaultPred(BuildMI(MBB, MI, DL, TII.get(ARM::VSTRD))
1178 .addReg(ARM::R4).addImm((NextReg-R4BaseReg)*2));
1181 // The last spill instruction inserted should kill the scratch register r4.
1182 std::prev(MI)->addRegisterKilled(ARM::R4, TRI);
1185 /// Skip past the code inserted by emitAlignedDPRCS2Spills, and return an
1186 /// iterator to the following instruction.
1187 static MachineBasicBlock::iterator
1188 skipAlignedDPRCS2Spills(MachineBasicBlock::iterator MI,
1189 unsigned NumAlignedDPRCS2Regs) {
1190 // sub r4, sp, #numregs * 8
1191 // bic r4, r4, #align - 1
1194 assert(MI->mayStore() && "Expecting spill instruction");
1196 // These switches all fall through.
1197 switch(NumAlignedDPRCS2Regs) {
1200 assert(MI->mayStore() && "Expecting spill instruction");
1203 assert(MI->mayStore() && "Expecting spill instruction");
1207 assert(MI->killsRegister(ARM::R4) && "Missed kill flag");
1213 /// Emit aligned reload instructions for NumAlignedDPRCS2Regs D-registers
1214 /// starting from d8. These instructions are assumed to execute while the
1215 /// stack is still aligned, unlike the code inserted by emitPopInst.
1216 static void emitAlignedDPRCS2Restores(MachineBasicBlock &MBB,
1217 MachineBasicBlock::iterator MI,
1218 unsigned NumAlignedDPRCS2Regs,
1219 const std::vector<CalleeSavedInfo> &CSI,
1220 const TargetRegisterInfo *TRI) {
1221 MachineFunction &MF = *MBB.getParent();
1222 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1223 DebugLoc DL = MI != MBB.end() ? MI->getDebugLoc() : DebugLoc();
1224 const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
1226 // Find the frame index assigned to d8.
1228 for (unsigned i = 0, e = CSI.size(); i != e; ++i)
1229 if (CSI[i].getReg() == ARM::D8) {
1230 D8SpillFI = CSI[i].getFrameIdx();
1234 // Materialize the address of the d8 spill slot into the scratch register r4.
1235 // This can be fairly complicated if the stack frame is large, so just use
1236 // the normal frame index elimination mechanism to do it. This code runs as
1237 // the initial part of the epilog where the stack and base pointers haven't
1238 // been changed yet.
1239 bool isThumb = AFI->isThumbFunction();
1240 assert(!AFI->isThumb1OnlyFunction() && "Can't realign stack for thumb1");
1242 unsigned Opc = isThumb ? ARM::t2ADDri : ARM::ADDri;
1243 AddDefaultCC(AddDefaultPred(BuildMI(MBB, MI, DL, TII.get(Opc), ARM::R4)
1244 .addFrameIndex(D8SpillFI).addImm(0)));
1246 // Now restore NumAlignedDPRCS2Regs registers starting from d8.
1247 unsigned NextReg = ARM::D8;
1249 // 16-byte aligned vld1.64 with 4 d-regs and writeback.
1250 if (NumAlignedDPRCS2Regs >= 6) {
1251 unsigned SupReg = TRI->getMatchingSuperReg(NextReg, ARM::dsub_0,
1252 &ARM::QQPRRegClass);
1253 AddDefaultPred(BuildMI(MBB, MI, DL, TII.get(ARM::VLD1d64Qwb_fixed), NextReg)
1254 .addReg(ARM::R4, RegState::Define)
1255 .addReg(ARM::R4, RegState::Kill).addImm(16)
1256 .addReg(SupReg, RegState::ImplicitDefine));
1258 NumAlignedDPRCS2Regs -= 4;
1261 // We won't modify r4 beyond this point. It currently points to the next
1262 // register to be spilled.
1263 unsigned R4BaseReg = NextReg;
1265 // 16-byte aligned vld1.64 with 4 d-regs, no writeback.
1266 if (NumAlignedDPRCS2Regs >= 4) {
1267 unsigned SupReg = TRI->getMatchingSuperReg(NextReg, ARM::dsub_0,
1268 &ARM::QQPRRegClass);
1269 AddDefaultPred(BuildMI(MBB, MI, DL, TII.get(ARM::VLD1d64Q), NextReg)
1270 .addReg(ARM::R4).addImm(16)
1271 .addReg(SupReg, RegState::ImplicitDefine));
1273 NumAlignedDPRCS2Regs -= 4;
1276 // 16-byte aligned vld1.64 with 2 d-regs.
1277 if (NumAlignedDPRCS2Regs >= 2) {
1278 unsigned SupReg = TRI->getMatchingSuperReg(NextReg, ARM::dsub_0,
1280 AddDefaultPred(BuildMI(MBB, MI, DL, TII.get(ARM::VLD1q64), SupReg)
1281 .addReg(ARM::R4).addImm(16));
1283 NumAlignedDPRCS2Regs -= 2;
1286 // Finally, use a vanilla vldr.64 for the remaining odd register.
1287 if (NumAlignedDPRCS2Regs)
1288 AddDefaultPred(BuildMI(MBB, MI, DL, TII.get(ARM::VLDRD), NextReg)
1289 .addReg(ARM::R4).addImm(2*(NextReg-R4BaseReg)));
1291 // Last store kills r4.
1292 std::prev(MI)->addRegisterKilled(ARM::R4, TRI);
1295 bool ARMFrameLowering::spillCalleeSavedRegisters(MachineBasicBlock &MBB,
1296 MachineBasicBlock::iterator MI,
1297 const std::vector<CalleeSavedInfo> &CSI,
1298 const TargetRegisterInfo *TRI) const {
1302 MachineFunction &MF = *MBB.getParent();
1303 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1305 unsigned PushOpc = AFI->isThumbFunction() ? ARM::t2STMDB_UPD : ARM::STMDB_UPD;
1306 unsigned PushOneOpc = AFI->isThumbFunction() ?
1307 ARM::t2STR_PRE : ARM::STR_PRE_IMM;
1308 unsigned FltOpc = ARM::VSTMDDB_UPD;
1309 unsigned NumAlignedDPRCS2Regs = AFI->getNumAlignedDPRCS2Regs();
1310 emitPushInst(MBB, MI, CSI, PushOpc, PushOneOpc, false, &isARMArea1Register, 0,
1311 MachineInstr::FrameSetup);
1312 emitPushInst(MBB, MI, CSI, PushOpc, PushOneOpc, false, &isARMArea2Register, 0,
1313 MachineInstr::FrameSetup);
1314 emitPushInst(MBB, MI, CSI, FltOpc, 0, true, &isARMArea3Register,
1315 NumAlignedDPRCS2Regs, MachineInstr::FrameSetup);
1317 // The code above does not insert spill code for the aligned DPRCS2 registers.
1318 // The stack realignment code will be inserted between the push instructions
1319 // and these spills.
1320 if (NumAlignedDPRCS2Regs)
1321 emitAlignedDPRCS2Spills(MBB, MI, NumAlignedDPRCS2Regs, CSI, TRI);
1326 bool ARMFrameLowering::restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
1327 MachineBasicBlock::iterator MI,
1328 const std::vector<CalleeSavedInfo> &CSI,
1329 const TargetRegisterInfo *TRI) const {
1333 MachineFunction &MF = *MBB.getParent();
1334 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1335 bool isVarArg = AFI->getArgRegsSaveSize() > 0;
1336 unsigned NumAlignedDPRCS2Regs = AFI->getNumAlignedDPRCS2Regs();
1338 // The emitPopInst calls below do not insert reloads for the aligned DPRCS2
1339 // registers. Do that here instead.
1340 if (NumAlignedDPRCS2Regs)
1341 emitAlignedDPRCS2Restores(MBB, MI, NumAlignedDPRCS2Regs, CSI, TRI);
1343 unsigned PopOpc = AFI->isThumbFunction() ? ARM::t2LDMIA_UPD : ARM::LDMIA_UPD;
1344 unsigned LdrOpc = AFI->isThumbFunction() ? ARM::t2LDR_POST :ARM::LDR_POST_IMM;
1345 unsigned FltOpc = ARM::VLDMDIA_UPD;
1346 emitPopInst(MBB, MI, CSI, FltOpc, 0, isVarArg, true, &isARMArea3Register,
1347 NumAlignedDPRCS2Regs);
1348 emitPopInst(MBB, MI, CSI, PopOpc, LdrOpc, isVarArg, false,
1349 &isARMArea2Register, 0);
1350 emitPopInst(MBB, MI, CSI, PopOpc, LdrOpc, isVarArg, false,
1351 &isARMArea1Register, 0);
1356 // FIXME: Make generic?
1357 static unsigned GetFunctionSizeInBytes(const MachineFunction &MF,
1358 const ARMBaseInstrInfo &TII) {
1359 unsigned FnSize = 0;
1360 for (auto &MBB : MF) {
1361 for (auto &MI : MBB)
1362 FnSize += TII.GetInstSizeInBytes(&MI);
1367 /// estimateRSStackSizeLimit - Look at each instruction that references stack
1368 /// frames and return the stack size limit beyond which some of these
1369 /// instructions will require a scratch register during their expansion later.
1370 // FIXME: Move to TII?
1371 static unsigned estimateRSStackSizeLimit(MachineFunction &MF,
1372 const TargetFrameLowering *TFI) {
1373 const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1374 unsigned Limit = (1 << 12) - 1;
1375 for (auto &MBB : MF) {
1376 for (auto &MI : MBB) {
1377 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
1378 if (!MI.getOperand(i).isFI())
1381 // When using ADDri to get the address of a stack object, 255 is the
1382 // largest offset guaranteed to fit in the immediate offset.
1383 if (MI.getOpcode() == ARM::ADDri) {
1384 Limit = std::min(Limit, (1U << 8) - 1);
1388 // Otherwise check the addressing mode.
1389 switch (MI.getDesc().TSFlags & ARMII::AddrModeMask) {
1390 case ARMII::AddrMode3:
1391 case ARMII::AddrModeT2_i8:
1392 Limit = std::min(Limit, (1U << 8) - 1);
1394 case ARMII::AddrMode5:
1395 case ARMII::AddrModeT2_i8s4:
1396 Limit = std::min(Limit, ((1U << 8) - 1) * 4);
1398 case ARMII::AddrModeT2_i12:
1399 // i12 supports only positive offset so these will be converted to
1400 // i8 opcodes. See llvm::rewriteT2FrameIndex.
1401 if (TFI->hasFP(MF) && AFI->hasStackFrame())
1402 Limit = std::min(Limit, (1U << 8) - 1);
1404 case ARMII::AddrMode4:
1405 case ARMII::AddrMode6:
1406 // Addressing modes 4 & 6 (load/store) instructions can't encode an
1407 // immediate offset for stack references.
1412 break; // At most one FI per instruction
1420 // In functions that realign the stack, it can be an advantage to spill the
1421 // callee-saved vector registers after realigning the stack. The vst1 and vld1
1422 // instructions take alignment hints that can improve performance.
1425 checkNumAlignedDPRCS2Regs(MachineFunction &MF, BitVector &SavedRegs) {
1426 MF.getInfo<ARMFunctionInfo>()->setNumAlignedDPRCS2Regs(0);
1427 if (!SpillAlignedNEONRegs)
1430 // Naked functions don't spill callee-saved registers.
1431 if (MF.getFunction()->hasFnAttribute(Attribute::Naked))
1434 // We are planning to use NEON instructions vst1 / vld1.
1435 if (!static_cast<const ARMSubtarget &>(MF.getSubtarget()).hasNEON())
1438 // Don't bother if the default stack alignment is sufficiently high.
1439 if (MF.getSubtarget().getFrameLowering()->getStackAlignment() >= 8)
1442 // Aligned spills require stack realignment.
1443 if (!static_cast<const ARMBaseRegisterInfo *>(
1444 MF.getSubtarget().getRegisterInfo())->canRealignStack(MF))
1447 // We always spill contiguous d-registers starting from d8. Count how many
1448 // needs spilling. The register allocator will almost always use the
1449 // callee-saved registers in order, but it can happen that there are holes in
1450 // the range. Registers above the hole will be spilled to the standard DPRCS
1452 unsigned NumSpills = 0;
1453 for (; NumSpills < 8; ++NumSpills)
1454 if (!SavedRegs.test(ARM::D8 + NumSpills))
1457 // Don't do this for just one d-register. It's not worth it.
1461 // Spill the first NumSpills D-registers after realigning the stack.
1462 MF.getInfo<ARMFunctionInfo>()->setNumAlignedDPRCS2Regs(NumSpills);
1464 // A scratch register is required for the vst1 / vld1 instructions.
1465 SavedRegs.set(ARM::R4);
1468 void ARMFrameLowering::determineCalleeSaves(MachineFunction &MF,
1469 BitVector &SavedRegs,
1470 RegScavenger *RS) const {
1471 TargetFrameLowering::determineCalleeSaves(MF, SavedRegs, RS);
1472 // This tells PEI to spill the FP as if it is any other callee-save register
1473 // to take advantage the eliminateFrameIndex machinery. This also ensures it
1474 // is spilled in the order specified by getCalleeSavedRegs() to make it easier
1475 // to combine multiple loads / stores.
1476 bool CanEliminateFrame = true;
1477 bool CS1Spilled = false;
1478 bool LRSpilled = false;
1479 unsigned NumGPRSpills = 0;
1480 SmallVector<unsigned, 4> UnspilledCS1GPRs;
1481 SmallVector<unsigned, 4> UnspilledCS2GPRs;
1482 const ARMBaseRegisterInfo *RegInfo = static_cast<const ARMBaseRegisterInfo *>(
1483 MF.getSubtarget().getRegisterInfo());
1484 const ARMBaseInstrInfo &TII =
1485 *static_cast<const ARMBaseInstrInfo *>(MF.getSubtarget().getInstrInfo());
1486 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1487 MachineFrameInfo *MFI = MF.getFrameInfo();
1488 MachineRegisterInfo &MRI = MF.getRegInfo();
1489 unsigned FramePtr = RegInfo->getFrameRegister(MF);
1491 // Spill R4 if Thumb2 function requires stack realignment - it will be used as
1492 // scratch register. Also spill R4 if Thumb2 function has varsized objects,
1493 // since it's not always possible to restore sp from fp in a single
1495 // FIXME: It will be better just to find spare register here.
1496 if (AFI->isThumb2Function() &&
1497 (MFI->hasVarSizedObjects() || RegInfo->needsStackRealignment(MF)))
1498 SavedRegs.set(ARM::R4);
1500 if (AFI->isThumb1OnlyFunction()) {
1501 // Spill LR if Thumb1 function uses variable length argument lists.
1502 if (AFI->getArgRegsSaveSize() > 0)
1503 SavedRegs.set(ARM::LR);
1505 // Spill R4 if Thumb1 epilogue has to restore SP from FP. We don't know
1506 // for sure what the stack size will be, but for this, an estimate is good
1507 // enough. If there anything changes it, it'll be a spill, which implies
1508 // we've used all the registers and so R4 is already used, so not marking
1509 // it here will be OK.
1510 // FIXME: It will be better just to find spare register here.
1511 unsigned StackSize = MFI->estimateStackSize(MF);
1512 if (MFI->hasVarSizedObjects() || StackSize > 508)
1513 SavedRegs.set(ARM::R4);
1516 // See if we can spill vector registers to aligned stack.
1517 checkNumAlignedDPRCS2Regs(MF, SavedRegs);
1519 // Spill the BasePtr if it's used.
1520 if (RegInfo->hasBasePointer(MF))
1521 SavedRegs.set(RegInfo->getBaseRegister());
1523 // Don't spill FP if the frame can be eliminated. This is determined
1524 // by scanning the callee-save registers to see if any is modified.
1525 const MCPhysReg *CSRegs = RegInfo->getCalleeSavedRegs(&MF);
1526 for (unsigned i = 0; CSRegs[i]; ++i) {
1527 unsigned Reg = CSRegs[i];
1528 bool Spilled = false;
1529 if (SavedRegs.test(Reg)) {
1531 CanEliminateFrame = false;
1534 if (!ARM::GPRRegClass.contains(Reg))
1540 if (!STI.isTargetDarwin()) {
1547 // Keep track if LR and any of R4, R5, R6, and R7 is spilled.
1552 case ARM::R0: case ARM::R1:
1553 case ARM::R2: case ARM::R3:
1554 case ARM::R4: case ARM::R5:
1555 case ARM::R6: case ARM::R7:
1562 if (!STI.isTargetDarwin()) {
1563 UnspilledCS1GPRs.push_back(Reg);
1568 case ARM::R0: case ARM::R1:
1569 case ARM::R2: case ARM::R3:
1570 case ARM::R4: case ARM::R5:
1571 case ARM::R6: case ARM::R7:
1573 UnspilledCS1GPRs.push_back(Reg);
1576 UnspilledCS2GPRs.push_back(Reg);
1582 bool ForceLRSpill = false;
1583 if (!LRSpilled && AFI->isThumb1OnlyFunction()) {
1584 unsigned FnSize = GetFunctionSizeInBytes(MF, TII);
1585 // Force LR to be spilled if the Thumb function size is > 2048. This enables
1586 // use of BL to implement far jump. If it turns out that it's not needed
1587 // then the branch fix up path will undo it.
1588 if (FnSize >= (1 << 11)) {
1589 CanEliminateFrame = false;
1590 ForceLRSpill = true;
1594 // If any of the stack slot references may be out of range of an immediate
1595 // offset, make sure a register (or a spill slot) is available for the
1596 // register scavenger. Note that if we're indexing off the frame pointer, the
1597 // effective stack size is 4 bytes larger since the FP points to the stack
1598 // slot of the previous FP. Also, if we have variable sized objects in the
1599 // function, stack slot references will often be negative, and some of
1600 // our instructions are positive-offset only, so conservatively consider
1601 // that case to want a spill slot (or register) as well. Similarly, if
1602 // the function adjusts the stack pointer during execution and the
1603 // adjustments aren't already part of our stack size estimate, our offset
1604 // calculations may be off, so be conservative.
1605 // FIXME: We could add logic to be more precise about negative offsets
1606 // and which instructions will need a scratch register for them. Is it
1607 // worth the effort and added fragility?
1608 bool BigStack = (RS && (MFI->estimateStackSize(MF) +
1609 ((hasFP(MF) && AFI->hasStackFrame()) ? 4 : 0) >=
1610 estimateRSStackSizeLimit(MF, this))) ||
1611 MFI->hasVarSizedObjects() ||
1612 (MFI->adjustsStack() && !canSimplifyCallFramePseudos(MF));
1614 bool ExtraCSSpill = false;
1615 if (BigStack || !CanEliminateFrame || RegInfo->cannotEliminateFrame(MF)) {
1616 AFI->setHasStackFrame(true);
1618 // If LR is not spilled, but at least one of R4, R5, R6, and R7 is spilled.
1619 // Spill LR as well so we can fold BX_RET to the registers restore (LDM).
1620 if (!LRSpilled && CS1Spilled) {
1621 SavedRegs.set(ARM::LR);
1623 SmallVectorImpl<unsigned>::iterator LRPos;
1624 LRPos = std::find(UnspilledCS1GPRs.begin(), UnspilledCS1GPRs.end(),
1626 if (LRPos != UnspilledCS1GPRs.end())
1627 UnspilledCS1GPRs.erase(LRPos);
1629 ForceLRSpill = false;
1630 ExtraCSSpill = true;
1634 SavedRegs.set(FramePtr);
1635 auto FPPos = std::find(UnspilledCS1GPRs.begin(), UnspilledCS1GPRs.end(),
1637 if (FPPos != UnspilledCS1GPRs.end())
1638 UnspilledCS1GPRs.erase(FPPos);
1642 // If stack and double are 8-byte aligned and we are spilling an odd number
1643 // of GPRs, spill one extra callee save GPR so we won't have to pad between
1644 // the integer and double callee save areas.
1645 unsigned TargetAlign = getStackAlignment();
1646 if (TargetAlign >= 8 && (NumGPRSpills & 1)) {
1647 if (CS1Spilled && !UnspilledCS1GPRs.empty()) {
1648 for (unsigned i = 0, e = UnspilledCS1GPRs.size(); i != e; ++i) {
1649 unsigned Reg = UnspilledCS1GPRs[i];
1650 // Don't spill high register if the function is thumb. In the case of
1651 // Windows on ARM, accept R11 (frame pointer)
1652 if (!AFI->isThumbFunction() ||
1653 (STI.isTargetWindows() && Reg == ARM::R11) ||
1654 isARMLowRegister(Reg) || Reg == ARM::LR) {
1656 if (!MRI.isReserved(Reg))
1657 ExtraCSSpill = true;
1661 } else if (!UnspilledCS2GPRs.empty() && !AFI->isThumb1OnlyFunction()) {
1662 unsigned Reg = UnspilledCS2GPRs.front();
1664 if (!MRI.isReserved(Reg))
1665 ExtraCSSpill = true;
1669 // Estimate if we might need to scavenge a register at some point in order
1670 // to materialize a stack offset. If so, either spill one additional
1671 // callee-saved register or reserve a special spill slot to facilitate
1672 // register scavenging. Thumb1 needs a spill slot for stack pointer
1673 // adjustments also, even when the frame itself is small.
1674 if (BigStack && !ExtraCSSpill) {
1675 // If any non-reserved CS register isn't spilled, just spill one or two
1676 // extra. That should take care of it!
1677 unsigned NumExtras = TargetAlign / 4;
1678 SmallVector<unsigned, 2> Extras;
1679 while (NumExtras && !UnspilledCS1GPRs.empty()) {
1680 unsigned Reg = UnspilledCS1GPRs.back();
1681 UnspilledCS1GPRs.pop_back();
1682 if (!MRI.isReserved(Reg) &&
1683 (!AFI->isThumb1OnlyFunction() || isARMLowRegister(Reg) ||
1685 Extras.push_back(Reg);
1689 // For non-Thumb1 functions, also check for hi-reg CS registers
1690 if (!AFI->isThumb1OnlyFunction()) {
1691 while (NumExtras && !UnspilledCS2GPRs.empty()) {
1692 unsigned Reg = UnspilledCS2GPRs.back();
1693 UnspilledCS2GPRs.pop_back();
1694 if (!MRI.isReserved(Reg)) {
1695 Extras.push_back(Reg);
1700 if (Extras.size() && NumExtras == 0) {
1701 for (unsigned i = 0, e = Extras.size(); i != e; ++i) {
1702 SavedRegs.set(Extras[i]);
1704 } else if (!AFI->isThumb1OnlyFunction()) {
1705 // note: Thumb1 functions spill to R12, not the stack. Reserve a slot
1706 // closest to SP or frame pointer.
1707 const TargetRegisterClass *RC = &ARM::GPRRegClass;
1708 RS->addScavengingFrameIndex(MFI->CreateStackObject(RC->getSize(),
1716 SavedRegs.set(ARM::LR);
1717 AFI->setLRIsSpilledForFarJump(true);
1722 void ARMFrameLowering::
1723 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
1724 MachineBasicBlock::iterator I) const {
1725 const ARMBaseInstrInfo &TII =
1726 *static_cast<const ARMBaseInstrInfo *>(MF.getSubtarget().getInstrInfo());
1727 if (!hasReservedCallFrame(MF)) {
1728 // If we have alloca, convert as follows:
1729 // ADJCALLSTACKDOWN -> sub, sp, sp, amount
1730 // ADJCALLSTACKUP -> add, sp, sp, amount
1731 MachineInstr *Old = I;
1732 DebugLoc dl = Old->getDebugLoc();
1733 unsigned Amount = Old->getOperand(0).getImm();
1735 // We need to keep the stack aligned properly. To do this, we round the
1736 // amount of space needed for the outgoing arguments up to the next
1737 // alignment boundary.
1738 Amount = alignSPAdjust(Amount);
1740 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1741 assert(!AFI->isThumb1OnlyFunction() &&
1742 "This eliminateCallFramePseudoInstr does not support Thumb1!");
1743 bool isARM = !AFI->isThumbFunction();
1745 // Replace the pseudo instruction with a new instruction...
1746 unsigned Opc = Old->getOpcode();
1747 int PIdx = Old->findFirstPredOperandIdx();
1748 ARMCC::CondCodes Pred = (PIdx == -1)
1749 ? ARMCC::AL : (ARMCC::CondCodes)Old->getOperand(PIdx).getImm();
1750 if (Opc == ARM::ADJCALLSTACKDOWN || Opc == ARM::tADJCALLSTACKDOWN) {
1751 // Note: PredReg is operand 2 for ADJCALLSTACKDOWN.
1752 unsigned PredReg = Old->getOperand(2).getReg();
1753 emitSPUpdate(isARM, MBB, I, dl, TII, -Amount, MachineInstr::NoFlags,
1756 // Note: PredReg is operand 3 for ADJCALLSTACKUP.
1757 unsigned PredReg = Old->getOperand(3).getReg();
1758 assert(Opc == ARM::ADJCALLSTACKUP || Opc == ARM::tADJCALLSTACKUP);
1759 emitSPUpdate(isARM, MBB, I, dl, TII, Amount, MachineInstr::NoFlags,
1767 /// Get the minimum constant for ARM that is greater than or equal to the
1768 /// argument. In ARM, constants can have any value that can be produced by
1769 /// rotating an 8-bit value to the right by an even number of bits within a
1771 static uint32_t alignToARMConstant(uint32_t Value) {
1772 unsigned Shifted = 0;
1777 while (!(Value & 0xC0000000)) {
1782 bool Carry = (Value & 0x00FFFFFF);
1783 Value = ((Value & 0xFF000000) >> 24) + Carry;
1785 if (Value & 0x0000100)
1786 Value = Value & 0x000001FC;
1789 Value = Value >> (Shifted - 24);
1791 Value = Value << (24 - Shifted);
1796 // The stack limit in the TCB is set to this many bytes above the actual
1798 static const uint64_t kSplitStackAvailable = 256;
1800 // Adjust the function prologue to enable split stacks. This currently only
1801 // supports android and linux.
1803 // The ABI of the segmented stack prologue is a little arbitrarily chosen, but
1804 // must be well defined in order to allow for consistent implementations of the
1805 // __morestack helper function. The ABI is also not a normal ABI in that it
1806 // doesn't follow the normal calling conventions because this allows the
1807 // prologue of each function to be optimized further.
1809 // Currently, the ABI looks like (when calling __morestack)
1811 // * r4 holds the minimum stack size requested for this function call
1812 // * r5 holds the stack size of the arguments to the function
1813 // * the beginning of the function is 3 instructions after the call to
1816 // Implementations of __morestack should use r4 to allocate a new stack, r5 to
1817 // place the arguments on to the new stack, and the 3-instruction knowledge to
1818 // jump directly to the body of the function when working on the new stack.
1820 // An old (and possibly no longer compatible) implementation of __morestack for
1821 // ARM can be found at [1].
1823 // [1] - https://github.com/mozilla/rust/blob/86efd9/src/rt/arch/arm/morestack.S
1824 void ARMFrameLowering::adjustForSegmentedStacks(
1825 MachineFunction &MF, MachineBasicBlock &PrologueMBB) const {
1828 const ARMSubtarget *ST = &MF.getSubtarget<ARMSubtarget>();
1829 bool Thumb = ST->isThumb();
1831 // Sadly, this currently doesn't support varargs, platforms other than
1832 // android/linux. Note that thumb1/thumb2 are support for android/linux.
1833 if (MF.getFunction()->isVarArg())
1834 report_fatal_error("Segmented stacks do not support vararg functions.");
1835 if (!ST->isTargetAndroid() && !ST->isTargetLinux())
1836 report_fatal_error("Segmented stacks not supported on this platform.");
1838 MachineFrameInfo *MFI = MF.getFrameInfo();
1839 MachineModuleInfo &MMI = MF.getMMI();
1840 MCContext &Context = MMI.getContext();
1841 const MCRegisterInfo *MRI = Context.getRegisterInfo();
1842 const ARMBaseInstrInfo &TII =
1843 *static_cast<const ARMBaseInstrInfo *>(MF.getSubtarget().getInstrInfo());
1844 ARMFunctionInfo *ARMFI = MF.getInfo<ARMFunctionInfo>();
1847 uint64_t StackSize = MFI->getStackSize();
1849 // Do not generate a prologue for functions with a stack of size zero
1853 // Use R4 and R5 as scratch registers.
1854 // We save R4 and R5 before use and restore them before leaving the function.
1855 unsigned ScratchReg0 = ARM::R4;
1856 unsigned ScratchReg1 = ARM::R5;
1857 uint64_t AlignedStackSize;
1859 MachineBasicBlock *PrevStackMBB = MF.CreateMachineBasicBlock();
1860 MachineBasicBlock *PostStackMBB = MF.CreateMachineBasicBlock();
1861 MachineBasicBlock *AllocMBB = MF.CreateMachineBasicBlock();
1862 MachineBasicBlock *GetMBB = MF.CreateMachineBasicBlock();
1863 MachineBasicBlock *McrMBB = MF.CreateMachineBasicBlock();
1865 // Grab everything that reaches PrologueMBB to update there liveness as well.
1866 SmallPtrSet<MachineBasicBlock *, 8> BeforePrologueRegion;
1867 SmallVector<MachineBasicBlock *, 2> WalkList;
1868 WalkList.push_back(&PrologueMBB);
1871 MachineBasicBlock *CurMBB = WalkList.pop_back_val();
1872 for (MachineBasicBlock *PredBB : CurMBB->predecessors()) {
1873 if (BeforePrologueRegion.insert(PredBB).second)
1874 WalkList.push_back(PredBB);
1876 } while (!WalkList.empty());
1878 // The order in that list is important.
1879 // The blocks will all be inserted before PrologueMBB using that order.
1880 // Therefore the block that should appear first in the CFG should appear
1881 // first in the list.
1882 MachineBasicBlock *AddedBlocks[] = {PrevStackMBB, McrMBB, GetMBB, AllocMBB,
1884 const int NbAddedBlocks = sizeof(AddedBlocks) / sizeof(AddedBlocks[0]);
1886 for (int Idx = 0; Idx < NbAddedBlocks; ++Idx)
1887 BeforePrologueRegion.insert(AddedBlocks[Idx]);
1889 for (const auto &LI : PrologueMBB.liveins()) {
1890 for (MachineBasicBlock *PredBB : BeforePrologueRegion)
1891 PredBB->addLiveIn(LI);
1894 // Remove the newly added blocks from the list, since we know
1895 // we do not have to do the following updates for them.
1896 for (int Idx = 0; Idx < NbAddedBlocks; ++Idx) {
1897 BeforePrologueRegion.erase(AddedBlocks[Idx]);
1898 MF.insert(PrologueMBB.getIterator(), AddedBlocks[Idx]);
1901 for (MachineBasicBlock *MBB : BeforePrologueRegion) {
1902 // Make sure the LiveIns are still sorted and unique.
1903 MBB->sortUniqueLiveIns();
1904 // Replace the edges to PrologueMBB by edges to the sequences
1905 // we are about to add.
1906 MBB->ReplaceUsesOfBlockWith(&PrologueMBB, AddedBlocks[0]);
1909 // The required stack size that is aligned to ARM constant criterion.
1910 AlignedStackSize = alignToARMConstant(StackSize);
1912 // When the frame size is less than 256 we just compare the stack
1913 // boundary directly to the value of the stack pointer, per gcc.
1914 bool CompareStackPointer = AlignedStackSize < kSplitStackAvailable;
1916 // We will use two of the callee save registers as scratch registers so we
1917 // need to save those registers onto the stack.
1918 // We will use SR0 to hold stack limit and SR1 to hold the stack size
1919 // requested and arguments for __morestack().
1920 // SR0: Scratch Register #0
1921 // SR1: Scratch Register #1
1924 AddDefaultPred(BuildMI(PrevStackMBB, DL, TII.get(ARM::tPUSH)))
1925 .addReg(ScratchReg0).addReg(ScratchReg1);
1927 AddDefaultPred(BuildMI(PrevStackMBB, DL, TII.get(ARM::STMDB_UPD))
1928 .addReg(ARM::SP, RegState::Define).addReg(ARM::SP))
1929 .addReg(ScratchReg0).addReg(ScratchReg1);
1932 // Emit the relevant DWARF information about the change in stack pointer as
1933 // well as where to find both r4 and r5 (the callee-save registers)
1935 MMI.addFrameInst(MCCFIInstruction::createDefCfaOffset(nullptr, -8));
1936 BuildMI(PrevStackMBB, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
1937 .addCFIIndex(CFIIndex);
1938 CFIIndex = MMI.addFrameInst(MCCFIInstruction::createOffset(
1939 nullptr, MRI->getDwarfRegNum(ScratchReg1, true), -4));
1940 BuildMI(PrevStackMBB, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
1941 .addCFIIndex(CFIIndex);
1942 CFIIndex = MMI.addFrameInst(MCCFIInstruction::createOffset(
1943 nullptr, MRI->getDwarfRegNum(ScratchReg0, true), -8));
1944 BuildMI(PrevStackMBB, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
1945 .addCFIIndex(CFIIndex);
1949 AddDefaultPred(BuildMI(McrMBB, DL, TII.get(ARM::tMOVr), ScratchReg1)
1951 } else if (CompareStackPointer) {
1952 AddDefaultPred(BuildMI(McrMBB, DL, TII.get(ARM::MOVr), ScratchReg1)
1953 .addReg(ARM::SP)).addReg(0);
1956 // sub SR1, sp, #StackSize
1957 if (!CompareStackPointer && Thumb) {
1959 AddDefaultCC(BuildMI(McrMBB, DL, TII.get(ARM::tSUBi8), ScratchReg1))
1960 .addReg(ScratchReg1).addImm(AlignedStackSize));
1961 } else if (!CompareStackPointer) {
1962 AddDefaultPred(BuildMI(McrMBB, DL, TII.get(ARM::SUBri), ScratchReg1)
1963 .addReg(ARM::SP).addImm(AlignedStackSize)).addReg(0);
1966 if (Thumb && ST->isThumb1Only()) {
1967 unsigned PCLabelId = ARMFI->createPICLabelUId();
1968 ARMConstantPoolValue *NewCPV = ARMConstantPoolSymbol::Create(
1969 MF.getFunction()->getContext(), "__STACK_LIMIT", PCLabelId, 0);
1970 MachineConstantPool *MCP = MF.getConstantPool();
1971 unsigned CPI = MCP->getConstantPoolIndex(NewCPV, 4);
1973 // ldr SR0, [pc, offset(STACK_LIMIT)]
1974 AddDefaultPred(BuildMI(GetMBB, DL, TII.get(ARM::tLDRpci), ScratchReg0)
1975 .addConstantPoolIndex(CPI));
1978 AddDefaultPred(BuildMI(GetMBB, DL, TII.get(ARM::tLDRi), ScratchReg0)
1979 .addReg(ScratchReg0).addImm(0));
1981 // Get TLS base address from the coprocessor
1982 // mrc p15, #0, SR0, c13, c0, #3
1983 AddDefaultPred(BuildMI(McrMBB, DL, TII.get(ARM::MRC), ScratchReg0)
1990 // Use the last tls slot on android and a private field of the TCP on linux.
1991 assert(ST->isTargetAndroid() || ST->isTargetLinux());
1992 unsigned TlsOffset = ST->isTargetAndroid() ? 63 : 1;
1994 // Get the stack limit from the right offset
1995 // ldr SR0, [sr0, #4 * TlsOffset]
1996 AddDefaultPred(BuildMI(GetMBB, DL, TII.get(ARM::LDRi12), ScratchReg0)
1997 .addReg(ScratchReg0).addImm(4 * TlsOffset));
2000 // Compare stack limit with stack size requested.
2002 Opcode = Thumb ? ARM::tCMPr : ARM::CMPrr;
2003 AddDefaultPred(BuildMI(GetMBB, DL, TII.get(Opcode))
2004 .addReg(ScratchReg0)
2005 .addReg(ScratchReg1));
2007 // This jump is taken if StackLimit < SP - stack required.
2008 Opcode = Thumb ? ARM::tBcc : ARM::Bcc;
2009 BuildMI(GetMBB, DL, TII.get(Opcode)).addMBB(PostStackMBB)
2014 // Calling __morestack(StackSize, Size of stack arguments).
2015 // __morestack knows that the stack size requested is in SR0(r4)
2016 // and amount size of stack arguments is in SR1(r5).
2018 // Pass first argument for the __morestack by Scratch Register #0.
2019 // The amount size of stack required
2021 AddDefaultPred(AddDefaultCC(BuildMI(AllocMBB, DL, TII.get(ARM::tMOVi8),
2022 ScratchReg0)).addImm(AlignedStackSize));
2024 AddDefaultPred(BuildMI(AllocMBB, DL, TII.get(ARM::MOVi), ScratchReg0)
2025 .addImm(AlignedStackSize)).addReg(0);
2027 // Pass second argument for the __morestack by Scratch Register #1.
2028 // The amount size of stack consumed to save function arguments.
2031 AddDefaultCC(BuildMI(AllocMBB, DL, TII.get(ARM::tMOVi8), ScratchReg1))
2032 .addImm(alignToARMConstant(ARMFI->getArgumentStackSize())));
2034 AddDefaultPred(BuildMI(AllocMBB, DL, TII.get(ARM::MOVi), ScratchReg1)
2035 .addImm(alignToARMConstant(ARMFI->getArgumentStackSize())))
2039 // push {lr} - Save return address of this function.
2041 AddDefaultPred(BuildMI(AllocMBB, DL, TII.get(ARM::tPUSH)))
2044 AddDefaultPred(BuildMI(AllocMBB, DL, TII.get(ARM::STMDB_UPD))
2045 .addReg(ARM::SP, RegState::Define)
2050 // Emit the DWARF info about the change in stack as well as where to find the
2051 // previous link register
2053 MMI.addFrameInst(MCCFIInstruction::createDefCfaOffset(nullptr, -12));
2054 BuildMI(AllocMBB, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
2055 .addCFIIndex(CFIIndex);
2056 CFIIndex = MMI.addFrameInst(MCCFIInstruction::createOffset(
2057 nullptr, MRI->getDwarfRegNum(ARM::LR, true), -12));
2058 BuildMI(AllocMBB, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
2059 .addCFIIndex(CFIIndex);
2061 // Call __morestack().
2063 AddDefaultPred(BuildMI(AllocMBB, DL, TII.get(ARM::tBL)))
2064 .addExternalSymbol("__morestack");
2066 BuildMI(AllocMBB, DL, TII.get(ARM::BL))
2067 .addExternalSymbol("__morestack");
2070 // pop {lr} - Restore return address of this original function.
2072 if (ST->isThumb1Only()) {
2073 AddDefaultPred(BuildMI(AllocMBB, DL, TII.get(ARM::tPOP)))
2074 .addReg(ScratchReg0);
2075 AddDefaultPred(BuildMI(AllocMBB, DL, TII.get(ARM::tMOVr), ARM::LR)
2076 .addReg(ScratchReg0));
2078 AddDefaultPred(BuildMI(AllocMBB, DL, TII.get(ARM::t2LDR_POST))
2079 .addReg(ARM::LR, RegState::Define)
2080 .addReg(ARM::SP, RegState::Define)
2085 AddDefaultPred(BuildMI(AllocMBB, DL, TII.get(ARM::LDMIA_UPD))
2086 .addReg(ARM::SP, RegState::Define)
2091 // Restore SR0 and SR1 in case of __morestack() was called.
2092 // __morestack() will skip PostStackMBB block so we need to restore
2093 // scratch registers from here.
2096 AddDefaultPred(BuildMI(AllocMBB, DL, TII.get(ARM::tPOP)))
2097 .addReg(ScratchReg0)
2098 .addReg(ScratchReg1);
2100 AddDefaultPred(BuildMI(AllocMBB, DL, TII.get(ARM::LDMIA_UPD))
2101 .addReg(ARM::SP, RegState::Define)
2103 .addReg(ScratchReg0)
2104 .addReg(ScratchReg1);
2107 // Update the CFA offset now that we've popped
2108 CFIIndex = MMI.addFrameInst(MCCFIInstruction::createDefCfaOffset(nullptr, 0));
2109 BuildMI(AllocMBB, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
2110 .addCFIIndex(CFIIndex);
2112 // bx lr - Return from this function.
2113 Opcode = Thumb ? ARM::tBX_RET : ARM::BX_RET;
2114 AddDefaultPred(BuildMI(AllocMBB, DL, TII.get(Opcode)));
2116 // Restore SR0 and SR1 in case of __morestack() was not called.
2119 AddDefaultPred(BuildMI(PostStackMBB, DL, TII.get(ARM::tPOP)))
2120 .addReg(ScratchReg0)
2121 .addReg(ScratchReg1);
2123 AddDefaultPred(BuildMI(PostStackMBB, DL, TII.get(ARM::LDMIA_UPD))
2124 .addReg(ARM::SP, RegState::Define)
2126 .addReg(ScratchReg0)
2127 .addReg(ScratchReg1);
2130 // Update the CFA offset now that we've popped
2131 CFIIndex = MMI.addFrameInst(MCCFIInstruction::createDefCfaOffset(nullptr, 0));
2132 BuildMI(PostStackMBB, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
2133 .addCFIIndex(CFIIndex);
2135 // Tell debuggers that r4 and r5 are now the same as they were in the
2136 // previous function, that they're the "Same Value".
2137 CFIIndex = MMI.addFrameInst(MCCFIInstruction::createSameValue(
2138 nullptr, MRI->getDwarfRegNum(ScratchReg0, true)));
2139 BuildMI(PostStackMBB, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
2140 .addCFIIndex(CFIIndex);
2141 CFIIndex = MMI.addFrameInst(MCCFIInstruction::createSameValue(
2142 nullptr, MRI->getDwarfRegNum(ScratchReg1, true)));
2143 BuildMI(PostStackMBB, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
2144 .addCFIIndex(CFIIndex);
2146 // Organizing MBB lists
2147 PostStackMBB->addSuccessor(&PrologueMBB);
2149 AllocMBB->addSuccessor(PostStackMBB);
2151 GetMBB->addSuccessor(PostStackMBB);
2152 GetMBB->addSuccessor(AllocMBB);
2154 McrMBB->addSuccessor(GetMBB);
2156 PrevStackMBB->addSuccessor(McrMBB);