1 //===-- ARMFrameLowering.cpp - ARM Frame Information ----------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the ARM implementation of TargetFrameLowering class.
12 //===----------------------------------------------------------------------===//
14 #include "ARMFrameLowering.h"
15 #include "ARMBaseInstrInfo.h"
16 #include "ARMBaseRegisterInfo.h"
17 #include "ARMConstantPoolValue.h"
18 #include "ARMMachineFunctionInfo.h"
19 #include "MCTargetDesc/ARMAddressingModes.h"
20 #include "llvm/CodeGen/MachineFrameInfo.h"
21 #include "llvm/CodeGen/MachineFunction.h"
22 #include "llvm/CodeGen/MachineInstrBuilder.h"
23 #include "llvm/CodeGen/MachineModuleInfo.h"
24 #include "llvm/CodeGen/MachineRegisterInfo.h"
25 #include "llvm/CodeGen/RegisterScavenging.h"
26 #include "llvm/IR/CallingConv.h"
27 #include "llvm/IR/Function.h"
28 #include "llvm/MC/MCContext.h"
29 #include "llvm/Support/CommandLine.h"
30 #include "llvm/Target/TargetOptions.h"
35 SpillAlignedNEONRegs("align-neon-spills", cl::Hidden, cl::init(true),
36 cl::desc("Align ARM NEON spills in prolog and epilog"));
38 static MachineBasicBlock::iterator
39 skipAlignedDPRCS2Spills(MachineBasicBlock::iterator MI,
40 unsigned NumAlignedDPRCS2Regs);
42 ARMFrameLowering::ARMFrameLowering(const ARMSubtarget &sti)
43 : TargetFrameLowering(StackGrowsDown, sti.getStackAlignment(), 0, 4),
46 bool ARMFrameLowering::noFramePointerElim(const MachineFunction &MF) const {
47 // iOS always has a FP for backtracking, force other targets to keep their FP
48 // when doing FastISel. The emitted code is currently superior, and in cases
49 // like test-suite's lencod FastISel isn't quite correct when FP is eliminated.
50 return TargetFrameLowering::noFramePointerElim(MF) ||
51 MF.getSubtarget<ARMSubtarget>().useFastISel();
54 /// hasFP - Return true if the specified function should have a dedicated frame
55 /// pointer register. This is true if the function has variable sized allocas
56 /// or if frame pointer elimination is disabled.
57 bool ARMFrameLowering::hasFP(const MachineFunction &MF) const {
58 const TargetRegisterInfo *RegInfo = MF.getSubtarget().getRegisterInfo();
60 // iOS requires FP not to be clobbered for backtracing purpose.
61 if (STI.isTargetIOS())
64 const MachineFrameInfo *MFI = MF.getFrameInfo();
65 // Always eliminate non-leaf frame pointers.
66 return ((MF.getTarget().Options.DisableFramePointerElim(MF) &&
68 RegInfo->needsStackRealignment(MF) ||
69 MFI->hasVarSizedObjects() ||
70 MFI->isFrameAddressTaken());
73 /// hasReservedCallFrame - Under normal circumstances, when a frame pointer is
74 /// not required, we reserve argument space for call sites in the function
75 /// immediately on entry to the current function. This eliminates the need for
76 /// add/sub sp brackets around call sites. Returns true if the call frame is
77 /// included as part of the stack frame.
78 bool ARMFrameLowering::hasReservedCallFrame(const MachineFunction &MF) const {
79 const MachineFrameInfo *FFI = MF.getFrameInfo();
80 unsigned CFSize = FFI->getMaxCallFrameSize();
81 // It's not always a good idea to include the call frame as part of the
82 // stack frame. ARM (especially Thumb) has small immediate offset to
83 // address the stack frame. So a large call frame can cause poor codegen
84 // and may even makes it impossible to scavenge a register.
85 if (CFSize >= ((1 << 12) - 1) / 2) // Half of imm12
88 return !MF.getFrameInfo()->hasVarSizedObjects();
91 /// canSimplifyCallFramePseudos - If there is a reserved call frame, the
92 /// call frame pseudos can be simplified. Unlike most targets, having a FP
93 /// is not sufficient here since we still may reference some objects via SP
94 /// even when FP is available in Thumb2 mode.
96 ARMFrameLowering::canSimplifyCallFramePseudos(const MachineFunction &MF) const {
97 return hasReservedCallFrame(MF) || MF.getFrameInfo()->hasVarSizedObjects();
100 static bool isCSRestore(MachineInstr *MI,
101 const ARMBaseInstrInfo &TII,
102 const MCPhysReg *CSRegs) {
103 // Integer spill area is handled with "pop".
104 if (isPopOpcode(MI->getOpcode())) {
105 // The first two operands are predicates. The last two are
106 // imp-def and imp-use of SP. Check everything in between.
107 for (int i = 5, e = MI->getNumOperands(); i != e; ++i)
108 if (!isCalleeSavedRegister(MI->getOperand(i).getReg(), CSRegs))
112 if ((MI->getOpcode() == ARM::LDR_POST_IMM ||
113 MI->getOpcode() == ARM::LDR_POST_REG ||
114 MI->getOpcode() == ARM::t2LDR_POST) &&
115 isCalleeSavedRegister(MI->getOperand(0).getReg(), CSRegs) &&
116 MI->getOperand(1).getReg() == ARM::SP)
122 static void emitRegPlusImmediate(bool isARM, MachineBasicBlock &MBB,
123 MachineBasicBlock::iterator &MBBI, DebugLoc dl,
124 const ARMBaseInstrInfo &TII, unsigned DestReg,
125 unsigned SrcReg, int NumBytes,
126 unsigned MIFlags = MachineInstr::NoFlags,
127 ARMCC::CondCodes Pred = ARMCC::AL,
128 unsigned PredReg = 0) {
130 emitARMRegPlusImmediate(MBB, MBBI, dl, DestReg, SrcReg, NumBytes,
131 Pred, PredReg, TII, MIFlags);
133 emitT2RegPlusImmediate(MBB, MBBI, dl, DestReg, SrcReg, NumBytes,
134 Pred, PredReg, TII, MIFlags);
137 static void emitSPUpdate(bool isARM, MachineBasicBlock &MBB,
138 MachineBasicBlock::iterator &MBBI, DebugLoc dl,
139 const ARMBaseInstrInfo &TII, int NumBytes,
140 unsigned MIFlags = MachineInstr::NoFlags,
141 ARMCC::CondCodes Pred = ARMCC::AL,
142 unsigned PredReg = 0) {
143 emitRegPlusImmediate(isARM, MBB, MBBI, dl, TII, ARM::SP, ARM::SP, NumBytes,
144 MIFlags, Pred, PredReg);
147 static int sizeOfSPAdjustment(const MachineInstr *MI) {
149 switch (MI->getOpcode()) {
150 case ARM::VSTMDDB_UPD:
154 case ARM::t2STMDB_UPD:
158 case ARM::STR_PRE_IMM:
161 llvm_unreachable("Unknown push or pop like instruction");
165 // ARM and Thumb2 push/pop insts have explicit "sp, sp" operands (+
166 // pred) so the list starts at 4.
167 for (int i = MI->getNumOperands() - 1; i >= 4; --i)
172 static bool WindowsRequiresStackProbe(const MachineFunction &MF,
173 size_t StackSizeInBytes) {
174 const MachineFrameInfo *MFI = MF.getFrameInfo();
175 const Function *F = MF.getFunction();
176 unsigned StackProbeSize = (MFI->getStackProtectorIndex() > 0) ? 4080 : 4096;
177 if (F->hasFnAttribute("stack-probe-size"))
178 F->getFnAttribute("stack-probe-size")
180 .getAsInteger(0, StackProbeSize);
181 return StackSizeInBytes >= StackProbeSize;
185 struct StackAdjustingInsts {
187 MachineBasicBlock::iterator I;
192 SmallVector<InstInfo, 4> Insts;
194 void addInst(MachineBasicBlock::iterator I, unsigned SPAdjust,
195 bool BeforeFPSet = false) {
196 InstInfo Info = {I, SPAdjust, BeforeFPSet};
197 Insts.push_back(Info);
200 void addExtraBytes(const MachineBasicBlock::iterator I, unsigned ExtraBytes) {
201 auto Info = std::find_if(Insts.begin(), Insts.end(),
202 [&](InstInfo &Info) { return Info.I == I; });
203 assert(Info != Insts.end() && "invalid sp adjusting instruction");
204 Info->SPAdjust += ExtraBytes;
207 void emitDefCFAOffsets(MachineModuleInfo &MMI, MachineBasicBlock &MBB,
208 DebugLoc dl, const ARMBaseInstrInfo &TII, bool HasFP) {
209 unsigned CFAOffset = 0;
210 for (auto &Info : Insts) {
211 if (HasFP && !Info.BeforeFPSet)
214 CFAOffset -= Info.SPAdjust;
215 unsigned CFIIndex = MMI.addFrameInst(
216 MCCFIInstruction::createDefCfaOffset(nullptr, CFAOffset));
217 BuildMI(MBB, std::next(Info.I), dl,
218 TII.get(TargetOpcode::CFI_INSTRUCTION))
219 .addCFIIndex(CFIIndex)
220 .setMIFlags(MachineInstr::FrameSetup);
226 /// Emit an instruction sequence that will align the address in
227 /// register Reg by zero-ing out the lower bits. For versions of the
228 /// architecture that support Neon, this must be done in a single
229 /// instruction, since skipAlignedDPRCS2Spills assumes it is done in a
230 /// single instruction. That function only gets called when optimizing
231 /// spilling of D registers on a core with the Neon instruction set
233 static void emitAligningInstructions(MachineFunction &MF, ARMFunctionInfo *AFI,
234 const TargetInstrInfo &TII,
235 MachineBasicBlock &MBB,
236 MachineBasicBlock::iterator MBBI,
237 DebugLoc DL, const unsigned Reg,
238 const unsigned Alignment,
239 const bool MustBeSingleInstruction) {
240 const ARMSubtarget &AST =
241 static_cast<const ARMSubtarget &>(MF.getSubtarget());
242 const bool CanUseBFC = AST.hasV6T2Ops() || AST.hasV7Ops();
243 const unsigned AlignMask = Alignment - 1;
244 const unsigned NrBitsToZero = countTrailingZeros(Alignment);
245 assert(!AFI->isThumb1OnlyFunction() && "Thumb1 not supported");
246 if (!AFI->isThumbFunction()) {
247 // if the BFC instruction is available, use that to zero the lower
249 // bfc Reg, #0, log2(Alignment)
250 // otherwise use BIC, if the mask to zero the required number of bits
251 // can be encoded in the bic immediate field
252 // bic Reg, Reg, Alignment-1
254 // lsr Reg, Reg, log2(Alignment)
255 // lsl Reg, Reg, log2(Alignment)
257 AddDefaultPred(BuildMI(MBB, MBBI, DL, TII.get(ARM::BFC), Reg)
258 .addReg(Reg, RegState::Kill)
259 .addImm(~AlignMask));
260 } else if (AlignMask <= 255) {
262 AddDefaultPred(BuildMI(MBB, MBBI, DL, TII.get(ARM::BICri), Reg)
263 .addReg(Reg, RegState::Kill)
264 .addImm(AlignMask)));
266 assert(!MustBeSingleInstruction &&
267 "Shouldn't call emitAligningInstructions demanding a single "
268 "instruction to be emitted for large stack alignment for a target "
270 AddDefaultCC(AddDefaultPred(
271 BuildMI(MBB, MBBI, DL, TII.get(ARM::MOVsi), Reg)
272 .addReg(Reg, RegState::Kill)
273 .addImm(ARM_AM::getSORegOpc(ARM_AM::lsr, NrBitsToZero))));
274 AddDefaultCC(AddDefaultPred(
275 BuildMI(MBB, MBBI, DL, TII.get(ARM::MOVsi), Reg)
276 .addReg(Reg, RegState::Kill)
277 .addImm(ARM_AM::getSORegOpc(ARM_AM::lsl, NrBitsToZero))));
280 // Since this is only reached for Thumb-2 targets, the BFC instruction
281 // should always be available.
283 AddDefaultPred(BuildMI(MBB, MBBI, DL, TII.get(ARM::t2BFC), Reg)
284 .addReg(Reg, RegState::Kill)
285 .addImm(~AlignMask));
289 void ARMFrameLowering::emitPrologue(MachineFunction &MF,
290 MachineBasicBlock &MBB) const {
291 MachineBasicBlock::iterator MBBI = MBB.begin();
292 MachineFrameInfo *MFI = MF.getFrameInfo();
293 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
294 MachineModuleInfo &MMI = MF.getMMI();
295 MCContext &Context = MMI.getContext();
296 const TargetMachine &TM = MF.getTarget();
297 const MCRegisterInfo *MRI = Context.getRegisterInfo();
298 const ARMBaseRegisterInfo *RegInfo = STI.getRegisterInfo();
299 const ARMBaseInstrInfo &TII = *STI.getInstrInfo();
300 assert(!AFI->isThumb1OnlyFunction() &&
301 "This emitPrologue does not support Thumb1!");
302 bool isARM = !AFI->isThumbFunction();
303 unsigned Align = STI.getFrameLowering()->getStackAlignment();
304 unsigned ArgRegsSaveSize = AFI->getArgRegsSaveSize();
305 unsigned NumBytes = MFI->getStackSize();
306 const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
307 DebugLoc dl = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
308 unsigned FramePtr = RegInfo->getFrameRegister(MF);
310 // Determine the sizes of each callee-save spill areas and record which frame
311 // belongs to which callee-save spill areas.
312 unsigned GPRCS1Size = 0, GPRCS2Size = 0, DPRCSSize = 0;
313 int FramePtrSpillFI = 0;
316 // All calls are tail calls in GHC calling conv, and functions have no
317 // prologue/epilogue.
318 if (MF.getFunction()->getCallingConv() == CallingConv::GHC)
321 StackAdjustingInsts DefCFAOffsetCandidates;
322 bool HasFP = hasFP(MF);
324 // Allocate the vararg register save area.
325 if (ArgRegsSaveSize) {
326 emitSPUpdate(isARM, MBB, MBBI, dl, TII, -ArgRegsSaveSize,
327 MachineInstr::FrameSetup);
328 DefCFAOffsetCandidates.addInst(std::prev(MBBI), ArgRegsSaveSize, true);
331 if (!AFI->hasStackFrame() &&
332 (!STI.isTargetWindows() || !WindowsRequiresStackProbe(MF, NumBytes))) {
333 if (NumBytes - ArgRegsSaveSize != 0) {
334 emitSPUpdate(isARM, MBB, MBBI, dl, TII, -(NumBytes - ArgRegsSaveSize),
335 MachineInstr::FrameSetup);
336 DefCFAOffsetCandidates.addInst(std::prev(MBBI),
337 NumBytes - ArgRegsSaveSize, true);
339 DefCFAOffsetCandidates.emitDefCFAOffsets(MMI, MBB, dl, TII, HasFP);
343 // Determine spill area sizes.
344 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
345 unsigned Reg = CSI[i].getReg();
346 int FI = CSI[i].getFrameIdx();
353 if (STI.isTargetDarwin()) {
368 FramePtrSpillFI = FI;
372 // This is a DPR. Exclude the aligned DPRCS2 spills.
375 if (Reg < ARM::D8 || Reg >= ARM::D8 + AFI->getNumAlignedDPRCS2Regs())
381 MachineBasicBlock::iterator LastPush = MBB.end(), GPRCS1Push, GPRCS2Push;
382 if (GPRCS1Size > 0) {
383 GPRCS1Push = LastPush = MBBI++;
384 DefCFAOffsetCandidates.addInst(LastPush, GPRCS1Size, true);
387 // Determine starting offsets of spill areas.
388 unsigned GPRCS1Offset = NumBytes - ArgRegsSaveSize - GPRCS1Size;
389 unsigned GPRCS2Offset = GPRCS1Offset - GPRCS2Size;
390 unsigned DPRAlign = DPRCSSize ? std::min(8U, Align) : 4U;
391 unsigned DPRGapSize = (GPRCS1Size + GPRCS2Size + ArgRegsSaveSize) % DPRAlign;
392 unsigned DPRCSOffset = GPRCS2Offset - DPRGapSize - DPRCSSize;
393 int FramePtrOffsetInPush = 0;
395 FramePtrOffsetInPush =
396 MFI->getObjectOffset(FramePtrSpillFI) + ArgRegsSaveSize;
397 AFI->setFramePtrSpillOffset(MFI->getObjectOffset(FramePtrSpillFI) +
400 AFI->setGPRCalleeSavedArea1Offset(GPRCS1Offset);
401 AFI->setGPRCalleeSavedArea2Offset(GPRCS2Offset);
402 AFI->setDPRCalleeSavedAreaOffset(DPRCSOffset);
405 if (GPRCS2Size > 0) {
406 GPRCS2Push = LastPush = MBBI++;
407 DefCFAOffsetCandidates.addInst(LastPush, GPRCS2Size);
410 // Prolog/epilog inserter assumes we correctly align DPRs on the stack, so our
411 // .cfi_offset operations will reflect that.
413 assert(DPRGapSize == 4 && "unexpected alignment requirements for DPRs");
414 if (tryFoldSPUpdateIntoPushPop(STI, MF, LastPush, DPRGapSize))
415 DefCFAOffsetCandidates.addExtraBytes(LastPush, DPRGapSize);
417 emitSPUpdate(isARM, MBB, MBBI, dl, TII, -DPRGapSize,
418 MachineInstr::FrameSetup);
419 DefCFAOffsetCandidates.addInst(std::prev(MBBI), DPRGapSize);
425 // Since vpush register list cannot have gaps, there may be multiple vpush
426 // instructions in the prologue.
427 while (MBBI->getOpcode() == ARM::VSTMDDB_UPD) {
428 DefCFAOffsetCandidates.addInst(MBBI, sizeOfSPAdjustment(MBBI));
433 // Move past the aligned DPRCS2 area.
434 if (AFI->getNumAlignedDPRCS2Regs() > 0) {
435 MBBI = skipAlignedDPRCS2Spills(MBBI, AFI->getNumAlignedDPRCS2Regs());
436 // The code inserted by emitAlignedDPRCS2Spills realigns the stack, and
437 // leaves the stack pointer pointing to the DPRCS2 area.
439 // Adjust NumBytes to represent the stack slots below the DPRCS2 area.
440 NumBytes += MFI->getObjectOffset(D8SpillFI);
442 NumBytes = DPRCSOffset;
444 if (STI.isTargetWindows() && WindowsRequiresStackProbe(MF, NumBytes)) {
445 uint32_t NumWords = NumBytes >> 2;
447 if (NumWords < 65536)
448 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::t2MOVi16), ARM::R4)
450 .setMIFlags(MachineInstr::FrameSetup));
452 BuildMI(MBB, MBBI, dl, TII.get(ARM::t2MOVi32imm), ARM::R4)
454 .setMIFlags(MachineInstr::FrameSetup);
456 switch (TM.getCodeModel()) {
457 case CodeModel::Small:
458 case CodeModel::Medium:
459 case CodeModel::Default:
460 case CodeModel::Kernel:
461 BuildMI(MBB, MBBI, dl, TII.get(ARM::tBL))
462 .addImm((unsigned)ARMCC::AL).addReg(0)
463 .addExternalSymbol("__chkstk")
464 .addReg(ARM::R4, RegState::Implicit)
465 .setMIFlags(MachineInstr::FrameSetup);
467 case CodeModel::Large:
468 case CodeModel::JITDefault:
469 BuildMI(MBB, MBBI, dl, TII.get(ARM::t2MOVi32imm), ARM::R12)
470 .addExternalSymbol("__chkstk")
471 .setMIFlags(MachineInstr::FrameSetup);
473 BuildMI(MBB, MBBI, dl, TII.get(ARM::tBLXr))
474 .addImm((unsigned)ARMCC::AL).addReg(0)
475 .addReg(ARM::R12, RegState::Kill)
476 .addReg(ARM::R4, RegState::Implicit)
477 .setMIFlags(MachineInstr::FrameSetup);
481 AddDefaultCC(AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::t2SUBrr),
483 .addReg(ARM::SP, RegState::Define)
484 .addReg(ARM::R4, RegState::Kill)
485 .setMIFlags(MachineInstr::FrameSetup)));
490 // Adjust SP after all the callee-save spills.
491 if (tryFoldSPUpdateIntoPushPop(STI, MF, LastPush, NumBytes))
492 DefCFAOffsetCandidates.addExtraBytes(LastPush, NumBytes);
494 emitSPUpdate(isARM, MBB, MBBI, dl, TII, -NumBytes,
495 MachineInstr::FrameSetup);
496 DefCFAOffsetCandidates.addInst(std::prev(MBBI), NumBytes);
500 // Restore from fp only in ARM mode: e.g. sub sp, r7, #24
501 // Note it's not safe to do this in Thumb2 mode because it would have
502 // taken two instructions:
505 // If an interrupt is taken between the two instructions, then sp is in
506 // an inconsistent state (pointing to the middle of callee-saved area).
507 // The interrupt handler can end up clobbering the registers.
508 AFI->setShouldRestoreSPFromFP(true);
511 // Set FP to point to the stack slot that contains the previous FP.
512 // For iOS, FP is R7, which has now been stored in spill area 1.
513 // Otherwise, if this is not iOS, all the callee-saved registers go
514 // into spill area 1, including the FP in R11. In either case, it
515 // is in area one and the adjustment needs to take place just after
518 MachineBasicBlock::iterator AfterPush = std::next(GPRCS1Push);
519 unsigned PushSize = sizeOfSPAdjustment(GPRCS1Push);
520 emitRegPlusImmediate(!AFI->isThumbFunction(), MBB, AfterPush,
521 dl, TII, FramePtr, ARM::SP,
522 PushSize + FramePtrOffsetInPush,
523 MachineInstr::FrameSetup);
524 if (FramePtrOffsetInPush + PushSize != 0) {
525 unsigned CFIIndex = MMI.addFrameInst(MCCFIInstruction::createDefCfa(
526 nullptr, MRI->getDwarfRegNum(FramePtr, true),
527 -(ArgRegsSaveSize - FramePtrOffsetInPush)));
528 BuildMI(MBB, AfterPush, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
529 .addCFIIndex(CFIIndex)
530 .setMIFlags(MachineInstr::FrameSetup);
533 MMI.addFrameInst(MCCFIInstruction::createDefCfaRegister(
534 nullptr, MRI->getDwarfRegNum(FramePtr, true)));
535 BuildMI(MBB, AfterPush, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
536 .addCFIIndex(CFIIndex)
537 .setMIFlags(MachineInstr::FrameSetup);
541 // Now that the prologue's actual instructions are finalised, we can insert
542 // the necessary DWARF cf instructions to describe the situation. Start by
543 // recording where each register ended up:
544 if (GPRCS1Size > 0) {
545 MachineBasicBlock::iterator Pos = std::next(GPRCS1Push);
547 for (const auto &Entry : CSI) {
548 unsigned Reg = Entry.getReg();
549 int FI = Entry.getFrameIdx();
556 if (STI.isTargetDarwin())
568 CFIIndex = MMI.addFrameInst(MCCFIInstruction::createOffset(
569 nullptr, MRI->getDwarfRegNum(Reg, true), MFI->getObjectOffset(FI)));
570 BuildMI(MBB, Pos, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
571 .addCFIIndex(CFIIndex)
572 .setMIFlags(MachineInstr::FrameSetup);
578 if (GPRCS2Size > 0) {
579 MachineBasicBlock::iterator Pos = std::next(GPRCS2Push);
580 for (const auto &Entry : CSI) {
581 unsigned Reg = Entry.getReg();
582 int FI = Entry.getFrameIdx();
589 if (STI.isTargetDarwin()) {
590 unsigned DwarfReg = MRI->getDwarfRegNum(Reg, true);
591 unsigned Offset = MFI->getObjectOffset(FI);
592 unsigned CFIIndex = MMI.addFrameInst(
593 MCCFIInstruction::createOffset(nullptr, DwarfReg, Offset));
594 BuildMI(MBB, Pos, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
595 .addCFIIndex(CFIIndex)
596 .setMIFlags(MachineInstr::FrameSetup);
604 // Since vpush register list cannot have gaps, there may be multiple vpush
605 // instructions in the prologue.
606 MachineBasicBlock::iterator Pos = std::next(LastPush);
607 for (const auto &Entry : CSI) {
608 unsigned Reg = Entry.getReg();
609 int FI = Entry.getFrameIdx();
610 if ((Reg >= ARM::D0 && Reg <= ARM::D31) &&
611 (Reg < ARM::D8 || Reg >= ARM::D8 + AFI->getNumAlignedDPRCS2Regs())) {
612 unsigned DwarfReg = MRI->getDwarfRegNum(Reg, true);
613 unsigned Offset = MFI->getObjectOffset(FI);
614 unsigned CFIIndex = MMI.addFrameInst(
615 MCCFIInstruction::createOffset(nullptr, DwarfReg, Offset));
616 BuildMI(MBB, Pos, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
617 .addCFIIndex(CFIIndex)
618 .setMIFlags(MachineInstr::FrameSetup);
623 // Now we can emit descriptions of where the canonical frame address was
624 // throughout the process. If we have a frame pointer, it takes over the job
625 // half-way through, so only the first few .cfi_def_cfa_offset instructions
626 // actually get emitted.
627 DefCFAOffsetCandidates.emitDefCFAOffsets(MMI, MBB, dl, TII, HasFP);
629 if (STI.isTargetELF() && hasFP(MF))
630 MFI->setOffsetAdjustment(MFI->getOffsetAdjustment() -
631 AFI->getFramePtrSpillOffset());
633 AFI->setGPRCalleeSavedArea1Size(GPRCS1Size);
634 AFI->setGPRCalleeSavedArea2Size(GPRCS2Size);
635 AFI->setDPRCalleeSavedGapSize(DPRGapSize);
636 AFI->setDPRCalleeSavedAreaSize(DPRCSSize);
638 // If we need dynamic stack realignment, do it here. Be paranoid and make
639 // sure if we also have VLAs, we have a base pointer for frame access.
640 // If aligned NEON registers were spilled, the stack has already been
642 if (!AFI->getNumAlignedDPRCS2Regs() && RegInfo->needsStackRealignment(MF)) {
643 unsigned MaxAlign = MFI->getMaxAlignment();
644 assert(!AFI->isThumb1OnlyFunction());
645 if (!AFI->isThumbFunction()) {
646 emitAligningInstructions(MF, AFI, TII, MBB, MBBI, dl, ARM::SP, MaxAlign,
649 // We cannot use sp as source/dest register here, thus we're using r4 to
650 // perform the calculations. We're emitting the following sequence:
652 // -- use emitAligningInstructions to produce best sequence to zero
653 // -- out lower bits in r4
655 // FIXME: It will be better just to find spare register here.
656 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), ARM::R4)
657 .addReg(ARM::SP, RegState::Kill));
658 emitAligningInstructions(MF, AFI, TII, MBB, MBBI, dl, ARM::R4, MaxAlign,
660 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), ARM::SP)
661 .addReg(ARM::R4, RegState::Kill));
664 AFI->setShouldRestoreSPFromFP(true);
667 // If we need a base pointer, set it up here. It's whatever the value
668 // of the stack pointer is at this point. Any variable size objects
669 // will be allocated after this, so we can still use the base pointer
670 // to reference locals.
671 // FIXME: Clarify FrameSetup flags here.
672 if (RegInfo->hasBasePointer(MF)) {
674 BuildMI(MBB, MBBI, dl,
675 TII.get(ARM::MOVr), RegInfo->getBaseRegister())
677 .addImm((unsigned)ARMCC::AL).addReg(0).addReg(0);
679 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr),
680 RegInfo->getBaseRegister())
684 // If the frame has variable sized objects then the epilogue must restore
685 // the sp from fp. We can assume there's an FP here since hasFP already
686 // checks for hasVarSizedObjects.
687 if (MFI->hasVarSizedObjects())
688 AFI->setShouldRestoreSPFromFP(true);
691 void ARMFrameLowering::emitEpilogue(MachineFunction &MF,
692 MachineBasicBlock &MBB) const {
693 MachineFrameInfo *MFI = MF.getFrameInfo();
694 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
695 const TargetRegisterInfo *RegInfo = MF.getSubtarget().getRegisterInfo();
696 const ARMBaseInstrInfo &TII =
697 *static_cast<const ARMBaseInstrInfo *>(MF.getSubtarget().getInstrInfo());
698 assert(!AFI->isThumb1OnlyFunction() &&
699 "This emitEpilogue does not support Thumb1!");
700 bool isARM = !AFI->isThumbFunction();
702 unsigned ArgRegsSaveSize = AFI->getArgRegsSaveSize();
703 int NumBytes = (int)MFI->getStackSize();
704 unsigned FramePtr = RegInfo->getFrameRegister(MF);
706 // All calls are tail calls in GHC calling conv, and functions have no
707 // prologue/epilogue.
708 if (MF.getFunction()->getCallingConv() == CallingConv::GHC)
711 // First put ourselves on the first (from top) terminator instructions.
712 MachineBasicBlock::iterator MBBI = MBB.getFirstTerminator();
713 DebugLoc dl = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
715 if (!AFI->hasStackFrame()) {
716 if (NumBytes - ArgRegsSaveSize != 0)
717 emitSPUpdate(isARM, MBB, MBBI, dl, TII, NumBytes - ArgRegsSaveSize);
719 // Unwind MBBI to point to first LDR / VLDRD.
720 const MCPhysReg *CSRegs = RegInfo->getCalleeSavedRegs(&MF);
721 if (MBBI != MBB.begin()) {
724 } while (MBBI != MBB.begin() && isCSRestore(MBBI, TII, CSRegs));
725 if (!isCSRestore(MBBI, TII, CSRegs))
729 // Move SP to start of FP callee save spill area.
730 NumBytes -= (ArgRegsSaveSize +
731 AFI->getGPRCalleeSavedArea1Size() +
732 AFI->getGPRCalleeSavedArea2Size() +
733 AFI->getDPRCalleeSavedGapSize() +
734 AFI->getDPRCalleeSavedAreaSize());
736 // Reset SP based on frame pointer only if the stack frame extends beyond
737 // frame pointer stack slot or target is ELF and the function has FP.
738 if (AFI->shouldRestoreSPFromFP()) {
739 NumBytes = AFI->getFramePtrSpillOffset() - NumBytes;
742 emitARMRegPlusImmediate(MBB, MBBI, dl, ARM::SP, FramePtr, -NumBytes,
745 // It's not possible to restore SP from FP in a single instruction.
746 // For iOS, this looks like:
749 // This is bad, if an interrupt is taken after the mov, sp is in an
750 // inconsistent state.
751 // Use the first callee-saved register as a scratch register.
752 assert(!MFI->getPristineRegs(MF).test(ARM::R4) &&
753 "No scratch register to restore SP from FP!");
754 emitT2RegPlusImmediate(MBB, MBBI, dl, ARM::R4, FramePtr, -NumBytes,
756 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr),
763 BuildMI(MBB, MBBI, dl, TII.get(ARM::MOVr), ARM::SP)
764 .addReg(FramePtr).addImm((unsigned)ARMCC::AL).addReg(0).addReg(0);
766 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr),
770 } else if (NumBytes &&
771 !tryFoldSPUpdateIntoPushPop(STI, MF, MBBI, NumBytes))
772 emitSPUpdate(isARM, MBB, MBBI, dl, TII, NumBytes);
774 // Increment past our save areas.
775 if (AFI->getDPRCalleeSavedAreaSize()) {
777 // Since vpop register list cannot have gaps, there may be multiple vpop
778 // instructions in the epilogue.
779 while (MBBI->getOpcode() == ARM::VLDMDIA_UPD)
782 if (AFI->getDPRCalleeSavedGapSize()) {
783 assert(AFI->getDPRCalleeSavedGapSize() == 4 &&
784 "unexpected DPR alignment gap");
785 emitSPUpdate(isARM, MBB, MBBI, dl, TII, AFI->getDPRCalleeSavedGapSize());
788 if (AFI->getGPRCalleeSavedArea2Size()) MBBI++;
789 if (AFI->getGPRCalleeSavedArea1Size()) MBBI++;
793 emitSPUpdate(isARM, MBB, MBBI, dl, TII, ArgRegsSaveSize);
796 /// getFrameIndexReference - Provide a base+offset reference to an FI slot for
797 /// debug info. It's the same as what we use for resolving the code-gen
798 /// references for now. FIXME: This can go wrong when references are
799 /// SP-relative and simple call frames aren't used.
801 ARMFrameLowering::getFrameIndexReference(const MachineFunction &MF, int FI,
802 unsigned &FrameReg) const {
803 return ResolveFrameIndexReference(MF, FI, FrameReg, 0);
807 ARMFrameLowering::ResolveFrameIndexReference(const MachineFunction &MF,
808 int FI, unsigned &FrameReg,
810 const MachineFrameInfo *MFI = MF.getFrameInfo();
811 const ARMBaseRegisterInfo *RegInfo = static_cast<const ARMBaseRegisterInfo *>(
812 MF.getSubtarget().getRegisterInfo());
813 const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
814 int Offset = MFI->getObjectOffset(FI) + MFI->getStackSize();
815 int FPOffset = Offset - AFI->getFramePtrSpillOffset();
816 bool isFixed = MFI->isFixedObjectIndex(FI);
821 // SP can move around if there are allocas. We may also lose track of SP
822 // when emergency spilling inside a non-reserved call frame setup.
823 bool hasMovingSP = !hasReservedCallFrame(MF);
825 // When dynamically realigning the stack, use the frame pointer for
826 // parameters, and the stack/base pointer for locals.
827 if (RegInfo->needsStackRealignment(MF)) {
828 assert (hasFP(MF) && "dynamic stack realignment without a FP!");
830 FrameReg = RegInfo->getFrameRegister(MF);
832 } else if (hasMovingSP) {
833 assert(RegInfo->hasBasePointer(MF) &&
834 "VLAs and dynamic stack alignment, but missing base pointer!");
835 FrameReg = RegInfo->getBaseRegister();
840 // If there is a frame pointer, use it when we can.
841 if (hasFP(MF) && AFI->hasStackFrame()) {
842 // Use frame pointer to reference fixed objects. Use it for locals if
843 // there are VLAs (and thus the SP isn't reliable as a base).
844 if (isFixed || (hasMovingSP && !RegInfo->hasBasePointer(MF))) {
845 FrameReg = RegInfo->getFrameRegister(MF);
847 } else if (hasMovingSP) {
848 assert(RegInfo->hasBasePointer(MF) && "missing base pointer!");
849 if (AFI->isThumb2Function()) {
850 // Try to use the frame pointer if we can, else use the base pointer
851 // since it's available. This is handy for the emergency spill slot, in
853 if (FPOffset >= -255 && FPOffset < 0) {
854 FrameReg = RegInfo->getFrameRegister(MF);
858 } else if (AFI->isThumb2Function()) {
859 // Use add <rd>, sp, #<imm8>
860 // ldr <rd>, [sp, #<imm8>]
861 // if at all possible to save space.
862 if (Offset >= 0 && (Offset & 3) == 0 && Offset <= 1020)
864 // In Thumb2 mode, the negative offset is very limited. Try to avoid
865 // out of range references. ldr <rt>,[<rn>, #-<imm8>]
866 if (FPOffset >= -255 && FPOffset < 0) {
867 FrameReg = RegInfo->getFrameRegister(MF);
870 } else if (Offset > (FPOffset < 0 ? -FPOffset : FPOffset)) {
871 // Otherwise, use SP or FP, whichever is closer to the stack slot.
872 FrameReg = RegInfo->getFrameRegister(MF);
876 // Use the base pointer if we have one.
877 if (RegInfo->hasBasePointer(MF))
878 FrameReg = RegInfo->getBaseRegister();
882 int ARMFrameLowering::getFrameIndexOffset(const MachineFunction &MF,
885 return getFrameIndexReference(MF, FI, FrameReg);
888 void ARMFrameLowering::emitPushInst(MachineBasicBlock &MBB,
889 MachineBasicBlock::iterator MI,
890 const std::vector<CalleeSavedInfo> &CSI,
891 unsigned StmOpc, unsigned StrOpc,
893 bool(*Func)(unsigned, bool),
894 unsigned NumAlignedDPRCS2Regs,
895 unsigned MIFlags) const {
896 MachineFunction &MF = *MBB.getParent();
897 const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
900 if (MI != MBB.end()) DL = MI->getDebugLoc();
902 SmallVector<std::pair<unsigned,bool>, 4> Regs;
903 unsigned i = CSI.size();
905 unsigned LastReg = 0;
906 for (; i != 0; --i) {
907 unsigned Reg = CSI[i-1].getReg();
908 if (!(Func)(Reg, STI.isTargetDarwin())) continue;
910 // D-registers in the aligned area DPRCS2 are NOT spilled here.
911 if (Reg >= ARM::D8 && Reg < ARM::D8 + NumAlignedDPRCS2Regs)
914 // Add the callee-saved register as live-in unless it's LR and
915 // @llvm.returnaddress is called. If LR is returned for
916 // @llvm.returnaddress then it's already added to the function and
917 // entry block live-in sets.
919 if (Reg == ARM::LR) {
920 if (MF.getFrameInfo()->isReturnAddressTaken() &&
921 MF.getRegInfo().isLiveIn(Reg))
928 // If NoGap is true, push consecutive registers and then leave the rest
929 // for other instructions. e.g.
930 // vpush {d8, d10, d11} -> vpush {d8}, vpush {d10, d11}
931 if (NoGap && LastReg && LastReg != Reg-1)
934 Regs.push_back(std::make_pair(Reg, isKill));
939 if (Regs.size() > 1 || StrOpc== 0) {
940 MachineInstrBuilder MIB =
941 AddDefaultPred(BuildMI(MBB, MI, DL, TII.get(StmOpc), ARM::SP)
942 .addReg(ARM::SP).setMIFlags(MIFlags));
943 for (unsigned i = 0, e = Regs.size(); i < e; ++i)
944 MIB.addReg(Regs[i].first, getKillRegState(Regs[i].second));
945 } else if (Regs.size() == 1) {
946 MachineInstrBuilder MIB = BuildMI(MBB, MI, DL, TII.get(StrOpc),
948 .addReg(Regs[0].first, getKillRegState(Regs[0].second))
949 .addReg(ARM::SP).setMIFlags(MIFlags)
955 // Put any subsequent vpush instructions before this one: they will refer to
956 // higher register numbers so need to be pushed first in order to preserve
958 if (MI != MBB.begin())
963 void ARMFrameLowering::emitPopInst(MachineBasicBlock &MBB,
964 MachineBasicBlock::iterator MI,
965 const std::vector<CalleeSavedInfo> &CSI,
966 unsigned LdmOpc, unsigned LdrOpc,
967 bool isVarArg, bool NoGap,
968 bool(*Func)(unsigned, bool),
969 unsigned NumAlignedDPRCS2Regs) const {
970 MachineFunction &MF = *MBB.getParent();
971 const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
972 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
974 bool isTailCall = false;
975 bool isInterrupt = false;
976 if (MBB.end() != MI) {
977 DL = MI->getDebugLoc();
978 unsigned RetOpcode = MI->getOpcode();
979 isTailCall = (RetOpcode == ARM::TCRETURNdi || RetOpcode == ARM::TCRETURNri);
981 RetOpcode == ARM::SUBS_PC_LR || RetOpcode == ARM::t2SUBS_PC_LR;
984 SmallVector<unsigned, 4> Regs;
985 unsigned i = CSI.size();
987 unsigned LastReg = 0;
988 bool DeleteRet = false;
989 for (; i != 0; --i) {
990 unsigned Reg = CSI[i-1].getReg();
991 if (!(Func)(Reg, STI.isTargetDarwin())) continue;
993 // The aligned reloads from area DPRCS2 are not inserted here.
994 if (Reg >= ARM::D8 && Reg < ARM::D8 + NumAlignedDPRCS2Regs)
997 if (Reg == ARM::LR && !isTailCall && !isVarArg && !isInterrupt &&
999 if (MBB.succ_empty()) {
1002 LdmOpc = AFI->isThumbFunction() ? ARM::t2LDMIA_RET : ARM::LDMIA_RET;
1004 LdmOpc = AFI->isThumbFunction() ? ARM::t2LDMIA_UPD : ARM::LDMIA_UPD;
1005 // Fold the return instruction into the LDM.
1008 // If NoGap is true, pop consecutive registers and then leave the rest
1009 // for other instructions. e.g.
1010 // vpop {d8, d10, d11} -> vpop {d8}, vpop {d10, d11}
1011 if (NoGap && LastReg && LastReg != Reg-1)
1015 Regs.push_back(Reg);
1020 if (Regs.size() > 1 || LdrOpc == 0) {
1021 MachineInstrBuilder MIB =
1022 AddDefaultPred(BuildMI(MBB, MI, DL, TII.get(LdmOpc), ARM::SP)
1024 for (unsigned i = 0, e = Regs.size(); i < e; ++i)
1025 MIB.addReg(Regs[i], getDefRegState(true));
1026 if (DeleteRet && MI != MBB.end()) {
1027 MIB.copyImplicitOps(&*MI);
1028 MI->eraseFromParent();
1031 } else if (Regs.size() == 1) {
1032 // If we adjusted the reg to PC from LR above, switch it back here. We
1033 // only do that for LDM.
1034 if (Regs[0] == ARM::PC)
1036 MachineInstrBuilder MIB =
1037 BuildMI(MBB, MI, DL, TII.get(LdrOpc), Regs[0])
1038 .addReg(ARM::SP, RegState::Define)
1040 // ARM mode needs an extra reg0 here due to addrmode2. Will go away once
1041 // that refactoring is complete (eventually).
1042 if (LdrOpc == ARM::LDR_POST_REG || LdrOpc == ARM::LDR_POST_IMM) {
1044 MIB.addImm(ARM_AM::getAM2Opc(ARM_AM::add, 4, ARM_AM::no_shift));
1047 AddDefaultPred(MIB);
1051 // Put any subsequent vpop instructions after this one: they will refer to
1052 // higher register numbers so need to be popped afterwards.
1053 if (MI != MBB.end())
1058 /// Emit aligned spill instructions for NumAlignedDPRCS2Regs D-registers
1059 /// starting from d8. Also insert stack realignment code and leave the stack
1060 /// pointer pointing to the d8 spill slot.
1061 static void emitAlignedDPRCS2Spills(MachineBasicBlock &MBB,
1062 MachineBasicBlock::iterator MI,
1063 unsigned NumAlignedDPRCS2Regs,
1064 const std::vector<CalleeSavedInfo> &CSI,
1065 const TargetRegisterInfo *TRI) {
1066 MachineFunction &MF = *MBB.getParent();
1067 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1068 DebugLoc DL = MI->getDebugLoc();
1069 const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
1070 MachineFrameInfo &MFI = *MF.getFrameInfo();
1072 // Mark the D-register spill slots as properly aligned. Since MFI computes
1073 // stack slot layout backwards, this can actually mean that the d-reg stack
1074 // slot offsets can be wrong. The offset for d8 will always be correct.
1075 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
1076 unsigned DNum = CSI[i].getReg() - ARM::D8;
1079 int FI = CSI[i].getFrameIdx();
1080 // The even-numbered registers will be 16-byte aligned, the odd-numbered
1081 // registers will be 8-byte aligned.
1082 MFI.setObjectAlignment(FI, DNum % 2 ? 8 : 16);
1084 // The stack slot for D8 needs to be maximally aligned because this is
1085 // actually the point where we align the stack pointer. MachineFrameInfo
1086 // computes all offsets relative to the incoming stack pointer which is a
1087 // bit weird when realigning the stack. Any extra padding for this
1088 // over-alignment is not realized because the code inserted below adjusts
1089 // the stack pointer by numregs * 8 before aligning the stack pointer.
1091 MFI.setObjectAlignment(FI, MFI.getMaxAlignment());
1094 // Move the stack pointer to the d8 spill slot, and align it at the same
1095 // time. Leave the stack slot address in the scratch register r4.
1097 // sub r4, sp, #numregs * 8
1098 // bic r4, r4, #align - 1
1101 bool isThumb = AFI->isThumbFunction();
1102 assert(!AFI->isThumb1OnlyFunction() && "Can't realign stack for thumb1");
1103 AFI->setShouldRestoreSPFromFP(true);
1105 // sub r4, sp, #numregs * 8
1106 // The immediate is <= 64, so it doesn't need any special encoding.
1107 unsigned Opc = isThumb ? ARM::t2SUBri : ARM::SUBri;
1108 AddDefaultCC(AddDefaultPred(BuildMI(MBB, MI, DL, TII.get(Opc), ARM::R4)
1110 .addImm(8 * NumAlignedDPRCS2Regs)));
1112 unsigned MaxAlign = MF.getFrameInfo()->getMaxAlignment();
1113 // We must set parameter MustBeSingleInstruction to true, since
1114 // skipAlignedDPRCS2Spills expects exactly 3 instructions to perform
1115 // stack alignment. Luckily, this can always be done since all ARM
1116 // architecture versions that support Neon also support the BFC
1118 emitAligningInstructions(MF, AFI, TII, MBB, MI, DL, ARM::R4, MaxAlign, true);
1121 // The stack pointer must be adjusted before spilling anything, otherwise
1122 // the stack slots could be clobbered by an interrupt handler.
1123 // Leave r4 live, it is used below.
1124 Opc = isThumb ? ARM::tMOVr : ARM::MOVr;
1125 MachineInstrBuilder MIB = BuildMI(MBB, MI, DL, TII.get(Opc), ARM::SP)
1127 MIB = AddDefaultPred(MIB);
1131 // Now spill NumAlignedDPRCS2Regs registers starting from d8.
1132 // r4 holds the stack slot address.
1133 unsigned NextReg = ARM::D8;
1135 // 16-byte aligned vst1.64 with 4 d-regs and address writeback.
1136 // The writeback is only needed when emitting two vst1.64 instructions.
1137 if (NumAlignedDPRCS2Regs >= 6) {
1138 unsigned SupReg = TRI->getMatchingSuperReg(NextReg, ARM::dsub_0,
1139 &ARM::QQPRRegClass);
1140 MBB.addLiveIn(SupReg);
1141 AddDefaultPred(BuildMI(MBB, MI, DL, TII.get(ARM::VST1d64Qwb_fixed),
1143 .addReg(ARM::R4, RegState::Kill).addImm(16)
1145 .addReg(SupReg, RegState::ImplicitKill));
1147 NumAlignedDPRCS2Regs -= 4;
1150 // We won't modify r4 beyond this point. It currently points to the next
1151 // register to be spilled.
1152 unsigned R4BaseReg = NextReg;
1154 // 16-byte aligned vst1.64 with 4 d-regs, no writeback.
1155 if (NumAlignedDPRCS2Regs >= 4) {
1156 unsigned SupReg = TRI->getMatchingSuperReg(NextReg, ARM::dsub_0,
1157 &ARM::QQPRRegClass);
1158 MBB.addLiveIn(SupReg);
1159 AddDefaultPred(BuildMI(MBB, MI, DL, TII.get(ARM::VST1d64Q))
1160 .addReg(ARM::R4).addImm(16).addReg(NextReg)
1161 .addReg(SupReg, RegState::ImplicitKill));
1163 NumAlignedDPRCS2Regs -= 4;
1166 // 16-byte aligned vst1.64 with 2 d-regs.
1167 if (NumAlignedDPRCS2Regs >= 2) {
1168 unsigned SupReg = TRI->getMatchingSuperReg(NextReg, ARM::dsub_0,
1170 MBB.addLiveIn(SupReg);
1171 AddDefaultPred(BuildMI(MBB, MI, DL, TII.get(ARM::VST1q64))
1172 .addReg(ARM::R4).addImm(16).addReg(SupReg));
1174 NumAlignedDPRCS2Regs -= 2;
1177 // Finally, use a vanilla vstr.64 for the odd last register.
1178 if (NumAlignedDPRCS2Regs) {
1179 MBB.addLiveIn(NextReg);
1180 // vstr.64 uses addrmode5 which has an offset scale of 4.
1181 AddDefaultPred(BuildMI(MBB, MI, DL, TII.get(ARM::VSTRD))
1183 .addReg(ARM::R4).addImm((NextReg-R4BaseReg)*2));
1186 // The last spill instruction inserted should kill the scratch register r4.
1187 std::prev(MI)->addRegisterKilled(ARM::R4, TRI);
1190 /// Skip past the code inserted by emitAlignedDPRCS2Spills, and return an
1191 /// iterator to the following instruction.
1192 static MachineBasicBlock::iterator
1193 skipAlignedDPRCS2Spills(MachineBasicBlock::iterator MI,
1194 unsigned NumAlignedDPRCS2Regs) {
1195 // sub r4, sp, #numregs * 8
1196 // bic r4, r4, #align - 1
1199 assert(MI->mayStore() && "Expecting spill instruction");
1201 // These switches all fall through.
1202 switch(NumAlignedDPRCS2Regs) {
1205 assert(MI->mayStore() && "Expecting spill instruction");
1208 assert(MI->mayStore() && "Expecting spill instruction");
1212 assert(MI->killsRegister(ARM::R4) && "Missed kill flag");
1218 /// Emit aligned reload instructions for NumAlignedDPRCS2Regs D-registers
1219 /// starting from d8. These instructions are assumed to execute while the
1220 /// stack is still aligned, unlike the code inserted by emitPopInst.
1221 static void emitAlignedDPRCS2Restores(MachineBasicBlock &MBB,
1222 MachineBasicBlock::iterator MI,
1223 unsigned NumAlignedDPRCS2Regs,
1224 const std::vector<CalleeSavedInfo> &CSI,
1225 const TargetRegisterInfo *TRI) {
1226 MachineFunction &MF = *MBB.getParent();
1227 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1228 DebugLoc DL = MI->getDebugLoc();
1229 const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
1231 // Find the frame index assigned to d8.
1233 for (unsigned i = 0, e = CSI.size(); i != e; ++i)
1234 if (CSI[i].getReg() == ARM::D8) {
1235 D8SpillFI = CSI[i].getFrameIdx();
1239 // Materialize the address of the d8 spill slot into the scratch register r4.
1240 // This can be fairly complicated if the stack frame is large, so just use
1241 // the normal frame index elimination mechanism to do it. This code runs as
1242 // the initial part of the epilog where the stack and base pointers haven't
1243 // been changed yet.
1244 bool isThumb = AFI->isThumbFunction();
1245 assert(!AFI->isThumb1OnlyFunction() && "Can't realign stack for thumb1");
1247 unsigned Opc = isThumb ? ARM::t2ADDri : ARM::ADDri;
1248 AddDefaultCC(AddDefaultPred(BuildMI(MBB, MI, DL, TII.get(Opc), ARM::R4)
1249 .addFrameIndex(D8SpillFI).addImm(0)));
1251 // Now restore NumAlignedDPRCS2Regs registers starting from d8.
1252 unsigned NextReg = ARM::D8;
1254 // 16-byte aligned vld1.64 with 4 d-regs and writeback.
1255 if (NumAlignedDPRCS2Regs >= 6) {
1256 unsigned SupReg = TRI->getMatchingSuperReg(NextReg, ARM::dsub_0,
1257 &ARM::QQPRRegClass);
1258 AddDefaultPred(BuildMI(MBB, MI, DL, TII.get(ARM::VLD1d64Qwb_fixed), NextReg)
1259 .addReg(ARM::R4, RegState::Define)
1260 .addReg(ARM::R4, RegState::Kill).addImm(16)
1261 .addReg(SupReg, RegState::ImplicitDefine));
1263 NumAlignedDPRCS2Regs -= 4;
1266 // We won't modify r4 beyond this point. It currently points to the next
1267 // register to be spilled.
1268 unsigned R4BaseReg = NextReg;
1270 // 16-byte aligned vld1.64 with 4 d-regs, no writeback.
1271 if (NumAlignedDPRCS2Regs >= 4) {
1272 unsigned SupReg = TRI->getMatchingSuperReg(NextReg, ARM::dsub_0,
1273 &ARM::QQPRRegClass);
1274 AddDefaultPred(BuildMI(MBB, MI, DL, TII.get(ARM::VLD1d64Q), NextReg)
1275 .addReg(ARM::R4).addImm(16)
1276 .addReg(SupReg, RegState::ImplicitDefine));
1278 NumAlignedDPRCS2Regs -= 4;
1281 // 16-byte aligned vld1.64 with 2 d-regs.
1282 if (NumAlignedDPRCS2Regs >= 2) {
1283 unsigned SupReg = TRI->getMatchingSuperReg(NextReg, ARM::dsub_0,
1285 AddDefaultPred(BuildMI(MBB, MI, DL, TII.get(ARM::VLD1q64), SupReg)
1286 .addReg(ARM::R4).addImm(16));
1288 NumAlignedDPRCS2Regs -= 2;
1291 // Finally, use a vanilla vldr.64 for the remaining odd register.
1292 if (NumAlignedDPRCS2Regs)
1293 AddDefaultPred(BuildMI(MBB, MI, DL, TII.get(ARM::VLDRD), NextReg)
1294 .addReg(ARM::R4).addImm(2*(NextReg-R4BaseReg)));
1296 // Last store kills r4.
1297 std::prev(MI)->addRegisterKilled(ARM::R4, TRI);
1300 bool ARMFrameLowering::spillCalleeSavedRegisters(MachineBasicBlock &MBB,
1301 MachineBasicBlock::iterator MI,
1302 const std::vector<CalleeSavedInfo> &CSI,
1303 const TargetRegisterInfo *TRI) const {
1307 MachineFunction &MF = *MBB.getParent();
1308 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1310 unsigned PushOpc = AFI->isThumbFunction() ? ARM::t2STMDB_UPD : ARM::STMDB_UPD;
1311 unsigned PushOneOpc = AFI->isThumbFunction() ?
1312 ARM::t2STR_PRE : ARM::STR_PRE_IMM;
1313 unsigned FltOpc = ARM::VSTMDDB_UPD;
1314 unsigned NumAlignedDPRCS2Regs = AFI->getNumAlignedDPRCS2Regs();
1315 emitPushInst(MBB, MI, CSI, PushOpc, PushOneOpc, false, &isARMArea1Register, 0,
1316 MachineInstr::FrameSetup);
1317 emitPushInst(MBB, MI, CSI, PushOpc, PushOneOpc, false, &isARMArea2Register, 0,
1318 MachineInstr::FrameSetup);
1319 emitPushInst(MBB, MI, CSI, FltOpc, 0, true, &isARMArea3Register,
1320 NumAlignedDPRCS2Regs, MachineInstr::FrameSetup);
1322 // The code above does not insert spill code for the aligned DPRCS2 registers.
1323 // The stack realignment code will be inserted between the push instructions
1324 // and these spills.
1325 if (NumAlignedDPRCS2Regs)
1326 emitAlignedDPRCS2Spills(MBB, MI, NumAlignedDPRCS2Regs, CSI, TRI);
1331 bool ARMFrameLowering::restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
1332 MachineBasicBlock::iterator MI,
1333 const std::vector<CalleeSavedInfo> &CSI,
1334 const TargetRegisterInfo *TRI) const {
1338 MachineFunction &MF = *MBB.getParent();
1339 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1340 bool isVarArg = AFI->getArgRegsSaveSize() > 0;
1341 unsigned NumAlignedDPRCS2Regs = AFI->getNumAlignedDPRCS2Regs();
1343 // The emitPopInst calls below do not insert reloads for the aligned DPRCS2
1344 // registers. Do that here instead.
1345 if (NumAlignedDPRCS2Regs)
1346 emitAlignedDPRCS2Restores(MBB, MI, NumAlignedDPRCS2Regs, CSI, TRI);
1348 unsigned PopOpc = AFI->isThumbFunction() ? ARM::t2LDMIA_UPD : ARM::LDMIA_UPD;
1349 unsigned LdrOpc = AFI->isThumbFunction() ? ARM::t2LDR_POST :ARM::LDR_POST_IMM;
1350 unsigned FltOpc = ARM::VLDMDIA_UPD;
1351 emitPopInst(MBB, MI, CSI, FltOpc, 0, isVarArg, true, &isARMArea3Register,
1352 NumAlignedDPRCS2Regs);
1353 emitPopInst(MBB, MI, CSI, PopOpc, LdrOpc, isVarArg, false,
1354 &isARMArea2Register, 0);
1355 emitPopInst(MBB, MI, CSI, PopOpc, LdrOpc, isVarArg, false,
1356 &isARMArea1Register, 0);
1361 // FIXME: Make generic?
1362 static unsigned GetFunctionSizeInBytes(const MachineFunction &MF,
1363 const ARMBaseInstrInfo &TII) {
1364 unsigned FnSize = 0;
1365 for (auto &MBB : MF) {
1366 for (auto &MI : MBB)
1367 FnSize += TII.GetInstSizeInBytes(&MI);
1372 /// estimateRSStackSizeLimit - Look at each instruction that references stack
1373 /// frames and return the stack size limit beyond which some of these
1374 /// instructions will require a scratch register during their expansion later.
1375 // FIXME: Move to TII?
1376 static unsigned estimateRSStackSizeLimit(MachineFunction &MF,
1377 const TargetFrameLowering *TFI) {
1378 const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1379 unsigned Limit = (1 << 12) - 1;
1380 for (auto &MBB : MF) {
1381 for (auto &MI : MBB) {
1382 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
1383 if (!MI.getOperand(i).isFI())
1386 // When using ADDri to get the address of a stack object, 255 is the
1387 // largest offset guaranteed to fit in the immediate offset.
1388 if (MI.getOpcode() == ARM::ADDri) {
1389 Limit = std::min(Limit, (1U << 8) - 1);
1393 // Otherwise check the addressing mode.
1394 switch (MI.getDesc().TSFlags & ARMII::AddrModeMask) {
1395 case ARMII::AddrMode3:
1396 case ARMII::AddrModeT2_i8:
1397 Limit = std::min(Limit, (1U << 8) - 1);
1399 case ARMII::AddrMode5:
1400 case ARMII::AddrModeT2_i8s4:
1401 Limit = std::min(Limit, ((1U << 8) - 1) * 4);
1403 case ARMII::AddrModeT2_i12:
1404 // i12 supports only positive offset so these will be converted to
1405 // i8 opcodes. See llvm::rewriteT2FrameIndex.
1406 if (TFI->hasFP(MF) && AFI->hasStackFrame())
1407 Limit = std::min(Limit, (1U << 8) - 1);
1409 case ARMII::AddrMode4:
1410 case ARMII::AddrMode6:
1411 // Addressing modes 4 & 6 (load/store) instructions can't encode an
1412 // immediate offset for stack references.
1417 break; // At most one FI per instruction
1425 // In functions that realign the stack, it can be an advantage to spill the
1426 // callee-saved vector registers after realigning the stack. The vst1 and vld1
1427 // instructions take alignment hints that can improve performance.
1430 checkNumAlignedDPRCS2Regs(MachineFunction &MF, BitVector &SavedRegs) {
1431 MF.getInfo<ARMFunctionInfo>()->setNumAlignedDPRCS2Regs(0);
1432 if (!SpillAlignedNEONRegs)
1435 // Naked functions don't spill callee-saved registers.
1436 if (MF.getFunction()->hasFnAttribute(Attribute::Naked))
1439 // We are planning to use NEON instructions vst1 / vld1.
1440 if (!static_cast<const ARMSubtarget &>(MF.getSubtarget()).hasNEON())
1443 // Don't bother if the default stack alignment is sufficiently high.
1444 if (MF.getSubtarget().getFrameLowering()->getStackAlignment() >= 8)
1447 // Aligned spills require stack realignment.
1448 if (!static_cast<const ARMBaseRegisterInfo *>(
1449 MF.getSubtarget().getRegisterInfo())->canRealignStack(MF))
1452 // We always spill contiguous d-registers starting from d8. Count how many
1453 // needs spilling. The register allocator will almost always use the
1454 // callee-saved registers in order, but it can happen that there are holes in
1455 // the range. Registers above the hole will be spilled to the standard DPRCS
1457 unsigned NumSpills = 0;
1458 for (; NumSpills < 8; ++NumSpills)
1459 if (!SavedRegs.test(ARM::D8 + NumSpills))
1462 // Don't do this for just one d-register. It's not worth it.
1466 // Spill the first NumSpills D-registers after realigning the stack.
1467 MF.getInfo<ARMFunctionInfo>()->setNumAlignedDPRCS2Regs(NumSpills);
1469 // A scratch register is required for the vst1 / vld1 instructions.
1470 SavedRegs.set(ARM::R4);
1473 void ARMFrameLowering::determineCalleeSaves(MachineFunction &MF,
1474 BitVector &SavedRegs,
1475 RegScavenger *RS) const {
1476 TargetFrameLowering::determineCalleeSaves(MF, SavedRegs, RS);
1477 // This tells PEI to spill the FP as if it is any other callee-save register
1478 // to take advantage the eliminateFrameIndex machinery. This also ensures it
1479 // is spilled in the order specified by getCalleeSavedRegs() to make it easier
1480 // to combine multiple loads / stores.
1481 bool CanEliminateFrame = true;
1482 bool CS1Spilled = false;
1483 bool LRSpilled = false;
1484 unsigned NumGPRSpills = 0;
1485 SmallVector<unsigned, 4> UnspilledCS1GPRs;
1486 SmallVector<unsigned, 4> UnspilledCS2GPRs;
1487 const ARMBaseRegisterInfo *RegInfo = static_cast<const ARMBaseRegisterInfo *>(
1488 MF.getSubtarget().getRegisterInfo());
1489 const ARMBaseInstrInfo &TII =
1490 *static_cast<const ARMBaseInstrInfo *>(MF.getSubtarget().getInstrInfo());
1491 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1492 MachineFrameInfo *MFI = MF.getFrameInfo();
1493 MachineRegisterInfo &MRI = MF.getRegInfo();
1494 unsigned FramePtr = RegInfo->getFrameRegister(MF);
1496 // Spill R4 if Thumb2 function requires stack realignment - it will be used as
1497 // scratch register. Also spill R4 if Thumb2 function has varsized objects,
1498 // since it's not always possible to restore sp from fp in a single
1500 // FIXME: It will be better just to find spare register here.
1501 if (AFI->isThumb2Function() &&
1502 (MFI->hasVarSizedObjects() || RegInfo->needsStackRealignment(MF)))
1503 SavedRegs.set(ARM::R4);
1505 if (AFI->isThumb1OnlyFunction()) {
1506 // Spill LR if Thumb1 function uses variable length argument lists.
1507 if (AFI->getArgRegsSaveSize() > 0)
1508 SavedRegs.set(ARM::LR);
1510 // Spill R4 if Thumb1 epilogue has to restore SP from FP. We don't know
1511 // for sure what the stack size will be, but for this, an estimate is good
1512 // enough. If there anything changes it, it'll be a spill, which implies
1513 // we've used all the registers and so R4 is already used, so not marking
1514 // it here will be OK.
1515 // FIXME: It will be better just to find spare register here.
1516 unsigned StackSize = MFI->estimateStackSize(MF);
1517 if (MFI->hasVarSizedObjects() || StackSize > 508)
1518 SavedRegs.set(ARM::R4);
1521 // See if we can spill vector registers to aligned stack.
1522 checkNumAlignedDPRCS2Regs(MF, SavedRegs);
1524 // Spill the BasePtr if it's used.
1525 if (RegInfo->hasBasePointer(MF))
1526 SavedRegs.set(RegInfo->getBaseRegister());
1528 // Don't spill FP if the frame can be eliminated. This is determined
1529 // by scanning the callee-save registers to see if any is modified.
1530 const MCPhysReg *CSRegs = RegInfo->getCalleeSavedRegs(&MF);
1531 for (unsigned i = 0; CSRegs[i]; ++i) {
1532 unsigned Reg = CSRegs[i];
1533 bool Spilled = false;
1534 if (SavedRegs.test(Reg)) {
1536 CanEliminateFrame = false;
1539 if (!ARM::GPRRegClass.contains(Reg))
1545 if (!STI.isTargetDarwin()) {
1552 // Keep track if LR and any of R4, R5, R6, and R7 is spilled.
1557 case ARM::R0: case ARM::R1:
1558 case ARM::R2: case ARM::R3:
1559 case ARM::R4: case ARM::R5:
1560 case ARM::R6: case ARM::R7:
1567 if (!STI.isTargetDarwin()) {
1568 UnspilledCS1GPRs.push_back(Reg);
1573 case ARM::R0: case ARM::R1:
1574 case ARM::R2: case ARM::R3:
1575 case ARM::R4: case ARM::R5:
1576 case ARM::R6: case ARM::R7:
1578 UnspilledCS1GPRs.push_back(Reg);
1581 UnspilledCS2GPRs.push_back(Reg);
1587 bool ForceLRSpill = false;
1588 if (!LRSpilled && AFI->isThumb1OnlyFunction()) {
1589 unsigned FnSize = GetFunctionSizeInBytes(MF, TII);
1590 // Force LR to be spilled if the Thumb function size is > 2048. This enables
1591 // use of BL to implement far jump. If it turns out that it's not needed
1592 // then the branch fix up path will undo it.
1593 if (FnSize >= (1 << 11)) {
1594 CanEliminateFrame = false;
1595 ForceLRSpill = true;
1599 // If any of the stack slot references may be out of range of an immediate
1600 // offset, make sure a register (or a spill slot) is available for the
1601 // register scavenger. Note that if we're indexing off the frame pointer, the
1602 // effective stack size is 4 bytes larger since the FP points to the stack
1603 // slot of the previous FP. Also, if we have variable sized objects in the
1604 // function, stack slot references will often be negative, and some of
1605 // our instructions are positive-offset only, so conservatively consider
1606 // that case to want a spill slot (or register) as well. Similarly, if
1607 // the function adjusts the stack pointer during execution and the
1608 // adjustments aren't already part of our stack size estimate, our offset
1609 // calculations may be off, so be conservative.
1610 // FIXME: We could add logic to be more precise about negative offsets
1611 // and which instructions will need a scratch register for them. Is it
1612 // worth the effort and added fragility?
1615 (MFI->estimateStackSize(MF) +
1616 ((hasFP(MF) && AFI->hasStackFrame()) ? 4:0) >=
1617 estimateRSStackSizeLimit(MF, this)))
1618 || MFI->hasVarSizedObjects()
1619 || (MFI->adjustsStack() && !canSimplifyCallFramePseudos(MF));
1621 bool ExtraCSSpill = false;
1622 if (BigStack || !CanEliminateFrame || RegInfo->cannotEliminateFrame(MF)) {
1623 AFI->setHasStackFrame(true);
1625 // If LR is not spilled, but at least one of R4, R5, R6, and R7 is spilled.
1626 // Spill LR as well so we can fold BX_RET to the registers restore (LDM).
1627 if (!LRSpilled && CS1Spilled) {
1628 SavedRegs.set(ARM::LR);
1630 SmallVectorImpl<unsigned>::iterator LRPos;
1631 LRPos = std::find(UnspilledCS1GPRs.begin(), UnspilledCS1GPRs.end(),
1633 if (LRPos != UnspilledCS1GPRs.end())
1634 UnspilledCS1GPRs.erase(LRPos);
1636 ForceLRSpill = false;
1637 ExtraCSSpill = true;
1641 SavedRegs.set(FramePtr);
1642 auto FPPos = std::find(UnspilledCS1GPRs.begin(), UnspilledCS1GPRs.end(),
1644 if (FPPos != UnspilledCS1GPRs.end())
1645 UnspilledCS1GPRs.erase(FPPos);
1649 // If stack and double are 8-byte aligned and we are spilling an odd number
1650 // of GPRs, spill one extra callee save GPR so we won't have to pad between
1651 // the integer and double callee save areas.
1652 unsigned TargetAlign = getStackAlignment();
1653 if (TargetAlign >= 8 && (NumGPRSpills & 1)) {
1654 if (CS1Spilled && !UnspilledCS1GPRs.empty()) {
1655 for (unsigned i = 0, e = UnspilledCS1GPRs.size(); i != e; ++i) {
1656 unsigned Reg = UnspilledCS1GPRs[i];
1657 // Don't spill high register if the function is thumb
1658 if (!AFI->isThumbFunction() ||
1659 isARMLowRegister(Reg) || Reg == ARM::LR) {
1661 if (!MRI.isReserved(Reg))
1662 ExtraCSSpill = true;
1666 } else if (!UnspilledCS2GPRs.empty() && !AFI->isThumb1OnlyFunction()) {
1667 unsigned Reg = UnspilledCS2GPRs.front();
1669 if (!MRI.isReserved(Reg))
1670 ExtraCSSpill = true;
1674 // Estimate if we might need to scavenge a register at some point in order
1675 // to materialize a stack offset. If so, either spill one additional
1676 // callee-saved register or reserve a special spill slot to facilitate
1677 // register scavenging. Thumb1 needs a spill slot for stack pointer
1678 // adjustments also, even when the frame itself is small.
1679 if (BigStack && !ExtraCSSpill) {
1680 // If any non-reserved CS register isn't spilled, just spill one or two
1681 // extra. That should take care of it!
1682 unsigned NumExtras = TargetAlign / 4;
1683 SmallVector<unsigned, 2> Extras;
1684 while (NumExtras && !UnspilledCS1GPRs.empty()) {
1685 unsigned Reg = UnspilledCS1GPRs.back();
1686 UnspilledCS1GPRs.pop_back();
1687 if (!MRI.isReserved(Reg) &&
1688 (!AFI->isThumb1OnlyFunction() || isARMLowRegister(Reg) ||
1690 Extras.push_back(Reg);
1694 // For non-Thumb1 functions, also check for hi-reg CS registers
1695 if (!AFI->isThumb1OnlyFunction()) {
1696 while (NumExtras && !UnspilledCS2GPRs.empty()) {
1697 unsigned Reg = UnspilledCS2GPRs.back();
1698 UnspilledCS2GPRs.pop_back();
1699 if (!MRI.isReserved(Reg)) {
1700 Extras.push_back(Reg);
1705 if (Extras.size() && NumExtras == 0) {
1706 for (unsigned i = 0, e = Extras.size(); i != e; ++i) {
1707 SavedRegs.set(Extras[i]);
1709 } else if (!AFI->isThumb1OnlyFunction()) {
1710 // note: Thumb1 functions spill to R12, not the stack. Reserve a slot
1711 // closest to SP or frame pointer.
1712 const TargetRegisterClass *RC = &ARM::GPRRegClass;
1713 RS->addScavengingFrameIndex(MFI->CreateStackObject(RC->getSize(),
1721 SavedRegs.set(ARM::LR);
1722 AFI->setLRIsSpilledForFarJump(true);
1727 void ARMFrameLowering::
1728 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
1729 MachineBasicBlock::iterator I) const {
1730 const ARMBaseInstrInfo &TII =
1731 *static_cast<const ARMBaseInstrInfo *>(MF.getSubtarget().getInstrInfo());
1732 if (!hasReservedCallFrame(MF)) {
1733 // If we have alloca, convert as follows:
1734 // ADJCALLSTACKDOWN -> sub, sp, sp, amount
1735 // ADJCALLSTACKUP -> add, sp, sp, amount
1736 MachineInstr *Old = I;
1737 DebugLoc dl = Old->getDebugLoc();
1738 unsigned Amount = Old->getOperand(0).getImm();
1740 // We need to keep the stack aligned properly. To do this, we round the
1741 // amount of space needed for the outgoing arguments up to the next
1742 // alignment boundary.
1743 unsigned Align = getStackAlignment();
1744 Amount = (Amount+Align-1)/Align*Align;
1746 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1747 assert(!AFI->isThumb1OnlyFunction() &&
1748 "This eliminateCallFramePseudoInstr does not support Thumb1!");
1749 bool isARM = !AFI->isThumbFunction();
1751 // Replace the pseudo instruction with a new instruction...
1752 unsigned Opc = Old->getOpcode();
1753 int PIdx = Old->findFirstPredOperandIdx();
1754 ARMCC::CondCodes Pred = (PIdx == -1)
1755 ? ARMCC::AL : (ARMCC::CondCodes)Old->getOperand(PIdx).getImm();
1756 if (Opc == ARM::ADJCALLSTACKDOWN || Opc == ARM::tADJCALLSTACKDOWN) {
1757 // Note: PredReg is operand 2 for ADJCALLSTACKDOWN.
1758 unsigned PredReg = Old->getOperand(2).getReg();
1759 emitSPUpdate(isARM, MBB, I, dl, TII, -Amount, MachineInstr::NoFlags,
1762 // Note: PredReg is operand 3 for ADJCALLSTACKUP.
1763 unsigned PredReg = Old->getOperand(3).getReg();
1764 assert(Opc == ARM::ADJCALLSTACKUP || Opc == ARM::tADJCALLSTACKUP);
1765 emitSPUpdate(isARM, MBB, I, dl, TII, Amount, MachineInstr::NoFlags,
1773 /// Get the minimum constant for ARM that is greater than or equal to the
1774 /// argument. In ARM, constants can have any value that can be produced by
1775 /// rotating an 8-bit value to the right by an even number of bits within a
1777 static uint32_t alignToARMConstant(uint32_t Value) {
1778 unsigned Shifted = 0;
1783 while (!(Value & 0xC0000000)) {
1788 bool Carry = (Value & 0x00FFFFFF);
1789 Value = ((Value & 0xFF000000) >> 24) + Carry;
1791 if (Value & 0x0000100)
1792 Value = Value & 0x000001FC;
1795 Value = Value >> (Shifted - 24);
1797 Value = Value << (24 - Shifted);
1802 // The stack limit in the TCB is set to this many bytes above the actual
1804 static const uint64_t kSplitStackAvailable = 256;
1806 // Adjust the function prologue to enable split stacks. This currently only
1807 // supports android and linux.
1809 // The ABI of the segmented stack prologue is a little arbitrarily chosen, but
1810 // must be well defined in order to allow for consistent implementations of the
1811 // __morestack helper function. The ABI is also not a normal ABI in that it
1812 // doesn't follow the normal calling conventions because this allows the
1813 // prologue of each function to be optimized further.
1815 // Currently, the ABI looks like (when calling __morestack)
1817 // * r4 holds the minimum stack size requested for this function call
1818 // * r5 holds the stack size of the arguments to the function
1819 // * the beginning of the function is 3 instructions after the call to
1822 // Implementations of __morestack should use r4 to allocate a new stack, r5 to
1823 // place the arguments on to the new stack, and the 3-instruction knowledge to
1824 // jump directly to the body of the function when working on the new stack.
1826 // An old (and possibly no longer compatible) implementation of __morestack for
1827 // ARM can be found at [1].
1829 // [1] - https://github.com/mozilla/rust/blob/86efd9/src/rt/arch/arm/morestack.S
1830 void ARMFrameLowering::adjustForSegmentedStacks(
1831 MachineFunction &MF, MachineBasicBlock &PrologueMBB) const {
1834 const ARMSubtarget *ST = &MF.getSubtarget<ARMSubtarget>();
1835 bool Thumb = ST->isThumb();
1837 // Sadly, this currently doesn't support varargs, platforms other than
1838 // android/linux. Note that thumb1/thumb2 are support for android/linux.
1839 if (MF.getFunction()->isVarArg())
1840 report_fatal_error("Segmented stacks do not support vararg functions.");
1841 if (!ST->isTargetAndroid() && !ST->isTargetLinux())
1842 report_fatal_error("Segmented stacks not supported on this platform.");
1844 MachineFrameInfo *MFI = MF.getFrameInfo();
1845 MachineModuleInfo &MMI = MF.getMMI();
1846 MCContext &Context = MMI.getContext();
1847 const MCRegisterInfo *MRI = Context.getRegisterInfo();
1848 const ARMBaseInstrInfo &TII =
1849 *static_cast<const ARMBaseInstrInfo *>(MF.getSubtarget().getInstrInfo());
1850 ARMFunctionInfo *ARMFI = MF.getInfo<ARMFunctionInfo>();
1853 uint64_t StackSize = MFI->getStackSize();
1855 // Do not generate a prologue for functions with a stack of size zero
1859 // Use R4 and R5 as scratch registers.
1860 // We save R4 and R5 before use and restore them before leaving the function.
1861 unsigned ScratchReg0 = ARM::R4;
1862 unsigned ScratchReg1 = ARM::R5;
1863 uint64_t AlignedStackSize;
1865 MachineBasicBlock *PrevStackMBB = MF.CreateMachineBasicBlock();
1866 MachineBasicBlock *PostStackMBB = MF.CreateMachineBasicBlock();
1867 MachineBasicBlock *AllocMBB = MF.CreateMachineBasicBlock();
1868 MachineBasicBlock *GetMBB = MF.CreateMachineBasicBlock();
1869 MachineBasicBlock *McrMBB = MF.CreateMachineBasicBlock();
1871 // Grab everything that reaches PrologueMBB to update there liveness as well.
1872 SmallPtrSet<MachineBasicBlock *, 8> BeforePrologueRegion;
1873 SmallVector<MachineBasicBlock *, 2> WalkList;
1874 WalkList.push_back(&PrologueMBB);
1877 MachineBasicBlock *CurMBB = WalkList.pop_back_val();
1878 for (MachineBasicBlock *PredBB : CurMBB->predecessors()) {
1879 if (BeforePrologueRegion.insert(PredBB).second)
1880 WalkList.push_back(PredBB);
1882 } while (!WalkList.empty());
1884 // The order in that list is important.
1885 // The blocks will all be inserted before PrologueMBB using that order.
1886 // Therefore the block that should appear first in the CFG should appear
1887 // first in the list.
1888 MachineBasicBlock *AddedBlocks[] = {PrevStackMBB, McrMBB, GetMBB, AllocMBB,
1890 const int NbAddedBlocks = sizeof(AddedBlocks) / sizeof(AddedBlocks[0]);
1892 for (int Idx = 0; Idx < NbAddedBlocks; ++Idx)
1893 BeforePrologueRegion.insert(AddedBlocks[Idx]);
1895 for (MachineBasicBlock::livein_iterator i = PrologueMBB.livein_begin(),
1896 e = PrologueMBB.livein_end();
1898 for (MachineBasicBlock *PredBB : BeforePrologueRegion)
1899 PredBB->addLiveIn(*i);
1902 // Remove the newly added blocks from the list, since we know
1903 // we do not have to do the following updates for them.
1904 for (int Idx = 0; Idx < NbAddedBlocks; ++Idx) {
1905 BeforePrologueRegion.erase(AddedBlocks[Idx]);
1906 MF.insert(&PrologueMBB, AddedBlocks[Idx]);
1909 for (MachineBasicBlock *MBB : BeforePrologueRegion) {
1910 // Make sure the LiveIns are still sorted and unique.
1911 MBB->sortUniqueLiveIns();
1912 // Replace the edges to PrologueMBB by edges to the sequences
1913 // we are about to add.
1914 MBB->ReplaceUsesOfBlockWith(&PrologueMBB, AddedBlocks[0]);
1917 // The required stack size that is aligned to ARM constant criterion.
1918 AlignedStackSize = alignToARMConstant(StackSize);
1920 // When the frame size is less than 256 we just compare the stack
1921 // boundary directly to the value of the stack pointer, per gcc.
1922 bool CompareStackPointer = AlignedStackSize < kSplitStackAvailable;
1924 // We will use two of the callee save registers as scratch registers so we
1925 // need to save those registers onto the stack.
1926 // We will use SR0 to hold stack limit and SR1 to hold the stack size
1927 // requested and arguments for __morestack().
1928 // SR0: Scratch Register #0
1929 // SR1: Scratch Register #1
1932 AddDefaultPred(BuildMI(PrevStackMBB, DL, TII.get(ARM::tPUSH)))
1933 .addReg(ScratchReg0).addReg(ScratchReg1);
1935 AddDefaultPred(BuildMI(PrevStackMBB, DL, TII.get(ARM::STMDB_UPD))
1936 .addReg(ARM::SP, RegState::Define).addReg(ARM::SP))
1937 .addReg(ScratchReg0).addReg(ScratchReg1);
1940 // Emit the relevant DWARF information about the change in stack pointer as
1941 // well as where to find both r4 and r5 (the callee-save registers)
1943 MMI.addFrameInst(MCCFIInstruction::createDefCfaOffset(nullptr, -8));
1944 BuildMI(PrevStackMBB, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
1945 .addCFIIndex(CFIIndex);
1946 CFIIndex = MMI.addFrameInst(MCCFIInstruction::createOffset(
1947 nullptr, MRI->getDwarfRegNum(ScratchReg1, true), -4));
1948 BuildMI(PrevStackMBB, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
1949 .addCFIIndex(CFIIndex);
1950 CFIIndex = MMI.addFrameInst(MCCFIInstruction::createOffset(
1951 nullptr, MRI->getDwarfRegNum(ScratchReg0, true), -8));
1952 BuildMI(PrevStackMBB, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
1953 .addCFIIndex(CFIIndex);
1957 AddDefaultPred(BuildMI(McrMBB, DL, TII.get(ARM::tMOVr), ScratchReg1)
1959 } else if (CompareStackPointer) {
1960 AddDefaultPred(BuildMI(McrMBB, DL, TII.get(ARM::MOVr), ScratchReg1)
1961 .addReg(ARM::SP)).addReg(0);
1964 // sub SR1, sp, #StackSize
1965 if (!CompareStackPointer && Thumb) {
1967 AddDefaultCC(BuildMI(McrMBB, DL, TII.get(ARM::tSUBi8), ScratchReg1))
1968 .addReg(ScratchReg1).addImm(AlignedStackSize));
1969 } else if (!CompareStackPointer) {
1970 AddDefaultPred(BuildMI(McrMBB, DL, TII.get(ARM::SUBri), ScratchReg1)
1971 .addReg(ARM::SP).addImm(AlignedStackSize)).addReg(0);
1974 if (Thumb && ST->isThumb1Only()) {
1975 unsigned PCLabelId = ARMFI->createPICLabelUId();
1976 ARMConstantPoolValue *NewCPV = ARMConstantPoolSymbol::Create(
1977 MF.getFunction()->getContext(), "__STACK_LIMIT", PCLabelId, 0);
1978 MachineConstantPool *MCP = MF.getConstantPool();
1979 unsigned CPI = MCP->getConstantPoolIndex(NewCPV, MF.getAlignment());
1981 // ldr SR0, [pc, offset(STACK_LIMIT)]
1982 AddDefaultPred(BuildMI(GetMBB, DL, TII.get(ARM::tLDRpci), ScratchReg0)
1983 .addConstantPoolIndex(CPI));
1986 AddDefaultPred(BuildMI(GetMBB, DL, TII.get(ARM::tLDRi), ScratchReg0)
1987 .addReg(ScratchReg0).addImm(0));
1989 // Get TLS base address from the coprocessor
1990 // mrc p15, #0, SR0, c13, c0, #3
1991 AddDefaultPred(BuildMI(McrMBB, DL, TII.get(ARM::MRC), ScratchReg0)
1998 // Use the last tls slot on android and a private field of the TCP on linux.
1999 assert(ST->isTargetAndroid() || ST->isTargetLinux());
2000 unsigned TlsOffset = ST->isTargetAndroid() ? 63 : 1;
2002 // Get the stack limit from the right offset
2003 // ldr SR0, [sr0, #4 * TlsOffset]
2004 AddDefaultPred(BuildMI(GetMBB, DL, TII.get(ARM::LDRi12), ScratchReg0)
2005 .addReg(ScratchReg0).addImm(4 * TlsOffset));
2008 // Compare stack limit with stack size requested.
2010 Opcode = Thumb ? ARM::tCMPr : ARM::CMPrr;
2011 AddDefaultPred(BuildMI(GetMBB, DL, TII.get(Opcode))
2012 .addReg(ScratchReg0)
2013 .addReg(ScratchReg1));
2015 // This jump is taken if StackLimit < SP - stack required.
2016 Opcode = Thumb ? ARM::tBcc : ARM::Bcc;
2017 BuildMI(GetMBB, DL, TII.get(Opcode)).addMBB(PostStackMBB)
2022 // Calling __morestack(StackSize, Size of stack arguments).
2023 // __morestack knows that the stack size requested is in SR0(r4)
2024 // and amount size of stack arguments is in SR1(r5).
2026 // Pass first argument for the __morestack by Scratch Register #0.
2027 // The amount size of stack required
2029 AddDefaultPred(AddDefaultCC(BuildMI(AllocMBB, DL, TII.get(ARM::tMOVi8),
2030 ScratchReg0)).addImm(AlignedStackSize));
2032 AddDefaultPred(BuildMI(AllocMBB, DL, TII.get(ARM::MOVi), ScratchReg0)
2033 .addImm(AlignedStackSize)).addReg(0);
2035 // Pass second argument for the __morestack by Scratch Register #1.
2036 // The amount size of stack consumed to save function arguments.
2039 AddDefaultCC(BuildMI(AllocMBB, DL, TII.get(ARM::tMOVi8), ScratchReg1))
2040 .addImm(alignToARMConstant(ARMFI->getArgumentStackSize())));
2042 AddDefaultPred(BuildMI(AllocMBB, DL, TII.get(ARM::MOVi), ScratchReg1)
2043 .addImm(alignToARMConstant(ARMFI->getArgumentStackSize())))
2047 // push {lr} - Save return address of this function.
2049 AddDefaultPred(BuildMI(AllocMBB, DL, TII.get(ARM::tPUSH)))
2052 AddDefaultPred(BuildMI(AllocMBB, DL, TII.get(ARM::STMDB_UPD))
2053 .addReg(ARM::SP, RegState::Define)
2058 // Emit the DWARF info about the change in stack as well as where to find the
2059 // previous link register
2061 MMI.addFrameInst(MCCFIInstruction::createDefCfaOffset(nullptr, -12));
2062 BuildMI(AllocMBB, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
2063 .addCFIIndex(CFIIndex);
2064 CFIIndex = MMI.addFrameInst(MCCFIInstruction::createOffset(
2065 nullptr, MRI->getDwarfRegNum(ARM::LR, true), -12));
2066 BuildMI(AllocMBB, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
2067 .addCFIIndex(CFIIndex);
2069 // Call __morestack().
2071 AddDefaultPred(BuildMI(AllocMBB, DL, TII.get(ARM::tBL)))
2072 .addExternalSymbol("__morestack");
2074 BuildMI(AllocMBB, DL, TII.get(ARM::BL))
2075 .addExternalSymbol("__morestack");
2078 // pop {lr} - Restore return address of this original function.
2080 if (ST->isThumb1Only()) {
2081 AddDefaultPred(BuildMI(AllocMBB, DL, TII.get(ARM::tPOP)))
2082 .addReg(ScratchReg0);
2083 AddDefaultPred(BuildMI(AllocMBB, DL, TII.get(ARM::tMOVr), ARM::LR)
2084 .addReg(ScratchReg0));
2086 AddDefaultPred(BuildMI(AllocMBB, DL, TII.get(ARM::t2LDR_POST))
2087 .addReg(ARM::LR, RegState::Define)
2088 .addReg(ARM::SP, RegState::Define)
2093 AddDefaultPred(BuildMI(AllocMBB, DL, TII.get(ARM::LDMIA_UPD))
2094 .addReg(ARM::SP, RegState::Define)
2099 // Restore SR0 and SR1 in case of __morestack() was called.
2100 // __morestack() will skip PostStackMBB block so we need to restore
2101 // scratch registers from here.
2104 AddDefaultPred(BuildMI(AllocMBB, DL, TII.get(ARM::tPOP)))
2105 .addReg(ScratchReg0)
2106 .addReg(ScratchReg1);
2108 AddDefaultPred(BuildMI(AllocMBB, DL, TII.get(ARM::LDMIA_UPD))
2109 .addReg(ARM::SP, RegState::Define)
2111 .addReg(ScratchReg0)
2112 .addReg(ScratchReg1);
2115 // Update the CFA offset now that we've popped
2116 CFIIndex = MMI.addFrameInst(MCCFIInstruction::createDefCfaOffset(nullptr, 0));
2117 BuildMI(AllocMBB, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
2118 .addCFIIndex(CFIIndex);
2120 // bx lr - Return from this function.
2121 Opcode = Thumb ? ARM::tBX_RET : ARM::BX_RET;
2122 AddDefaultPred(BuildMI(AllocMBB, DL, TII.get(Opcode)));
2124 // Restore SR0 and SR1 in case of __morestack() was not called.
2127 AddDefaultPred(BuildMI(PostStackMBB, DL, TII.get(ARM::tPOP)))
2128 .addReg(ScratchReg0)
2129 .addReg(ScratchReg1);
2131 AddDefaultPred(BuildMI(PostStackMBB, DL, TII.get(ARM::LDMIA_UPD))
2132 .addReg(ARM::SP, RegState::Define)
2134 .addReg(ScratchReg0)
2135 .addReg(ScratchReg1);
2138 // Update the CFA offset now that we've popped
2139 CFIIndex = MMI.addFrameInst(MCCFIInstruction::createDefCfaOffset(nullptr, 0));
2140 BuildMI(PostStackMBB, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
2141 .addCFIIndex(CFIIndex);
2143 // Tell debuggers that r4 and r5 are now the same as they were in the
2144 // previous function, that they're the "Same Value".
2145 CFIIndex = MMI.addFrameInst(MCCFIInstruction::createSameValue(
2146 nullptr, MRI->getDwarfRegNum(ScratchReg0, true)));
2147 BuildMI(PostStackMBB, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
2148 .addCFIIndex(CFIIndex);
2149 CFIIndex = MMI.addFrameInst(MCCFIInstruction::createSameValue(
2150 nullptr, MRI->getDwarfRegNum(ScratchReg1, true)));
2151 BuildMI(PostStackMBB, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
2152 .addCFIIndex(CFIIndex);
2154 // Organizing MBB lists
2155 PostStackMBB->addSuccessor(&PrologueMBB);
2157 AllocMBB->addSuccessor(PostStackMBB);
2159 GetMBB->addSuccessor(PostStackMBB);
2160 GetMBB->addSuccessor(AllocMBB);
2162 McrMBB->addSuccessor(GetMBB);
2164 PrevStackMBB->addSuccessor(McrMBB);