1 //===-- ARMFrameLowering.cpp - ARM Frame Information ----------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the ARM implementation of TargetFrameLowering class.
12 //===----------------------------------------------------------------------===//
14 #include "ARMFrameLowering.h"
15 #include "ARMBaseInstrInfo.h"
16 #include "ARMBaseRegisterInfo.h"
17 #include "ARMMachineFunctionInfo.h"
18 #include "MCTargetDesc/ARMAddressingModes.h"
19 #include "llvm/CallingConv.h"
20 #include "llvm/CodeGen/MachineFrameInfo.h"
21 #include "llvm/CodeGen/MachineFunction.h"
22 #include "llvm/CodeGen/MachineInstrBuilder.h"
23 #include "llvm/CodeGen/MachineRegisterInfo.h"
24 #include "llvm/CodeGen/RegisterScavenging.h"
25 #include "llvm/Function.h"
26 #include "llvm/Support/CommandLine.h"
27 #include "llvm/Target/TargetOptions.h"
32 SpillAlignedNEONRegs("align-neon-spills", cl::Hidden, cl::init(true),
33 cl::desc("Align ARM NEON spills in prolog and epilog"));
35 static MachineBasicBlock::iterator
36 skipAlignedDPRCS2Spills(MachineBasicBlock::iterator MI,
37 unsigned NumAlignedDPRCS2Regs);
39 /// hasFP - Return true if the specified function should have a dedicated frame
40 /// pointer register. This is true if the function has variable sized allocas
41 /// or if frame pointer elimination is disabled.
42 bool ARMFrameLowering::hasFP(const MachineFunction &MF) const {
43 const TargetRegisterInfo *RegInfo = MF.getTarget().getRegisterInfo();
45 // iOS requires FP not to be clobbered for backtracing purpose.
46 if (STI.isTargetIOS())
49 const MachineFrameInfo *MFI = MF.getFrameInfo();
50 // Always eliminate non-leaf frame pointers.
51 return ((MF.getTarget().Options.DisableFramePointerElim(MF) &&
53 RegInfo->needsStackRealignment(MF) ||
54 MFI->hasVarSizedObjects() ||
55 MFI->isFrameAddressTaken());
58 /// hasReservedCallFrame - Under normal circumstances, when a frame pointer is
59 /// not required, we reserve argument space for call sites in the function
60 /// immediately on entry to the current function. This eliminates the need for
61 /// add/sub sp brackets around call sites. Returns true if the call frame is
62 /// included as part of the stack frame.
63 bool ARMFrameLowering::hasReservedCallFrame(const MachineFunction &MF) const {
64 const MachineFrameInfo *FFI = MF.getFrameInfo();
65 unsigned CFSize = FFI->getMaxCallFrameSize();
66 // It's not always a good idea to include the call frame as part of the
67 // stack frame. ARM (especially Thumb) has small immediate offset to
68 // address the stack frame. So a large call frame can cause poor codegen
69 // and may even makes it impossible to scavenge a register.
70 if (CFSize >= ((1 << 12) - 1) / 2) // Half of imm12
73 return !MF.getFrameInfo()->hasVarSizedObjects();
76 /// canSimplifyCallFramePseudos - If there is a reserved call frame, the
77 /// call frame pseudos can be simplified. Unlike most targets, having a FP
78 /// is not sufficient here since we still may reference some objects via SP
79 /// even when FP is available in Thumb2 mode.
81 ARMFrameLowering::canSimplifyCallFramePseudos(const MachineFunction &MF) const {
82 return hasReservedCallFrame(MF) || MF.getFrameInfo()->hasVarSizedObjects();
85 static bool isCalleeSavedRegister(unsigned Reg, const uint16_t *CSRegs) {
86 for (unsigned i = 0; CSRegs[i]; ++i)
92 static bool isCSRestore(MachineInstr *MI,
93 const ARMBaseInstrInfo &TII,
94 const uint16_t *CSRegs) {
95 // Integer spill area is handled with "pop".
96 if (MI->getOpcode() == ARM::LDMIA_RET ||
97 MI->getOpcode() == ARM::t2LDMIA_RET ||
98 MI->getOpcode() == ARM::LDMIA_UPD ||
99 MI->getOpcode() == ARM::t2LDMIA_UPD ||
100 MI->getOpcode() == ARM::VLDMDIA_UPD) {
101 // The first two operands are predicates. The last two are
102 // imp-def and imp-use of SP. Check everything in between.
103 for (int i = 5, e = MI->getNumOperands(); i != e; ++i)
104 if (!isCalleeSavedRegister(MI->getOperand(i).getReg(), CSRegs))
108 if ((MI->getOpcode() == ARM::LDR_POST_IMM ||
109 MI->getOpcode() == ARM::LDR_POST_REG ||
110 MI->getOpcode() == ARM::t2LDR_POST) &&
111 isCalleeSavedRegister(MI->getOperand(0).getReg(), CSRegs) &&
112 MI->getOperand(1).getReg() == ARM::SP)
119 emitSPUpdate(bool isARM,
120 MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,
121 DebugLoc dl, const ARMBaseInstrInfo &TII,
122 int NumBytes, unsigned MIFlags = MachineInstr::NoFlags) {
124 emitARMRegPlusImmediate(MBB, MBBI, dl, ARM::SP, ARM::SP, NumBytes,
125 ARMCC::AL, 0, TII, MIFlags);
127 emitT2RegPlusImmediate(MBB, MBBI, dl, ARM::SP, ARM::SP, NumBytes,
128 ARMCC::AL, 0, TII, MIFlags);
131 void ARMFrameLowering::emitPrologue(MachineFunction &MF) const {
132 MachineBasicBlock &MBB = MF.front();
133 MachineBasicBlock::iterator MBBI = MBB.begin();
134 MachineFrameInfo *MFI = MF.getFrameInfo();
135 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
136 const ARMBaseRegisterInfo *RegInfo =
137 static_cast<const ARMBaseRegisterInfo*>(MF.getTarget().getRegisterInfo());
138 const ARMBaseInstrInfo &TII =
139 *static_cast<const ARMBaseInstrInfo*>(MF.getTarget().getInstrInfo());
140 assert(!AFI->isThumb1OnlyFunction() &&
141 "This emitPrologue does not support Thumb1!");
142 bool isARM = !AFI->isThumbFunction();
143 unsigned VARegSaveSize = AFI->getVarArgsRegSaveSize();
144 unsigned NumBytes = MFI->getStackSize();
145 const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
146 DebugLoc dl = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
147 unsigned FramePtr = RegInfo->getFrameRegister(MF);
149 // Determine the sizes of each callee-save spill areas and record which frame
150 // belongs to which callee-save spill areas.
151 unsigned GPRCS1Size = 0, GPRCS2Size = 0, DPRCSSize = 0;
152 int FramePtrSpillFI = 0;
155 // All calls are tail calls in GHC calling conv, and functions have no
156 // prologue/epilogue.
157 if (MF.getFunction()->getCallingConv() == CallingConv::GHC)
160 // Allocate the vararg register save area. This is not counted in NumBytes.
162 emitSPUpdate(isARM, MBB, MBBI, dl, TII, -VARegSaveSize,
163 MachineInstr::FrameSetup);
165 if (!AFI->hasStackFrame()) {
167 emitSPUpdate(isARM, MBB, MBBI, dl, TII, -NumBytes,
168 MachineInstr::FrameSetup);
172 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
173 unsigned Reg = CSI[i].getReg();
174 int FI = CSI[i].getFrameIdx();
182 FramePtrSpillFI = FI;
183 AFI->addGPRCalleeSavedArea1Frame(FI);
191 FramePtrSpillFI = FI;
192 if (STI.isTargetIOS()) {
193 AFI->addGPRCalleeSavedArea2Frame(FI);
196 AFI->addGPRCalleeSavedArea1Frame(FI);
201 // This is a DPR. Exclude the aligned DPRCS2 spills.
204 if (Reg < ARM::D8 || Reg >= ARM::D8 + AFI->getNumAlignedDPRCS2Regs()) {
205 AFI->addDPRCalleeSavedAreaFrame(FI);
212 if (GPRCS1Size > 0) MBBI++;
214 // Set FP to point to the stack slot that contains the previous FP.
215 // For iOS, FP is R7, which has now been stored in spill area 1.
216 // Otherwise, if this is not iOS, all the callee-saved registers go
217 // into spill area 1, including the FP in R11. In either case, it is
218 // now safe to emit this assignment.
219 bool HasFP = hasFP(MF);
221 unsigned ADDriOpc = !AFI->isThumbFunction() ? ARM::ADDri : ARM::t2ADDri;
222 MachineInstrBuilder MIB =
223 BuildMI(MBB, MBBI, dl, TII.get(ADDriOpc), FramePtr)
224 .addFrameIndex(FramePtrSpillFI).addImm(0)
225 .setMIFlag(MachineInstr::FrameSetup);
226 AddDefaultCC(AddDefaultPred(MIB));
230 if (GPRCS2Size > 0) MBBI++;
232 // Determine starting offsets of spill areas.
233 unsigned DPRCSOffset = NumBytes - (GPRCS1Size + GPRCS2Size + DPRCSSize);
234 unsigned GPRCS2Offset = DPRCSOffset + DPRCSSize;
235 unsigned GPRCS1Offset = GPRCS2Offset + GPRCS2Size;
237 AFI->setFramePtrSpillOffset(MFI->getObjectOffset(FramePtrSpillFI) +
239 AFI->setGPRCalleeSavedArea1Offset(GPRCS1Offset);
240 AFI->setGPRCalleeSavedArea2Offset(GPRCS2Offset);
241 AFI->setDPRCalleeSavedAreaOffset(DPRCSOffset);
246 // Since vpush register list cannot have gaps, there may be multiple vpush
247 // instructions in the prologue.
248 while (MBBI->getOpcode() == ARM::VSTMDDB_UPD)
252 // Move past the aligned DPRCS2 area.
253 if (AFI->getNumAlignedDPRCS2Regs() > 0) {
254 MBBI = skipAlignedDPRCS2Spills(MBBI, AFI->getNumAlignedDPRCS2Regs());
255 // The code inserted by emitAlignedDPRCS2Spills realigns the stack, and
256 // leaves the stack pointer pointing to the DPRCS2 area.
258 // Adjust NumBytes to represent the stack slots below the DPRCS2 area.
259 NumBytes += MFI->getObjectOffset(D8SpillFI);
261 NumBytes = DPRCSOffset;
264 // Adjust SP after all the callee-save spills.
265 emitSPUpdate(isARM, MBB, MBBI, dl, TII, -NumBytes,
266 MachineInstr::FrameSetup);
268 // Restore from fp only in ARM mode: e.g. sub sp, r7, #24
269 // Note it's not safe to do this in Thumb2 mode because it would have
270 // taken two instructions:
273 // If an interrupt is taken between the two instructions, then sp is in
274 // an inconsistent state (pointing to the middle of callee-saved area).
275 // The interrupt handler can end up clobbering the registers.
276 AFI->setShouldRestoreSPFromFP(true);
279 if (STI.isTargetELF() && hasFP(MF))
280 MFI->setOffsetAdjustment(MFI->getOffsetAdjustment() -
281 AFI->getFramePtrSpillOffset());
283 AFI->setGPRCalleeSavedArea1Size(GPRCS1Size);
284 AFI->setGPRCalleeSavedArea2Size(GPRCS2Size);
285 AFI->setDPRCalleeSavedAreaSize(DPRCSSize);
287 // If we need dynamic stack realignment, do it here. Be paranoid and make
288 // sure if we also have VLAs, we have a base pointer for frame access.
289 // If aligned NEON registers were spilled, the stack has already been
291 if (!AFI->getNumAlignedDPRCS2Regs() && RegInfo->needsStackRealignment(MF)) {
292 unsigned MaxAlign = MFI->getMaxAlignment();
293 assert (!AFI->isThumb1OnlyFunction());
294 if (!AFI->isThumbFunction()) {
295 // Emit bic sp, sp, MaxAlign
296 AddDefaultCC(AddDefaultPred(BuildMI(MBB, MBBI, dl,
297 TII.get(ARM::BICri), ARM::SP)
298 .addReg(ARM::SP, RegState::Kill)
299 .addImm(MaxAlign-1)));
301 // We cannot use sp as source/dest register here, thus we're emitting the
302 // following sequence:
304 // bic r4, r4, MaxAlign
306 // FIXME: It will be better just to find spare register here.
307 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), ARM::R4)
308 .addReg(ARM::SP, RegState::Kill));
309 AddDefaultCC(AddDefaultPred(BuildMI(MBB, MBBI, dl,
310 TII.get(ARM::t2BICri), ARM::R4)
311 .addReg(ARM::R4, RegState::Kill)
312 .addImm(MaxAlign-1)));
313 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), ARM::SP)
314 .addReg(ARM::R4, RegState::Kill));
317 AFI->setShouldRestoreSPFromFP(true);
320 // If we need a base pointer, set it up here. It's whatever the value
321 // of the stack pointer is at this point. Any variable size objects
322 // will be allocated after this, so we can still use the base pointer
323 // to reference locals.
324 // FIXME: Clarify FrameSetup flags here.
325 if (RegInfo->hasBasePointer(MF)) {
327 BuildMI(MBB, MBBI, dl,
328 TII.get(ARM::MOVr), RegInfo->getBaseRegister())
330 .addImm((unsigned)ARMCC::AL).addReg(0).addReg(0);
332 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr),
333 RegInfo->getBaseRegister())
337 // If the frame has variable sized objects then the epilogue must restore
338 // the sp from fp. We can assume there's an FP here since hasFP already
339 // checks for hasVarSizedObjects.
340 if (MFI->hasVarSizedObjects())
341 AFI->setShouldRestoreSPFromFP(true);
344 void ARMFrameLowering::emitEpilogue(MachineFunction &MF,
345 MachineBasicBlock &MBB) const {
346 MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr();
347 assert(MBBI->isReturn() && "Can only insert epilog into returning blocks");
348 unsigned RetOpcode = MBBI->getOpcode();
349 DebugLoc dl = MBBI->getDebugLoc();
350 MachineFrameInfo *MFI = MF.getFrameInfo();
351 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
352 const TargetRegisterInfo *RegInfo = MF.getTarget().getRegisterInfo();
353 const ARMBaseInstrInfo &TII =
354 *static_cast<const ARMBaseInstrInfo*>(MF.getTarget().getInstrInfo());
355 assert(!AFI->isThumb1OnlyFunction() &&
356 "This emitEpilogue does not support Thumb1!");
357 bool isARM = !AFI->isThumbFunction();
359 unsigned VARegSaveSize = AFI->getVarArgsRegSaveSize();
360 int NumBytes = (int)MFI->getStackSize();
361 unsigned FramePtr = RegInfo->getFrameRegister(MF);
363 // All calls are tail calls in GHC calling conv, and functions have no
364 // prologue/epilogue.
365 if (MF.getFunction()->getCallingConv() == CallingConv::GHC)
368 if (!AFI->hasStackFrame()) {
370 emitSPUpdate(isARM, MBB, MBBI, dl, TII, NumBytes);
372 // Unwind MBBI to point to first LDR / VLDRD.
373 const uint16_t *CSRegs = RegInfo->getCalleeSavedRegs();
374 if (MBBI != MBB.begin()) {
377 while (MBBI != MBB.begin() && isCSRestore(MBBI, TII, CSRegs));
378 if (!isCSRestore(MBBI, TII, CSRegs))
382 // Move SP to start of FP callee save spill area.
383 NumBytes -= (AFI->getGPRCalleeSavedArea1Size() +
384 AFI->getGPRCalleeSavedArea2Size() +
385 AFI->getDPRCalleeSavedAreaSize());
387 // Reset SP based on frame pointer only if the stack frame extends beyond
388 // frame pointer stack slot or target is ELF and the function has FP.
389 if (AFI->shouldRestoreSPFromFP()) {
390 NumBytes = AFI->getFramePtrSpillOffset() - NumBytes;
393 emitARMRegPlusImmediate(MBB, MBBI, dl, ARM::SP, FramePtr, -NumBytes,
396 // It's not possible to restore SP from FP in a single instruction.
397 // For iOS, this looks like:
400 // This is bad, if an interrupt is taken after the mov, sp is in an
401 // inconsistent state.
402 // Use the first callee-saved register as a scratch register.
403 assert(MF.getRegInfo().isPhysRegUsed(ARM::R4) &&
404 "No scratch register to restore SP from FP!");
405 emitT2RegPlusImmediate(MBB, MBBI, dl, ARM::R4, FramePtr, -NumBytes,
407 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr),
414 BuildMI(MBB, MBBI, dl, TII.get(ARM::MOVr), ARM::SP)
415 .addReg(FramePtr).addImm((unsigned)ARMCC::AL).addReg(0).addReg(0);
417 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr),
422 emitSPUpdate(isARM, MBB, MBBI, dl, TII, NumBytes);
424 // Increment past our save areas.
425 if (AFI->getDPRCalleeSavedAreaSize()) {
427 // Since vpop register list cannot have gaps, there may be multiple vpop
428 // instructions in the epilogue.
429 while (MBBI->getOpcode() == ARM::VLDMDIA_UPD)
432 if (AFI->getGPRCalleeSavedArea2Size()) MBBI++;
433 if (AFI->getGPRCalleeSavedArea1Size()) MBBI++;
436 if (RetOpcode == ARM::TCRETURNdi || RetOpcode == ARM::TCRETURNri) {
437 // Tail call return: adjust the stack pointer and jump to callee.
438 MBBI = MBB.getLastNonDebugInstr();
439 MachineOperand &JumpTarget = MBBI->getOperand(0);
441 // Jump to label or value in register.
442 if (RetOpcode == ARM::TCRETURNdi) {
443 unsigned TCOpcode = STI.isThumb() ?
444 (STI.isTargetIOS() ? ARM::tTAILJMPd : ARM::tTAILJMPdND) :
446 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII.get(TCOpcode));
447 if (JumpTarget.isGlobal())
448 MIB.addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset(),
449 JumpTarget.getTargetFlags());
451 assert(JumpTarget.isSymbol());
452 MIB.addExternalSymbol(JumpTarget.getSymbolName(),
453 JumpTarget.getTargetFlags());
456 // Add the default predicate in Thumb mode.
457 if (STI.isThumb()) MIB.addImm(ARMCC::AL).addReg(0);
458 } else if (RetOpcode == ARM::TCRETURNri) {
459 BuildMI(MBB, MBBI, dl,
460 TII.get(STI.isThumb() ? ARM::tTAILJMPr : ARM::TAILJMPr)).
461 addReg(JumpTarget.getReg(), RegState::Kill);
464 MachineInstr *NewMI = prior(MBBI);
465 for (unsigned i = 1, e = MBBI->getNumOperands(); i != e; ++i)
466 NewMI->addOperand(MBBI->getOperand(i));
468 // Delete the pseudo instruction TCRETURN.
474 emitSPUpdate(isARM, MBB, MBBI, dl, TII, VARegSaveSize);
477 /// getFrameIndexReference - Provide a base+offset reference to an FI slot for
478 /// debug info. It's the same as what we use for resolving the code-gen
479 /// references for now. FIXME: This can go wrong when references are
480 /// SP-relative and simple call frames aren't used.
482 ARMFrameLowering::getFrameIndexReference(const MachineFunction &MF, int FI,
483 unsigned &FrameReg) const {
484 return ResolveFrameIndexReference(MF, FI, FrameReg, 0);
488 ARMFrameLowering::ResolveFrameIndexReference(const MachineFunction &MF,
489 int FI, unsigned &FrameReg,
491 const MachineFrameInfo *MFI = MF.getFrameInfo();
492 const ARMBaseRegisterInfo *RegInfo =
493 static_cast<const ARMBaseRegisterInfo*>(MF.getTarget().getRegisterInfo());
494 const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
495 int Offset = MFI->getObjectOffset(FI) + MFI->getStackSize();
496 int FPOffset = Offset - AFI->getFramePtrSpillOffset();
497 bool isFixed = MFI->isFixedObjectIndex(FI);
501 if (AFI->isGPRCalleeSavedArea1Frame(FI))
502 return Offset - AFI->getGPRCalleeSavedArea1Offset();
503 else if (AFI->isGPRCalleeSavedArea2Frame(FI))
504 return Offset - AFI->getGPRCalleeSavedArea2Offset();
505 else if (AFI->isDPRCalleeSavedAreaFrame(FI))
506 return Offset - AFI->getDPRCalleeSavedAreaOffset();
508 // SP can move around if there are allocas. We may also lose track of SP
509 // when emergency spilling inside a non-reserved call frame setup.
510 bool hasMovingSP = !hasReservedCallFrame(MF);
512 // When dynamically realigning the stack, use the frame pointer for
513 // parameters, and the stack/base pointer for locals.
514 if (RegInfo->needsStackRealignment(MF)) {
515 assert (hasFP(MF) && "dynamic stack realignment without a FP!");
517 FrameReg = RegInfo->getFrameRegister(MF);
519 } else if (hasMovingSP) {
520 assert(RegInfo->hasBasePointer(MF) &&
521 "VLAs and dynamic stack alignment, but missing base pointer!");
522 FrameReg = RegInfo->getBaseRegister();
527 // If there is a frame pointer, use it when we can.
528 if (hasFP(MF) && AFI->hasStackFrame()) {
529 // Use frame pointer to reference fixed objects. Use it for locals if
530 // there are VLAs (and thus the SP isn't reliable as a base).
531 if (isFixed || (hasMovingSP && !RegInfo->hasBasePointer(MF))) {
532 FrameReg = RegInfo->getFrameRegister(MF);
534 } else if (hasMovingSP) {
535 assert(RegInfo->hasBasePointer(MF) && "missing base pointer!");
536 if (AFI->isThumb2Function()) {
537 // Try to use the frame pointer if we can, else use the base pointer
538 // since it's available. This is handy for the emergency spill slot, in
540 if (FPOffset >= -255 && FPOffset < 0) {
541 FrameReg = RegInfo->getFrameRegister(MF);
545 } else if (AFI->isThumb2Function()) {
546 // Use add <rd>, sp, #<imm8>
547 // ldr <rd>, [sp, #<imm8>]
548 // if at all possible to save space.
549 if (Offset >= 0 && (Offset & 3) == 0 && Offset <= 1020)
551 // In Thumb2 mode, the negative offset is very limited. Try to avoid
552 // out of range references. ldr <rt>,[<rn>, #-<imm8>]
553 if (FPOffset >= -255 && FPOffset < 0) {
554 FrameReg = RegInfo->getFrameRegister(MF);
557 } else if (Offset > (FPOffset < 0 ? -FPOffset : FPOffset)) {
558 // Otherwise, use SP or FP, whichever is closer to the stack slot.
559 FrameReg = RegInfo->getFrameRegister(MF);
563 // Use the base pointer if we have one.
564 if (RegInfo->hasBasePointer(MF))
565 FrameReg = RegInfo->getBaseRegister();
569 int ARMFrameLowering::getFrameIndexOffset(const MachineFunction &MF,
572 return getFrameIndexReference(MF, FI, FrameReg);
575 void ARMFrameLowering::emitPushInst(MachineBasicBlock &MBB,
576 MachineBasicBlock::iterator MI,
577 const std::vector<CalleeSavedInfo> &CSI,
578 unsigned StmOpc, unsigned StrOpc,
580 bool(*Func)(unsigned, bool),
581 unsigned NumAlignedDPRCS2Regs,
582 unsigned MIFlags) const {
583 MachineFunction &MF = *MBB.getParent();
584 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
587 if (MI != MBB.end()) DL = MI->getDebugLoc();
589 SmallVector<std::pair<unsigned,bool>, 4> Regs;
590 unsigned i = CSI.size();
592 unsigned LastReg = 0;
593 for (; i != 0; --i) {
594 unsigned Reg = CSI[i-1].getReg();
595 if (!(Func)(Reg, STI.isTargetIOS())) continue;
597 // D-registers in the aligned area DPRCS2 are NOT spilled here.
598 if (Reg >= ARM::D8 && Reg < ARM::D8 + NumAlignedDPRCS2Regs)
601 // Add the callee-saved register as live-in unless it's LR and
602 // @llvm.returnaddress is called. If LR is returned for
603 // @llvm.returnaddress then it's already added to the function and
604 // entry block live-in sets.
606 if (Reg == ARM::LR) {
607 if (MF.getFrameInfo()->isReturnAddressTaken() &&
608 MF.getRegInfo().isLiveIn(Reg))
615 // If NoGap is true, push consecutive registers and then leave the rest
616 // for other instructions. e.g.
617 // vpush {d8, d10, d11} -> vpush {d8}, vpush {d10, d11}
618 if (NoGap && LastReg && LastReg != Reg-1)
621 Regs.push_back(std::make_pair(Reg, isKill));
626 if (Regs.size() > 1 || StrOpc== 0) {
627 MachineInstrBuilder MIB =
628 AddDefaultPred(BuildMI(MBB, MI, DL, TII.get(StmOpc), ARM::SP)
629 .addReg(ARM::SP).setMIFlags(MIFlags));
630 for (unsigned i = 0, e = Regs.size(); i < e; ++i)
631 MIB.addReg(Regs[i].first, getKillRegState(Regs[i].second));
632 } else if (Regs.size() == 1) {
633 MachineInstrBuilder MIB = BuildMI(MBB, MI, DL, TII.get(StrOpc),
635 .addReg(Regs[0].first, getKillRegState(Regs[0].second))
636 .addReg(ARM::SP).setMIFlags(MIFlags)
644 void ARMFrameLowering::emitPopInst(MachineBasicBlock &MBB,
645 MachineBasicBlock::iterator MI,
646 const std::vector<CalleeSavedInfo> &CSI,
647 unsigned LdmOpc, unsigned LdrOpc,
648 bool isVarArg, bool NoGap,
649 bool(*Func)(unsigned, bool),
650 unsigned NumAlignedDPRCS2Regs) const {
651 MachineFunction &MF = *MBB.getParent();
652 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
653 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
654 DebugLoc DL = MI->getDebugLoc();
655 unsigned RetOpcode = MI->getOpcode();
656 bool isTailCall = (RetOpcode == ARM::TCRETURNdi ||
657 RetOpcode == ARM::TCRETURNri);
659 SmallVector<unsigned, 4> Regs;
660 unsigned i = CSI.size();
662 unsigned LastReg = 0;
663 bool DeleteRet = false;
664 for (; i != 0; --i) {
665 unsigned Reg = CSI[i-1].getReg();
666 if (!(Func)(Reg, STI.isTargetIOS())) continue;
668 // The aligned reloads from area DPRCS2 are not inserted here.
669 if (Reg >= ARM::D8 && Reg < ARM::D8 + NumAlignedDPRCS2Regs)
672 if (Reg == ARM::LR && !isTailCall && !isVarArg && STI.hasV5TOps()) {
674 LdmOpc = AFI->isThumbFunction() ? ARM::t2LDMIA_RET : ARM::LDMIA_RET;
675 // Fold the return instruction into the LDM.
679 // If NoGap is true, pop consecutive registers and then leave the rest
680 // for other instructions. e.g.
681 // vpop {d8, d10, d11} -> vpop {d8}, vpop {d10, d11}
682 if (NoGap && LastReg && LastReg != Reg-1)
691 if (Regs.size() > 1 || LdrOpc == 0) {
692 MachineInstrBuilder MIB =
693 AddDefaultPred(BuildMI(MBB, MI, DL, TII.get(LdmOpc), ARM::SP)
695 for (unsigned i = 0, e = Regs.size(); i < e; ++i)
696 MIB.addReg(Regs[i], getDefRegState(true));
698 MIB.copyImplicitOps(&*MI);
699 MI->eraseFromParent();
702 } else if (Regs.size() == 1) {
703 // If we adjusted the reg to PC from LR above, switch it back here. We
704 // only do that for LDM.
705 if (Regs[0] == ARM::PC)
707 MachineInstrBuilder MIB =
708 BuildMI(MBB, MI, DL, TII.get(LdrOpc), Regs[0])
709 .addReg(ARM::SP, RegState::Define)
711 // ARM mode needs an extra reg0 here due to addrmode2. Will go away once
712 // that refactoring is complete (eventually).
713 if (LdrOpc == ARM::LDR_POST_REG || LdrOpc == ARM::LDR_POST_IMM) {
715 MIB.addImm(ARM_AM::getAM2Opc(ARM_AM::add, 4, ARM_AM::no_shift));
724 /// Emit aligned spill instructions for NumAlignedDPRCS2Regs D-registers
725 /// starting from d8. Also insert stack realignment code and leave the stack
726 /// pointer pointing to the d8 spill slot.
727 static void emitAlignedDPRCS2Spills(MachineBasicBlock &MBB,
728 MachineBasicBlock::iterator MI,
729 unsigned NumAlignedDPRCS2Regs,
730 const std::vector<CalleeSavedInfo> &CSI,
731 const TargetRegisterInfo *TRI) {
732 MachineFunction &MF = *MBB.getParent();
733 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
734 DebugLoc DL = MI->getDebugLoc();
735 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
736 MachineFrameInfo &MFI = *MF.getFrameInfo();
738 // Mark the D-register spill slots as properly aligned. Since MFI computes
739 // stack slot layout backwards, this can actually mean that the d-reg stack
740 // slot offsets can be wrong. The offset for d8 will always be correct.
741 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
742 unsigned DNum = CSI[i].getReg() - ARM::D8;
745 int FI = CSI[i].getFrameIdx();
746 // The even-numbered registers will be 16-byte aligned, the odd-numbered
747 // registers will be 8-byte aligned.
748 MFI.setObjectAlignment(FI, DNum % 2 ? 8 : 16);
750 // The stack slot for D8 needs to be maximally aligned because this is
751 // actually the point where we align the stack pointer. MachineFrameInfo
752 // computes all offsets relative to the incoming stack pointer which is a
753 // bit weird when realigning the stack. Any extra padding for this
754 // over-alignment is not realized because the code inserted below adjusts
755 // the stack pointer by numregs * 8 before aligning the stack pointer.
757 MFI.setObjectAlignment(FI, MFI.getMaxAlignment());
760 // Move the stack pointer to the d8 spill slot, and align it at the same
761 // time. Leave the stack slot address in the scratch register r4.
763 // sub r4, sp, #numregs * 8
764 // bic r4, r4, #align - 1
767 bool isThumb = AFI->isThumbFunction();
768 assert(!AFI->isThumb1OnlyFunction() && "Can't realign stack for thumb1");
769 AFI->setShouldRestoreSPFromFP(true);
771 // sub r4, sp, #numregs * 8
772 // The immediate is <= 64, so it doesn't need any special encoding.
773 unsigned Opc = isThumb ? ARM::t2SUBri : ARM::SUBri;
774 AddDefaultCC(AddDefaultPred(BuildMI(MBB, MI, DL, TII.get(Opc), ARM::R4)
776 .addImm(8 * NumAlignedDPRCS2Regs)));
778 // bic r4, r4, #align-1
779 Opc = isThumb ? ARM::t2BICri : ARM::BICri;
780 unsigned MaxAlign = MF.getFrameInfo()->getMaxAlignment();
781 AddDefaultCC(AddDefaultPred(BuildMI(MBB, MI, DL, TII.get(Opc), ARM::R4)
782 .addReg(ARM::R4, RegState::Kill)
783 .addImm(MaxAlign - 1)));
786 // The stack pointer must be adjusted before spilling anything, otherwise
787 // the stack slots could be clobbered by an interrupt handler.
788 // Leave r4 live, it is used below.
789 Opc = isThumb ? ARM::tMOVr : ARM::MOVr;
790 MachineInstrBuilder MIB = BuildMI(MBB, MI, DL, TII.get(Opc), ARM::SP)
792 MIB = AddDefaultPred(MIB);
796 // Now spill NumAlignedDPRCS2Regs registers starting from d8.
797 // r4 holds the stack slot address.
798 unsigned NextReg = ARM::D8;
800 // 16-byte aligned vst1.64 with 4 d-regs and address writeback.
801 // The writeback is only needed when emitting two vst1.64 instructions.
802 if (NumAlignedDPRCS2Regs >= 6) {
803 unsigned SupReg = TRI->getMatchingSuperReg(NextReg, ARM::dsub_0,
805 MBB.addLiveIn(SupReg);
806 AddDefaultPred(BuildMI(MBB, MI, DL, TII.get(ARM::VST1d64Qwb_fixed),
808 .addReg(ARM::R4, RegState::Kill).addImm(16)
810 .addReg(SupReg, RegState::ImplicitKill));
812 NumAlignedDPRCS2Regs -= 4;
815 // We won't modify r4 beyond this point. It currently points to the next
816 // register to be spilled.
817 unsigned R4BaseReg = NextReg;
819 // 16-byte aligned vst1.64 with 4 d-regs, no writeback.
820 if (NumAlignedDPRCS2Regs >= 4) {
821 unsigned SupReg = TRI->getMatchingSuperReg(NextReg, ARM::dsub_0,
823 MBB.addLiveIn(SupReg);
824 AddDefaultPred(BuildMI(MBB, MI, DL, TII.get(ARM::VST1d64Q))
825 .addReg(ARM::R4).addImm(16).addReg(NextReg)
826 .addReg(SupReg, RegState::ImplicitKill));
828 NumAlignedDPRCS2Regs -= 4;
831 // 16-byte aligned vst1.64 with 2 d-regs.
832 if (NumAlignedDPRCS2Regs >= 2) {
833 unsigned SupReg = TRI->getMatchingSuperReg(NextReg, ARM::dsub_0,
835 MBB.addLiveIn(SupReg);
836 AddDefaultPred(BuildMI(MBB, MI, DL, TII.get(ARM::VST1q64))
837 .addReg(ARM::R4).addImm(16).addReg(SupReg));
839 NumAlignedDPRCS2Regs -= 2;
842 // Finally, use a vanilla vstr.64 for the odd last register.
843 if (NumAlignedDPRCS2Regs) {
844 MBB.addLiveIn(NextReg);
845 // vstr.64 uses addrmode5 which has an offset scale of 4.
846 AddDefaultPred(BuildMI(MBB, MI, DL, TII.get(ARM::VSTRD))
848 .addReg(ARM::R4).addImm((NextReg-R4BaseReg)*2));
851 // The last spill instruction inserted should kill the scratch register r4.
852 llvm::prior(MI)->addRegisterKilled(ARM::R4, TRI);
855 /// Skip past the code inserted by emitAlignedDPRCS2Spills, and return an
856 /// iterator to the following instruction.
857 static MachineBasicBlock::iterator
858 skipAlignedDPRCS2Spills(MachineBasicBlock::iterator MI,
859 unsigned NumAlignedDPRCS2Regs) {
860 // sub r4, sp, #numregs * 8
861 // bic r4, r4, #align - 1
864 assert(MI->mayStore() && "Expecting spill instruction");
866 // These switches all fall through.
867 switch(NumAlignedDPRCS2Regs) {
870 assert(MI->mayStore() && "Expecting spill instruction");
873 assert(MI->mayStore() && "Expecting spill instruction");
877 assert(MI->killsRegister(ARM::R4) && "Missed kill flag");
883 /// Emit aligned reload instructions for NumAlignedDPRCS2Regs D-registers
884 /// starting from d8. These instructions are assumed to execute while the
885 /// stack is still aligned, unlike the code inserted by emitPopInst.
886 static void emitAlignedDPRCS2Restores(MachineBasicBlock &MBB,
887 MachineBasicBlock::iterator MI,
888 unsigned NumAlignedDPRCS2Regs,
889 const std::vector<CalleeSavedInfo> &CSI,
890 const TargetRegisterInfo *TRI) {
891 MachineFunction &MF = *MBB.getParent();
892 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
893 DebugLoc DL = MI->getDebugLoc();
894 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
896 // Find the frame index assigned to d8.
898 for (unsigned i = 0, e = CSI.size(); i != e; ++i)
899 if (CSI[i].getReg() == ARM::D8) {
900 D8SpillFI = CSI[i].getFrameIdx();
904 // Materialize the address of the d8 spill slot into the scratch register r4.
905 // This can be fairly complicated if the stack frame is large, so just use
906 // the normal frame index elimination mechanism to do it. This code runs as
907 // the initial part of the epilog where the stack and base pointers haven't
909 bool isThumb = AFI->isThumbFunction();
910 assert(!AFI->isThumb1OnlyFunction() && "Can't realign stack for thumb1");
912 unsigned Opc = isThumb ? ARM::t2ADDri : ARM::ADDri;
913 AddDefaultCC(AddDefaultPred(BuildMI(MBB, MI, DL, TII.get(Opc), ARM::R4)
914 .addFrameIndex(D8SpillFI).addImm(0)));
916 // Now restore NumAlignedDPRCS2Regs registers starting from d8.
917 unsigned NextReg = ARM::D8;
919 // 16-byte aligned vld1.64 with 4 d-regs and writeback.
920 if (NumAlignedDPRCS2Regs >= 6) {
921 unsigned SupReg = TRI->getMatchingSuperReg(NextReg, ARM::dsub_0,
923 AddDefaultPred(BuildMI(MBB, MI, DL, TII.get(ARM::VLD1d64Qwb_fixed), NextReg)
924 .addReg(ARM::R4, RegState::Define)
925 .addReg(ARM::R4, RegState::Kill).addImm(16)
926 .addReg(SupReg, RegState::ImplicitDefine));
928 NumAlignedDPRCS2Regs -= 4;
931 // We won't modify r4 beyond this point. It currently points to the next
932 // register to be spilled.
933 unsigned R4BaseReg = NextReg;
935 // 16-byte aligned vld1.64 with 4 d-regs, no writeback.
936 if (NumAlignedDPRCS2Regs >= 4) {
937 unsigned SupReg = TRI->getMatchingSuperReg(NextReg, ARM::dsub_0,
939 AddDefaultPred(BuildMI(MBB, MI, DL, TII.get(ARM::VLD1d64Q), NextReg)
940 .addReg(ARM::R4).addImm(16)
941 .addReg(SupReg, RegState::ImplicitDefine));
943 NumAlignedDPRCS2Regs -= 4;
946 // 16-byte aligned vld1.64 with 2 d-regs.
947 if (NumAlignedDPRCS2Regs >= 2) {
948 unsigned SupReg = TRI->getMatchingSuperReg(NextReg, ARM::dsub_0,
950 AddDefaultPred(BuildMI(MBB, MI, DL, TII.get(ARM::VLD1q64), SupReg)
951 .addReg(ARM::R4).addImm(16));
953 NumAlignedDPRCS2Regs -= 2;
956 // Finally, use a vanilla vldr.64 for the remaining odd register.
957 if (NumAlignedDPRCS2Regs)
958 AddDefaultPred(BuildMI(MBB, MI, DL, TII.get(ARM::VLDRD), NextReg)
959 .addReg(ARM::R4).addImm(2*(NextReg-R4BaseReg)));
961 // Last store kills r4.
962 llvm::prior(MI)->addRegisterKilled(ARM::R4, TRI);
965 bool ARMFrameLowering::spillCalleeSavedRegisters(MachineBasicBlock &MBB,
966 MachineBasicBlock::iterator MI,
967 const std::vector<CalleeSavedInfo> &CSI,
968 const TargetRegisterInfo *TRI) const {
972 MachineFunction &MF = *MBB.getParent();
973 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
975 unsigned PushOpc = AFI->isThumbFunction() ? ARM::t2STMDB_UPD : ARM::STMDB_UPD;
976 unsigned PushOneOpc = AFI->isThumbFunction() ?
977 ARM::t2STR_PRE : ARM::STR_PRE_IMM;
978 unsigned FltOpc = ARM::VSTMDDB_UPD;
979 unsigned NumAlignedDPRCS2Regs = AFI->getNumAlignedDPRCS2Regs();
980 emitPushInst(MBB, MI, CSI, PushOpc, PushOneOpc, false, &isARMArea1Register, 0,
981 MachineInstr::FrameSetup);
982 emitPushInst(MBB, MI, CSI, PushOpc, PushOneOpc, false, &isARMArea2Register, 0,
983 MachineInstr::FrameSetup);
984 emitPushInst(MBB, MI, CSI, FltOpc, 0, true, &isARMArea3Register,
985 NumAlignedDPRCS2Regs, MachineInstr::FrameSetup);
987 // The code above does not insert spill code for the aligned DPRCS2 registers.
988 // The stack realignment code will be inserted between the push instructions
990 if (NumAlignedDPRCS2Regs)
991 emitAlignedDPRCS2Spills(MBB, MI, NumAlignedDPRCS2Regs, CSI, TRI);
996 bool ARMFrameLowering::restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
997 MachineBasicBlock::iterator MI,
998 const std::vector<CalleeSavedInfo> &CSI,
999 const TargetRegisterInfo *TRI) const {
1003 MachineFunction &MF = *MBB.getParent();
1004 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1005 bool isVarArg = AFI->getVarArgsRegSaveSize() > 0;
1006 unsigned NumAlignedDPRCS2Regs = AFI->getNumAlignedDPRCS2Regs();
1008 // The emitPopInst calls below do not insert reloads for the aligned DPRCS2
1009 // registers. Do that here instead.
1010 if (NumAlignedDPRCS2Regs)
1011 emitAlignedDPRCS2Restores(MBB, MI, NumAlignedDPRCS2Regs, CSI, TRI);
1013 unsigned PopOpc = AFI->isThumbFunction() ? ARM::t2LDMIA_UPD : ARM::LDMIA_UPD;
1014 unsigned LdrOpc = AFI->isThumbFunction() ? ARM::t2LDR_POST :ARM::LDR_POST_IMM;
1015 unsigned FltOpc = ARM::VLDMDIA_UPD;
1016 emitPopInst(MBB, MI, CSI, FltOpc, 0, isVarArg, true, &isARMArea3Register,
1017 NumAlignedDPRCS2Regs);
1018 emitPopInst(MBB, MI, CSI, PopOpc, LdrOpc, isVarArg, false,
1019 &isARMArea2Register, 0);
1020 emitPopInst(MBB, MI, CSI, PopOpc, LdrOpc, isVarArg, false,
1021 &isARMArea1Register, 0);
1026 // FIXME: Make generic?
1027 static unsigned GetFunctionSizeInBytes(const MachineFunction &MF,
1028 const ARMBaseInstrInfo &TII) {
1029 unsigned FnSize = 0;
1030 for (MachineFunction::const_iterator MBBI = MF.begin(), E = MF.end();
1031 MBBI != E; ++MBBI) {
1032 const MachineBasicBlock &MBB = *MBBI;
1033 for (MachineBasicBlock::const_iterator I = MBB.begin(),E = MBB.end();
1035 FnSize += TII.GetInstSizeInBytes(I);
1040 /// estimateStackSize - Estimate and return the size of the frame.
1041 /// FIXME: Make generic?
1042 static unsigned estimateStackSize(MachineFunction &MF) {
1043 const MachineFrameInfo *MFI = MF.getFrameInfo();
1044 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
1045 const TargetRegisterInfo *RegInfo = MF.getTarget().getRegisterInfo();
1046 unsigned MaxAlign = MFI->getMaxAlignment();
1049 // This code is very, very similar to PEI::calculateFrameObjectOffsets().
1050 // It really should be refactored to share code. Until then, changes
1051 // should keep in mind that there's tight coupling between the two.
1053 for (int i = MFI->getObjectIndexBegin(); i != 0; ++i) {
1054 int FixedOff = -MFI->getObjectOffset(i);
1055 if (FixedOff > Offset) Offset = FixedOff;
1057 for (unsigned i = 0, e = MFI->getObjectIndexEnd(); i != e; ++i) {
1058 if (MFI->isDeadObjectIndex(i))
1060 Offset += MFI->getObjectSize(i);
1061 unsigned Align = MFI->getObjectAlignment(i);
1062 // Adjust to alignment boundary
1063 Offset = (Offset+Align-1)/Align*Align;
1065 MaxAlign = std::max(Align, MaxAlign);
1068 if (MFI->adjustsStack() && TFI->hasReservedCallFrame(MF))
1069 Offset += MFI->getMaxCallFrameSize();
1071 // Round up the size to a multiple of the alignment. If the function has
1072 // any calls or alloca's, align to the target's StackAlignment value to
1073 // ensure that the callee's frame or the alloca data is suitably aligned;
1074 // otherwise, for leaf functions, align to the TransientStackAlignment
1076 unsigned StackAlign;
1077 if (MFI->adjustsStack() || MFI->hasVarSizedObjects() ||
1078 (RegInfo->needsStackRealignment(MF) && MFI->getObjectIndexEnd() != 0))
1079 StackAlign = TFI->getStackAlignment();
1081 StackAlign = TFI->getTransientStackAlignment();
1083 // If the frame pointer is eliminated, all frame offsets will be relative to
1084 // SP not FP. Align to MaxAlign so this works.
1085 StackAlign = std::max(StackAlign, MaxAlign);
1086 unsigned AlignMask = StackAlign - 1;
1087 Offset = (Offset + AlignMask) & ~uint64_t(AlignMask);
1089 return (unsigned)Offset;
1092 /// estimateRSStackSizeLimit - Look at each instruction that references stack
1093 /// frames and return the stack size limit beyond which some of these
1094 /// instructions will require a scratch register during their expansion later.
1095 // FIXME: Move to TII?
1096 static unsigned estimateRSStackSizeLimit(MachineFunction &MF,
1097 const TargetFrameLowering *TFI) {
1098 const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1099 unsigned Limit = (1 << 12) - 1;
1100 for (MachineFunction::iterator BB = MF.begin(),E = MF.end(); BB != E; ++BB) {
1101 for (MachineBasicBlock::iterator I = BB->begin(), E = BB->end();
1103 for (unsigned i = 0, e = I->getNumOperands(); i != e; ++i) {
1104 if (!I->getOperand(i).isFI()) continue;
1106 // When using ADDri to get the address of a stack object, 255 is the
1107 // largest offset guaranteed to fit in the immediate offset.
1108 if (I->getOpcode() == ARM::ADDri) {
1109 Limit = std::min(Limit, (1U << 8) - 1);
1113 // Otherwise check the addressing mode.
1114 switch (I->getDesc().TSFlags & ARMII::AddrModeMask) {
1115 case ARMII::AddrMode3:
1116 case ARMII::AddrModeT2_i8:
1117 Limit = std::min(Limit, (1U << 8) - 1);
1119 case ARMII::AddrMode5:
1120 case ARMII::AddrModeT2_i8s4:
1121 Limit = std::min(Limit, ((1U << 8) - 1) * 4);
1123 case ARMII::AddrModeT2_i12:
1124 // i12 supports only positive offset so these will be converted to
1125 // i8 opcodes. See llvm::rewriteT2FrameIndex.
1126 if (TFI->hasFP(MF) && AFI->hasStackFrame())
1127 Limit = std::min(Limit, (1U << 8) - 1);
1129 case ARMII::AddrMode4:
1130 case ARMII::AddrMode6:
1131 // Addressing modes 4 & 6 (load/store) instructions can't encode an
1132 // immediate offset for stack references.
1137 break; // At most one FI per instruction
1145 // In functions that realign the stack, it can be an advantage to spill the
1146 // callee-saved vector registers after realigning the stack. The vst1 and vld1
1147 // instructions take alignment hints that can improve performance.
1149 static void checkNumAlignedDPRCS2Regs(MachineFunction &MF) {
1150 MF.getInfo<ARMFunctionInfo>()->setNumAlignedDPRCS2Regs(0);
1151 if (!SpillAlignedNEONRegs)
1154 // Naked functions don't spill callee-saved registers.
1155 if (MF.getFunction()->getFnAttributes().hasAttribute(Attribute::Naked))
1158 // We are planning to use NEON instructions vst1 / vld1.
1159 if (!MF.getTarget().getSubtarget<ARMSubtarget>().hasNEON())
1162 // Don't bother if the default stack alignment is sufficiently high.
1163 if (MF.getTarget().getFrameLowering()->getStackAlignment() >= 8)
1166 // Aligned spills require stack realignment.
1167 const ARMBaseRegisterInfo *RegInfo =
1168 static_cast<const ARMBaseRegisterInfo*>(MF.getTarget().getRegisterInfo());
1169 if (!RegInfo->canRealignStack(MF))
1172 // We always spill contiguous d-registers starting from d8. Count how many
1173 // needs spilling. The register allocator will almost always use the
1174 // callee-saved registers in order, but it can happen that there are holes in
1175 // the range. Registers above the hole will be spilled to the standard DPRCS
1177 MachineRegisterInfo &MRI = MF.getRegInfo();
1178 unsigned NumSpills = 0;
1179 for (; NumSpills < 8; ++NumSpills)
1180 if (!MRI.isPhysRegUsed(ARM::D8 + NumSpills))
1183 // Don't do this for just one d-register. It's not worth it.
1187 // Spill the first NumSpills D-registers after realigning the stack.
1188 MF.getInfo<ARMFunctionInfo>()->setNumAlignedDPRCS2Regs(NumSpills);
1190 // A scratch register is required for the vst1 / vld1 instructions.
1191 MF.getRegInfo().setPhysRegUsed(ARM::R4);
1195 ARMFrameLowering::processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
1196 RegScavenger *RS) const {
1197 // This tells PEI to spill the FP as if it is any other callee-save register
1198 // to take advantage the eliminateFrameIndex machinery. This also ensures it
1199 // is spilled in the order specified by getCalleeSavedRegs() to make it easier
1200 // to combine multiple loads / stores.
1201 bool CanEliminateFrame = true;
1202 bool CS1Spilled = false;
1203 bool LRSpilled = false;
1204 unsigned NumGPRSpills = 0;
1205 SmallVector<unsigned, 4> UnspilledCS1GPRs;
1206 SmallVector<unsigned, 4> UnspilledCS2GPRs;
1207 const ARMBaseRegisterInfo *RegInfo =
1208 static_cast<const ARMBaseRegisterInfo*>(MF.getTarget().getRegisterInfo());
1209 const ARMBaseInstrInfo &TII =
1210 *static_cast<const ARMBaseInstrInfo*>(MF.getTarget().getInstrInfo());
1211 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1212 MachineFrameInfo *MFI = MF.getFrameInfo();
1213 MachineRegisterInfo &MRI = MF.getRegInfo();
1214 unsigned FramePtr = RegInfo->getFrameRegister(MF);
1216 // Spill R4 if Thumb2 function requires stack realignment - it will be used as
1217 // scratch register. Also spill R4 if Thumb2 function has varsized objects,
1218 // since it's not always possible to restore sp from fp in a single
1220 // FIXME: It will be better just to find spare register here.
1221 if (AFI->isThumb2Function() &&
1222 (MFI->hasVarSizedObjects() || RegInfo->needsStackRealignment(MF)))
1223 MRI.setPhysRegUsed(ARM::R4);
1225 if (AFI->isThumb1OnlyFunction()) {
1226 // Spill LR if Thumb1 function uses variable length argument lists.
1227 if (AFI->getVarArgsRegSaveSize() > 0)
1228 MRI.setPhysRegUsed(ARM::LR);
1230 // Spill R4 if Thumb1 epilogue has to restore SP from FP. We don't know
1231 // for sure what the stack size will be, but for this, an estimate is good
1232 // enough. If there anything changes it, it'll be a spill, which implies
1233 // we've used all the registers and so R4 is already used, so not marking
1234 // it here will be OK.
1235 // FIXME: It will be better just to find spare register here.
1236 unsigned StackSize = estimateStackSize(MF);
1237 if (MFI->hasVarSizedObjects() || StackSize > 508)
1238 MRI.setPhysRegUsed(ARM::R4);
1241 // See if we can spill vector registers to aligned stack.
1242 checkNumAlignedDPRCS2Regs(MF);
1244 // Spill the BasePtr if it's used.
1245 if (RegInfo->hasBasePointer(MF))
1246 MRI.setPhysRegUsed(RegInfo->getBaseRegister());
1248 // Don't spill FP if the frame can be eliminated. This is determined
1249 // by scanning the callee-save registers to see if any is used.
1250 const uint16_t *CSRegs = RegInfo->getCalleeSavedRegs();
1251 for (unsigned i = 0; CSRegs[i]; ++i) {
1252 unsigned Reg = CSRegs[i];
1253 bool Spilled = false;
1254 if (MRI.isPhysRegUsed(Reg)) {
1256 CanEliminateFrame = false;
1259 if (!ARM::GPRRegClass.contains(Reg))
1265 if (!STI.isTargetIOS()) {
1272 // Keep track if LR and any of R4, R5, R6, and R7 is spilled.
1277 case ARM::R4: case ARM::R5:
1278 case ARM::R6: case ARM::R7:
1285 if (!STI.isTargetIOS()) {
1286 UnspilledCS1GPRs.push_back(Reg);
1291 case ARM::R4: case ARM::R5:
1292 case ARM::R6: case ARM::R7:
1294 UnspilledCS1GPRs.push_back(Reg);
1297 UnspilledCS2GPRs.push_back(Reg);
1303 bool ForceLRSpill = false;
1304 if (!LRSpilled && AFI->isThumb1OnlyFunction()) {
1305 unsigned FnSize = GetFunctionSizeInBytes(MF, TII);
1306 // Force LR to be spilled if the Thumb function size is > 2048. This enables
1307 // use of BL to implement far jump. If it turns out that it's not needed
1308 // then the branch fix up path will undo it.
1309 if (FnSize >= (1 << 11)) {
1310 CanEliminateFrame = false;
1311 ForceLRSpill = true;
1315 // If any of the stack slot references may be out of range of an immediate
1316 // offset, make sure a register (or a spill slot) is available for the
1317 // register scavenger. Note that if we're indexing off the frame pointer, the
1318 // effective stack size is 4 bytes larger since the FP points to the stack
1319 // slot of the previous FP. Also, if we have variable sized objects in the
1320 // function, stack slot references will often be negative, and some of
1321 // our instructions are positive-offset only, so conservatively consider
1322 // that case to want a spill slot (or register) as well. Similarly, if
1323 // the function adjusts the stack pointer during execution and the
1324 // adjustments aren't already part of our stack size estimate, our offset
1325 // calculations may be off, so be conservative.
1326 // FIXME: We could add logic to be more precise about negative offsets
1327 // and which instructions will need a scratch register for them. Is it
1328 // worth the effort and added fragility?
1331 (estimateStackSize(MF) + ((hasFP(MF) && AFI->hasStackFrame()) ? 4:0) >=
1332 estimateRSStackSizeLimit(MF, this)))
1333 || MFI->hasVarSizedObjects()
1334 || (MFI->adjustsStack() && !canSimplifyCallFramePseudos(MF));
1336 bool ExtraCSSpill = false;
1337 if (BigStack || !CanEliminateFrame || RegInfo->cannotEliminateFrame(MF)) {
1338 AFI->setHasStackFrame(true);
1340 // If LR is not spilled, but at least one of R4, R5, R6, and R7 is spilled.
1341 // Spill LR as well so we can fold BX_RET to the registers restore (LDM).
1342 if (!LRSpilled && CS1Spilled) {
1343 MRI.setPhysRegUsed(ARM::LR);
1345 UnspilledCS1GPRs.erase(std::find(UnspilledCS1GPRs.begin(),
1346 UnspilledCS1GPRs.end(), (unsigned)ARM::LR));
1347 ForceLRSpill = false;
1348 ExtraCSSpill = true;
1352 MRI.setPhysRegUsed(FramePtr);
1356 // If stack and double are 8-byte aligned and we are spilling an odd number
1357 // of GPRs, spill one extra callee save GPR so we won't have to pad between
1358 // the integer and double callee save areas.
1359 unsigned TargetAlign = getStackAlignment();
1360 if (TargetAlign == 8 && (NumGPRSpills & 1)) {
1361 if (CS1Spilled && !UnspilledCS1GPRs.empty()) {
1362 for (unsigned i = 0, e = UnspilledCS1GPRs.size(); i != e; ++i) {
1363 unsigned Reg = UnspilledCS1GPRs[i];
1364 // Don't spill high register if the function is thumb1
1365 if (!AFI->isThumb1OnlyFunction() ||
1366 isARMLowRegister(Reg) || Reg == ARM::LR) {
1367 MRI.setPhysRegUsed(Reg);
1368 if (!MRI.isReserved(Reg))
1369 ExtraCSSpill = true;
1373 } else if (!UnspilledCS2GPRs.empty() && !AFI->isThumb1OnlyFunction()) {
1374 unsigned Reg = UnspilledCS2GPRs.front();
1375 MRI.setPhysRegUsed(Reg);
1376 if (!MRI.isReserved(Reg))
1377 ExtraCSSpill = true;
1381 // Estimate if we might need to scavenge a register at some point in order
1382 // to materialize a stack offset. If so, either spill one additional
1383 // callee-saved register or reserve a special spill slot to facilitate
1384 // register scavenging. Thumb1 needs a spill slot for stack pointer
1385 // adjustments also, even when the frame itself is small.
1386 if (BigStack && !ExtraCSSpill) {
1387 // If any non-reserved CS register isn't spilled, just spill one or two
1388 // extra. That should take care of it!
1389 unsigned NumExtras = TargetAlign / 4;
1390 SmallVector<unsigned, 2> Extras;
1391 while (NumExtras && !UnspilledCS1GPRs.empty()) {
1392 unsigned Reg = UnspilledCS1GPRs.back();
1393 UnspilledCS1GPRs.pop_back();
1394 if (!MRI.isReserved(Reg) &&
1395 (!AFI->isThumb1OnlyFunction() || isARMLowRegister(Reg) ||
1397 Extras.push_back(Reg);
1401 // For non-Thumb1 functions, also check for hi-reg CS registers
1402 if (!AFI->isThumb1OnlyFunction()) {
1403 while (NumExtras && !UnspilledCS2GPRs.empty()) {
1404 unsigned Reg = UnspilledCS2GPRs.back();
1405 UnspilledCS2GPRs.pop_back();
1406 if (!MRI.isReserved(Reg)) {
1407 Extras.push_back(Reg);
1412 if (Extras.size() && NumExtras == 0) {
1413 for (unsigned i = 0, e = Extras.size(); i != e; ++i) {
1414 MRI.setPhysRegUsed(Extras[i]);
1416 } else if (!AFI->isThumb1OnlyFunction()) {
1417 // note: Thumb1 functions spill to R12, not the stack. Reserve a slot
1418 // closest to SP or frame pointer.
1419 const TargetRegisterClass *RC = &ARM::GPRRegClass;
1420 RS->setScavengingFrameIndex(MFI->CreateStackObject(RC->getSize(),
1428 MRI.setPhysRegUsed(ARM::LR);
1429 AFI->setLRIsSpilledForFarJump(true);