1 //===-- ARMFrameLowering.cpp - ARM Frame Information ----------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the ARM implementation of TargetFrameLowering class.
12 //===----------------------------------------------------------------------===//
14 #include "ARMFrameLowering.h"
15 #include "ARMBaseInstrInfo.h"
16 #include "ARMBaseRegisterInfo.h"
17 #include "ARMConstantPoolValue.h"
18 #include "ARMMachineFunctionInfo.h"
19 #include "MCTargetDesc/ARMAddressingModes.h"
20 #include "llvm/CodeGen/MachineFrameInfo.h"
21 #include "llvm/CodeGen/MachineFunction.h"
22 #include "llvm/CodeGen/MachineInstrBuilder.h"
23 #include "llvm/CodeGen/MachineModuleInfo.h"
24 #include "llvm/CodeGen/MachineRegisterInfo.h"
25 #include "llvm/CodeGen/RegisterScavenging.h"
26 #include "llvm/IR/CallingConv.h"
27 #include "llvm/IR/Function.h"
28 #include "llvm/MC/MCContext.h"
29 #include "llvm/Support/CommandLine.h"
30 #include "llvm/Target/TargetOptions.h"
35 SpillAlignedNEONRegs("align-neon-spills", cl::Hidden, cl::init(true),
36 cl::desc("Align ARM NEON spills in prolog and epilog"));
38 static MachineBasicBlock::iterator
39 skipAlignedDPRCS2Spills(MachineBasicBlock::iterator MI,
40 unsigned NumAlignedDPRCS2Regs);
42 ARMFrameLowering::ARMFrameLowering(const ARMSubtarget &sti)
43 : TargetFrameLowering(StackGrowsDown, sti.getStackAlignment(), 0, 4),
46 /// hasFP - Return true if the specified function should have a dedicated frame
47 /// pointer register. This is true if the function has variable sized allocas
48 /// or if frame pointer elimination is disabled.
49 bool ARMFrameLowering::hasFP(const MachineFunction &MF) const {
50 const TargetRegisterInfo *RegInfo = MF.getSubtarget().getRegisterInfo();
52 // iOS requires FP not to be clobbered for backtracing purpose.
53 if (STI.isTargetIOS())
56 const MachineFrameInfo *MFI = MF.getFrameInfo();
57 // Always eliminate non-leaf frame pointers.
58 return ((MF.getTarget().Options.DisableFramePointerElim(MF) &&
60 RegInfo->needsStackRealignment(MF) ||
61 MFI->hasVarSizedObjects() ||
62 MFI->isFrameAddressTaken());
65 /// hasReservedCallFrame - Under normal circumstances, when a frame pointer is
66 /// not required, we reserve argument space for call sites in the function
67 /// immediately on entry to the current function. This eliminates the need for
68 /// add/sub sp brackets around call sites. Returns true if the call frame is
69 /// included as part of the stack frame.
70 bool ARMFrameLowering::hasReservedCallFrame(const MachineFunction &MF) const {
71 const MachineFrameInfo *FFI = MF.getFrameInfo();
72 unsigned CFSize = FFI->getMaxCallFrameSize();
73 // It's not always a good idea to include the call frame as part of the
74 // stack frame. ARM (especially Thumb) has small immediate offset to
75 // address the stack frame. So a large call frame can cause poor codegen
76 // and may even makes it impossible to scavenge a register.
77 if (CFSize >= ((1 << 12) - 1) / 2) // Half of imm12
80 return !MF.getFrameInfo()->hasVarSizedObjects();
83 /// canSimplifyCallFramePseudos - If there is a reserved call frame, the
84 /// call frame pseudos can be simplified. Unlike most targets, having a FP
85 /// is not sufficient here since we still may reference some objects via SP
86 /// even when FP is available in Thumb2 mode.
88 ARMFrameLowering::canSimplifyCallFramePseudos(const MachineFunction &MF) const {
89 return hasReservedCallFrame(MF) || MF.getFrameInfo()->hasVarSizedObjects();
92 static bool isCSRestore(MachineInstr *MI,
93 const ARMBaseInstrInfo &TII,
94 const MCPhysReg *CSRegs) {
95 // Integer spill area is handled with "pop".
96 if (isPopOpcode(MI->getOpcode())) {
97 // The first two operands are predicates. The last two are
98 // imp-def and imp-use of SP. Check everything in between.
99 for (int i = 5, e = MI->getNumOperands(); i != e; ++i)
100 if (!isCalleeSavedRegister(MI->getOperand(i).getReg(), CSRegs))
104 if ((MI->getOpcode() == ARM::LDR_POST_IMM ||
105 MI->getOpcode() == ARM::LDR_POST_REG ||
106 MI->getOpcode() == ARM::t2LDR_POST) &&
107 isCalleeSavedRegister(MI->getOperand(0).getReg(), CSRegs) &&
108 MI->getOperand(1).getReg() == ARM::SP)
114 static void emitRegPlusImmediate(bool isARM, MachineBasicBlock &MBB,
115 MachineBasicBlock::iterator &MBBI, DebugLoc dl,
116 const ARMBaseInstrInfo &TII, unsigned DestReg,
117 unsigned SrcReg, int NumBytes,
118 unsigned MIFlags = MachineInstr::NoFlags,
119 ARMCC::CondCodes Pred = ARMCC::AL,
120 unsigned PredReg = 0) {
122 emitARMRegPlusImmediate(MBB, MBBI, dl, DestReg, SrcReg, NumBytes,
123 Pred, PredReg, TII, MIFlags);
125 emitT2RegPlusImmediate(MBB, MBBI, dl, DestReg, SrcReg, NumBytes,
126 Pred, PredReg, TII, MIFlags);
129 static void emitSPUpdate(bool isARM, MachineBasicBlock &MBB,
130 MachineBasicBlock::iterator &MBBI, DebugLoc dl,
131 const ARMBaseInstrInfo &TII, int NumBytes,
132 unsigned MIFlags = MachineInstr::NoFlags,
133 ARMCC::CondCodes Pred = ARMCC::AL,
134 unsigned PredReg = 0) {
135 emitRegPlusImmediate(isARM, MBB, MBBI, dl, TII, ARM::SP, ARM::SP, NumBytes,
136 MIFlags, Pred, PredReg);
139 static int sizeOfSPAdjustment(const MachineInstr *MI) {
141 switch (MI->getOpcode()) {
142 case ARM::VSTMDDB_UPD:
146 case ARM::t2STMDB_UPD:
150 case ARM::STR_PRE_IMM:
153 llvm_unreachable("Unknown push or pop like instruction");
157 // ARM and Thumb2 push/pop insts have explicit "sp, sp" operands (+
158 // pred) so the list starts at 4.
159 for (int i = MI->getNumOperands() - 1; i >= 4; --i)
164 static bool WindowsRequiresStackProbe(const MachineFunction &MF,
165 size_t StackSizeInBytes) {
166 const MachineFrameInfo *MFI = MF.getFrameInfo();
167 if (MFI->getStackProtectorIndex() > 0)
168 return StackSizeInBytes >= 4080;
169 return StackSizeInBytes >= 4096;
173 struct StackAdjustingInsts {
175 MachineBasicBlock::iterator I;
180 SmallVector<InstInfo, 4> Insts;
182 void addInst(MachineBasicBlock::iterator I, unsigned SPAdjust,
183 bool BeforeFPSet = false) {
184 InstInfo Info = {I, SPAdjust, BeforeFPSet};
185 Insts.push_back(Info);
188 void addExtraBytes(const MachineBasicBlock::iterator I, unsigned ExtraBytes) {
189 auto Info = std::find_if(Insts.begin(), Insts.end(),
190 [&](InstInfo &Info) { return Info.I == I; });
191 assert(Info != Insts.end() && "invalid sp adjusting instruction");
192 Info->SPAdjust += ExtraBytes;
195 void emitDefCFAOffsets(MachineModuleInfo &MMI, MachineBasicBlock &MBB,
196 DebugLoc dl, const ARMBaseInstrInfo &TII, bool HasFP) {
197 unsigned CFAOffset = 0;
198 for (auto &Info : Insts) {
199 if (HasFP && !Info.BeforeFPSet)
202 CFAOffset -= Info.SPAdjust;
203 unsigned CFIIndex = MMI.addFrameInst(
204 MCCFIInstruction::createDefCfaOffset(nullptr, CFAOffset));
205 BuildMI(MBB, std::next(Info.I), dl,
206 TII.get(TargetOpcode::CFI_INSTRUCTION))
207 .addCFIIndex(CFIIndex)
208 .setMIFlags(MachineInstr::FrameSetup);
214 void ARMFrameLowering::emitPrologue(MachineFunction &MF) const {
215 MachineBasicBlock &MBB = MF.front();
216 MachineBasicBlock::iterator MBBI = MBB.begin();
217 MachineFrameInfo *MFI = MF.getFrameInfo();
218 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
219 MachineModuleInfo &MMI = MF.getMMI();
220 MCContext &Context = MMI.getContext();
221 const TargetMachine &TM = MF.getTarget();
222 const MCRegisterInfo *MRI = Context.getRegisterInfo();
223 const ARMBaseRegisterInfo *RegInfo = static_cast<const ARMBaseRegisterInfo *>(
224 TM.getSubtargetImpl()->getRegisterInfo());
225 const ARMBaseInstrInfo &TII = *static_cast<const ARMBaseInstrInfo *>(
226 TM.getSubtargetImpl()->getInstrInfo());
227 assert(!AFI->isThumb1OnlyFunction() &&
228 "This emitPrologue does not support Thumb1!");
229 bool isARM = !AFI->isThumbFunction();
231 TM.getSubtargetImpl()->getFrameLowering()->getStackAlignment();
232 unsigned ArgRegsSaveSize = AFI->getArgRegsSaveSize(Align);
233 unsigned NumBytes = MFI->getStackSize();
234 const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
235 DebugLoc dl = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
236 unsigned FramePtr = RegInfo->getFrameRegister(MF);
238 // Determine the sizes of each callee-save spill areas and record which frame
239 // belongs to which callee-save spill areas.
240 unsigned GPRCS1Size = 0, GPRCS2Size = 0, DPRCSSize = 0;
241 int FramePtrSpillFI = 0;
244 // All calls are tail calls in GHC calling conv, and functions have no
245 // prologue/epilogue.
246 if (MF.getFunction()->getCallingConv() == CallingConv::GHC)
249 StackAdjustingInsts DefCFAOffsetCandidates;
251 // Allocate the vararg register save area.
252 if (ArgRegsSaveSize) {
253 emitSPUpdate(isARM, MBB, MBBI, dl, TII, -ArgRegsSaveSize,
254 MachineInstr::FrameSetup);
255 DefCFAOffsetCandidates.addInst(std::prev(MBBI), ArgRegsSaveSize, true);
258 if (!AFI->hasStackFrame() &&
259 (!STI.isTargetWindows() || !WindowsRequiresStackProbe(MF, NumBytes))) {
260 if (NumBytes - ArgRegsSaveSize != 0) {
261 emitSPUpdate(isARM, MBB, MBBI, dl, TII, -(NumBytes - ArgRegsSaveSize),
262 MachineInstr::FrameSetup);
263 DefCFAOffsetCandidates.addInst(std::prev(MBBI),
264 NumBytes - ArgRegsSaveSize, true);
269 // Determine spill area sizes.
270 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
271 unsigned Reg = CSI[i].getReg();
272 int FI = CSI[i].getFrameIdx();
279 if (STI.isTargetDarwin()) {
294 FramePtrSpillFI = FI;
298 // This is a DPR. Exclude the aligned DPRCS2 spills.
301 if (Reg < ARM::D8 || Reg >= ARM::D8 + AFI->getNumAlignedDPRCS2Regs())
307 MachineBasicBlock::iterator LastPush = MBB.end(), GPRCS1Push, GPRCS2Push;
308 if (GPRCS1Size > 0) {
309 GPRCS1Push = LastPush = MBBI++;
310 DefCFAOffsetCandidates.addInst(LastPush, GPRCS1Size, true);
313 // Determine starting offsets of spill areas.
314 bool HasFP = hasFP(MF);
315 unsigned GPRCS1Offset = NumBytes - ArgRegsSaveSize - GPRCS1Size;
316 unsigned GPRCS2Offset = GPRCS1Offset - GPRCS2Size;
317 unsigned DPRAlign = DPRCSSize ? std::min(8U, Align) : 4U;
318 unsigned DPRGapSize = (GPRCS1Size + GPRCS2Size + ArgRegsSaveSize) % DPRAlign;
319 unsigned DPRCSOffset = GPRCS2Offset - DPRGapSize - DPRCSSize;
320 int FramePtrOffsetInPush = 0;
322 FramePtrOffsetInPush =
323 MFI->getObjectOffset(FramePtrSpillFI) + ArgRegsSaveSize;
324 AFI->setFramePtrSpillOffset(MFI->getObjectOffset(FramePtrSpillFI) +
327 AFI->setGPRCalleeSavedArea1Offset(GPRCS1Offset);
328 AFI->setGPRCalleeSavedArea2Offset(GPRCS2Offset);
329 AFI->setDPRCalleeSavedAreaOffset(DPRCSOffset);
332 if (GPRCS2Size > 0) {
333 GPRCS2Push = LastPush = MBBI++;
334 DefCFAOffsetCandidates.addInst(LastPush, GPRCS2Size);
337 // Prolog/epilog inserter assumes we correctly align DPRs on the stack, so our
338 // .cfi_offset operations will reflect that.
340 assert(DPRGapSize == 4 && "unexpected alignment requirements for DPRs");
341 if (tryFoldSPUpdateIntoPushPop(STI, MF, LastPush, DPRGapSize))
342 DefCFAOffsetCandidates.addExtraBytes(LastPush, DPRGapSize);
344 emitSPUpdate(isARM, MBB, MBBI, dl, TII, -DPRGapSize,
345 MachineInstr::FrameSetup);
346 DefCFAOffsetCandidates.addInst(std::prev(MBBI), DPRGapSize);
352 // Since vpush register list cannot have gaps, there may be multiple vpush
353 // instructions in the prologue.
354 while (MBBI->getOpcode() == ARM::VSTMDDB_UPD) {
355 DefCFAOffsetCandidates.addInst(MBBI, sizeOfSPAdjustment(MBBI));
360 // Move past the aligned DPRCS2 area.
361 if (AFI->getNumAlignedDPRCS2Regs() > 0) {
362 MBBI = skipAlignedDPRCS2Spills(MBBI, AFI->getNumAlignedDPRCS2Regs());
363 // The code inserted by emitAlignedDPRCS2Spills realigns the stack, and
364 // leaves the stack pointer pointing to the DPRCS2 area.
366 // Adjust NumBytes to represent the stack slots below the DPRCS2 area.
367 NumBytes += MFI->getObjectOffset(D8SpillFI);
369 NumBytes = DPRCSOffset;
371 if (STI.isTargetWindows() && WindowsRequiresStackProbe(MF, NumBytes)) {
372 uint32_t NumWords = NumBytes >> 2;
374 if (NumWords < 65536)
375 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::t2MOVi16), ARM::R4)
377 .setMIFlags(MachineInstr::FrameSetup));
379 BuildMI(MBB, MBBI, dl, TII.get(ARM::t2MOVi32imm), ARM::R4)
381 .setMIFlags(MachineInstr::FrameSetup);
383 switch (TM.getCodeModel()) {
384 case CodeModel::Small:
385 case CodeModel::Medium:
386 case CodeModel::Default:
387 case CodeModel::Kernel:
388 BuildMI(MBB, MBBI, dl, TII.get(ARM::tBL))
389 .addImm((unsigned)ARMCC::AL).addReg(0)
390 .addExternalSymbol("__chkstk")
391 .addReg(ARM::R4, RegState::Implicit)
392 .setMIFlags(MachineInstr::FrameSetup);
394 case CodeModel::Large:
395 case CodeModel::JITDefault:
396 BuildMI(MBB, MBBI, dl, TII.get(ARM::t2MOVi32imm), ARM::R12)
397 .addExternalSymbol("__chkstk")
398 .setMIFlags(MachineInstr::FrameSetup);
400 BuildMI(MBB, MBBI, dl, TII.get(ARM::tBLXr))
401 .addImm((unsigned)ARMCC::AL).addReg(0)
402 .addReg(ARM::R12, RegState::Kill)
403 .addReg(ARM::R4, RegState::Implicit)
404 .setMIFlags(MachineInstr::FrameSetup);
408 AddDefaultCC(AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::t2SUBrr),
410 .addReg(ARM::SP, RegState::Define)
411 .addReg(ARM::R4, RegState::Kill)
412 .setMIFlags(MachineInstr::FrameSetup)));
417 // Adjust SP after all the callee-save spills.
418 if (tryFoldSPUpdateIntoPushPop(STI, MF, LastPush, NumBytes))
419 DefCFAOffsetCandidates.addExtraBytes(LastPush, NumBytes);
421 emitSPUpdate(isARM, MBB, MBBI, dl, TII, -NumBytes,
422 MachineInstr::FrameSetup);
423 DefCFAOffsetCandidates.addInst(std::prev(MBBI), NumBytes);
427 // Restore from fp only in ARM mode: e.g. sub sp, r7, #24
428 // Note it's not safe to do this in Thumb2 mode because it would have
429 // taken two instructions:
432 // If an interrupt is taken between the two instructions, then sp is in
433 // an inconsistent state (pointing to the middle of callee-saved area).
434 // The interrupt handler can end up clobbering the registers.
435 AFI->setShouldRestoreSPFromFP(true);
438 // Set FP to point to the stack slot that contains the previous FP.
439 // For iOS, FP is R7, which has now been stored in spill area 1.
440 // Otherwise, if this is not iOS, all the callee-saved registers go
441 // into spill area 1, including the FP in R11. In either case, it
442 // is in area one and the adjustment needs to take place just after
445 MachineBasicBlock::iterator AfterPush = std::next(GPRCS1Push);
446 unsigned PushSize = sizeOfSPAdjustment(GPRCS1Push);
447 emitRegPlusImmediate(!AFI->isThumbFunction(), MBB, AfterPush,
448 dl, TII, FramePtr, ARM::SP,
449 PushSize + FramePtrOffsetInPush,
450 MachineInstr::FrameSetup);
451 if (FramePtrOffsetInPush + PushSize != 0) {
452 unsigned CFIIndex = MMI.addFrameInst(MCCFIInstruction::createDefCfa(
453 nullptr, MRI->getDwarfRegNum(FramePtr, true),
454 -(ArgRegsSaveSize - FramePtrOffsetInPush)));
455 BuildMI(MBB, AfterPush, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
456 .addCFIIndex(CFIIndex)
457 .setMIFlags(MachineInstr::FrameSetup);
460 MMI.addFrameInst(MCCFIInstruction::createDefCfaRegister(
461 nullptr, MRI->getDwarfRegNum(FramePtr, true)));
462 BuildMI(MBB, AfterPush, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
463 .addCFIIndex(CFIIndex)
464 .setMIFlags(MachineInstr::FrameSetup);
468 // Now that the prologue's actual instructions are finalised, we can insert
469 // the necessary DWARF cf instructions to describe the situation. Start by
470 // recording where each register ended up:
471 if (GPRCS1Size > 0) {
472 MachineBasicBlock::iterator Pos = std::next(GPRCS1Push);
474 for (const auto &Entry : CSI) {
475 unsigned Reg = Entry.getReg();
476 int FI = Entry.getFrameIdx();
483 if (STI.isTargetDarwin())
495 CFIIndex = MMI.addFrameInst(MCCFIInstruction::createOffset(
496 nullptr, MRI->getDwarfRegNum(Reg, true), MFI->getObjectOffset(FI)));
497 BuildMI(MBB, Pos, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
498 .addCFIIndex(CFIIndex)
499 .setMIFlags(MachineInstr::FrameSetup);
505 if (GPRCS2Size > 0) {
506 MachineBasicBlock::iterator Pos = std::next(GPRCS2Push);
507 for (const auto &Entry : CSI) {
508 unsigned Reg = Entry.getReg();
509 int FI = Entry.getFrameIdx();
516 if (STI.isTargetDarwin()) {
517 unsigned DwarfReg = MRI->getDwarfRegNum(Reg, true);
518 unsigned Offset = MFI->getObjectOffset(FI);
519 unsigned CFIIndex = MMI.addFrameInst(
520 MCCFIInstruction::createOffset(nullptr, DwarfReg, Offset));
521 BuildMI(MBB, Pos, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
522 .addCFIIndex(CFIIndex)
523 .setMIFlags(MachineInstr::FrameSetup);
531 // Since vpush register list cannot have gaps, there may be multiple vpush
532 // instructions in the prologue.
533 MachineBasicBlock::iterator Pos = std::next(LastPush);
534 for (const auto &Entry : CSI) {
535 unsigned Reg = Entry.getReg();
536 int FI = Entry.getFrameIdx();
537 if ((Reg >= ARM::D0 && Reg <= ARM::D31) &&
538 (Reg < ARM::D8 || Reg >= ARM::D8 + AFI->getNumAlignedDPRCS2Regs())) {
539 unsigned DwarfReg = MRI->getDwarfRegNum(Reg, true);
540 unsigned Offset = MFI->getObjectOffset(FI);
541 unsigned CFIIndex = MMI.addFrameInst(
542 MCCFIInstruction::createOffset(nullptr, DwarfReg, Offset));
543 BuildMI(MBB, Pos, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
544 .addCFIIndex(CFIIndex)
545 .setMIFlags(MachineInstr::FrameSetup);
550 // Now we can emit descriptions of where the canonical frame address was
551 // throughout the process. If we have a frame pointer, it takes over the job
552 // half-way through, so only the first few .cfi_def_cfa_offset instructions
553 // actually get emitted.
554 DefCFAOffsetCandidates.emitDefCFAOffsets(MMI, MBB, dl, TII, HasFP);
556 if (STI.isTargetELF() && hasFP(MF))
557 MFI->setOffsetAdjustment(MFI->getOffsetAdjustment() -
558 AFI->getFramePtrSpillOffset());
560 AFI->setGPRCalleeSavedArea1Size(GPRCS1Size);
561 AFI->setGPRCalleeSavedArea2Size(GPRCS2Size);
562 AFI->setDPRCalleeSavedGapSize(DPRGapSize);
563 AFI->setDPRCalleeSavedAreaSize(DPRCSSize);
565 // If we need dynamic stack realignment, do it here. Be paranoid and make
566 // sure if we also have VLAs, we have a base pointer for frame access.
567 // If aligned NEON registers were spilled, the stack has already been
569 if (!AFI->getNumAlignedDPRCS2Regs() && RegInfo->needsStackRealignment(MF)) {
570 unsigned MaxAlign = MFI->getMaxAlignment();
571 assert (!AFI->isThumb1OnlyFunction());
572 if (!AFI->isThumbFunction()) {
573 // Emit bic sp, sp, MaxAlign
574 AddDefaultCC(AddDefaultPred(BuildMI(MBB, MBBI, dl,
575 TII.get(ARM::BICri), ARM::SP)
576 .addReg(ARM::SP, RegState::Kill)
577 .addImm(MaxAlign-1)));
579 // We cannot use sp as source/dest register here, thus we're emitting the
580 // following sequence:
582 // bic r4, r4, MaxAlign
584 // FIXME: It will be better just to find spare register here.
585 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), ARM::R4)
586 .addReg(ARM::SP, RegState::Kill));
587 AddDefaultCC(AddDefaultPred(BuildMI(MBB, MBBI, dl,
588 TII.get(ARM::t2BICri), ARM::R4)
589 .addReg(ARM::R4, RegState::Kill)
590 .addImm(MaxAlign-1)));
591 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), ARM::SP)
592 .addReg(ARM::R4, RegState::Kill));
595 AFI->setShouldRestoreSPFromFP(true);
598 // If we need a base pointer, set it up here. It's whatever the value
599 // of the stack pointer is at this point. Any variable size objects
600 // will be allocated after this, so we can still use the base pointer
601 // to reference locals.
602 // FIXME: Clarify FrameSetup flags here.
603 if (RegInfo->hasBasePointer(MF)) {
605 BuildMI(MBB, MBBI, dl,
606 TII.get(ARM::MOVr), RegInfo->getBaseRegister())
608 .addImm((unsigned)ARMCC::AL).addReg(0).addReg(0);
610 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr),
611 RegInfo->getBaseRegister())
615 // If the frame has variable sized objects then the epilogue must restore
616 // the sp from fp. We can assume there's an FP here since hasFP already
617 // checks for hasVarSizedObjects.
618 if (MFI->hasVarSizedObjects())
619 AFI->setShouldRestoreSPFromFP(true);
622 // Resolve TCReturn pseudo-instruction
623 void ARMFrameLowering::fixTCReturn(MachineFunction &MF,
624 MachineBasicBlock &MBB) const {
625 MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr();
626 assert(MBBI->isReturn() && "Can only insert epilog into returning blocks");
627 unsigned RetOpcode = MBBI->getOpcode();
628 DebugLoc dl = MBBI->getDebugLoc();
629 const ARMBaseInstrInfo &TII =
630 *static_cast<const ARMBaseInstrInfo *>(MF.getSubtarget().getInstrInfo());
632 if (!(RetOpcode == ARM::TCRETURNdi || RetOpcode == ARM::TCRETURNri))
635 // Tail call return: adjust the stack pointer and jump to callee.
636 MBBI = MBB.getLastNonDebugInstr();
637 MachineOperand &JumpTarget = MBBI->getOperand(0);
639 // Jump to label or value in register.
640 if (RetOpcode == ARM::TCRETURNdi) {
641 unsigned TCOpcode = STI.isThumb() ?
642 (STI.isTargetMachO() ? ARM::tTAILJMPd : ARM::tTAILJMPdND) :
644 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII.get(TCOpcode));
645 if (JumpTarget.isGlobal())
646 MIB.addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset(),
647 JumpTarget.getTargetFlags());
649 assert(JumpTarget.isSymbol());
650 MIB.addExternalSymbol(JumpTarget.getSymbolName(),
651 JumpTarget.getTargetFlags());
654 // Add the default predicate in Thumb mode.
655 if (STI.isThumb()) MIB.addImm(ARMCC::AL).addReg(0);
656 } else if (RetOpcode == ARM::TCRETURNri) {
657 BuildMI(MBB, MBBI, dl,
658 TII.get(STI.isThumb() ? ARM::tTAILJMPr : ARM::TAILJMPr)).
659 addReg(JumpTarget.getReg(), RegState::Kill);
662 MachineInstr *NewMI = std::prev(MBBI);
663 for (unsigned i = 1, e = MBBI->getNumOperands(); i != e; ++i)
664 NewMI->addOperand(MBBI->getOperand(i));
666 // Delete the pseudo instruction TCRETURN.
671 void ARMFrameLowering::emitEpilogue(MachineFunction &MF,
672 MachineBasicBlock &MBB) const {
673 MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr();
674 assert(MBBI->isReturn() && "Can only insert epilog into returning blocks");
675 DebugLoc dl = MBBI->getDebugLoc();
676 MachineFrameInfo *MFI = MF.getFrameInfo();
677 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
678 const TargetRegisterInfo *RegInfo = MF.getSubtarget().getRegisterInfo();
679 const ARMBaseInstrInfo &TII =
680 *static_cast<const ARMBaseInstrInfo *>(MF.getSubtarget().getInstrInfo());
681 assert(!AFI->isThumb1OnlyFunction() &&
682 "This emitEpilogue does not support Thumb1!");
683 bool isARM = !AFI->isThumbFunction();
685 unsigned Align = MF.getTarget()
688 ->getStackAlignment();
689 unsigned ArgRegsSaveSize = AFI->getArgRegsSaveSize(Align);
690 int NumBytes = (int)MFI->getStackSize();
691 unsigned FramePtr = RegInfo->getFrameRegister(MF);
693 // All calls are tail calls in GHC calling conv, and functions have no
694 // prologue/epilogue.
695 if (MF.getFunction()->getCallingConv() == CallingConv::GHC) {
696 fixTCReturn(MF, MBB);
700 if (!AFI->hasStackFrame()) {
701 if (NumBytes - ArgRegsSaveSize != 0)
702 emitSPUpdate(isARM, MBB, MBBI, dl, TII, NumBytes - ArgRegsSaveSize);
704 // Unwind MBBI to point to first LDR / VLDRD.
705 const MCPhysReg *CSRegs = RegInfo->getCalleeSavedRegs(&MF);
706 if (MBBI != MBB.begin()) {
709 } while (MBBI != MBB.begin() && isCSRestore(MBBI, TII, CSRegs));
710 if (!isCSRestore(MBBI, TII, CSRegs))
714 // Move SP to start of FP callee save spill area.
715 NumBytes -= (ArgRegsSaveSize +
716 AFI->getGPRCalleeSavedArea1Size() +
717 AFI->getGPRCalleeSavedArea2Size() +
718 AFI->getDPRCalleeSavedGapSize() +
719 AFI->getDPRCalleeSavedAreaSize());
721 // Reset SP based on frame pointer only if the stack frame extends beyond
722 // frame pointer stack slot or target is ELF and the function has FP.
723 if (AFI->shouldRestoreSPFromFP()) {
724 NumBytes = AFI->getFramePtrSpillOffset() - NumBytes;
727 emitARMRegPlusImmediate(MBB, MBBI, dl, ARM::SP, FramePtr, -NumBytes,
730 // It's not possible to restore SP from FP in a single instruction.
731 // For iOS, this looks like:
734 // This is bad, if an interrupt is taken after the mov, sp is in an
735 // inconsistent state.
736 // Use the first callee-saved register as a scratch register.
737 assert(MF.getRegInfo().isPhysRegUsed(ARM::R4) &&
738 "No scratch register to restore SP from FP!");
739 emitT2RegPlusImmediate(MBB, MBBI, dl, ARM::R4, FramePtr, -NumBytes,
741 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr),
748 BuildMI(MBB, MBBI, dl, TII.get(ARM::MOVr), ARM::SP)
749 .addReg(FramePtr).addImm((unsigned)ARMCC::AL).addReg(0).addReg(0);
751 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr),
755 } else if (NumBytes &&
756 !tryFoldSPUpdateIntoPushPop(STI, MF, MBBI, NumBytes))
757 emitSPUpdate(isARM, MBB, MBBI, dl, TII, NumBytes);
759 // Increment past our save areas.
760 if (AFI->getDPRCalleeSavedAreaSize()) {
762 // Since vpop register list cannot have gaps, there may be multiple vpop
763 // instructions in the epilogue.
764 while (MBBI->getOpcode() == ARM::VLDMDIA_UPD)
767 if (AFI->getDPRCalleeSavedGapSize()) {
768 assert(AFI->getDPRCalleeSavedGapSize() == 4 &&
769 "unexpected DPR alignment gap");
770 emitSPUpdate(isARM, MBB, MBBI, dl, TII, AFI->getDPRCalleeSavedGapSize());
773 if (AFI->getGPRCalleeSavedArea2Size()) MBBI++;
774 if (AFI->getGPRCalleeSavedArea1Size()) MBBI++;
777 fixTCReturn(MF, MBB);
780 emitSPUpdate(isARM, MBB, MBBI, dl, TII, ArgRegsSaveSize);
783 /// getFrameIndexReference - Provide a base+offset reference to an FI slot for
784 /// debug info. It's the same as what we use for resolving the code-gen
785 /// references for now. FIXME: This can go wrong when references are
786 /// SP-relative and simple call frames aren't used.
788 ARMFrameLowering::getFrameIndexReference(const MachineFunction &MF, int FI,
789 unsigned &FrameReg) const {
790 return ResolveFrameIndexReference(MF, FI, FrameReg, 0);
794 ARMFrameLowering::ResolveFrameIndexReference(const MachineFunction &MF,
795 int FI, unsigned &FrameReg,
797 const MachineFrameInfo *MFI = MF.getFrameInfo();
798 const ARMBaseRegisterInfo *RegInfo = static_cast<const ARMBaseRegisterInfo *>(
799 MF.getSubtarget().getRegisterInfo());
800 const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
801 int Offset = MFI->getObjectOffset(FI) + MFI->getStackSize();
802 int FPOffset = Offset - AFI->getFramePtrSpillOffset();
803 bool isFixed = MFI->isFixedObjectIndex(FI);
808 // SP can move around if there are allocas. We may also lose track of SP
809 // when emergency spilling inside a non-reserved call frame setup.
810 bool hasMovingSP = !hasReservedCallFrame(MF);
812 // When dynamically realigning the stack, use the frame pointer for
813 // parameters, and the stack/base pointer for locals.
814 if (RegInfo->needsStackRealignment(MF)) {
815 assert (hasFP(MF) && "dynamic stack realignment without a FP!");
817 FrameReg = RegInfo->getFrameRegister(MF);
819 } else if (hasMovingSP) {
820 assert(RegInfo->hasBasePointer(MF) &&
821 "VLAs and dynamic stack alignment, but missing base pointer!");
822 FrameReg = RegInfo->getBaseRegister();
827 // If there is a frame pointer, use it when we can.
828 if (hasFP(MF) && AFI->hasStackFrame()) {
829 // Use frame pointer to reference fixed objects. Use it for locals if
830 // there are VLAs (and thus the SP isn't reliable as a base).
831 if (isFixed || (hasMovingSP && !RegInfo->hasBasePointer(MF))) {
832 FrameReg = RegInfo->getFrameRegister(MF);
834 } else if (hasMovingSP) {
835 assert(RegInfo->hasBasePointer(MF) && "missing base pointer!");
836 if (AFI->isThumb2Function()) {
837 // Try to use the frame pointer if we can, else use the base pointer
838 // since it's available. This is handy for the emergency spill slot, in
840 if (FPOffset >= -255 && FPOffset < 0) {
841 FrameReg = RegInfo->getFrameRegister(MF);
845 } else if (AFI->isThumb2Function()) {
846 // Use add <rd>, sp, #<imm8>
847 // ldr <rd>, [sp, #<imm8>]
848 // if at all possible to save space.
849 if (Offset >= 0 && (Offset & 3) == 0 && Offset <= 1020)
851 // In Thumb2 mode, the negative offset is very limited. Try to avoid
852 // out of range references. ldr <rt>,[<rn>, #-<imm8>]
853 if (FPOffset >= -255 && FPOffset < 0) {
854 FrameReg = RegInfo->getFrameRegister(MF);
857 } else if (Offset > (FPOffset < 0 ? -FPOffset : FPOffset)) {
858 // Otherwise, use SP or FP, whichever is closer to the stack slot.
859 FrameReg = RegInfo->getFrameRegister(MF);
863 // Use the base pointer if we have one.
864 if (RegInfo->hasBasePointer(MF))
865 FrameReg = RegInfo->getBaseRegister();
869 int ARMFrameLowering::getFrameIndexOffset(const MachineFunction &MF,
872 return getFrameIndexReference(MF, FI, FrameReg);
875 void ARMFrameLowering::emitPushInst(MachineBasicBlock &MBB,
876 MachineBasicBlock::iterator MI,
877 const std::vector<CalleeSavedInfo> &CSI,
878 unsigned StmOpc, unsigned StrOpc,
880 bool(*Func)(unsigned, bool),
881 unsigned NumAlignedDPRCS2Regs,
882 unsigned MIFlags) const {
883 MachineFunction &MF = *MBB.getParent();
884 const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
887 if (MI != MBB.end()) DL = MI->getDebugLoc();
889 SmallVector<std::pair<unsigned,bool>, 4> Regs;
890 unsigned i = CSI.size();
892 unsigned LastReg = 0;
893 for (; i != 0; --i) {
894 unsigned Reg = CSI[i-1].getReg();
895 if (!(Func)(Reg, STI.isTargetDarwin())) continue;
897 // D-registers in the aligned area DPRCS2 are NOT spilled here.
898 if (Reg >= ARM::D8 && Reg < ARM::D8 + NumAlignedDPRCS2Regs)
901 // Add the callee-saved register as live-in unless it's LR and
902 // @llvm.returnaddress is called. If LR is returned for
903 // @llvm.returnaddress then it's already added to the function and
904 // entry block live-in sets.
906 if (Reg == ARM::LR) {
907 if (MF.getFrameInfo()->isReturnAddressTaken() &&
908 MF.getRegInfo().isLiveIn(Reg))
915 // If NoGap is true, push consecutive registers and then leave the rest
916 // for other instructions. e.g.
917 // vpush {d8, d10, d11} -> vpush {d8}, vpush {d10, d11}
918 if (NoGap && LastReg && LastReg != Reg-1)
921 Regs.push_back(std::make_pair(Reg, isKill));
926 if (Regs.size() > 1 || StrOpc== 0) {
927 MachineInstrBuilder MIB =
928 AddDefaultPred(BuildMI(MBB, MI, DL, TII.get(StmOpc), ARM::SP)
929 .addReg(ARM::SP).setMIFlags(MIFlags));
930 for (unsigned i = 0, e = Regs.size(); i < e; ++i)
931 MIB.addReg(Regs[i].first, getKillRegState(Regs[i].second));
932 } else if (Regs.size() == 1) {
933 MachineInstrBuilder MIB = BuildMI(MBB, MI, DL, TII.get(StrOpc),
935 .addReg(Regs[0].first, getKillRegState(Regs[0].second))
936 .addReg(ARM::SP).setMIFlags(MIFlags)
942 // Put any subsequent vpush instructions before this one: they will refer to
943 // higher register numbers so need to be pushed first in order to preserve
949 void ARMFrameLowering::emitPopInst(MachineBasicBlock &MBB,
950 MachineBasicBlock::iterator MI,
951 const std::vector<CalleeSavedInfo> &CSI,
952 unsigned LdmOpc, unsigned LdrOpc,
953 bool isVarArg, bool NoGap,
954 bool(*Func)(unsigned, bool),
955 unsigned NumAlignedDPRCS2Regs) const {
956 MachineFunction &MF = *MBB.getParent();
957 const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
958 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
959 DebugLoc DL = MI->getDebugLoc();
960 unsigned RetOpcode = MI->getOpcode();
961 bool isTailCall = (RetOpcode == ARM::TCRETURNdi ||
962 RetOpcode == ARM::TCRETURNri);
964 RetOpcode == ARM::SUBS_PC_LR || RetOpcode == ARM::t2SUBS_PC_LR;
966 SmallVector<unsigned, 4> Regs;
967 unsigned i = CSI.size();
969 unsigned LastReg = 0;
970 bool DeleteRet = false;
971 for (; i != 0; --i) {
972 unsigned Reg = CSI[i-1].getReg();
973 if (!(Func)(Reg, STI.isTargetDarwin())) continue;
975 // The aligned reloads from area DPRCS2 are not inserted here.
976 if (Reg >= ARM::D8 && Reg < ARM::D8 + NumAlignedDPRCS2Regs)
979 if (Reg == ARM::LR && !isTailCall && !isVarArg && !isInterrupt &&
982 LdmOpc = AFI->isThumbFunction() ? ARM::t2LDMIA_RET : ARM::LDMIA_RET;
983 // Fold the return instruction into the LDM.
987 // If NoGap is true, pop consecutive registers and then leave the rest
988 // for other instructions. e.g.
989 // vpop {d8, d10, d11} -> vpop {d8}, vpop {d10, d11}
990 if (NoGap && LastReg && LastReg != Reg-1)
999 if (Regs.size() > 1 || LdrOpc == 0) {
1000 MachineInstrBuilder MIB =
1001 AddDefaultPred(BuildMI(MBB, MI, DL, TII.get(LdmOpc), ARM::SP)
1003 for (unsigned i = 0, e = Regs.size(); i < e; ++i)
1004 MIB.addReg(Regs[i], getDefRegState(true));
1006 MIB.copyImplicitOps(&*MI);
1007 MI->eraseFromParent();
1010 } else if (Regs.size() == 1) {
1011 // If we adjusted the reg to PC from LR above, switch it back here. We
1012 // only do that for LDM.
1013 if (Regs[0] == ARM::PC)
1015 MachineInstrBuilder MIB =
1016 BuildMI(MBB, MI, DL, TII.get(LdrOpc), Regs[0])
1017 .addReg(ARM::SP, RegState::Define)
1019 // ARM mode needs an extra reg0 here due to addrmode2. Will go away once
1020 // that refactoring is complete (eventually).
1021 if (LdrOpc == ARM::LDR_POST_REG || LdrOpc == ARM::LDR_POST_IMM) {
1023 MIB.addImm(ARM_AM::getAM2Opc(ARM_AM::add, 4, ARM_AM::no_shift));
1026 AddDefaultPred(MIB);
1030 // Put any subsequent vpop instructions after this one: they will refer to
1031 // higher register numbers so need to be popped afterwards.
1036 /// Emit aligned spill instructions for NumAlignedDPRCS2Regs D-registers
1037 /// starting from d8. Also insert stack realignment code and leave the stack
1038 /// pointer pointing to the d8 spill slot.
1039 static void emitAlignedDPRCS2Spills(MachineBasicBlock &MBB,
1040 MachineBasicBlock::iterator MI,
1041 unsigned NumAlignedDPRCS2Regs,
1042 const std::vector<CalleeSavedInfo> &CSI,
1043 const TargetRegisterInfo *TRI) {
1044 MachineFunction &MF = *MBB.getParent();
1045 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1046 DebugLoc DL = MI->getDebugLoc();
1047 const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
1048 MachineFrameInfo &MFI = *MF.getFrameInfo();
1050 // Mark the D-register spill slots as properly aligned. Since MFI computes
1051 // stack slot layout backwards, this can actually mean that the d-reg stack
1052 // slot offsets can be wrong. The offset for d8 will always be correct.
1053 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
1054 unsigned DNum = CSI[i].getReg() - ARM::D8;
1057 int FI = CSI[i].getFrameIdx();
1058 // The even-numbered registers will be 16-byte aligned, the odd-numbered
1059 // registers will be 8-byte aligned.
1060 MFI.setObjectAlignment(FI, DNum % 2 ? 8 : 16);
1062 // The stack slot for D8 needs to be maximally aligned because this is
1063 // actually the point where we align the stack pointer. MachineFrameInfo
1064 // computes all offsets relative to the incoming stack pointer which is a
1065 // bit weird when realigning the stack. Any extra padding for this
1066 // over-alignment is not realized because the code inserted below adjusts
1067 // the stack pointer by numregs * 8 before aligning the stack pointer.
1069 MFI.setObjectAlignment(FI, MFI.getMaxAlignment());
1072 // Move the stack pointer to the d8 spill slot, and align it at the same
1073 // time. Leave the stack slot address in the scratch register r4.
1075 // sub r4, sp, #numregs * 8
1076 // bic r4, r4, #align - 1
1079 bool isThumb = AFI->isThumbFunction();
1080 assert(!AFI->isThumb1OnlyFunction() && "Can't realign stack for thumb1");
1081 AFI->setShouldRestoreSPFromFP(true);
1083 // sub r4, sp, #numregs * 8
1084 // The immediate is <= 64, so it doesn't need any special encoding.
1085 unsigned Opc = isThumb ? ARM::t2SUBri : ARM::SUBri;
1086 AddDefaultCC(AddDefaultPred(BuildMI(MBB, MI, DL, TII.get(Opc), ARM::R4)
1088 .addImm(8 * NumAlignedDPRCS2Regs)));
1090 // bic r4, r4, #align-1
1091 Opc = isThumb ? ARM::t2BICri : ARM::BICri;
1092 unsigned MaxAlign = MF.getFrameInfo()->getMaxAlignment();
1093 AddDefaultCC(AddDefaultPred(BuildMI(MBB, MI, DL, TII.get(Opc), ARM::R4)
1094 .addReg(ARM::R4, RegState::Kill)
1095 .addImm(MaxAlign - 1)));
1098 // The stack pointer must be adjusted before spilling anything, otherwise
1099 // the stack slots could be clobbered by an interrupt handler.
1100 // Leave r4 live, it is used below.
1101 Opc = isThumb ? ARM::tMOVr : ARM::MOVr;
1102 MachineInstrBuilder MIB = BuildMI(MBB, MI, DL, TII.get(Opc), ARM::SP)
1104 MIB = AddDefaultPred(MIB);
1108 // Now spill NumAlignedDPRCS2Regs registers starting from d8.
1109 // r4 holds the stack slot address.
1110 unsigned NextReg = ARM::D8;
1112 // 16-byte aligned vst1.64 with 4 d-regs and address writeback.
1113 // The writeback is only needed when emitting two vst1.64 instructions.
1114 if (NumAlignedDPRCS2Regs >= 6) {
1115 unsigned SupReg = TRI->getMatchingSuperReg(NextReg, ARM::dsub_0,
1116 &ARM::QQPRRegClass);
1117 MBB.addLiveIn(SupReg);
1118 AddDefaultPred(BuildMI(MBB, MI, DL, TII.get(ARM::VST1d64Qwb_fixed),
1120 .addReg(ARM::R4, RegState::Kill).addImm(16)
1122 .addReg(SupReg, RegState::ImplicitKill));
1124 NumAlignedDPRCS2Regs -= 4;
1127 // We won't modify r4 beyond this point. It currently points to the next
1128 // register to be spilled.
1129 unsigned R4BaseReg = NextReg;
1131 // 16-byte aligned vst1.64 with 4 d-regs, no writeback.
1132 if (NumAlignedDPRCS2Regs >= 4) {
1133 unsigned SupReg = TRI->getMatchingSuperReg(NextReg, ARM::dsub_0,
1134 &ARM::QQPRRegClass);
1135 MBB.addLiveIn(SupReg);
1136 AddDefaultPred(BuildMI(MBB, MI, DL, TII.get(ARM::VST1d64Q))
1137 .addReg(ARM::R4).addImm(16).addReg(NextReg)
1138 .addReg(SupReg, RegState::ImplicitKill));
1140 NumAlignedDPRCS2Regs -= 4;
1143 // 16-byte aligned vst1.64 with 2 d-regs.
1144 if (NumAlignedDPRCS2Regs >= 2) {
1145 unsigned SupReg = TRI->getMatchingSuperReg(NextReg, ARM::dsub_0,
1147 MBB.addLiveIn(SupReg);
1148 AddDefaultPred(BuildMI(MBB, MI, DL, TII.get(ARM::VST1q64))
1149 .addReg(ARM::R4).addImm(16).addReg(SupReg));
1151 NumAlignedDPRCS2Regs -= 2;
1154 // Finally, use a vanilla vstr.64 for the odd last register.
1155 if (NumAlignedDPRCS2Regs) {
1156 MBB.addLiveIn(NextReg);
1157 // vstr.64 uses addrmode5 which has an offset scale of 4.
1158 AddDefaultPred(BuildMI(MBB, MI, DL, TII.get(ARM::VSTRD))
1160 .addReg(ARM::R4).addImm((NextReg-R4BaseReg)*2));
1163 // The last spill instruction inserted should kill the scratch register r4.
1164 std::prev(MI)->addRegisterKilled(ARM::R4, TRI);
1167 /// Skip past the code inserted by emitAlignedDPRCS2Spills, and return an
1168 /// iterator to the following instruction.
1169 static MachineBasicBlock::iterator
1170 skipAlignedDPRCS2Spills(MachineBasicBlock::iterator MI,
1171 unsigned NumAlignedDPRCS2Regs) {
1172 // sub r4, sp, #numregs * 8
1173 // bic r4, r4, #align - 1
1176 assert(MI->mayStore() && "Expecting spill instruction");
1178 // These switches all fall through.
1179 switch(NumAlignedDPRCS2Regs) {
1182 assert(MI->mayStore() && "Expecting spill instruction");
1185 assert(MI->mayStore() && "Expecting spill instruction");
1189 assert(MI->killsRegister(ARM::R4) && "Missed kill flag");
1195 /// Emit aligned reload instructions for NumAlignedDPRCS2Regs D-registers
1196 /// starting from d8. These instructions are assumed to execute while the
1197 /// stack is still aligned, unlike the code inserted by emitPopInst.
1198 static void emitAlignedDPRCS2Restores(MachineBasicBlock &MBB,
1199 MachineBasicBlock::iterator MI,
1200 unsigned NumAlignedDPRCS2Regs,
1201 const std::vector<CalleeSavedInfo> &CSI,
1202 const TargetRegisterInfo *TRI) {
1203 MachineFunction &MF = *MBB.getParent();
1204 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1205 DebugLoc DL = MI->getDebugLoc();
1206 const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
1208 // Find the frame index assigned to d8.
1210 for (unsigned i = 0, e = CSI.size(); i != e; ++i)
1211 if (CSI[i].getReg() == ARM::D8) {
1212 D8SpillFI = CSI[i].getFrameIdx();
1216 // Materialize the address of the d8 spill slot into the scratch register r4.
1217 // This can be fairly complicated if the stack frame is large, so just use
1218 // the normal frame index elimination mechanism to do it. This code runs as
1219 // the initial part of the epilog where the stack and base pointers haven't
1220 // been changed yet.
1221 bool isThumb = AFI->isThumbFunction();
1222 assert(!AFI->isThumb1OnlyFunction() && "Can't realign stack for thumb1");
1224 unsigned Opc = isThumb ? ARM::t2ADDri : ARM::ADDri;
1225 AddDefaultCC(AddDefaultPred(BuildMI(MBB, MI, DL, TII.get(Opc), ARM::R4)
1226 .addFrameIndex(D8SpillFI).addImm(0)));
1228 // Now restore NumAlignedDPRCS2Regs registers starting from d8.
1229 unsigned NextReg = ARM::D8;
1231 // 16-byte aligned vld1.64 with 4 d-regs and writeback.
1232 if (NumAlignedDPRCS2Regs >= 6) {
1233 unsigned SupReg = TRI->getMatchingSuperReg(NextReg, ARM::dsub_0,
1234 &ARM::QQPRRegClass);
1235 AddDefaultPred(BuildMI(MBB, MI, DL, TII.get(ARM::VLD1d64Qwb_fixed), NextReg)
1236 .addReg(ARM::R4, RegState::Define)
1237 .addReg(ARM::R4, RegState::Kill).addImm(16)
1238 .addReg(SupReg, RegState::ImplicitDefine));
1240 NumAlignedDPRCS2Regs -= 4;
1243 // We won't modify r4 beyond this point. It currently points to the next
1244 // register to be spilled.
1245 unsigned R4BaseReg = NextReg;
1247 // 16-byte aligned vld1.64 with 4 d-regs, no writeback.
1248 if (NumAlignedDPRCS2Regs >= 4) {
1249 unsigned SupReg = TRI->getMatchingSuperReg(NextReg, ARM::dsub_0,
1250 &ARM::QQPRRegClass);
1251 AddDefaultPred(BuildMI(MBB, MI, DL, TII.get(ARM::VLD1d64Q), NextReg)
1252 .addReg(ARM::R4).addImm(16)
1253 .addReg(SupReg, RegState::ImplicitDefine));
1255 NumAlignedDPRCS2Regs -= 4;
1258 // 16-byte aligned vld1.64 with 2 d-regs.
1259 if (NumAlignedDPRCS2Regs >= 2) {
1260 unsigned SupReg = TRI->getMatchingSuperReg(NextReg, ARM::dsub_0,
1262 AddDefaultPred(BuildMI(MBB, MI, DL, TII.get(ARM::VLD1q64), SupReg)
1263 .addReg(ARM::R4).addImm(16));
1265 NumAlignedDPRCS2Regs -= 2;
1268 // Finally, use a vanilla vldr.64 for the remaining odd register.
1269 if (NumAlignedDPRCS2Regs)
1270 AddDefaultPred(BuildMI(MBB, MI, DL, TII.get(ARM::VLDRD), NextReg)
1271 .addReg(ARM::R4).addImm(2*(NextReg-R4BaseReg)));
1273 // Last store kills r4.
1274 std::prev(MI)->addRegisterKilled(ARM::R4, TRI);
1277 bool ARMFrameLowering::spillCalleeSavedRegisters(MachineBasicBlock &MBB,
1278 MachineBasicBlock::iterator MI,
1279 const std::vector<CalleeSavedInfo> &CSI,
1280 const TargetRegisterInfo *TRI) const {
1284 MachineFunction &MF = *MBB.getParent();
1285 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1287 unsigned PushOpc = AFI->isThumbFunction() ? ARM::t2STMDB_UPD : ARM::STMDB_UPD;
1288 unsigned PushOneOpc = AFI->isThumbFunction() ?
1289 ARM::t2STR_PRE : ARM::STR_PRE_IMM;
1290 unsigned FltOpc = ARM::VSTMDDB_UPD;
1291 unsigned NumAlignedDPRCS2Regs = AFI->getNumAlignedDPRCS2Regs();
1292 emitPushInst(MBB, MI, CSI, PushOpc, PushOneOpc, false, &isARMArea1Register, 0,
1293 MachineInstr::FrameSetup);
1294 emitPushInst(MBB, MI, CSI, PushOpc, PushOneOpc, false, &isARMArea2Register, 0,
1295 MachineInstr::FrameSetup);
1296 emitPushInst(MBB, MI, CSI, FltOpc, 0, true, &isARMArea3Register,
1297 NumAlignedDPRCS2Regs, MachineInstr::FrameSetup);
1299 // The code above does not insert spill code for the aligned DPRCS2 registers.
1300 // The stack realignment code will be inserted between the push instructions
1301 // and these spills.
1302 if (NumAlignedDPRCS2Regs)
1303 emitAlignedDPRCS2Spills(MBB, MI, NumAlignedDPRCS2Regs, CSI, TRI);
1308 bool ARMFrameLowering::restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
1309 MachineBasicBlock::iterator MI,
1310 const std::vector<CalleeSavedInfo> &CSI,
1311 const TargetRegisterInfo *TRI) const {
1315 MachineFunction &MF = *MBB.getParent();
1316 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1317 bool isVarArg = AFI->getArgRegsSaveSize() > 0;
1318 unsigned NumAlignedDPRCS2Regs = AFI->getNumAlignedDPRCS2Regs();
1320 // The emitPopInst calls below do not insert reloads for the aligned DPRCS2
1321 // registers. Do that here instead.
1322 if (NumAlignedDPRCS2Regs)
1323 emitAlignedDPRCS2Restores(MBB, MI, NumAlignedDPRCS2Regs, CSI, TRI);
1325 unsigned PopOpc = AFI->isThumbFunction() ? ARM::t2LDMIA_UPD : ARM::LDMIA_UPD;
1326 unsigned LdrOpc = AFI->isThumbFunction() ? ARM::t2LDR_POST :ARM::LDR_POST_IMM;
1327 unsigned FltOpc = ARM::VLDMDIA_UPD;
1328 emitPopInst(MBB, MI, CSI, FltOpc, 0, isVarArg, true, &isARMArea3Register,
1329 NumAlignedDPRCS2Regs);
1330 emitPopInst(MBB, MI, CSI, PopOpc, LdrOpc, isVarArg, false,
1331 &isARMArea2Register, 0);
1332 emitPopInst(MBB, MI, CSI, PopOpc, LdrOpc, isVarArg, false,
1333 &isARMArea1Register, 0);
1338 // FIXME: Make generic?
1339 static unsigned GetFunctionSizeInBytes(const MachineFunction &MF,
1340 const ARMBaseInstrInfo &TII) {
1341 unsigned FnSize = 0;
1342 for (auto &MBB : MF) {
1343 for (auto &MI : MBB)
1344 FnSize += TII.GetInstSizeInBytes(&MI);
1349 /// estimateRSStackSizeLimit - Look at each instruction that references stack
1350 /// frames and return the stack size limit beyond which some of these
1351 /// instructions will require a scratch register during their expansion later.
1352 // FIXME: Move to TII?
1353 static unsigned estimateRSStackSizeLimit(MachineFunction &MF,
1354 const TargetFrameLowering *TFI) {
1355 const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1356 unsigned Limit = (1 << 12) - 1;
1357 for (auto &MBB : MF) {
1358 for (auto &MI : MBB) {
1359 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
1360 if (!MI.getOperand(i).isFI())
1363 // When using ADDri to get the address of a stack object, 255 is the
1364 // largest offset guaranteed to fit in the immediate offset.
1365 if (MI.getOpcode() == ARM::ADDri) {
1366 Limit = std::min(Limit, (1U << 8) - 1);
1370 // Otherwise check the addressing mode.
1371 switch (MI.getDesc().TSFlags & ARMII::AddrModeMask) {
1372 case ARMII::AddrMode3:
1373 case ARMII::AddrModeT2_i8:
1374 Limit = std::min(Limit, (1U << 8) - 1);
1376 case ARMII::AddrMode5:
1377 case ARMII::AddrModeT2_i8s4:
1378 Limit = std::min(Limit, ((1U << 8) - 1) * 4);
1380 case ARMII::AddrModeT2_i12:
1381 // i12 supports only positive offset so these will be converted to
1382 // i8 opcodes. See llvm::rewriteT2FrameIndex.
1383 if (TFI->hasFP(MF) && AFI->hasStackFrame())
1384 Limit = std::min(Limit, (1U << 8) - 1);
1386 case ARMII::AddrMode4:
1387 case ARMII::AddrMode6:
1388 // Addressing modes 4 & 6 (load/store) instructions can't encode an
1389 // immediate offset for stack references.
1394 break; // At most one FI per instruction
1402 // In functions that realign the stack, it can be an advantage to spill the
1403 // callee-saved vector registers after realigning the stack. The vst1 and vld1
1404 // instructions take alignment hints that can improve performance.
1406 static void checkNumAlignedDPRCS2Regs(MachineFunction &MF) {
1407 MF.getInfo<ARMFunctionInfo>()->setNumAlignedDPRCS2Regs(0);
1408 if (!SpillAlignedNEONRegs)
1411 // Naked functions don't spill callee-saved registers.
1412 if (MF.getFunction()->getAttributes().hasAttribute(AttributeSet::FunctionIndex,
1416 // We are planning to use NEON instructions vst1 / vld1.
1417 if (!MF.getTarget().getSubtarget<ARMSubtarget>().hasNEON())
1420 // Don't bother if the default stack alignment is sufficiently high.
1423 ->getFrameLowering()
1424 ->getStackAlignment() >= 8)
1427 // Aligned spills require stack realignment.
1428 const ARMBaseRegisterInfo *RegInfo = static_cast<const ARMBaseRegisterInfo *>(
1429 MF.getSubtarget().getRegisterInfo());
1430 if (!RegInfo->canRealignStack(MF))
1433 // We always spill contiguous d-registers starting from d8. Count how many
1434 // needs spilling. The register allocator will almost always use the
1435 // callee-saved registers in order, but it can happen that there are holes in
1436 // the range. Registers above the hole will be spilled to the standard DPRCS
1438 MachineRegisterInfo &MRI = MF.getRegInfo();
1439 unsigned NumSpills = 0;
1440 for (; NumSpills < 8; ++NumSpills)
1441 if (!MRI.isPhysRegUsed(ARM::D8 + NumSpills))
1444 // Don't do this for just one d-register. It's not worth it.
1448 // Spill the first NumSpills D-registers after realigning the stack.
1449 MF.getInfo<ARMFunctionInfo>()->setNumAlignedDPRCS2Regs(NumSpills);
1451 // A scratch register is required for the vst1 / vld1 instructions.
1452 MF.getRegInfo().setPhysRegUsed(ARM::R4);
1456 ARMFrameLowering::processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
1457 RegScavenger *RS) const {
1458 // This tells PEI to spill the FP as if it is any other callee-save register
1459 // to take advantage the eliminateFrameIndex machinery. This also ensures it
1460 // is spilled in the order specified by getCalleeSavedRegs() to make it easier
1461 // to combine multiple loads / stores.
1462 bool CanEliminateFrame = true;
1463 bool CS1Spilled = false;
1464 bool LRSpilled = false;
1465 unsigned NumGPRSpills = 0;
1466 SmallVector<unsigned, 4> UnspilledCS1GPRs;
1467 SmallVector<unsigned, 4> UnspilledCS2GPRs;
1468 const ARMBaseRegisterInfo *RegInfo = static_cast<const ARMBaseRegisterInfo *>(
1469 MF.getSubtarget().getRegisterInfo());
1470 const ARMBaseInstrInfo &TII =
1471 *static_cast<const ARMBaseInstrInfo *>(MF.getSubtarget().getInstrInfo());
1472 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1473 MachineFrameInfo *MFI = MF.getFrameInfo();
1474 MachineRegisterInfo &MRI = MF.getRegInfo();
1475 unsigned FramePtr = RegInfo->getFrameRegister(MF);
1477 // Spill R4 if Thumb2 function requires stack realignment - it will be used as
1478 // scratch register. Also spill R4 if Thumb2 function has varsized objects,
1479 // since it's not always possible to restore sp from fp in a single
1481 // FIXME: It will be better just to find spare register here.
1482 if (AFI->isThumb2Function() &&
1483 (MFI->hasVarSizedObjects() || RegInfo->needsStackRealignment(MF)))
1484 MRI.setPhysRegUsed(ARM::R4);
1486 if (AFI->isThumb1OnlyFunction()) {
1487 // Spill LR if Thumb1 function uses variable length argument lists.
1488 if (AFI->getArgRegsSaveSize() > 0)
1489 MRI.setPhysRegUsed(ARM::LR);
1491 // Spill R4 if Thumb1 epilogue has to restore SP from FP. We don't know
1492 // for sure what the stack size will be, but for this, an estimate is good
1493 // enough. If there anything changes it, it'll be a spill, which implies
1494 // we've used all the registers and so R4 is already used, so not marking
1495 // it here will be OK.
1496 // FIXME: It will be better just to find spare register here.
1497 unsigned StackSize = MFI->estimateStackSize(MF);
1498 if (MFI->hasVarSizedObjects() || StackSize > 508)
1499 MRI.setPhysRegUsed(ARM::R4);
1502 // See if we can spill vector registers to aligned stack.
1503 checkNumAlignedDPRCS2Regs(MF);
1505 // Spill the BasePtr if it's used.
1506 if (RegInfo->hasBasePointer(MF))
1507 MRI.setPhysRegUsed(RegInfo->getBaseRegister());
1509 // Don't spill FP if the frame can be eliminated. This is determined
1510 // by scanning the callee-save registers to see if any is used.
1511 const MCPhysReg *CSRegs = RegInfo->getCalleeSavedRegs(&MF);
1512 for (unsigned i = 0; CSRegs[i]; ++i) {
1513 unsigned Reg = CSRegs[i];
1514 bool Spilled = false;
1515 if (MRI.isPhysRegUsed(Reg)) {
1517 CanEliminateFrame = false;
1520 if (!ARM::GPRRegClass.contains(Reg))
1526 if (!STI.isTargetDarwin()) {
1533 // Keep track if LR and any of R4, R5, R6, and R7 is spilled.
1538 case ARM::R0: case ARM::R1:
1539 case ARM::R2: case ARM::R3:
1540 case ARM::R4: case ARM::R5:
1541 case ARM::R6: case ARM::R7:
1548 if (!STI.isTargetDarwin()) {
1549 UnspilledCS1GPRs.push_back(Reg);
1554 case ARM::R0: case ARM::R1:
1555 case ARM::R2: case ARM::R3:
1556 case ARM::R4: case ARM::R5:
1557 case ARM::R6: case ARM::R7:
1559 UnspilledCS1GPRs.push_back(Reg);
1562 UnspilledCS2GPRs.push_back(Reg);
1568 bool ForceLRSpill = false;
1569 if (!LRSpilled && AFI->isThumb1OnlyFunction()) {
1570 unsigned FnSize = GetFunctionSizeInBytes(MF, TII);
1571 // Force LR to be spilled if the Thumb function size is > 2048. This enables
1572 // use of BL to implement far jump. If it turns out that it's not needed
1573 // then the branch fix up path will undo it.
1574 if (FnSize >= (1 << 11)) {
1575 CanEliminateFrame = false;
1576 ForceLRSpill = true;
1580 // If any of the stack slot references may be out of range of an immediate
1581 // offset, make sure a register (or a spill slot) is available for the
1582 // register scavenger. Note that if we're indexing off the frame pointer, the
1583 // effective stack size is 4 bytes larger since the FP points to the stack
1584 // slot of the previous FP. Also, if we have variable sized objects in the
1585 // function, stack slot references will often be negative, and some of
1586 // our instructions are positive-offset only, so conservatively consider
1587 // that case to want a spill slot (or register) as well. Similarly, if
1588 // the function adjusts the stack pointer during execution and the
1589 // adjustments aren't already part of our stack size estimate, our offset
1590 // calculations may be off, so be conservative.
1591 // FIXME: We could add logic to be more precise about negative offsets
1592 // and which instructions will need a scratch register for them. Is it
1593 // worth the effort and added fragility?
1596 (MFI->estimateStackSize(MF) +
1597 ((hasFP(MF) && AFI->hasStackFrame()) ? 4:0) >=
1598 estimateRSStackSizeLimit(MF, this)))
1599 || MFI->hasVarSizedObjects()
1600 || (MFI->adjustsStack() && !canSimplifyCallFramePseudos(MF));
1602 bool ExtraCSSpill = false;
1603 if (BigStack || !CanEliminateFrame || RegInfo->cannotEliminateFrame(MF)) {
1604 AFI->setHasStackFrame(true);
1606 // If LR is not spilled, but at least one of R4, R5, R6, and R7 is spilled.
1607 // Spill LR as well so we can fold BX_RET to the registers restore (LDM).
1608 if (!LRSpilled && CS1Spilled) {
1609 MRI.setPhysRegUsed(ARM::LR);
1611 SmallVectorImpl<unsigned>::iterator LRPos;
1612 LRPos = std::find(UnspilledCS1GPRs.begin(), UnspilledCS1GPRs.end(),
1614 if (LRPos != UnspilledCS1GPRs.end())
1615 UnspilledCS1GPRs.erase(LRPos);
1617 ForceLRSpill = false;
1618 ExtraCSSpill = true;
1622 MRI.setPhysRegUsed(FramePtr);
1623 auto FPPos = std::find(UnspilledCS1GPRs.begin(), UnspilledCS1GPRs.end(),
1625 if (FPPos != UnspilledCS1GPRs.end())
1626 UnspilledCS1GPRs.erase(FPPos);
1630 // If stack and double are 8-byte aligned and we are spilling an odd number
1631 // of GPRs, spill one extra callee save GPR so we won't have to pad between
1632 // the integer and double callee save areas.
1633 unsigned TargetAlign = getStackAlignment();
1634 if (TargetAlign >= 8 && (NumGPRSpills & 1)) {
1635 if (CS1Spilled && !UnspilledCS1GPRs.empty()) {
1636 for (unsigned i = 0, e = UnspilledCS1GPRs.size(); i != e; ++i) {
1637 unsigned Reg = UnspilledCS1GPRs[i];
1638 // Don't spill high register if the function is thumb1
1639 if (!AFI->isThumb1OnlyFunction() ||
1640 isARMLowRegister(Reg) || Reg == ARM::LR) {
1641 MRI.setPhysRegUsed(Reg);
1642 if (!MRI.isReserved(Reg))
1643 ExtraCSSpill = true;
1647 } else if (!UnspilledCS2GPRs.empty() && !AFI->isThumb1OnlyFunction()) {
1648 unsigned Reg = UnspilledCS2GPRs.front();
1649 MRI.setPhysRegUsed(Reg);
1650 if (!MRI.isReserved(Reg))
1651 ExtraCSSpill = true;
1655 // Estimate if we might need to scavenge a register at some point in order
1656 // to materialize a stack offset. If so, either spill one additional
1657 // callee-saved register or reserve a special spill slot to facilitate
1658 // register scavenging. Thumb1 needs a spill slot for stack pointer
1659 // adjustments also, even when the frame itself is small.
1660 if (BigStack && !ExtraCSSpill) {
1661 // If any non-reserved CS register isn't spilled, just spill one or two
1662 // extra. That should take care of it!
1663 unsigned NumExtras = TargetAlign / 4;
1664 SmallVector<unsigned, 2> Extras;
1665 while (NumExtras && !UnspilledCS1GPRs.empty()) {
1666 unsigned Reg = UnspilledCS1GPRs.back();
1667 UnspilledCS1GPRs.pop_back();
1668 if (!MRI.isReserved(Reg) &&
1669 (!AFI->isThumb1OnlyFunction() || isARMLowRegister(Reg) ||
1671 Extras.push_back(Reg);
1675 // For non-Thumb1 functions, also check for hi-reg CS registers
1676 if (!AFI->isThumb1OnlyFunction()) {
1677 while (NumExtras && !UnspilledCS2GPRs.empty()) {
1678 unsigned Reg = UnspilledCS2GPRs.back();
1679 UnspilledCS2GPRs.pop_back();
1680 if (!MRI.isReserved(Reg)) {
1681 Extras.push_back(Reg);
1686 if (Extras.size() && NumExtras == 0) {
1687 for (unsigned i = 0, e = Extras.size(); i != e; ++i) {
1688 MRI.setPhysRegUsed(Extras[i]);
1690 } else if (!AFI->isThumb1OnlyFunction()) {
1691 // note: Thumb1 functions spill to R12, not the stack. Reserve a slot
1692 // closest to SP or frame pointer.
1693 const TargetRegisterClass *RC = &ARM::GPRRegClass;
1694 RS->addScavengingFrameIndex(MFI->CreateStackObject(RC->getSize(),
1702 MRI.setPhysRegUsed(ARM::LR);
1703 AFI->setLRIsSpilledForFarJump(true);
1708 void ARMFrameLowering::
1709 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
1710 MachineBasicBlock::iterator I) const {
1711 const ARMBaseInstrInfo &TII =
1712 *static_cast<const ARMBaseInstrInfo *>(MF.getSubtarget().getInstrInfo());
1713 if (!hasReservedCallFrame(MF)) {
1714 // If we have alloca, convert as follows:
1715 // ADJCALLSTACKDOWN -> sub, sp, sp, amount
1716 // ADJCALLSTACKUP -> add, sp, sp, amount
1717 MachineInstr *Old = I;
1718 DebugLoc dl = Old->getDebugLoc();
1719 unsigned Amount = Old->getOperand(0).getImm();
1721 // We need to keep the stack aligned properly. To do this, we round the
1722 // amount of space needed for the outgoing arguments up to the next
1723 // alignment boundary.
1724 unsigned Align = getStackAlignment();
1725 Amount = (Amount+Align-1)/Align*Align;
1727 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1728 assert(!AFI->isThumb1OnlyFunction() &&
1729 "This eliminateCallFramePseudoInstr does not support Thumb1!");
1730 bool isARM = !AFI->isThumbFunction();
1732 // Replace the pseudo instruction with a new instruction...
1733 unsigned Opc = Old->getOpcode();
1734 int PIdx = Old->findFirstPredOperandIdx();
1735 ARMCC::CondCodes Pred = (PIdx == -1)
1736 ? ARMCC::AL : (ARMCC::CondCodes)Old->getOperand(PIdx).getImm();
1737 if (Opc == ARM::ADJCALLSTACKDOWN || Opc == ARM::tADJCALLSTACKDOWN) {
1738 // Note: PredReg is operand 2 for ADJCALLSTACKDOWN.
1739 unsigned PredReg = Old->getOperand(2).getReg();
1740 emitSPUpdate(isARM, MBB, I, dl, TII, -Amount, MachineInstr::NoFlags,
1743 // Note: PredReg is operand 3 for ADJCALLSTACKUP.
1744 unsigned PredReg = Old->getOperand(3).getReg();
1745 assert(Opc == ARM::ADJCALLSTACKUP || Opc == ARM::tADJCALLSTACKUP);
1746 emitSPUpdate(isARM, MBB, I, dl, TII, Amount, MachineInstr::NoFlags,
1754 /// Get the minimum constant for ARM that is greater than or equal to the
1755 /// argument. In ARM, constants can have any value that can be produced by
1756 /// rotating an 8-bit value to the right by an even number of bits within a
1758 static uint32_t alignToARMConstant(uint32_t Value) {
1759 unsigned Shifted = 0;
1764 while (!(Value & 0xC0000000)) {
1769 bool Carry = (Value & 0x00FFFFFF);
1770 Value = ((Value & 0xFF000000) >> 24) + Carry;
1772 if (Value & 0x0000100)
1773 Value = Value & 0x000001FC;
1776 Value = Value >> (Shifted - 24);
1778 Value = Value << (24 - Shifted);
1783 // The stack limit in the TCB is set to this many bytes above the actual
1785 static const uint64_t kSplitStackAvailable = 256;
1787 // Adjust the function prologue to enable split stacks. This currently only
1788 // supports android and linux.
1790 // The ABI of the segmented stack prologue is a little arbitrarily chosen, but
1791 // must be well defined in order to allow for consistent implementations of the
1792 // __morestack helper function. The ABI is also not a normal ABI in that it
1793 // doesn't follow the normal calling conventions because this allows the
1794 // prologue of each function to be optimized further.
1796 // Currently, the ABI looks like (when calling __morestack)
1798 // * r4 holds the minimum stack size requested for this function call
1799 // * r5 holds the stack size of the arguments to the function
1800 // * the beginning of the function is 3 instructions after the call to
1803 // Implementations of __morestack should use r4 to allocate a new stack, r5 to
1804 // place the arguments on to the new stack, and the 3-instruction knowledge to
1805 // jump directly to the body of the function when working on the new stack.
1807 // An old (and possibly no longer compatible) implementation of __morestack for
1808 // ARM can be found at [1].
1810 // [1] - https://github.com/mozilla/rust/blob/86efd9/src/rt/arch/arm/morestack.S
1811 void ARMFrameLowering::adjustForSegmentedStacks(MachineFunction &MF) const {
1814 const ARMSubtarget *ST = &MF.getTarget().getSubtarget<ARMSubtarget>();
1815 bool Thumb = ST->isThumb();
1817 // Sadly, this currently doesn't support varargs, platforms other than
1818 // android/linux. Note that thumb1/thumb2 are support for android/linux.
1819 if (MF.getFunction()->isVarArg())
1820 report_fatal_error("Segmented stacks do not support vararg functions.");
1821 if (!ST->isTargetAndroid() && !ST->isTargetLinux())
1822 report_fatal_error("Segmented stacks not supported on this platform.");
1824 MachineBasicBlock &prologueMBB = MF.front();
1825 MachineFrameInfo *MFI = MF.getFrameInfo();
1826 MachineModuleInfo &MMI = MF.getMMI();
1827 MCContext &Context = MMI.getContext();
1828 const MCRegisterInfo *MRI = Context.getRegisterInfo();
1829 const ARMBaseInstrInfo &TII =
1830 *static_cast<const ARMBaseInstrInfo *>(MF.getSubtarget().getInstrInfo());
1831 ARMFunctionInfo *ARMFI = MF.getInfo<ARMFunctionInfo>();
1834 uint64_t StackSize = MFI->getStackSize();
1836 // Do not generate a prologue for functions with a stack of size zero
1840 // Use R4 and R5 as scratch registers.
1841 // We save R4 and R5 before use and restore them before leaving the function.
1842 unsigned ScratchReg0 = ARM::R4;
1843 unsigned ScratchReg1 = ARM::R5;
1844 uint64_t AlignedStackSize;
1846 MachineBasicBlock *PrevStackMBB = MF.CreateMachineBasicBlock();
1847 MachineBasicBlock *PostStackMBB = MF.CreateMachineBasicBlock();
1848 MachineBasicBlock *AllocMBB = MF.CreateMachineBasicBlock();
1849 MachineBasicBlock *GetMBB = MF.CreateMachineBasicBlock();
1850 MachineBasicBlock *McrMBB = MF.CreateMachineBasicBlock();
1852 for (MachineBasicBlock::livein_iterator i = prologueMBB.livein_begin(),
1853 e = prologueMBB.livein_end();
1855 AllocMBB->addLiveIn(*i);
1856 GetMBB->addLiveIn(*i);
1857 McrMBB->addLiveIn(*i);
1858 PrevStackMBB->addLiveIn(*i);
1859 PostStackMBB->addLiveIn(*i);
1862 MF.push_front(PostStackMBB);
1863 MF.push_front(AllocMBB);
1864 MF.push_front(GetMBB);
1865 MF.push_front(McrMBB);
1866 MF.push_front(PrevStackMBB);
1868 // The required stack size that is aligned to ARM constant criterion.
1869 AlignedStackSize = alignToARMConstant(StackSize);
1871 // When the frame size is less than 256 we just compare the stack
1872 // boundary directly to the value of the stack pointer, per gcc.
1873 bool CompareStackPointer = AlignedStackSize < kSplitStackAvailable;
1875 // We will use two of the callee save registers as scratch registers so we
1876 // need to save those registers onto the stack.
1877 // We will use SR0 to hold stack limit and SR1 to hold the stack size
1878 // requested and arguments for __morestack().
1879 // SR0: Scratch Register #0
1880 // SR1: Scratch Register #1
1883 AddDefaultPred(BuildMI(PrevStackMBB, DL, TII.get(ARM::tPUSH)))
1884 .addReg(ScratchReg0).addReg(ScratchReg1);
1886 AddDefaultPred(BuildMI(PrevStackMBB, DL, TII.get(ARM::STMDB_UPD))
1887 .addReg(ARM::SP, RegState::Define).addReg(ARM::SP))
1888 .addReg(ScratchReg0).addReg(ScratchReg1);
1891 // Emit the relevant DWARF information about the change in stack pointer as
1892 // well as where to find both r4 and r5 (the callee-save registers)
1894 MMI.addFrameInst(MCCFIInstruction::createDefCfaOffset(nullptr, -8));
1895 BuildMI(PrevStackMBB, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
1896 .addCFIIndex(CFIIndex);
1897 CFIIndex = MMI.addFrameInst(MCCFIInstruction::createOffset(
1898 nullptr, MRI->getDwarfRegNum(ScratchReg1, true), -4));
1899 BuildMI(PrevStackMBB, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
1900 .addCFIIndex(CFIIndex);
1901 CFIIndex = MMI.addFrameInst(MCCFIInstruction::createOffset(
1902 nullptr, MRI->getDwarfRegNum(ScratchReg0, true), -8));
1903 BuildMI(PrevStackMBB, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
1904 .addCFIIndex(CFIIndex);
1908 AddDefaultPred(BuildMI(McrMBB, DL, TII.get(ARM::tMOVr), ScratchReg1)
1910 } else if (CompareStackPointer) {
1911 AddDefaultPred(BuildMI(McrMBB, DL, TII.get(ARM::MOVr), ScratchReg1)
1912 .addReg(ARM::SP)).addReg(0);
1915 // sub SR1, sp, #StackSize
1916 if (!CompareStackPointer && Thumb) {
1918 AddDefaultCC(BuildMI(McrMBB, DL, TII.get(ARM::tSUBi8), ScratchReg1))
1919 .addReg(ScratchReg1).addImm(AlignedStackSize));
1920 } else if (!CompareStackPointer) {
1921 AddDefaultPred(BuildMI(McrMBB, DL, TII.get(ARM::SUBri), ScratchReg1)
1922 .addReg(ARM::SP).addImm(AlignedStackSize)).addReg(0);
1925 if (Thumb && ST->isThumb1Only()) {
1926 unsigned PCLabelId = ARMFI->createPICLabelUId();
1927 ARMConstantPoolValue *NewCPV = ARMConstantPoolSymbol::Create(
1928 MF.getFunction()->getContext(), "__STACK_LIMIT", PCLabelId, 0);
1929 MachineConstantPool *MCP = MF.getConstantPool();
1930 unsigned CPI = MCP->getConstantPoolIndex(NewCPV, MF.getAlignment());
1932 // ldr SR0, [pc, offset(STACK_LIMIT)]
1933 AddDefaultPred(BuildMI(GetMBB, DL, TII.get(ARM::tLDRpci), ScratchReg0)
1934 .addConstantPoolIndex(CPI));
1937 AddDefaultPred(BuildMI(GetMBB, DL, TII.get(ARM::tLDRi), ScratchReg0)
1938 .addReg(ScratchReg0).addImm(0));
1940 // Get TLS base address from the coprocessor
1941 // mrc p15, #0, SR0, c13, c0, #3
1942 AddDefaultPred(BuildMI(McrMBB, DL, TII.get(ARM::MRC), ScratchReg0)
1949 // Use the last tls slot on android and a private field of the TCP on linux.
1950 assert(ST->isTargetAndroid() || ST->isTargetLinux());
1951 unsigned TlsOffset = ST->isTargetAndroid() ? 63 : 1;
1953 // Get the stack limit from the right offset
1954 // ldr SR0, [sr0, #4 * TlsOffset]
1955 AddDefaultPred(BuildMI(GetMBB, DL, TII.get(ARM::LDRi12), ScratchReg0)
1956 .addReg(ScratchReg0).addImm(4 * TlsOffset));
1959 // Compare stack limit with stack size requested.
1961 Opcode = Thumb ? ARM::tCMPr : ARM::CMPrr;
1962 AddDefaultPred(BuildMI(GetMBB, DL, TII.get(Opcode))
1963 .addReg(ScratchReg0)
1964 .addReg(ScratchReg1));
1966 // This jump is taken if StackLimit < SP - stack required.
1967 Opcode = Thumb ? ARM::tBcc : ARM::Bcc;
1968 BuildMI(GetMBB, DL, TII.get(Opcode)).addMBB(PostStackMBB)
1973 // Calling __morestack(StackSize, Size of stack arguments).
1974 // __morestack knows that the stack size requested is in SR0(r4)
1975 // and amount size of stack arguments is in SR1(r5).
1977 // Pass first argument for the __morestack by Scratch Register #0.
1978 // The amount size of stack required
1980 AddDefaultPred(AddDefaultCC(BuildMI(AllocMBB, DL, TII.get(ARM::tMOVi8),
1981 ScratchReg0)).addImm(AlignedStackSize));
1983 AddDefaultPred(BuildMI(AllocMBB, DL, TII.get(ARM::MOVi), ScratchReg0)
1984 .addImm(AlignedStackSize)).addReg(0);
1986 // Pass second argument for the __morestack by Scratch Register #1.
1987 // The amount size of stack consumed to save function arguments.
1990 AddDefaultCC(BuildMI(AllocMBB, DL, TII.get(ARM::tMOVi8), ScratchReg1))
1991 .addImm(alignToARMConstant(ARMFI->getArgumentStackSize())));
1993 AddDefaultPred(BuildMI(AllocMBB, DL, TII.get(ARM::MOVi), ScratchReg1)
1994 .addImm(alignToARMConstant(ARMFI->getArgumentStackSize())))
1998 // push {lr} - Save return address of this function.
2000 AddDefaultPred(BuildMI(AllocMBB, DL, TII.get(ARM::tPUSH)))
2003 AddDefaultPred(BuildMI(AllocMBB, DL, TII.get(ARM::STMDB_UPD))
2004 .addReg(ARM::SP, RegState::Define)
2009 // Emit the DWARF info about the change in stack as well as where to find the
2010 // previous link register
2012 MMI.addFrameInst(MCCFIInstruction::createDefCfaOffset(nullptr, -12));
2013 BuildMI(AllocMBB, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
2014 .addCFIIndex(CFIIndex);
2015 CFIIndex = MMI.addFrameInst(MCCFIInstruction::createOffset(
2016 nullptr, MRI->getDwarfRegNum(ARM::LR, true), -12));
2017 BuildMI(AllocMBB, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
2018 .addCFIIndex(CFIIndex);
2020 // Call __morestack().
2022 AddDefaultPred(BuildMI(AllocMBB, DL, TII.get(ARM::tBL)))
2023 .addExternalSymbol("__morestack");
2025 BuildMI(AllocMBB, DL, TII.get(ARM::BL))
2026 .addExternalSymbol("__morestack");
2029 // pop {lr} - Restore return address of this original function.
2031 if (ST->isThumb1Only()) {
2032 AddDefaultPred(BuildMI(AllocMBB, DL, TII.get(ARM::tPOP)))
2033 .addReg(ScratchReg0);
2034 AddDefaultPred(BuildMI(AllocMBB, DL, TII.get(ARM::tMOVr), ARM::LR)
2035 .addReg(ScratchReg0));
2037 AddDefaultPred(BuildMI(AllocMBB, DL, TII.get(ARM::t2LDR_POST))
2038 .addReg(ARM::LR, RegState::Define)
2039 .addReg(ARM::SP, RegState::Define)
2044 AddDefaultPred(BuildMI(AllocMBB, DL, TII.get(ARM::LDMIA_UPD))
2045 .addReg(ARM::SP, RegState::Define)
2050 // Restore SR0 and SR1 in case of __morestack() was called.
2051 // __morestack() will skip PostStackMBB block so we need to restore
2052 // scratch registers from here.
2055 AddDefaultPred(BuildMI(AllocMBB, DL, TII.get(ARM::tPOP)))
2056 .addReg(ScratchReg0)
2057 .addReg(ScratchReg1);
2059 AddDefaultPred(BuildMI(AllocMBB, DL, TII.get(ARM::LDMIA_UPD))
2060 .addReg(ARM::SP, RegState::Define)
2062 .addReg(ScratchReg0)
2063 .addReg(ScratchReg1);
2066 // Update the CFA offset now that we've popped
2067 CFIIndex = MMI.addFrameInst(MCCFIInstruction::createDefCfaOffset(nullptr, 0));
2068 BuildMI(AllocMBB, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
2069 .addCFIIndex(CFIIndex);
2071 // bx lr - Return from this function.
2072 Opcode = Thumb ? ARM::tBX_RET : ARM::BX_RET;
2073 AddDefaultPred(BuildMI(AllocMBB, DL, TII.get(Opcode)));
2075 // Restore SR0 and SR1 in case of __morestack() was not called.
2078 AddDefaultPred(BuildMI(PostStackMBB, DL, TII.get(ARM::tPOP)))
2079 .addReg(ScratchReg0)
2080 .addReg(ScratchReg1);
2082 AddDefaultPred(BuildMI(PostStackMBB, DL, TII.get(ARM::LDMIA_UPD))
2083 .addReg(ARM::SP, RegState::Define)
2085 .addReg(ScratchReg0)
2086 .addReg(ScratchReg1);
2089 // Update the CFA offset now that we've popped
2090 CFIIndex = MMI.addFrameInst(MCCFIInstruction::createDefCfaOffset(nullptr, 0));
2091 BuildMI(PostStackMBB, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
2092 .addCFIIndex(CFIIndex);
2094 // Tell debuggers that r4 and r5 are now the same as they were in the
2095 // previous function, that they're the "Same Value".
2096 CFIIndex = MMI.addFrameInst(MCCFIInstruction::createSameValue(
2097 nullptr, MRI->getDwarfRegNum(ScratchReg0, true)));
2098 BuildMI(PostStackMBB, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
2099 .addCFIIndex(CFIIndex);
2100 CFIIndex = MMI.addFrameInst(MCCFIInstruction::createSameValue(
2101 nullptr, MRI->getDwarfRegNum(ScratchReg1, true)));
2102 BuildMI(PostStackMBB, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
2103 .addCFIIndex(CFIIndex);
2105 // Organizing MBB lists
2106 PostStackMBB->addSuccessor(&prologueMBB);
2108 AllocMBB->addSuccessor(PostStackMBB);
2110 GetMBB->addSuccessor(PostStackMBB);
2111 GetMBB->addSuccessor(AllocMBB);
2113 McrMBB->addSuccessor(GetMBB);
2115 PrevStackMBB->addSuccessor(McrMBB);