1 //===-- ARMFrameLowering.cpp - ARM Frame Information ----------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the ARM implementation of TargetFrameLowering class.
12 //===----------------------------------------------------------------------===//
14 #include "ARMFrameLowering.h"
15 #include "ARMBaseInstrInfo.h"
16 #include "ARMBaseRegisterInfo.h"
17 #include "ARMMachineFunctionInfo.h"
18 #include "llvm/CallingConv.h"
19 #include "llvm/Function.h"
20 #include "MCTargetDesc/ARMAddressingModes.h"
21 #include "llvm/Function.h"
22 #include "llvm/CodeGen/MachineFrameInfo.h"
23 #include "llvm/CodeGen/MachineFunction.h"
24 #include "llvm/CodeGen/MachineInstrBuilder.h"
25 #include "llvm/CodeGen/MachineRegisterInfo.h"
26 #include "llvm/CodeGen/RegisterScavenging.h"
27 #include "llvm/Target/TargetOptions.h"
28 #include "llvm/Support/CommandLine.h"
33 SpillAlignedNEONRegs("align-neon-spills", cl::Hidden, cl::init(true),
34 cl::desc("Align ARM NEON spills in prolog and epilog"));
36 static MachineBasicBlock::iterator
37 skipAlignedDPRCS2Spills(MachineBasicBlock::iterator MI,
38 unsigned NumAlignedDPRCS2Regs);
40 /// hasFP - Return true if the specified function should have a dedicated frame
41 /// pointer register. This is true if the function has variable sized allocas
42 /// or if frame pointer elimination is disabled.
43 bool ARMFrameLowering::hasFP(const MachineFunction &MF) const {
44 const TargetRegisterInfo *RegInfo = MF.getTarget().getRegisterInfo();
46 // iOS requires FP not to be clobbered for backtracing purpose.
47 if (STI.isTargetIOS())
50 const MachineFrameInfo *MFI = MF.getFrameInfo();
51 // Always eliminate non-leaf frame pointers.
52 return ((MF.getTarget().Options.DisableFramePointerElim(MF) &&
54 RegInfo->needsStackRealignment(MF) ||
55 MFI->hasVarSizedObjects() ||
56 MFI->isFrameAddressTaken());
59 /// hasReservedCallFrame - Under normal circumstances, when a frame pointer is
60 /// not required, we reserve argument space for call sites in the function
61 /// immediately on entry to the current function. This eliminates the need for
62 /// add/sub sp brackets around call sites. Returns true if the call frame is
63 /// included as part of the stack frame.
64 bool ARMFrameLowering::hasReservedCallFrame(const MachineFunction &MF) const {
65 const MachineFrameInfo *FFI = MF.getFrameInfo();
66 unsigned CFSize = FFI->getMaxCallFrameSize();
67 // It's not always a good idea to include the call frame as part of the
68 // stack frame. ARM (especially Thumb) has small immediate offset to
69 // address the stack frame. So a large call frame can cause poor codegen
70 // and may even makes it impossible to scavenge a register.
71 if (CFSize >= ((1 << 12) - 1) / 2) // Half of imm12
74 return !MF.getFrameInfo()->hasVarSizedObjects();
77 /// canSimplifyCallFramePseudos - If there is a reserved call frame, the
78 /// call frame pseudos can be simplified. Unlike most targets, having a FP
79 /// is not sufficient here since we still may reference some objects via SP
80 /// even when FP is available in Thumb2 mode.
82 ARMFrameLowering::canSimplifyCallFramePseudos(const MachineFunction &MF) const {
83 return hasReservedCallFrame(MF) || MF.getFrameInfo()->hasVarSizedObjects();
86 static bool isCalleeSavedRegister(unsigned Reg, const uint16_t *CSRegs) {
87 for (unsigned i = 0; CSRegs[i]; ++i)
93 static bool isCSRestore(MachineInstr *MI,
94 const ARMBaseInstrInfo &TII,
95 const uint16_t *CSRegs) {
96 // Integer spill area is handled with "pop".
97 if (MI->getOpcode() == ARM::LDMIA_RET ||
98 MI->getOpcode() == ARM::t2LDMIA_RET ||
99 MI->getOpcode() == ARM::LDMIA_UPD ||
100 MI->getOpcode() == ARM::t2LDMIA_UPD ||
101 MI->getOpcode() == ARM::VLDMDIA_UPD) {
102 // The first two operands are predicates. The last two are
103 // imp-def and imp-use of SP. Check everything in between.
104 for (int i = 5, e = MI->getNumOperands(); i != e; ++i)
105 if (!isCalleeSavedRegister(MI->getOperand(i).getReg(), CSRegs))
109 if ((MI->getOpcode() == ARM::LDR_POST_IMM ||
110 MI->getOpcode() == ARM::LDR_POST_REG ||
111 MI->getOpcode() == ARM::t2LDR_POST) &&
112 isCalleeSavedRegister(MI->getOperand(0).getReg(), CSRegs) &&
113 MI->getOperand(1).getReg() == ARM::SP)
120 emitSPUpdate(bool isARM,
121 MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,
122 DebugLoc dl, const ARMBaseInstrInfo &TII,
123 int NumBytes, unsigned MIFlags = MachineInstr::NoFlags) {
125 emitARMRegPlusImmediate(MBB, MBBI, dl, ARM::SP, ARM::SP, NumBytes,
126 ARMCC::AL, 0, TII, MIFlags);
128 emitT2RegPlusImmediate(MBB, MBBI, dl, ARM::SP, ARM::SP, NumBytes,
129 ARMCC::AL, 0, TII, MIFlags);
132 void ARMFrameLowering::emitPrologue(MachineFunction &MF) const {
133 MachineBasicBlock &MBB = MF.front();
134 MachineBasicBlock::iterator MBBI = MBB.begin();
135 MachineFrameInfo *MFI = MF.getFrameInfo();
136 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
137 const ARMBaseRegisterInfo *RegInfo =
138 static_cast<const ARMBaseRegisterInfo*>(MF.getTarget().getRegisterInfo());
139 const ARMBaseInstrInfo &TII =
140 *static_cast<const ARMBaseInstrInfo*>(MF.getTarget().getInstrInfo());
141 assert(!AFI->isThumb1OnlyFunction() &&
142 "This emitPrologue does not support Thumb1!");
143 bool isARM = !AFI->isThumbFunction();
144 unsigned VARegSaveSize = AFI->getVarArgsRegSaveSize();
145 unsigned NumBytes = MFI->getStackSize();
146 const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
147 DebugLoc dl = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
148 unsigned FramePtr = RegInfo->getFrameRegister(MF);
150 // Determine the sizes of each callee-save spill areas and record which frame
151 // belongs to which callee-save spill areas.
152 unsigned GPRCS1Size = 0, GPRCS2Size = 0, DPRCSSize = 0;
153 int FramePtrSpillFI = 0;
156 // All calls are tail calls in GHC calling conv, and functions have no
157 // prologue/epilogue.
158 if (MF.getFunction()->getCallingConv() == CallingConv::GHC)
161 // Allocate the vararg register save area. This is not counted in NumBytes.
163 emitSPUpdate(isARM, MBB, MBBI, dl, TII, -VARegSaveSize,
164 MachineInstr::FrameSetup);
166 if (!AFI->hasStackFrame()) {
168 emitSPUpdate(isARM, MBB, MBBI, dl, TII, -NumBytes,
169 MachineInstr::FrameSetup);
173 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
174 unsigned Reg = CSI[i].getReg();
175 int FI = CSI[i].getFrameIdx();
183 FramePtrSpillFI = FI;
184 AFI->addGPRCalleeSavedArea1Frame(FI);
192 FramePtrSpillFI = FI;
193 if (STI.isTargetIOS()) {
194 AFI->addGPRCalleeSavedArea2Frame(FI);
197 AFI->addGPRCalleeSavedArea1Frame(FI);
202 // This is a DPR. Exclude the aligned DPRCS2 spills.
205 if (Reg < ARM::D8 || Reg >= ARM::D8 + AFI->getNumAlignedDPRCS2Regs()) {
206 AFI->addDPRCalleeSavedAreaFrame(FI);
213 if (GPRCS1Size > 0) MBBI++;
215 // Set FP to point to the stack slot that contains the previous FP.
216 // For iOS, FP is R7, which has now been stored in spill area 1.
217 // Otherwise, if this is not iOS, all the callee-saved registers go
218 // into spill area 1, including the FP in R11. In either case, it is
219 // now safe to emit this assignment.
220 bool HasFP = hasFP(MF);
222 unsigned ADDriOpc = !AFI->isThumbFunction() ? ARM::ADDri : ARM::t2ADDri;
223 MachineInstrBuilder MIB =
224 BuildMI(MBB, MBBI, dl, TII.get(ADDriOpc), FramePtr)
225 .addFrameIndex(FramePtrSpillFI).addImm(0)
226 .setMIFlag(MachineInstr::FrameSetup);
227 AddDefaultCC(AddDefaultPred(MIB));
231 if (GPRCS2Size > 0) MBBI++;
233 // Determine starting offsets of spill areas.
234 unsigned DPRCSOffset = NumBytes - (GPRCS1Size + GPRCS2Size + DPRCSSize);
235 unsigned GPRCS2Offset = DPRCSOffset + DPRCSSize;
236 unsigned GPRCS1Offset = GPRCS2Offset + GPRCS2Size;
238 AFI->setFramePtrSpillOffset(MFI->getObjectOffset(FramePtrSpillFI) +
240 AFI->setGPRCalleeSavedArea1Offset(GPRCS1Offset);
241 AFI->setGPRCalleeSavedArea2Offset(GPRCS2Offset);
242 AFI->setDPRCalleeSavedAreaOffset(DPRCSOffset);
247 // Since vpush register list cannot have gaps, there may be multiple vpush
248 // instructions in the prologue.
249 while (MBBI->getOpcode() == ARM::VSTMDDB_UPD)
253 // Move past the aligned DPRCS2 area.
254 if (AFI->getNumAlignedDPRCS2Regs() > 0) {
255 MBBI = skipAlignedDPRCS2Spills(MBBI, AFI->getNumAlignedDPRCS2Regs());
256 // The code inserted by emitAlignedDPRCS2Spills realigns the stack, and
257 // leaves the stack pointer pointing to the DPRCS2 area.
259 // Adjust NumBytes to represent the stack slots below the DPRCS2 area.
260 NumBytes += MFI->getObjectOffset(D8SpillFI);
262 NumBytes = DPRCSOffset;
265 // Adjust SP after all the callee-save spills.
266 emitSPUpdate(isARM, MBB, MBBI, dl, TII, -NumBytes,
267 MachineInstr::FrameSetup);
269 // Restore from fp only in ARM mode: e.g. sub sp, r7, #24
270 // Note it's not safe to do this in Thumb2 mode because it would have
271 // taken two instructions:
274 // If an interrupt is taken between the two instructions, then sp is in
275 // an inconsistent state (pointing to the middle of callee-saved area).
276 // The interrupt handler can end up clobbering the registers.
277 AFI->setShouldRestoreSPFromFP(true);
280 if (STI.isTargetELF() && hasFP(MF))
281 MFI->setOffsetAdjustment(MFI->getOffsetAdjustment() -
282 AFI->getFramePtrSpillOffset());
284 AFI->setGPRCalleeSavedArea1Size(GPRCS1Size);
285 AFI->setGPRCalleeSavedArea2Size(GPRCS2Size);
286 AFI->setDPRCalleeSavedAreaSize(DPRCSSize);
288 // If we need dynamic stack realignment, do it here. Be paranoid and make
289 // sure if we also have VLAs, we have a base pointer for frame access.
290 // If aligned NEON registers were spilled, the stack has already been
292 if (!AFI->getNumAlignedDPRCS2Regs() && RegInfo->needsStackRealignment(MF)) {
293 unsigned MaxAlign = MFI->getMaxAlignment();
294 assert (!AFI->isThumb1OnlyFunction());
295 if (!AFI->isThumbFunction()) {
296 // Emit bic sp, sp, MaxAlign
297 AddDefaultCC(AddDefaultPred(BuildMI(MBB, MBBI, dl,
298 TII.get(ARM::BICri), ARM::SP)
299 .addReg(ARM::SP, RegState::Kill)
300 .addImm(MaxAlign-1)));
302 // We cannot use sp as source/dest register here, thus we're emitting the
303 // following sequence:
305 // bic r4, r4, MaxAlign
307 // FIXME: It will be better just to find spare register here.
308 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), ARM::R4)
309 .addReg(ARM::SP, RegState::Kill));
310 AddDefaultCC(AddDefaultPred(BuildMI(MBB, MBBI, dl,
311 TII.get(ARM::t2BICri), ARM::R4)
312 .addReg(ARM::R4, RegState::Kill)
313 .addImm(MaxAlign-1)));
314 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), ARM::SP)
315 .addReg(ARM::R4, RegState::Kill));
318 AFI->setShouldRestoreSPFromFP(true);
321 // If we need a base pointer, set it up here. It's whatever the value
322 // of the stack pointer is at this point. Any variable size objects
323 // will be allocated after this, so we can still use the base pointer
324 // to reference locals.
325 // FIXME: Clarify FrameSetup flags here.
326 if (RegInfo->hasBasePointer(MF)) {
328 BuildMI(MBB, MBBI, dl,
329 TII.get(ARM::MOVr), RegInfo->getBaseRegister())
331 .addImm((unsigned)ARMCC::AL).addReg(0).addReg(0);
333 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr),
334 RegInfo->getBaseRegister())
338 // If the frame has variable sized objects then the epilogue must restore
339 // the sp from fp. We can assume there's an FP here since hasFP already
340 // checks for hasVarSizedObjects.
341 if (MFI->hasVarSizedObjects())
342 AFI->setShouldRestoreSPFromFP(true);
345 void ARMFrameLowering::emitEpilogue(MachineFunction &MF,
346 MachineBasicBlock &MBB) const {
347 MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr();
348 assert(MBBI->isReturn() && "Can only insert epilog into returning blocks");
349 unsigned RetOpcode = MBBI->getOpcode();
350 DebugLoc dl = MBBI->getDebugLoc();
351 MachineFrameInfo *MFI = MF.getFrameInfo();
352 MachineRegisterInfo &MRI = MF.getRegInfo();
353 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
354 const TargetRegisterInfo *RegInfo = MF.getTarget().getRegisterInfo();
355 const ARMBaseInstrInfo &TII =
356 *static_cast<const ARMBaseInstrInfo*>(MF.getTarget().getInstrInfo());
357 assert(!AFI->isThumb1OnlyFunction() &&
358 "This emitEpilogue does not support Thumb1!");
359 bool isARM = !AFI->isThumbFunction();
361 unsigned VARegSaveSize = AFI->getVarArgsRegSaveSize();
362 int NumBytes = (int)MFI->getStackSize();
363 unsigned FramePtr = RegInfo->getFrameRegister(MF);
365 // All calls are tail calls in GHC calling conv, and functions have no
366 // prologue/epilogue.
367 if (MF.getFunction()->getCallingConv() == CallingConv::GHC)
370 if (!AFI->hasStackFrame()) {
372 emitSPUpdate(isARM, MBB, MBBI, dl, TII, NumBytes);
374 // Unwind MBBI to point to first LDR / VLDRD.
375 const uint16_t *CSRegs = RegInfo->getCalleeSavedRegs();
376 if (MBBI != MBB.begin()) {
379 while (MBBI != MBB.begin() && isCSRestore(MBBI, TII, CSRegs));
380 if (!isCSRestore(MBBI, TII, CSRegs))
384 // Move SP to start of FP callee save spill area.
385 NumBytes -= (AFI->getGPRCalleeSavedArea1Size() +
386 AFI->getGPRCalleeSavedArea2Size() +
387 AFI->getDPRCalleeSavedAreaSize());
389 // Reset SP based on frame pointer only if the stack frame extends beyond
390 // frame pointer stack slot or target is ELF and the function has FP.
391 if (AFI->shouldRestoreSPFromFP()) {
392 NumBytes = AFI->getFramePtrSpillOffset() - NumBytes;
395 emitARMRegPlusImmediate(MBB, MBBI, dl, ARM::SP, FramePtr, -NumBytes,
398 // It's not possible to restore SP from FP in a single instruction.
399 // For iOS, this looks like:
402 // This is bad, if an interrupt is taken after the mov, sp is in an
403 // inconsistent state.
404 // Use the first callee-saved register as a scratch register.
405 assert(MRI.isPhysRegUsed(ARM::R4) &&
406 "No scratch register to restore SP from FP!");
407 emitT2RegPlusImmediate(MBB, MBBI, dl, ARM::R4, FramePtr, -NumBytes,
409 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr),
416 BuildMI(MBB, MBBI, dl, TII.get(ARM::MOVr), ARM::SP)
417 .addReg(FramePtr).addImm((unsigned)ARMCC::AL).addReg(0).addReg(0);
419 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr),
424 emitSPUpdate(isARM, MBB, MBBI, dl, TII, NumBytes);
426 // Increment past our save areas.
427 if (AFI->getDPRCalleeSavedAreaSize()) {
429 // Since vpop register list cannot have gaps, there may be multiple vpop
430 // instructions in the epilogue.
431 while (MBBI->getOpcode() == ARM::VLDMDIA_UPD)
434 if (AFI->getGPRCalleeSavedArea2Size()) MBBI++;
435 if (AFI->getGPRCalleeSavedArea1Size()) MBBI++;
438 if (RetOpcode == ARM::TCRETURNdi || RetOpcode == ARM::TCRETURNri) {
439 // Tail call return: adjust the stack pointer and jump to callee.
440 MBBI = MBB.getLastNonDebugInstr();
441 MachineOperand &JumpTarget = MBBI->getOperand(0);
443 // Jump to label or value in register.
444 if (RetOpcode == ARM::TCRETURNdi) {
445 unsigned TCOpcode = STI.isThumb() ?
446 (STI.isTargetIOS() ? ARM::tTAILJMPd : ARM::tTAILJMPdND) :
448 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII.get(TCOpcode));
449 if (JumpTarget.isGlobal())
450 MIB.addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset(),
451 JumpTarget.getTargetFlags());
453 assert(JumpTarget.isSymbol());
454 MIB.addExternalSymbol(JumpTarget.getSymbolName(),
455 JumpTarget.getTargetFlags());
458 // Add the default predicate in Thumb mode.
459 if (STI.isThumb()) MIB.addImm(ARMCC::AL).addReg(0);
460 } else if (RetOpcode == ARM::TCRETURNri) {
461 BuildMI(MBB, MBBI, dl,
462 TII.get(STI.isThumb() ? ARM::tTAILJMPr : ARM::TAILJMPr)).
463 addReg(JumpTarget.getReg(), RegState::Kill);
466 MachineInstr *NewMI = prior(MBBI);
467 for (unsigned i = 1, e = MBBI->getNumOperands(); i != e; ++i)
468 NewMI->addOperand(MBBI->getOperand(i));
470 // Delete the pseudo instruction TCRETURN.
476 emitSPUpdate(isARM, MBB, MBBI, dl, TII, VARegSaveSize);
479 /// getFrameIndexReference - Provide a base+offset reference to an FI slot for
480 /// debug info. It's the same as what we use for resolving the code-gen
481 /// references for now. FIXME: This can go wrong when references are
482 /// SP-relative and simple call frames aren't used.
484 ARMFrameLowering::getFrameIndexReference(const MachineFunction &MF, int FI,
485 unsigned &FrameReg) const {
486 return ResolveFrameIndexReference(MF, FI, FrameReg, 0);
490 ARMFrameLowering::ResolveFrameIndexReference(const MachineFunction &MF,
491 int FI, unsigned &FrameReg,
493 const MachineFrameInfo *MFI = MF.getFrameInfo();
494 const ARMBaseRegisterInfo *RegInfo =
495 static_cast<const ARMBaseRegisterInfo*>(MF.getTarget().getRegisterInfo());
496 const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
497 int Offset = MFI->getObjectOffset(FI) + MFI->getStackSize();
498 int FPOffset = Offset - AFI->getFramePtrSpillOffset();
499 bool isFixed = MFI->isFixedObjectIndex(FI);
503 if (AFI->isGPRCalleeSavedArea1Frame(FI))
504 return Offset - AFI->getGPRCalleeSavedArea1Offset();
505 else if (AFI->isGPRCalleeSavedArea2Frame(FI))
506 return Offset - AFI->getGPRCalleeSavedArea2Offset();
507 else if (AFI->isDPRCalleeSavedAreaFrame(FI))
508 return Offset - AFI->getDPRCalleeSavedAreaOffset();
510 // SP can move around if there are allocas. We may also lose track of SP
511 // when emergency spilling inside a non-reserved call frame setup.
512 bool hasMovingSP = !hasReservedCallFrame(MF);
514 // When dynamically realigning the stack, use the frame pointer for
515 // parameters, and the stack/base pointer for locals.
516 if (RegInfo->needsStackRealignment(MF)) {
517 assert (hasFP(MF) && "dynamic stack realignment without a FP!");
519 FrameReg = RegInfo->getFrameRegister(MF);
521 } else if (hasMovingSP) {
522 assert(RegInfo->hasBasePointer(MF) &&
523 "VLAs and dynamic stack alignment, but missing base pointer!");
524 FrameReg = RegInfo->getBaseRegister();
529 // If there is a frame pointer, use it when we can.
530 if (hasFP(MF) && AFI->hasStackFrame()) {
531 // Use frame pointer to reference fixed objects. Use it for locals if
532 // there are VLAs (and thus the SP isn't reliable as a base).
533 if (isFixed || (hasMovingSP && !RegInfo->hasBasePointer(MF))) {
534 FrameReg = RegInfo->getFrameRegister(MF);
536 } else if (hasMovingSP) {
537 assert(RegInfo->hasBasePointer(MF) && "missing base pointer!");
538 if (AFI->isThumb2Function()) {
539 // Try to use the frame pointer if we can, else use the base pointer
540 // since it's available. This is handy for the emergency spill slot, in
542 if (FPOffset >= -255 && FPOffset < 0) {
543 FrameReg = RegInfo->getFrameRegister(MF);
547 } else if (AFI->isThumb2Function()) {
548 // Use add <rd>, sp, #<imm8>
549 // ldr <rd>, [sp, #<imm8>]
550 // if at all possible to save space.
551 if (Offset >= 0 && (Offset & 3) == 0 && Offset <= 1020)
553 // In Thumb2 mode, the negative offset is very limited. Try to avoid
554 // out of range references. ldr <rt>,[<rn>, #-<imm8>]
555 if (FPOffset >= -255 && FPOffset < 0) {
556 FrameReg = RegInfo->getFrameRegister(MF);
559 } else if (Offset > (FPOffset < 0 ? -FPOffset : FPOffset)) {
560 // Otherwise, use SP or FP, whichever is closer to the stack slot.
561 FrameReg = RegInfo->getFrameRegister(MF);
565 // Use the base pointer if we have one.
566 if (RegInfo->hasBasePointer(MF))
567 FrameReg = RegInfo->getBaseRegister();
571 int ARMFrameLowering::getFrameIndexOffset(const MachineFunction &MF,
574 return getFrameIndexReference(MF, FI, FrameReg);
577 void ARMFrameLowering::emitPushInst(MachineBasicBlock &MBB,
578 MachineBasicBlock::iterator MI,
579 const std::vector<CalleeSavedInfo> &CSI,
580 unsigned StmOpc, unsigned StrOpc,
582 bool(*Func)(unsigned, bool),
583 unsigned NumAlignedDPRCS2Regs,
584 unsigned MIFlags) const {
585 MachineFunction &MF = *MBB.getParent();
586 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
589 if (MI != MBB.end()) DL = MI->getDebugLoc();
591 SmallVector<std::pair<unsigned,bool>, 4> Regs;
592 unsigned i = CSI.size();
594 unsigned LastReg = 0;
595 for (; i != 0; --i) {
596 unsigned Reg = CSI[i-1].getReg();
597 if (!(Func)(Reg, STI.isTargetIOS())) continue;
599 // D-registers in the aligned area DPRCS2 are NOT spilled here.
600 if (Reg >= ARM::D8 && Reg < ARM::D8 + NumAlignedDPRCS2Regs)
603 // Add the callee-saved register as live-in unless it's LR and
604 // @llvm.returnaddress is called. If LR is returned for
605 // @llvm.returnaddress then it's already added to the function and
606 // entry block live-in sets.
608 if (Reg == ARM::LR) {
609 if (MF.getFrameInfo()->isReturnAddressTaken() &&
610 MF.getRegInfo().isLiveIn(Reg))
617 // If NoGap is true, push consecutive registers and then leave the rest
618 // for other instructions. e.g.
619 // vpush {d8, d10, d11} -> vpush {d8}, vpush {d10, d11}
620 if (NoGap && LastReg && LastReg != Reg-1)
623 Regs.push_back(std::make_pair(Reg, isKill));
628 if (Regs.size() > 1 || StrOpc== 0) {
629 MachineInstrBuilder MIB =
630 AddDefaultPred(BuildMI(MBB, MI, DL, TII.get(StmOpc), ARM::SP)
631 .addReg(ARM::SP).setMIFlags(MIFlags));
632 for (unsigned i = 0, e = Regs.size(); i < e; ++i)
633 MIB.addReg(Regs[i].first, getKillRegState(Regs[i].second));
634 } else if (Regs.size() == 1) {
635 MachineInstrBuilder MIB = BuildMI(MBB, MI, DL, TII.get(StrOpc),
637 .addReg(Regs[0].first, getKillRegState(Regs[0].second))
638 .addReg(ARM::SP).setMIFlags(MIFlags)
646 void ARMFrameLowering::emitPopInst(MachineBasicBlock &MBB,
647 MachineBasicBlock::iterator MI,
648 const std::vector<CalleeSavedInfo> &CSI,
649 unsigned LdmOpc, unsigned LdrOpc,
650 bool isVarArg, bool NoGap,
651 bool(*Func)(unsigned, bool),
652 unsigned NumAlignedDPRCS2Regs) const {
653 MachineFunction &MF = *MBB.getParent();
654 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
655 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
656 DebugLoc DL = MI->getDebugLoc();
657 unsigned RetOpcode = MI->getOpcode();
658 bool isTailCall = (RetOpcode == ARM::TCRETURNdi ||
659 RetOpcode == ARM::TCRETURNri);
661 SmallVector<unsigned, 4> Regs;
662 unsigned i = CSI.size();
664 unsigned LastReg = 0;
665 bool DeleteRet = false;
666 for (; i != 0; --i) {
667 unsigned Reg = CSI[i-1].getReg();
668 if (!(Func)(Reg, STI.isTargetIOS())) continue;
670 // The aligned reloads from area DPRCS2 are not inserted here.
671 if (Reg >= ARM::D8 && Reg < ARM::D8 + NumAlignedDPRCS2Regs)
674 if (Reg == ARM::LR && !isTailCall && !isVarArg && STI.hasV5TOps()) {
676 LdmOpc = AFI->isThumbFunction() ? ARM::t2LDMIA_RET : ARM::LDMIA_RET;
677 // Fold the return instruction into the LDM.
681 // If NoGap is true, pop consecutive registers and then leave the rest
682 // for other instructions. e.g.
683 // vpop {d8, d10, d11} -> vpop {d8}, vpop {d10, d11}
684 if (NoGap && LastReg && LastReg != Reg-1)
693 if (Regs.size() > 1 || LdrOpc == 0) {
694 MachineInstrBuilder MIB =
695 AddDefaultPred(BuildMI(MBB, MI, DL, TII.get(LdmOpc), ARM::SP)
697 for (unsigned i = 0, e = Regs.size(); i < e; ++i)
698 MIB.addReg(Regs[i], getDefRegState(true));
700 MIB->copyImplicitOps(&*MI);
701 MI->eraseFromParent();
704 } else if (Regs.size() == 1) {
705 // If we adjusted the reg to PC from LR above, switch it back here. We
706 // only do that for LDM.
707 if (Regs[0] == ARM::PC)
709 MachineInstrBuilder MIB =
710 BuildMI(MBB, MI, DL, TII.get(LdrOpc), Regs[0])
711 .addReg(ARM::SP, RegState::Define)
713 // ARM mode needs an extra reg0 here due to addrmode2. Will go away once
714 // that refactoring is complete (eventually).
715 if (LdrOpc == ARM::LDR_POST_REG || LdrOpc == ARM::LDR_POST_IMM) {
717 MIB.addImm(ARM_AM::getAM2Opc(ARM_AM::add, 4, ARM_AM::no_shift));
726 /// Emit aligned spill instructions for NumAlignedDPRCS2Regs D-registers
727 /// starting from d8. Also insert stack realignment code and leave the stack
728 /// pointer pointing to the d8 spill slot.
729 static void emitAlignedDPRCS2Spills(MachineBasicBlock &MBB,
730 MachineBasicBlock::iterator MI,
731 unsigned NumAlignedDPRCS2Regs,
732 const std::vector<CalleeSavedInfo> &CSI,
733 const TargetRegisterInfo *TRI) {
734 MachineFunction &MF = *MBB.getParent();
735 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
736 DebugLoc DL = MI->getDebugLoc();
737 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
738 MachineFrameInfo &MFI = *MF.getFrameInfo();
740 // Mark the D-register spill slots as properly aligned. Since MFI computes
741 // stack slot layout backwards, this can actually mean that the d-reg stack
742 // slot offsets can be wrong. The offset for d8 will always be correct.
743 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
744 unsigned DNum = CSI[i].getReg() - ARM::D8;
747 int FI = CSI[i].getFrameIdx();
748 // The even-numbered registers will be 16-byte aligned, the odd-numbered
749 // registers will be 8-byte aligned.
750 MFI.setObjectAlignment(FI, DNum % 2 ? 8 : 16);
752 // The stack slot for D8 needs to be maximally aligned because this is
753 // actually the point where we align the stack pointer. MachineFrameInfo
754 // computes all offsets relative to the incoming stack pointer which is a
755 // bit weird when realigning the stack. Any extra padding for this
756 // over-alignment is not realized because the code inserted below adjusts
757 // the stack pointer by numregs * 8 before aligning the stack pointer.
759 MFI.setObjectAlignment(FI, MFI.getMaxAlignment());
762 // Move the stack pointer to the d8 spill slot, and align it at the same
763 // time. Leave the stack slot address in the scratch register r4.
765 // sub r4, sp, #numregs * 8
766 // bic r4, r4, #align - 1
769 bool isThumb = AFI->isThumbFunction();
770 assert(!AFI->isThumb1OnlyFunction() && "Can't realign stack for thumb1");
771 AFI->setShouldRestoreSPFromFP(true);
773 // sub r4, sp, #numregs * 8
774 // The immediate is <= 64, so it doesn't need any special encoding.
775 unsigned Opc = isThumb ? ARM::t2SUBri : ARM::SUBri;
776 AddDefaultCC(AddDefaultPred(BuildMI(MBB, MI, DL, TII.get(Opc), ARM::R4)
778 .addImm(8 * NumAlignedDPRCS2Regs)));
780 // bic r4, r4, #align-1
781 Opc = isThumb ? ARM::t2BICri : ARM::BICri;
782 unsigned MaxAlign = MF.getFrameInfo()->getMaxAlignment();
783 AddDefaultCC(AddDefaultPred(BuildMI(MBB, MI, DL, TII.get(Opc), ARM::R4)
784 .addReg(ARM::R4, RegState::Kill)
785 .addImm(MaxAlign - 1)));
788 // The stack pointer must be adjusted before spilling anything, otherwise
789 // the stack slots could be clobbered by an interrupt handler.
790 // Leave r4 live, it is used below.
791 Opc = isThumb ? ARM::tMOVr : ARM::MOVr;
792 MachineInstrBuilder MIB = BuildMI(MBB, MI, DL, TII.get(Opc), ARM::SP)
794 MIB = AddDefaultPred(MIB);
798 // Now spill NumAlignedDPRCS2Regs registers starting from d8.
799 // r4 holds the stack slot address.
800 unsigned NextReg = ARM::D8;
802 // 16-byte aligned vst1.64 with 4 d-regs and address writeback.
803 // The writeback is only needed when emitting two vst1.64 instructions.
804 if (NumAlignedDPRCS2Regs >= 6) {
805 unsigned SupReg = TRI->getMatchingSuperReg(NextReg, ARM::dsub_0,
807 MBB.addLiveIn(SupReg);
808 AddDefaultPred(BuildMI(MBB, MI, DL, TII.get(ARM::VST1d64Qwb_fixed),
810 .addReg(ARM::R4, RegState::Kill).addImm(16)
812 .addReg(SupReg, RegState::ImplicitKill));
814 NumAlignedDPRCS2Regs -= 4;
817 // We won't modify r4 beyond this point. It currently points to the next
818 // register to be spilled.
819 unsigned R4BaseReg = NextReg;
821 // 16-byte aligned vst1.64 with 4 d-regs, no writeback.
822 if (NumAlignedDPRCS2Regs >= 4) {
823 unsigned SupReg = TRI->getMatchingSuperReg(NextReg, ARM::dsub_0,
825 MBB.addLiveIn(SupReg);
826 AddDefaultPred(BuildMI(MBB, MI, DL, TII.get(ARM::VST1d64Q))
827 .addReg(ARM::R4).addImm(16).addReg(NextReg)
828 .addReg(SupReg, RegState::ImplicitKill));
830 NumAlignedDPRCS2Regs -= 4;
833 // 16-byte aligned vst1.64 with 2 d-regs.
834 if (NumAlignedDPRCS2Regs >= 2) {
835 unsigned SupReg = TRI->getMatchingSuperReg(NextReg, ARM::dsub_0,
837 MBB.addLiveIn(SupReg);
838 AddDefaultPred(BuildMI(MBB, MI, DL, TII.get(ARM::VST1q64))
839 .addReg(ARM::R4).addImm(16).addReg(SupReg));
841 NumAlignedDPRCS2Regs -= 2;
844 // Finally, use a vanilla vstr.64 for the odd last register.
845 if (NumAlignedDPRCS2Regs) {
846 MBB.addLiveIn(NextReg);
847 // vstr.64 uses addrmode5 which has an offset scale of 4.
848 AddDefaultPred(BuildMI(MBB, MI, DL, TII.get(ARM::VSTRD))
850 .addReg(ARM::R4).addImm((NextReg-R4BaseReg)*2));
853 // The last spill instruction inserted should kill the scratch register r4.
854 llvm::prior(MI)->addRegisterKilled(ARM::R4, TRI);
857 /// Skip past the code inserted by emitAlignedDPRCS2Spills, and return an
858 /// iterator to the following instruction.
859 static MachineBasicBlock::iterator
860 skipAlignedDPRCS2Spills(MachineBasicBlock::iterator MI,
861 unsigned NumAlignedDPRCS2Regs) {
862 // sub r4, sp, #numregs * 8
863 // bic r4, r4, #align - 1
866 assert(MI->mayStore() && "Expecting spill instruction");
868 // These switches all fall through.
869 switch(NumAlignedDPRCS2Regs) {
872 assert(MI->mayStore() && "Expecting spill instruction");
875 assert(MI->mayStore() && "Expecting spill instruction");
879 assert(MI->killsRegister(ARM::R4) && "Missed kill flag");
885 /// Emit aligned reload instructions for NumAlignedDPRCS2Regs D-registers
886 /// starting from d8. These instructions are assumed to execute while the
887 /// stack is still aligned, unlike the code inserted by emitPopInst.
888 static void emitAlignedDPRCS2Restores(MachineBasicBlock &MBB,
889 MachineBasicBlock::iterator MI,
890 unsigned NumAlignedDPRCS2Regs,
891 const std::vector<CalleeSavedInfo> &CSI,
892 const TargetRegisterInfo *TRI) {
893 MachineFunction &MF = *MBB.getParent();
894 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
895 DebugLoc DL = MI->getDebugLoc();
896 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
898 // Find the frame index assigned to d8.
900 for (unsigned i = 0, e = CSI.size(); i != e; ++i)
901 if (CSI[i].getReg() == ARM::D8) {
902 D8SpillFI = CSI[i].getFrameIdx();
906 // Materialize the address of the d8 spill slot into the scratch register r4.
907 // This can be fairly complicated if the stack frame is large, so just use
908 // the normal frame index elimination mechanism to do it. This code runs as
909 // the initial part of the epilog where the stack and base pointers haven't
911 bool isThumb = AFI->isThumbFunction();
912 assert(!AFI->isThumb1OnlyFunction() && "Can't realign stack for thumb1");
914 unsigned Opc = isThumb ? ARM::t2ADDri : ARM::ADDri;
915 AddDefaultCC(AddDefaultPred(BuildMI(MBB, MI, DL, TII.get(Opc), ARM::R4)
916 .addFrameIndex(D8SpillFI).addImm(0)));
918 // Now restore NumAlignedDPRCS2Regs registers starting from d8.
919 unsigned NextReg = ARM::D8;
921 // 16-byte aligned vld1.64 with 4 d-regs and writeback.
922 if (NumAlignedDPRCS2Regs >= 6) {
923 unsigned SupReg = TRI->getMatchingSuperReg(NextReg, ARM::dsub_0,
925 AddDefaultPred(BuildMI(MBB, MI, DL, TII.get(ARM::VLD1d64Qwb_fixed), NextReg)
926 .addReg(ARM::R4, RegState::Define)
927 .addReg(ARM::R4, RegState::Kill).addImm(16)
928 .addReg(SupReg, RegState::ImplicitDefine));
930 NumAlignedDPRCS2Regs -= 4;
933 // We won't modify r4 beyond this point. It currently points to the next
934 // register to be spilled.
935 unsigned R4BaseReg = NextReg;
937 // 16-byte aligned vld1.64 with 4 d-regs, no writeback.
938 if (NumAlignedDPRCS2Regs >= 4) {
939 unsigned SupReg = TRI->getMatchingSuperReg(NextReg, ARM::dsub_0,
941 AddDefaultPred(BuildMI(MBB, MI, DL, TII.get(ARM::VLD1d64Q), NextReg)
942 .addReg(ARM::R4).addImm(16)
943 .addReg(SupReg, RegState::ImplicitDefine));
945 NumAlignedDPRCS2Regs -= 4;
948 // 16-byte aligned vld1.64 with 2 d-regs.
949 if (NumAlignedDPRCS2Regs >= 2) {
950 unsigned SupReg = TRI->getMatchingSuperReg(NextReg, ARM::dsub_0,
952 AddDefaultPred(BuildMI(MBB, MI, DL, TII.get(ARM::VLD1q64), SupReg)
953 .addReg(ARM::R4).addImm(16));
955 NumAlignedDPRCS2Regs -= 2;
958 // Finally, use a vanilla vldr.64 for the remaining odd register.
959 if (NumAlignedDPRCS2Regs)
960 AddDefaultPred(BuildMI(MBB, MI, DL, TII.get(ARM::VLDRD), NextReg)
961 .addReg(ARM::R4).addImm(2*(NextReg-R4BaseReg)));
963 // Last store kills r4.
964 llvm::prior(MI)->addRegisterKilled(ARM::R4, TRI);
967 bool ARMFrameLowering::spillCalleeSavedRegisters(MachineBasicBlock &MBB,
968 MachineBasicBlock::iterator MI,
969 const std::vector<CalleeSavedInfo> &CSI,
970 const TargetRegisterInfo *TRI) const {
974 MachineFunction &MF = *MBB.getParent();
975 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
977 unsigned PushOpc = AFI->isThumbFunction() ? ARM::t2STMDB_UPD : ARM::STMDB_UPD;
978 unsigned PushOneOpc = AFI->isThumbFunction() ?
979 ARM::t2STR_PRE : ARM::STR_PRE_IMM;
980 unsigned FltOpc = ARM::VSTMDDB_UPD;
981 unsigned NumAlignedDPRCS2Regs = AFI->getNumAlignedDPRCS2Regs();
982 emitPushInst(MBB, MI, CSI, PushOpc, PushOneOpc, false, &isARMArea1Register, 0,
983 MachineInstr::FrameSetup);
984 emitPushInst(MBB, MI, CSI, PushOpc, PushOneOpc, false, &isARMArea2Register, 0,
985 MachineInstr::FrameSetup);
986 emitPushInst(MBB, MI, CSI, FltOpc, 0, true, &isARMArea3Register,
987 NumAlignedDPRCS2Regs, MachineInstr::FrameSetup);
989 // The code above does not insert spill code for the aligned DPRCS2 registers.
990 // The stack realignment code will be inserted between the push instructions
992 if (NumAlignedDPRCS2Regs)
993 emitAlignedDPRCS2Spills(MBB, MI, NumAlignedDPRCS2Regs, CSI, TRI);
998 bool ARMFrameLowering::restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
999 MachineBasicBlock::iterator MI,
1000 const std::vector<CalleeSavedInfo> &CSI,
1001 const TargetRegisterInfo *TRI) const {
1005 MachineFunction &MF = *MBB.getParent();
1006 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1007 bool isVarArg = AFI->getVarArgsRegSaveSize() > 0;
1008 unsigned NumAlignedDPRCS2Regs = AFI->getNumAlignedDPRCS2Regs();
1010 // The emitPopInst calls below do not insert reloads for the aligned DPRCS2
1011 // registers. Do that here instead.
1012 if (NumAlignedDPRCS2Regs)
1013 emitAlignedDPRCS2Restores(MBB, MI, NumAlignedDPRCS2Regs, CSI, TRI);
1015 unsigned PopOpc = AFI->isThumbFunction() ? ARM::t2LDMIA_UPD : ARM::LDMIA_UPD;
1016 unsigned LdrOpc = AFI->isThumbFunction() ? ARM::t2LDR_POST :ARM::LDR_POST_IMM;
1017 unsigned FltOpc = ARM::VLDMDIA_UPD;
1018 emitPopInst(MBB, MI, CSI, FltOpc, 0, isVarArg, true, &isARMArea3Register,
1019 NumAlignedDPRCS2Regs);
1020 emitPopInst(MBB, MI, CSI, PopOpc, LdrOpc, isVarArg, false,
1021 &isARMArea2Register, 0);
1022 emitPopInst(MBB, MI, CSI, PopOpc, LdrOpc, isVarArg, false,
1023 &isARMArea1Register, 0);
1028 // FIXME: Make generic?
1029 static unsigned GetFunctionSizeInBytes(const MachineFunction &MF,
1030 const ARMBaseInstrInfo &TII) {
1031 unsigned FnSize = 0;
1032 for (MachineFunction::const_iterator MBBI = MF.begin(), E = MF.end();
1033 MBBI != E; ++MBBI) {
1034 const MachineBasicBlock &MBB = *MBBI;
1035 for (MachineBasicBlock::const_iterator I = MBB.begin(),E = MBB.end();
1037 FnSize += TII.GetInstSizeInBytes(I);
1042 /// estimateStackSize - Estimate and return the size of the frame.
1043 /// FIXME: Make generic?
1044 static unsigned estimateStackSize(MachineFunction &MF) {
1045 const MachineFrameInfo *MFI = MF.getFrameInfo();
1046 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
1047 const TargetRegisterInfo *RegInfo = MF.getTarget().getRegisterInfo();
1048 unsigned MaxAlign = MFI->getMaxAlignment();
1051 // This code is very, very similar to PEI::calculateFrameObjectOffsets().
1052 // It really should be refactored to share code. Until then, changes
1053 // should keep in mind that there's tight coupling between the two.
1055 for (int i = MFI->getObjectIndexBegin(); i != 0; ++i) {
1056 int FixedOff = -MFI->getObjectOffset(i);
1057 if (FixedOff > Offset) Offset = FixedOff;
1059 for (unsigned i = 0, e = MFI->getObjectIndexEnd(); i != e; ++i) {
1060 if (MFI->isDeadObjectIndex(i))
1062 Offset += MFI->getObjectSize(i);
1063 unsigned Align = MFI->getObjectAlignment(i);
1064 // Adjust to alignment boundary
1065 Offset = (Offset+Align-1)/Align*Align;
1067 MaxAlign = std::max(Align, MaxAlign);
1070 if (MFI->adjustsStack() && TFI->hasReservedCallFrame(MF))
1071 Offset += MFI->getMaxCallFrameSize();
1073 // Round up the size to a multiple of the alignment. If the function has
1074 // any calls or alloca's, align to the target's StackAlignment value to
1075 // ensure that the callee's frame or the alloca data is suitably aligned;
1076 // otherwise, for leaf functions, align to the TransientStackAlignment
1078 unsigned StackAlign;
1079 if (MFI->adjustsStack() || MFI->hasVarSizedObjects() ||
1080 (RegInfo->needsStackRealignment(MF) && MFI->getObjectIndexEnd() != 0))
1081 StackAlign = TFI->getStackAlignment();
1083 StackAlign = TFI->getTransientStackAlignment();
1085 // If the frame pointer is eliminated, all frame offsets will be relative to
1086 // SP not FP. Align to MaxAlign so this works.
1087 StackAlign = std::max(StackAlign, MaxAlign);
1088 unsigned AlignMask = StackAlign - 1;
1089 Offset = (Offset + AlignMask) & ~uint64_t(AlignMask);
1091 return (unsigned)Offset;
1094 /// estimateRSStackSizeLimit - Look at each instruction that references stack
1095 /// frames and return the stack size limit beyond which some of these
1096 /// instructions will require a scratch register during their expansion later.
1097 // FIXME: Move to TII?
1098 static unsigned estimateRSStackSizeLimit(MachineFunction &MF,
1099 const TargetFrameLowering *TFI) {
1100 const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1101 unsigned Limit = (1 << 12) - 1;
1102 for (MachineFunction::iterator BB = MF.begin(),E = MF.end(); BB != E; ++BB) {
1103 for (MachineBasicBlock::iterator I = BB->begin(), E = BB->end();
1105 for (unsigned i = 0, e = I->getNumOperands(); i != e; ++i) {
1106 if (!I->getOperand(i).isFI()) continue;
1108 // When using ADDri to get the address of a stack object, 255 is the
1109 // largest offset guaranteed to fit in the immediate offset.
1110 if (I->getOpcode() == ARM::ADDri) {
1111 Limit = std::min(Limit, (1U << 8) - 1);
1115 // Otherwise check the addressing mode.
1116 switch (I->getDesc().TSFlags & ARMII::AddrModeMask) {
1117 case ARMII::AddrMode3:
1118 case ARMII::AddrModeT2_i8:
1119 Limit = std::min(Limit, (1U << 8) - 1);
1121 case ARMII::AddrMode5:
1122 case ARMII::AddrModeT2_i8s4:
1123 Limit = std::min(Limit, ((1U << 8) - 1) * 4);
1125 case ARMII::AddrModeT2_i12:
1126 // i12 supports only positive offset so these will be converted to
1127 // i8 opcodes. See llvm::rewriteT2FrameIndex.
1128 if (TFI->hasFP(MF) && AFI->hasStackFrame())
1129 Limit = std::min(Limit, (1U << 8) - 1);
1131 case ARMII::AddrMode4:
1132 case ARMII::AddrMode6:
1133 // Addressing modes 4 & 6 (load/store) instructions can't encode an
1134 // immediate offset for stack references.
1139 break; // At most one FI per instruction
1147 // In functions that realign the stack, it can be an advantage to spill the
1148 // callee-saved vector registers after realigning the stack. The vst1 and vld1
1149 // instructions take alignment hints that can improve performance.
1151 static void checkNumAlignedDPRCS2Regs(MachineFunction &MF) {
1152 MF.getInfo<ARMFunctionInfo>()->setNumAlignedDPRCS2Regs(0);
1153 if (!SpillAlignedNEONRegs)
1156 // Naked functions don't spill callee-saved registers.
1157 if (MF.getFunction()->getFnAttributes().hasAttribute(Attributes::Naked))
1160 // We are planning to use NEON instructions vst1 / vld1.
1161 if (!MF.getTarget().getSubtarget<ARMSubtarget>().hasNEON())
1164 // Don't bother if the default stack alignment is sufficiently high.
1165 if (MF.getTarget().getFrameLowering()->getStackAlignment() >= 8)
1168 // Aligned spills require stack realignment.
1169 const ARMBaseRegisterInfo *RegInfo =
1170 static_cast<const ARMBaseRegisterInfo*>(MF.getTarget().getRegisterInfo());
1171 if (!RegInfo->canRealignStack(MF))
1174 // We always spill contiguous d-registers starting from d8. Count how many
1175 // needs spilling. The register allocator will almost always use the
1176 // callee-saved registers in order, but it can happen that there are holes in
1177 // the range. Registers above the hole will be spilled to the standard DPRCS
1179 MachineRegisterInfo &MRI = MF.getRegInfo();
1180 unsigned NumSpills = 0;
1181 for (; NumSpills < 8; ++NumSpills)
1182 if (!MRI.isPhysRegUsed(ARM::D8 + NumSpills))
1185 // Don't do this for just one d-register. It's not worth it.
1189 // Spill the first NumSpills D-registers after realigning the stack.
1190 MF.getInfo<ARMFunctionInfo>()->setNumAlignedDPRCS2Regs(NumSpills);
1192 // A scratch register is required for the vst1 / vld1 instructions.
1193 MF.getRegInfo().setPhysRegUsed(ARM::R4);
1197 ARMFrameLowering::processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
1198 RegScavenger *RS) const {
1199 // This tells PEI to spill the FP as if it is any other callee-save register
1200 // to take advantage the eliminateFrameIndex machinery. This also ensures it
1201 // is spilled in the order specified by getCalleeSavedRegs() to make it easier
1202 // to combine multiple loads / stores.
1203 bool CanEliminateFrame = true;
1204 bool CS1Spilled = false;
1205 bool LRSpilled = false;
1206 unsigned NumGPRSpills = 0;
1207 SmallVector<unsigned, 4> UnspilledCS1GPRs;
1208 SmallVector<unsigned, 4> UnspilledCS2GPRs;
1209 const ARMBaseRegisterInfo *RegInfo =
1210 static_cast<const ARMBaseRegisterInfo*>(MF.getTarget().getRegisterInfo());
1211 const ARMBaseInstrInfo &TII =
1212 *static_cast<const ARMBaseInstrInfo*>(MF.getTarget().getInstrInfo());
1213 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1214 MachineFrameInfo *MFI = MF.getFrameInfo();
1215 MachineRegisterInfo &MRI = MF.getRegInfo();
1216 unsigned FramePtr = RegInfo->getFrameRegister(MF);
1218 // Spill R4 if Thumb2 function requires stack realignment - it will be used as
1219 // scratch register. Also spill R4 if Thumb2 function has varsized objects,
1220 // since it's not always possible to restore sp from fp in a single
1222 // FIXME: It will be better just to find spare register here.
1223 if (AFI->isThumb2Function() &&
1224 (MFI->hasVarSizedObjects() || RegInfo->needsStackRealignment(MF)))
1225 MRI.setPhysRegUsed(ARM::R4);
1227 if (AFI->isThumb1OnlyFunction()) {
1228 // Spill LR if Thumb1 function uses variable length argument lists.
1229 if (AFI->getVarArgsRegSaveSize() > 0)
1230 MRI.setPhysRegUsed(ARM::LR);
1232 // Spill R4 if Thumb1 epilogue has to restore SP from FP. We don't know
1233 // for sure what the stack size will be, but for this, an estimate is good
1234 // enough. If there anything changes it, it'll be a spill, which implies
1235 // we've used all the registers and so R4 is already used, so not marking
1236 // it here will be OK.
1237 // FIXME: It will be better just to find spare register here.
1238 unsigned StackSize = estimateStackSize(MF);
1239 if (MFI->hasVarSizedObjects() || StackSize > 508)
1240 MRI.setPhysRegUsed(ARM::R4);
1243 // See if we can spill vector registers to aligned stack.
1244 checkNumAlignedDPRCS2Regs(MF);
1246 // Spill the BasePtr if it's used.
1247 if (RegInfo->hasBasePointer(MF))
1248 MRI.setPhysRegUsed(RegInfo->getBaseRegister());
1250 // Don't spill FP if the frame can be eliminated. This is determined
1251 // by scanning the callee-save registers to see if any is used.
1252 const uint16_t *CSRegs = RegInfo->getCalleeSavedRegs();
1253 for (unsigned i = 0; CSRegs[i]; ++i) {
1254 unsigned Reg = CSRegs[i];
1255 bool Spilled = false;
1256 if (MRI.isPhysRegUsed(Reg)) {
1258 CanEliminateFrame = false;
1261 if (!ARM::GPRRegClass.contains(Reg))
1267 if (!STI.isTargetIOS()) {
1274 // Keep track if LR and any of R4, R5, R6, and R7 is spilled.
1279 case ARM::R4: case ARM::R5:
1280 case ARM::R6: case ARM::R7:
1287 if (!STI.isTargetIOS()) {
1288 UnspilledCS1GPRs.push_back(Reg);
1293 case ARM::R4: case ARM::R5:
1294 case ARM::R6: case ARM::R7:
1296 UnspilledCS1GPRs.push_back(Reg);
1299 UnspilledCS2GPRs.push_back(Reg);
1305 bool ForceLRSpill = false;
1306 if (!LRSpilled && AFI->isThumb1OnlyFunction()) {
1307 unsigned FnSize = GetFunctionSizeInBytes(MF, TII);
1308 // Force LR to be spilled if the Thumb function size is > 2048. This enables
1309 // use of BL to implement far jump. If it turns out that it's not needed
1310 // then the branch fix up path will undo it.
1311 if (FnSize >= (1 << 11)) {
1312 CanEliminateFrame = false;
1313 ForceLRSpill = true;
1317 // If any of the stack slot references may be out of range of an immediate
1318 // offset, make sure a register (or a spill slot) is available for the
1319 // register scavenger. Note that if we're indexing off the frame pointer, the
1320 // effective stack size is 4 bytes larger since the FP points to the stack
1321 // slot of the previous FP. Also, if we have variable sized objects in the
1322 // function, stack slot references will often be negative, and some of
1323 // our instructions are positive-offset only, so conservatively consider
1324 // that case to want a spill slot (or register) as well. Similarly, if
1325 // the function adjusts the stack pointer during execution and the
1326 // adjustments aren't already part of our stack size estimate, our offset
1327 // calculations may be off, so be conservative.
1328 // FIXME: We could add logic to be more precise about negative offsets
1329 // and which instructions will need a scratch register for them. Is it
1330 // worth the effort and added fragility?
1333 (estimateStackSize(MF) + ((hasFP(MF) && AFI->hasStackFrame()) ? 4:0) >=
1334 estimateRSStackSizeLimit(MF, this)))
1335 || MFI->hasVarSizedObjects()
1336 || (MFI->adjustsStack() && !canSimplifyCallFramePseudos(MF));
1338 bool ExtraCSSpill = false;
1339 if (BigStack || !CanEliminateFrame || RegInfo->cannotEliminateFrame(MF)) {
1340 AFI->setHasStackFrame(true);
1342 // If LR is not spilled, but at least one of R4, R5, R6, and R7 is spilled.
1343 // Spill LR as well so we can fold BX_RET to the registers restore (LDM).
1344 if (!LRSpilled && CS1Spilled) {
1345 MRI.setPhysRegUsed(ARM::LR);
1347 UnspilledCS1GPRs.erase(std::find(UnspilledCS1GPRs.begin(),
1348 UnspilledCS1GPRs.end(), (unsigned)ARM::LR));
1349 ForceLRSpill = false;
1350 ExtraCSSpill = true;
1354 MRI.setPhysRegUsed(FramePtr);
1358 // If stack and double are 8-byte aligned and we are spilling an odd number
1359 // of GPRs, spill one extra callee save GPR so we won't have to pad between
1360 // the integer and double callee save areas.
1361 unsigned TargetAlign = getStackAlignment();
1362 if (TargetAlign == 8 && (NumGPRSpills & 1)) {
1363 if (CS1Spilled && !UnspilledCS1GPRs.empty()) {
1364 for (unsigned i = 0, e = UnspilledCS1GPRs.size(); i != e; ++i) {
1365 unsigned Reg = UnspilledCS1GPRs[i];
1366 // Don't spill high register if the function is thumb1
1367 if (!AFI->isThumb1OnlyFunction() ||
1368 isARMLowRegister(Reg) || Reg == ARM::LR) {
1369 MRI.setPhysRegUsed(Reg);
1370 if (!MRI.isReserved(Reg))
1371 ExtraCSSpill = true;
1375 } else if (!UnspilledCS2GPRs.empty() && !AFI->isThumb1OnlyFunction()) {
1376 unsigned Reg = UnspilledCS2GPRs.front();
1377 MRI.setPhysRegUsed(Reg);
1378 if (!MRI.isReserved(Reg))
1379 ExtraCSSpill = true;
1383 // Estimate if we might need to scavenge a register at some point in order
1384 // to materialize a stack offset. If so, either spill one additional
1385 // callee-saved register or reserve a special spill slot to facilitate
1386 // register scavenging. Thumb1 needs a spill slot for stack pointer
1387 // adjustments also, even when the frame itself is small.
1388 if (BigStack && !ExtraCSSpill) {
1389 // If any non-reserved CS register isn't spilled, just spill one or two
1390 // extra. That should take care of it!
1391 unsigned NumExtras = TargetAlign / 4;
1392 SmallVector<unsigned, 2> Extras;
1393 while (NumExtras && !UnspilledCS1GPRs.empty()) {
1394 unsigned Reg = UnspilledCS1GPRs.back();
1395 UnspilledCS1GPRs.pop_back();
1396 if (!MRI.isReserved(Reg) &&
1397 (!AFI->isThumb1OnlyFunction() || isARMLowRegister(Reg) ||
1399 Extras.push_back(Reg);
1403 // For non-Thumb1 functions, also check for hi-reg CS registers
1404 if (!AFI->isThumb1OnlyFunction()) {
1405 while (NumExtras && !UnspilledCS2GPRs.empty()) {
1406 unsigned Reg = UnspilledCS2GPRs.back();
1407 UnspilledCS2GPRs.pop_back();
1408 if (!MRI.isReserved(Reg)) {
1409 Extras.push_back(Reg);
1414 if (Extras.size() && NumExtras == 0) {
1415 for (unsigned i = 0, e = Extras.size(); i != e; ++i) {
1416 MRI.setPhysRegUsed(Extras[i]);
1418 } else if (!AFI->isThumb1OnlyFunction()) {
1419 // note: Thumb1 functions spill to R12, not the stack. Reserve a slot
1420 // closest to SP or frame pointer.
1421 const TargetRegisterClass *RC = &ARM::GPRRegClass;
1422 RS->setScavengingFrameIndex(MFI->CreateStackObject(RC->getSize(),
1430 MRI.setPhysRegUsed(ARM::LR);
1431 AFI->setLRIsSpilledForFarJump(true);