1 //===-- ARMFrameLowering.cpp - ARM Frame Information ----------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the ARM implementation of TargetFrameLowering class.
12 //===----------------------------------------------------------------------===//
14 #include "ARMFrameLowering.h"
15 #include "ARMBaseInstrInfo.h"
16 #include "ARMBaseRegisterInfo.h"
17 #include "ARMMachineFunctionInfo.h"
18 #include "MCTargetDesc/ARMAddressingModes.h"
19 #include "llvm/CodeGen/MachineFrameInfo.h"
20 #include "llvm/CodeGen/MachineFunction.h"
21 #include "llvm/CodeGen/MachineInstrBuilder.h"
22 #include "llvm/CodeGen/MachineRegisterInfo.h"
23 #include "llvm/CodeGen/RegisterScavenging.h"
24 #include "llvm/IR/CallingConv.h"
25 #include "llvm/IR/Function.h"
26 #include "llvm/Support/CommandLine.h"
27 #include "llvm/Target/TargetOptions.h"
32 SpillAlignedNEONRegs("align-neon-spills", cl::Hidden, cl::init(true),
33 cl::desc("Align ARM NEON spills in prolog and epilog"));
35 static MachineBasicBlock::iterator
36 skipAlignedDPRCS2Spills(MachineBasicBlock::iterator MI,
37 unsigned NumAlignedDPRCS2Regs);
39 /// hasFP - Return true if the specified function should have a dedicated frame
40 /// pointer register. This is true if the function has variable sized allocas
41 /// or if frame pointer elimination is disabled.
42 bool ARMFrameLowering::hasFP(const MachineFunction &MF) const {
43 const TargetRegisterInfo *RegInfo = MF.getTarget().getRegisterInfo();
45 // iOS requires FP not to be clobbered for backtracing purpose.
46 if (STI.isTargetIOS())
49 const MachineFrameInfo *MFI = MF.getFrameInfo();
50 // Always eliminate non-leaf frame pointers.
51 return ((MF.getTarget().Options.DisableFramePointerElim(MF) &&
53 RegInfo->needsStackRealignment(MF) ||
54 MFI->hasVarSizedObjects() ||
55 MFI->isFrameAddressTaken());
58 /// hasReservedCallFrame - Under normal circumstances, when a frame pointer is
59 /// not required, we reserve argument space for call sites in the function
60 /// immediately on entry to the current function. This eliminates the need for
61 /// add/sub sp brackets around call sites. Returns true if the call frame is
62 /// included as part of the stack frame.
63 bool ARMFrameLowering::hasReservedCallFrame(const MachineFunction &MF) const {
64 const MachineFrameInfo *FFI = MF.getFrameInfo();
65 unsigned CFSize = FFI->getMaxCallFrameSize();
66 // It's not always a good idea to include the call frame as part of the
67 // stack frame. ARM (especially Thumb) has small immediate offset to
68 // address the stack frame. So a large call frame can cause poor codegen
69 // and may even makes it impossible to scavenge a register.
70 if (CFSize >= ((1 << 12) - 1) / 2) // Half of imm12
73 return !MF.getFrameInfo()->hasVarSizedObjects();
76 /// canSimplifyCallFramePseudos - If there is a reserved call frame, the
77 /// call frame pseudos can be simplified. Unlike most targets, having a FP
78 /// is not sufficient here since we still may reference some objects via SP
79 /// even when FP is available in Thumb2 mode.
81 ARMFrameLowering::canSimplifyCallFramePseudos(const MachineFunction &MF) const {
82 return hasReservedCallFrame(MF) || MF.getFrameInfo()->hasVarSizedObjects();
85 static bool isCSRestore(MachineInstr *MI,
86 const ARMBaseInstrInfo &TII,
87 const uint16_t *CSRegs) {
88 // Integer spill area is handled with "pop".
89 if (isPopOpcode(MI->getOpcode())) {
90 // The first two operands are predicates. The last two are
91 // imp-def and imp-use of SP. Check everything in between.
92 for (int i = 5, e = MI->getNumOperands(); i != e; ++i)
93 if (!isCalleeSavedRegister(MI->getOperand(i).getReg(), CSRegs))
97 if ((MI->getOpcode() == ARM::LDR_POST_IMM ||
98 MI->getOpcode() == ARM::LDR_POST_REG ||
99 MI->getOpcode() == ARM::t2LDR_POST) &&
100 isCalleeSavedRegister(MI->getOperand(0).getReg(), CSRegs) &&
101 MI->getOperand(1).getReg() == ARM::SP)
107 static void emitRegPlusImmediate(bool isARM, MachineBasicBlock &MBB,
108 MachineBasicBlock::iterator &MBBI, DebugLoc dl,
109 const ARMBaseInstrInfo &TII, unsigned DestReg,
110 unsigned SrcReg, int NumBytes,
111 unsigned MIFlags = MachineInstr::NoFlags,
112 ARMCC::CondCodes Pred = ARMCC::AL,
113 unsigned PredReg = 0) {
115 emitARMRegPlusImmediate(MBB, MBBI, dl, DestReg, SrcReg, NumBytes,
116 Pred, PredReg, TII, MIFlags);
118 emitT2RegPlusImmediate(MBB, MBBI, dl, DestReg, SrcReg, NumBytes,
119 Pred, PredReg, TII, MIFlags);
122 static void emitSPUpdate(bool isARM, MachineBasicBlock &MBB,
123 MachineBasicBlock::iterator &MBBI, DebugLoc dl,
124 const ARMBaseInstrInfo &TII, int NumBytes,
125 unsigned MIFlags = MachineInstr::NoFlags,
126 ARMCC::CondCodes Pred = ARMCC::AL,
127 unsigned PredReg = 0) {
128 emitRegPlusImmediate(isARM, MBB, MBBI, dl, TII, ARM::SP, ARM::SP, NumBytes,
129 MIFlags, Pred, PredReg);
132 void ARMFrameLowering::emitPrologue(MachineFunction &MF) const {
133 MachineBasicBlock &MBB = MF.front();
134 MachineBasicBlock::iterator MBBI = MBB.begin();
135 MachineFrameInfo *MFI = MF.getFrameInfo();
136 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
137 const ARMBaseRegisterInfo *RegInfo =
138 static_cast<const ARMBaseRegisterInfo*>(MF.getTarget().getRegisterInfo());
139 const ARMBaseInstrInfo &TII =
140 *static_cast<const ARMBaseInstrInfo*>(MF.getTarget().getInstrInfo());
141 assert(!AFI->isThumb1OnlyFunction() &&
142 "This emitPrologue does not support Thumb1!");
143 bool isARM = !AFI->isThumbFunction();
144 unsigned Align = MF.getTarget().getFrameLowering()->getStackAlignment();
145 unsigned ArgRegsSaveSize = AFI->getArgRegsSaveSize(Align);
146 unsigned NumBytes = MFI->getStackSize();
147 const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
148 DebugLoc dl = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
149 unsigned FramePtr = RegInfo->getFrameRegister(MF);
151 // Determine the sizes of each callee-save spill areas and record which frame
152 // belongs to which callee-save spill areas.
153 unsigned GPRCS1Size = 0, GPRCS2Size = 0, DPRCSSize = 0;
154 int FramePtrSpillFI = 0;
157 // All calls are tail calls in GHC calling conv, and functions have no
158 // prologue/epilogue.
159 if (MF.getFunction()->getCallingConv() == CallingConv::GHC)
162 // Allocate the vararg register save area. This is not counted in NumBytes.
164 emitSPUpdate(isARM, MBB, MBBI, dl, TII, -ArgRegsSaveSize,
165 MachineInstr::FrameSetup);
167 if (!AFI->hasStackFrame()) {
169 emitSPUpdate(isARM, MBB, MBBI, dl, TII, -NumBytes,
170 MachineInstr::FrameSetup);
174 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
175 unsigned Reg = CSI[i].getReg();
176 int FI = CSI[i].getFrameIdx();
188 FramePtrSpillFI = FI;
197 FramePtrSpillFI = FI;
198 if (STI.isTargetIOS())
204 // This is a DPR. Exclude the aligned DPRCS2 spills.
207 if (Reg < ARM::D8 || Reg >= ARM::D8 + AFI->getNumAlignedDPRCS2Regs())
213 MachineBasicBlock::iterator LastPush = MBB.end(), FramePtrPush;
215 FramePtrPush = LastPush = MBBI++;
217 // Determine starting offsets of spill areas.
218 bool HasFP = hasFP(MF);
219 unsigned DPRCSOffset = NumBytes - (GPRCS1Size + GPRCS2Size + DPRCSSize);
220 unsigned GPRCS2Offset = DPRCSOffset + DPRCSSize;
221 unsigned GPRCS1Offset = GPRCS2Offset + GPRCS2Size;
222 int FramePtrOffsetInPush = 0;
224 FramePtrOffsetInPush = MFI->getObjectOffset(FramePtrSpillFI) + GPRCS1Size;
225 AFI->setFramePtrSpillOffset(MFI->getObjectOffset(FramePtrSpillFI) +
228 AFI->setGPRCalleeSavedArea1Offset(GPRCS1Offset);
229 AFI->setGPRCalleeSavedArea2Offset(GPRCS2Offset);
230 AFI->setDPRCalleeSavedAreaOffset(DPRCSOffset);
233 if (GPRCS2Size > 0) {
240 // Since vpush register list cannot have gaps, there may be multiple vpush
241 // instructions in the prologue.
242 while (MBBI->getOpcode() == ARM::VSTMDDB_UPD)
246 // Move past the aligned DPRCS2 area.
247 if (AFI->getNumAlignedDPRCS2Regs() > 0) {
248 MBBI = skipAlignedDPRCS2Spills(MBBI, AFI->getNumAlignedDPRCS2Regs());
249 // The code inserted by emitAlignedDPRCS2Spills realigns the stack, and
250 // leaves the stack pointer pointing to the DPRCS2 area.
252 // Adjust NumBytes to represent the stack slots below the DPRCS2 area.
253 NumBytes += MFI->getObjectOffset(D8SpillFI);
255 NumBytes = DPRCSOffset;
258 // Adjust SP after all the callee-save spills.
259 if (tryFoldSPUpdateIntoPushPop(STI, MF, LastPush, NumBytes))
260 FramePtrOffsetInPush += NumBytes;
262 emitSPUpdate(isARM, MBB, MBBI, dl, TII, -NumBytes,
263 MachineInstr::FrameSetup);
266 // Restore from fp only in ARM mode: e.g. sub sp, r7, #24
267 // Note it's not safe to do this in Thumb2 mode because it would have
268 // taken two instructions:
271 // If an interrupt is taken between the two instructions, then sp is in
272 // an inconsistent state (pointing to the middle of callee-saved area).
273 // The interrupt handler can end up clobbering the registers.
274 AFI->setShouldRestoreSPFromFP(true);
277 // Set FP to point to the stack slot that contains the previous FP.
278 // For iOS, FP is R7, which has now been stored in spill area 1.
279 // Otherwise, if this is not iOS, all the callee-saved registers go
280 // into spill area 1, including the FP in R11. In either case, it
281 // is in area one and the adjustment needs to take place just after
284 emitRegPlusImmediate(!AFI->isThumbFunction(), MBB, ++FramePtrPush, dl, TII,
285 FramePtr, ARM::SP, FramePtrOffsetInPush,
286 MachineInstr::FrameSetup);
289 if (STI.isTargetELF() && hasFP(MF))
290 MFI->setOffsetAdjustment(MFI->getOffsetAdjustment() -
291 AFI->getFramePtrSpillOffset());
293 AFI->setGPRCalleeSavedArea1Size(GPRCS1Size);
294 AFI->setGPRCalleeSavedArea2Size(GPRCS2Size);
295 AFI->setDPRCalleeSavedAreaSize(DPRCSSize);
297 // If we need dynamic stack realignment, do it here. Be paranoid and make
298 // sure if we also have VLAs, we have a base pointer for frame access.
299 // If aligned NEON registers were spilled, the stack has already been
301 if (!AFI->getNumAlignedDPRCS2Regs() && RegInfo->needsStackRealignment(MF)) {
302 unsigned MaxAlign = MFI->getMaxAlignment();
303 assert (!AFI->isThumb1OnlyFunction());
304 if (!AFI->isThumbFunction()) {
305 // Emit bic sp, sp, MaxAlign
306 AddDefaultCC(AddDefaultPred(BuildMI(MBB, MBBI, dl,
307 TII.get(ARM::BICri), ARM::SP)
308 .addReg(ARM::SP, RegState::Kill)
309 .addImm(MaxAlign-1)));
311 // We cannot use sp as source/dest register here, thus we're emitting the
312 // following sequence:
314 // bic r4, r4, MaxAlign
316 // FIXME: It will be better just to find spare register here.
317 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), ARM::R4)
318 .addReg(ARM::SP, RegState::Kill));
319 AddDefaultCC(AddDefaultPred(BuildMI(MBB, MBBI, dl,
320 TII.get(ARM::t2BICri), ARM::R4)
321 .addReg(ARM::R4, RegState::Kill)
322 .addImm(MaxAlign-1)));
323 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), ARM::SP)
324 .addReg(ARM::R4, RegState::Kill));
327 AFI->setShouldRestoreSPFromFP(true);
330 // If we need a base pointer, set it up here. It's whatever the value
331 // of the stack pointer is at this point. Any variable size objects
332 // will be allocated after this, so we can still use the base pointer
333 // to reference locals.
334 // FIXME: Clarify FrameSetup flags here.
335 if (RegInfo->hasBasePointer(MF)) {
337 BuildMI(MBB, MBBI, dl,
338 TII.get(ARM::MOVr), RegInfo->getBaseRegister())
340 .addImm((unsigned)ARMCC::AL).addReg(0).addReg(0);
342 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr),
343 RegInfo->getBaseRegister())
347 // If the frame has variable sized objects then the epilogue must restore
348 // the sp from fp. We can assume there's an FP here since hasFP already
349 // checks for hasVarSizedObjects.
350 if (MFI->hasVarSizedObjects())
351 AFI->setShouldRestoreSPFromFP(true);
354 void ARMFrameLowering::emitEpilogue(MachineFunction &MF,
355 MachineBasicBlock &MBB) const {
356 MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr();
357 assert(MBBI->isReturn() && "Can only insert epilog into returning blocks");
358 unsigned RetOpcode = MBBI->getOpcode();
359 DebugLoc dl = MBBI->getDebugLoc();
360 MachineFrameInfo *MFI = MF.getFrameInfo();
361 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
362 const TargetRegisterInfo *RegInfo = MF.getTarget().getRegisterInfo();
363 const ARMBaseInstrInfo &TII =
364 *static_cast<const ARMBaseInstrInfo*>(MF.getTarget().getInstrInfo());
365 assert(!AFI->isThumb1OnlyFunction() &&
366 "This emitEpilogue does not support Thumb1!");
367 bool isARM = !AFI->isThumbFunction();
369 unsigned Align = MF.getTarget().getFrameLowering()->getStackAlignment();
370 unsigned ArgRegsSaveSize = AFI->getArgRegsSaveSize(Align);
371 int NumBytes = (int)MFI->getStackSize();
372 unsigned FramePtr = RegInfo->getFrameRegister(MF);
374 // All calls are tail calls in GHC calling conv, and functions have no
375 // prologue/epilogue.
376 if (MF.getFunction()->getCallingConv() == CallingConv::GHC)
379 if (!AFI->hasStackFrame()) {
381 emitSPUpdate(isARM, MBB, MBBI, dl, TII, NumBytes);
383 MachineBasicBlock::iterator FirstPop = MBBI;
385 // Unwind MBBI to point to first LDR / VLDRD.
386 const uint16_t *CSRegs = RegInfo->getCalleeSavedRegs(&MF);
387 if (MBBI != MBB.begin()) {
389 if (isPopOpcode(MBBI->getOpcode()))
393 } while (MBBI != MBB.begin() && isCSRestore(MBBI, TII, CSRegs));
394 if (!isCSRestore(MBBI, TII, CSRegs))
398 // Move SP to start of FP callee save spill area.
399 NumBytes -= (AFI->getGPRCalleeSavedArea1Size() +
400 AFI->getGPRCalleeSavedArea2Size() +
401 AFI->getDPRCalleeSavedAreaSize());
403 // Reset SP based on frame pointer only if the stack frame extends beyond
404 // frame pointer stack slot or target is ELF and the function has FP.
405 if (AFI->shouldRestoreSPFromFP()) {
406 NumBytes = AFI->getFramePtrSpillOffset() - NumBytes;
409 emitARMRegPlusImmediate(MBB, MBBI, dl, ARM::SP, FramePtr, -NumBytes,
412 // It's not possible to restore SP from FP in a single instruction.
413 // For iOS, this looks like:
416 // This is bad, if an interrupt is taken after the mov, sp is in an
417 // inconsistent state.
418 // Use the first callee-saved register as a scratch register.
419 assert(MF.getRegInfo().isPhysRegUsed(ARM::R4) &&
420 "No scratch register to restore SP from FP!");
421 emitT2RegPlusImmediate(MBB, MBBI, dl, ARM::R4, FramePtr, -NumBytes,
423 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr),
430 BuildMI(MBB, MBBI, dl, TII.get(ARM::MOVr), ARM::SP)
431 .addReg(FramePtr).addImm((unsigned)ARMCC::AL).addReg(0).addReg(0);
433 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr),
437 } else if (NumBytes &&
438 !tryFoldSPUpdateIntoPushPop(STI, MF, FirstPop, NumBytes))
439 emitSPUpdate(isARM, MBB, MBBI, dl, TII, NumBytes);
441 // Increment past our save areas.
442 if (AFI->getDPRCalleeSavedAreaSize()) {
444 // Since vpop register list cannot have gaps, there may be multiple vpop
445 // instructions in the epilogue.
446 while (MBBI->getOpcode() == ARM::VLDMDIA_UPD)
449 if (AFI->getGPRCalleeSavedArea2Size()) MBBI++;
450 if (AFI->getGPRCalleeSavedArea1Size()) MBBI++;
453 if (RetOpcode == ARM::TCRETURNdi || RetOpcode == ARM::TCRETURNri) {
454 // Tail call return: adjust the stack pointer and jump to callee.
455 MBBI = MBB.getLastNonDebugInstr();
456 MachineOperand &JumpTarget = MBBI->getOperand(0);
458 // Jump to label or value in register.
459 if (RetOpcode == ARM::TCRETURNdi) {
460 unsigned TCOpcode = STI.isThumb() ?
461 (STI.isTargetIOS() ? ARM::tTAILJMPd : ARM::tTAILJMPdND) :
463 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII.get(TCOpcode));
464 if (JumpTarget.isGlobal())
465 MIB.addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset(),
466 JumpTarget.getTargetFlags());
468 assert(JumpTarget.isSymbol());
469 MIB.addExternalSymbol(JumpTarget.getSymbolName(),
470 JumpTarget.getTargetFlags());
473 // Add the default predicate in Thumb mode.
474 if (STI.isThumb()) MIB.addImm(ARMCC::AL).addReg(0);
475 } else if (RetOpcode == ARM::TCRETURNri) {
476 BuildMI(MBB, MBBI, dl,
477 TII.get(STI.isThumb() ? ARM::tTAILJMPr : ARM::TAILJMPr)).
478 addReg(JumpTarget.getReg(), RegState::Kill);
481 MachineInstr *NewMI = prior(MBBI);
482 for (unsigned i = 1, e = MBBI->getNumOperands(); i != e; ++i)
483 NewMI->addOperand(MBBI->getOperand(i));
485 // Delete the pseudo instruction TCRETURN.
491 emitSPUpdate(isARM, MBB, MBBI, dl, TII, ArgRegsSaveSize);
494 /// getFrameIndexReference - Provide a base+offset reference to an FI slot for
495 /// debug info. It's the same as what we use for resolving the code-gen
496 /// references for now. FIXME: This can go wrong when references are
497 /// SP-relative and simple call frames aren't used.
499 ARMFrameLowering::getFrameIndexReference(const MachineFunction &MF, int FI,
500 unsigned &FrameReg) const {
501 return ResolveFrameIndexReference(MF, FI, FrameReg, 0);
505 ARMFrameLowering::ResolveFrameIndexReference(const MachineFunction &MF,
506 int FI, unsigned &FrameReg,
508 const MachineFrameInfo *MFI = MF.getFrameInfo();
509 const ARMBaseRegisterInfo *RegInfo =
510 static_cast<const ARMBaseRegisterInfo*>(MF.getTarget().getRegisterInfo());
511 const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
512 int Offset = MFI->getObjectOffset(FI) + MFI->getStackSize();
513 int FPOffset = Offset - AFI->getFramePtrSpillOffset();
514 bool isFixed = MFI->isFixedObjectIndex(FI);
519 // SP can move around if there are allocas. We may also lose track of SP
520 // when emergency spilling inside a non-reserved call frame setup.
521 bool hasMovingSP = !hasReservedCallFrame(MF);
523 // When dynamically realigning the stack, use the frame pointer for
524 // parameters, and the stack/base pointer for locals.
525 if (RegInfo->needsStackRealignment(MF)) {
526 assert (hasFP(MF) && "dynamic stack realignment without a FP!");
528 FrameReg = RegInfo->getFrameRegister(MF);
530 } else if (hasMovingSP) {
531 assert(RegInfo->hasBasePointer(MF) &&
532 "VLAs and dynamic stack alignment, but missing base pointer!");
533 FrameReg = RegInfo->getBaseRegister();
538 // If there is a frame pointer, use it when we can.
539 if (hasFP(MF) && AFI->hasStackFrame()) {
540 // Use frame pointer to reference fixed objects. Use it for locals if
541 // there are VLAs (and thus the SP isn't reliable as a base).
542 if (isFixed || (hasMovingSP && !RegInfo->hasBasePointer(MF))) {
543 FrameReg = RegInfo->getFrameRegister(MF);
545 } else if (hasMovingSP) {
546 assert(RegInfo->hasBasePointer(MF) && "missing base pointer!");
547 if (AFI->isThumb2Function()) {
548 // Try to use the frame pointer if we can, else use the base pointer
549 // since it's available. This is handy for the emergency spill slot, in
551 if (FPOffset >= -255 && FPOffset < 0) {
552 FrameReg = RegInfo->getFrameRegister(MF);
556 } else if (AFI->isThumb2Function()) {
557 // Use add <rd>, sp, #<imm8>
558 // ldr <rd>, [sp, #<imm8>]
559 // if at all possible to save space.
560 if (Offset >= 0 && (Offset & 3) == 0 && Offset <= 1020)
562 // In Thumb2 mode, the negative offset is very limited. Try to avoid
563 // out of range references. ldr <rt>,[<rn>, #-<imm8>]
564 if (FPOffset >= -255 && FPOffset < 0) {
565 FrameReg = RegInfo->getFrameRegister(MF);
568 } else if (Offset > (FPOffset < 0 ? -FPOffset : FPOffset)) {
569 // Otherwise, use SP or FP, whichever is closer to the stack slot.
570 FrameReg = RegInfo->getFrameRegister(MF);
574 // Use the base pointer if we have one.
575 if (RegInfo->hasBasePointer(MF))
576 FrameReg = RegInfo->getBaseRegister();
580 int ARMFrameLowering::getFrameIndexOffset(const MachineFunction &MF,
583 return getFrameIndexReference(MF, FI, FrameReg);
586 void ARMFrameLowering::emitPushInst(MachineBasicBlock &MBB,
587 MachineBasicBlock::iterator MI,
588 const std::vector<CalleeSavedInfo> &CSI,
589 unsigned StmOpc, unsigned StrOpc,
591 bool(*Func)(unsigned, bool),
592 unsigned NumAlignedDPRCS2Regs,
593 unsigned MIFlags) const {
594 MachineFunction &MF = *MBB.getParent();
595 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
598 if (MI != MBB.end()) DL = MI->getDebugLoc();
600 SmallVector<std::pair<unsigned,bool>, 4> Regs;
601 unsigned i = CSI.size();
603 unsigned LastReg = 0;
604 for (; i != 0; --i) {
605 unsigned Reg = CSI[i-1].getReg();
606 if (!(Func)(Reg, STI.isTargetIOS())) continue;
608 // D-registers in the aligned area DPRCS2 are NOT spilled here.
609 if (Reg >= ARM::D8 && Reg < ARM::D8 + NumAlignedDPRCS2Regs)
612 // Add the callee-saved register as live-in unless it's LR and
613 // @llvm.returnaddress is called. If LR is returned for
614 // @llvm.returnaddress then it's already added to the function and
615 // entry block live-in sets.
617 if (Reg == ARM::LR) {
618 if (MF.getFrameInfo()->isReturnAddressTaken() &&
619 MF.getRegInfo().isLiveIn(Reg))
626 // If NoGap is true, push consecutive registers and then leave the rest
627 // for other instructions. e.g.
628 // vpush {d8, d10, d11} -> vpush {d8}, vpush {d10, d11}
629 if (NoGap && LastReg && LastReg != Reg-1)
632 Regs.push_back(std::make_pair(Reg, isKill));
637 if (Regs.size() > 1 || StrOpc== 0) {
638 MachineInstrBuilder MIB =
639 AddDefaultPred(BuildMI(MBB, MI, DL, TII.get(StmOpc), ARM::SP)
640 .addReg(ARM::SP).setMIFlags(MIFlags));
641 for (unsigned i = 0, e = Regs.size(); i < e; ++i)
642 MIB.addReg(Regs[i].first, getKillRegState(Regs[i].second));
643 } else if (Regs.size() == 1) {
644 MachineInstrBuilder MIB = BuildMI(MBB, MI, DL, TII.get(StrOpc),
646 .addReg(Regs[0].first, getKillRegState(Regs[0].second))
647 .addReg(ARM::SP).setMIFlags(MIFlags)
655 void ARMFrameLowering::emitPopInst(MachineBasicBlock &MBB,
656 MachineBasicBlock::iterator MI,
657 const std::vector<CalleeSavedInfo> &CSI,
658 unsigned LdmOpc, unsigned LdrOpc,
659 bool isVarArg, bool NoGap,
660 bool(*Func)(unsigned, bool),
661 unsigned NumAlignedDPRCS2Regs) const {
662 MachineFunction &MF = *MBB.getParent();
663 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
664 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
665 DebugLoc DL = MI->getDebugLoc();
666 unsigned RetOpcode = MI->getOpcode();
667 bool isTailCall = (RetOpcode == ARM::TCRETURNdi ||
668 RetOpcode == ARM::TCRETURNri);
670 RetOpcode == ARM::SUBS_PC_LR || RetOpcode == ARM::t2SUBS_PC_LR;
672 SmallVector<unsigned, 4> Regs;
673 unsigned i = CSI.size();
675 unsigned LastReg = 0;
676 bool DeleteRet = false;
677 for (; i != 0; --i) {
678 unsigned Reg = CSI[i-1].getReg();
679 if (!(Func)(Reg, STI.isTargetIOS())) continue;
681 // The aligned reloads from area DPRCS2 are not inserted here.
682 if (Reg >= ARM::D8 && Reg < ARM::D8 + NumAlignedDPRCS2Regs)
685 if (Reg == ARM::LR && !isTailCall && !isVarArg && !isInterrupt &&
688 LdmOpc = AFI->isThumbFunction() ? ARM::t2LDMIA_RET : ARM::LDMIA_RET;
689 // Fold the return instruction into the LDM.
693 // If NoGap is true, pop consecutive registers and then leave the rest
694 // for other instructions. e.g.
695 // vpop {d8, d10, d11} -> vpop {d8}, vpop {d10, d11}
696 if (NoGap && LastReg && LastReg != Reg-1)
705 if (Regs.size() > 1 || LdrOpc == 0) {
706 MachineInstrBuilder MIB =
707 AddDefaultPred(BuildMI(MBB, MI, DL, TII.get(LdmOpc), ARM::SP)
709 for (unsigned i = 0, e = Regs.size(); i < e; ++i)
710 MIB.addReg(Regs[i], getDefRegState(true));
712 MIB.copyImplicitOps(&*MI);
713 MI->eraseFromParent();
716 } else if (Regs.size() == 1) {
717 // If we adjusted the reg to PC from LR above, switch it back here. We
718 // only do that for LDM.
719 if (Regs[0] == ARM::PC)
721 MachineInstrBuilder MIB =
722 BuildMI(MBB, MI, DL, TII.get(LdrOpc), Regs[0])
723 .addReg(ARM::SP, RegState::Define)
725 // ARM mode needs an extra reg0 here due to addrmode2. Will go away once
726 // that refactoring is complete (eventually).
727 if (LdrOpc == ARM::LDR_POST_REG || LdrOpc == ARM::LDR_POST_IMM) {
729 MIB.addImm(ARM_AM::getAM2Opc(ARM_AM::add, 4, ARM_AM::no_shift));
738 /// Emit aligned spill instructions for NumAlignedDPRCS2Regs D-registers
739 /// starting from d8. Also insert stack realignment code and leave the stack
740 /// pointer pointing to the d8 spill slot.
741 static void emitAlignedDPRCS2Spills(MachineBasicBlock &MBB,
742 MachineBasicBlock::iterator MI,
743 unsigned NumAlignedDPRCS2Regs,
744 const std::vector<CalleeSavedInfo> &CSI,
745 const TargetRegisterInfo *TRI) {
746 MachineFunction &MF = *MBB.getParent();
747 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
748 DebugLoc DL = MI->getDebugLoc();
749 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
750 MachineFrameInfo &MFI = *MF.getFrameInfo();
752 // Mark the D-register spill slots as properly aligned. Since MFI computes
753 // stack slot layout backwards, this can actually mean that the d-reg stack
754 // slot offsets can be wrong. The offset for d8 will always be correct.
755 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
756 unsigned DNum = CSI[i].getReg() - ARM::D8;
759 int FI = CSI[i].getFrameIdx();
760 // The even-numbered registers will be 16-byte aligned, the odd-numbered
761 // registers will be 8-byte aligned.
762 MFI.setObjectAlignment(FI, DNum % 2 ? 8 : 16);
764 // The stack slot for D8 needs to be maximally aligned because this is
765 // actually the point where we align the stack pointer. MachineFrameInfo
766 // computes all offsets relative to the incoming stack pointer which is a
767 // bit weird when realigning the stack. Any extra padding for this
768 // over-alignment is not realized because the code inserted below adjusts
769 // the stack pointer by numregs * 8 before aligning the stack pointer.
771 MFI.setObjectAlignment(FI, MFI.getMaxAlignment());
774 // Move the stack pointer to the d8 spill slot, and align it at the same
775 // time. Leave the stack slot address in the scratch register r4.
777 // sub r4, sp, #numregs * 8
778 // bic r4, r4, #align - 1
781 bool isThumb = AFI->isThumbFunction();
782 assert(!AFI->isThumb1OnlyFunction() && "Can't realign stack for thumb1");
783 AFI->setShouldRestoreSPFromFP(true);
785 // sub r4, sp, #numregs * 8
786 // The immediate is <= 64, so it doesn't need any special encoding.
787 unsigned Opc = isThumb ? ARM::t2SUBri : ARM::SUBri;
788 AddDefaultCC(AddDefaultPred(BuildMI(MBB, MI, DL, TII.get(Opc), ARM::R4)
790 .addImm(8 * NumAlignedDPRCS2Regs)));
792 // bic r4, r4, #align-1
793 Opc = isThumb ? ARM::t2BICri : ARM::BICri;
794 unsigned MaxAlign = MF.getFrameInfo()->getMaxAlignment();
795 AddDefaultCC(AddDefaultPred(BuildMI(MBB, MI, DL, TII.get(Opc), ARM::R4)
796 .addReg(ARM::R4, RegState::Kill)
797 .addImm(MaxAlign - 1)));
800 // The stack pointer must be adjusted before spilling anything, otherwise
801 // the stack slots could be clobbered by an interrupt handler.
802 // Leave r4 live, it is used below.
803 Opc = isThumb ? ARM::tMOVr : ARM::MOVr;
804 MachineInstrBuilder MIB = BuildMI(MBB, MI, DL, TII.get(Opc), ARM::SP)
806 MIB = AddDefaultPred(MIB);
810 // Now spill NumAlignedDPRCS2Regs registers starting from d8.
811 // r4 holds the stack slot address.
812 unsigned NextReg = ARM::D8;
814 // 16-byte aligned vst1.64 with 4 d-regs and address writeback.
815 // The writeback is only needed when emitting two vst1.64 instructions.
816 if (NumAlignedDPRCS2Regs >= 6) {
817 unsigned SupReg = TRI->getMatchingSuperReg(NextReg, ARM::dsub_0,
819 MBB.addLiveIn(SupReg);
820 AddDefaultPred(BuildMI(MBB, MI, DL, TII.get(ARM::VST1d64Qwb_fixed),
822 .addReg(ARM::R4, RegState::Kill).addImm(16)
824 .addReg(SupReg, RegState::ImplicitKill));
826 NumAlignedDPRCS2Regs -= 4;
829 // We won't modify r4 beyond this point. It currently points to the next
830 // register to be spilled.
831 unsigned R4BaseReg = NextReg;
833 // 16-byte aligned vst1.64 with 4 d-regs, no writeback.
834 if (NumAlignedDPRCS2Regs >= 4) {
835 unsigned SupReg = TRI->getMatchingSuperReg(NextReg, ARM::dsub_0,
837 MBB.addLiveIn(SupReg);
838 AddDefaultPred(BuildMI(MBB, MI, DL, TII.get(ARM::VST1d64Q))
839 .addReg(ARM::R4).addImm(16).addReg(NextReg)
840 .addReg(SupReg, RegState::ImplicitKill));
842 NumAlignedDPRCS2Regs -= 4;
845 // 16-byte aligned vst1.64 with 2 d-regs.
846 if (NumAlignedDPRCS2Regs >= 2) {
847 unsigned SupReg = TRI->getMatchingSuperReg(NextReg, ARM::dsub_0,
849 MBB.addLiveIn(SupReg);
850 AddDefaultPred(BuildMI(MBB, MI, DL, TII.get(ARM::VST1q64))
851 .addReg(ARM::R4).addImm(16).addReg(SupReg));
853 NumAlignedDPRCS2Regs -= 2;
856 // Finally, use a vanilla vstr.64 for the odd last register.
857 if (NumAlignedDPRCS2Regs) {
858 MBB.addLiveIn(NextReg);
859 // vstr.64 uses addrmode5 which has an offset scale of 4.
860 AddDefaultPred(BuildMI(MBB, MI, DL, TII.get(ARM::VSTRD))
862 .addReg(ARM::R4).addImm((NextReg-R4BaseReg)*2));
865 // The last spill instruction inserted should kill the scratch register r4.
866 llvm::prior(MI)->addRegisterKilled(ARM::R4, TRI);
869 /// Skip past the code inserted by emitAlignedDPRCS2Spills, and return an
870 /// iterator to the following instruction.
871 static MachineBasicBlock::iterator
872 skipAlignedDPRCS2Spills(MachineBasicBlock::iterator MI,
873 unsigned NumAlignedDPRCS2Regs) {
874 // sub r4, sp, #numregs * 8
875 // bic r4, r4, #align - 1
878 assert(MI->mayStore() && "Expecting spill instruction");
880 // These switches all fall through.
881 switch(NumAlignedDPRCS2Regs) {
884 assert(MI->mayStore() && "Expecting spill instruction");
887 assert(MI->mayStore() && "Expecting spill instruction");
891 assert(MI->killsRegister(ARM::R4) && "Missed kill flag");
897 /// Emit aligned reload instructions for NumAlignedDPRCS2Regs D-registers
898 /// starting from d8. These instructions are assumed to execute while the
899 /// stack is still aligned, unlike the code inserted by emitPopInst.
900 static void emitAlignedDPRCS2Restores(MachineBasicBlock &MBB,
901 MachineBasicBlock::iterator MI,
902 unsigned NumAlignedDPRCS2Regs,
903 const std::vector<CalleeSavedInfo> &CSI,
904 const TargetRegisterInfo *TRI) {
905 MachineFunction &MF = *MBB.getParent();
906 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
907 DebugLoc DL = MI->getDebugLoc();
908 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
910 // Find the frame index assigned to d8.
912 for (unsigned i = 0, e = CSI.size(); i != e; ++i)
913 if (CSI[i].getReg() == ARM::D8) {
914 D8SpillFI = CSI[i].getFrameIdx();
918 // Materialize the address of the d8 spill slot into the scratch register r4.
919 // This can be fairly complicated if the stack frame is large, so just use
920 // the normal frame index elimination mechanism to do it. This code runs as
921 // the initial part of the epilog where the stack and base pointers haven't
923 bool isThumb = AFI->isThumbFunction();
924 assert(!AFI->isThumb1OnlyFunction() && "Can't realign stack for thumb1");
926 unsigned Opc = isThumb ? ARM::t2ADDri : ARM::ADDri;
927 AddDefaultCC(AddDefaultPred(BuildMI(MBB, MI, DL, TII.get(Opc), ARM::R4)
928 .addFrameIndex(D8SpillFI).addImm(0)));
930 // Now restore NumAlignedDPRCS2Regs registers starting from d8.
931 unsigned NextReg = ARM::D8;
933 // 16-byte aligned vld1.64 with 4 d-regs and writeback.
934 if (NumAlignedDPRCS2Regs >= 6) {
935 unsigned SupReg = TRI->getMatchingSuperReg(NextReg, ARM::dsub_0,
937 AddDefaultPred(BuildMI(MBB, MI, DL, TII.get(ARM::VLD1d64Qwb_fixed), NextReg)
938 .addReg(ARM::R4, RegState::Define)
939 .addReg(ARM::R4, RegState::Kill).addImm(16)
940 .addReg(SupReg, RegState::ImplicitDefine));
942 NumAlignedDPRCS2Regs -= 4;
945 // We won't modify r4 beyond this point. It currently points to the next
946 // register to be spilled.
947 unsigned R4BaseReg = NextReg;
949 // 16-byte aligned vld1.64 with 4 d-regs, no writeback.
950 if (NumAlignedDPRCS2Regs >= 4) {
951 unsigned SupReg = TRI->getMatchingSuperReg(NextReg, ARM::dsub_0,
953 AddDefaultPred(BuildMI(MBB, MI, DL, TII.get(ARM::VLD1d64Q), NextReg)
954 .addReg(ARM::R4).addImm(16)
955 .addReg(SupReg, RegState::ImplicitDefine));
957 NumAlignedDPRCS2Regs -= 4;
960 // 16-byte aligned vld1.64 with 2 d-regs.
961 if (NumAlignedDPRCS2Regs >= 2) {
962 unsigned SupReg = TRI->getMatchingSuperReg(NextReg, ARM::dsub_0,
964 AddDefaultPred(BuildMI(MBB, MI, DL, TII.get(ARM::VLD1q64), SupReg)
965 .addReg(ARM::R4).addImm(16));
967 NumAlignedDPRCS2Regs -= 2;
970 // Finally, use a vanilla vldr.64 for the remaining odd register.
971 if (NumAlignedDPRCS2Regs)
972 AddDefaultPred(BuildMI(MBB, MI, DL, TII.get(ARM::VLDRD), NextReg)
973 .addReg(ARM::R4).addImm(2*(NextReg-R4BaseReg)));
975 // Last store kills r4.
976 llvm::prior(MI)->addRegisterKilled(ARM::R4, TRI);
979 bool ARMFrameLowering::spillCalleeSavedRegisters(MachineBasicBlock &MBB,
980 MachineBasicBlock::iterator MI,
981 const std::vector<CalleeSavedInfo> &CSI,
982 const TargetRegisterInfo *TRI) const {
986 MachineFunction &MF = *MBB.getParent();
987 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
989 unsigned PushOpc = AFI->isThumbFunction() ? ARM::t2STMDB_UPD : ARM::STMDB_UPD;
990 unsigned PushOneOpc = AFI->isThumbFunction() ?
991 ARM::t2STR_PRE : ARM::STR_PRE_IMM;
992 unsigned FltOpc = ARM::VSTMDDB_UPD;
993 unsigned NumAlignedDPRCS2Regs = AFI->getNumAlignedDPRCS2Regs();
994 emitPushInst(MBB, MI, CSI, PushOpc, PushOneOpc, false, &isARMArea1Register, 0,
995 MachineInstr::FrameSetup);
996 emitPushInst(MBB, MI, CSI, PushOpc, PushOneOpc, false, &isARMArea2Register, 0,
997 MachineInstr::FrameSetup);
998 emitPushInst(MBB, MI, CSI, FltOpc, 0, true, &isARMArea3Register,
999 NumAlignedDPRCS2Regs, MachineInstr::FrameSetup);
1001 // The code above does not insert spill code for the aligned DPRCS2 registers.
1002 // The stack realignment code will be inserted between the push instructions
1003 // and these spills.
1004 if (NumAlignedDPRCS2Regs)
1005 emitAlignedDPRCS2Spills(MBB, MI, NumAlignedDPRCS2Regs, CSI, TRI);
1010 bool ARMFrameLowering::restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
1011 MachineBasicBlock::iterator MI,
1012 const std::vector<CalleeSavedInfo> &CSI,
1013 const TargetRegisterInfo *TRI) const {
1017 MachineFunction &MF = *MBB.getParent();
1018 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1019 bool isVarArg = AFI->getArgRegsSaveSize() > 0;
1020 unsigned NumAlignedDPRCS2Regs = AFI->getNumAlignedDPRCS2Regs();
1022 // The emitPopInst calls below do not insert reloads for the aligned DPRCS2
1023 // registers. Do that here instead.
1024 if (NumAlignedDPRCS2Regs)
1025 emitAlignedDPRCS2Restores(MBB, MI, NumAlignedDPRCS2Regs, CSI, TRI);
1027 unsigned PopOpc = AFI->isThumbFunction() ? ARM::t2LDMIA_UPD : ARM::LDMIA_UPD;
1028 unsigned LdrOpc = AFI->isThumbFunction() ? ARM::t2LDR_POST :ARM::LDR_POST_IMM;
1029 unsigned FltOpc = ARM::VLDMDIA_UPD;
1030 emitPopInst(MBB, MI, CSI, FltOpc, 0, isVarArg, true, &isARMArea3Register,
1031 NumAlignedDPRCS2Regs);
1032 emitPopInst(MBB, MI, CSI, PopOpc, LdrOpc, isVarArg, false,
1033 &isARMArea2Register, 0);
1034 emitPopInst(MBB, MI, CSI, PopOpc, LdrOpc, isVarArg, false,
1035 &isARMArea1Register, 0);
1040 // FIXME: Make generic?
1041 static unsigned GetFunctionSizeInBytes(const MachineFunction &MF,
1042 const ARMBaseInstrInfo &TII) {
1043 unsigned FnSize = 0;
1044 for (MachineFunction::const_iterator MBBI = MF.begin(), E = MF.end();
1045 MBBI != E; ++MBBI) {
1046 const MachineBasicBlock &MBB = *MBBI;
1047 for (MachineBasicBlock::const_iterator I = MBB.begin(),E = MBB.end();
1049 FnSize += TII.GetInstSizeInBytes(I);
1054 /// estimateRSStackSizeLimit - Look at each instruction that references stack
1055 /// frames and return the stack size limit beyond which some of these
1056 /// instructions will require a scratch register during their expansion later.
1057 // FIXME: Move to TII?
1058 static unsigned estimateRSStackSizeLimit(MachineFunction &MF,
1059 const TargetFrameLowering *TFI) {
1060 const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1061 unsigned Limit = (1 << 12) - 1;
1062 for (MachineFunction::iterator BB = MF.begin(),E = MF.end(); BB != E; ++BB) {
1063 for (MachineBasicBlock::iterator I = BB->begin(), E = BB->end();
1065 for (unsigned i = 0, e = I->getNumOperands(); i != e; ++i) {
1066 if (!I->getOperand(i).isFI()) continue;
1068 // When using ADDri to get the address of a stack object, 255 is the
1069 // largest offset guaranteed to fit in the immediate offset.
1070 if (I->getOpcode() == ARM::ADDri) {
1071 Limit = std::min(Limit, (1U << 8) - 1);
1075 // Otherwise check the addressing mode.
1076 switch (I->getDesc().TSFlags & ARMII::AddrModeMask) {
1077 case ARMII::AddrMode3:
1078 case ARMII::AddrModeT2_i8:
1079 Limit = std::min(Limit, (1U << 8) - 1);
1081 case ARMII::AddrMode5:
1082 case ARMII::AddrModeT2_i8s4:
1083 Limit = std::min(Limit, ((1U << 8) - 1) * 4);
1085 case ARMII::AddrModeT2_i12:
1086 // i12 supports only positive offset so these will be converted to
1087 // i8 opcodes. See llvm::rewriteT2FrameIndex.
1088 if (TFI->hasFP(MF) && AFI->hasStackFrame())
1089 Limit = std::min(Limit, (1U << 8) - 1);
1091 case ARMII::AddrMode4:
1092 case ARMII::AddrMode6:
1093 // Addressing modes 4 & 6 (load/store) instructions can't encode an
1094 // immediate offset for stack references.
1099 break; // At most one FI per instruction
1107 // In functions that realign the stack, it can be an advantage to spill the
1108 // callee-saved vector registers after realigning the stack. The vst1 and vld1
1109 // instructions take alignment hints that can improve performance.
1111 static void checkNumAlignedDPRCS2Regs(MachineFunction &MF) {
1112 MF.getInfo<ARMFunctionInfo>()->setNumAlignedDPRCS2Regs(0);
1113 if (!SpillAlignedNEONRegs)
1116 // Naked functions don't spill callee-saved registers.
1117 if (MF.getFunction()->getAttributes().hasAttribute(AttributeSet::FunctionIndex,
1121 // We are planning to use NEON instructions vst1 / vld1.
1122 if (!MF.getTarget().getSubtarget<ARMSubtarget>().hasNEON())
1125 // Don't bother if the default stack alignment is sufficiently high.
1126 if (MF.getTarget().getFrameLowering()->getStackAlignment() >= 8)
1129 // Aligned spills require stack realignment.
1130 const ARMBaseRegisterInfo *RegInfo =
1131 static_cast<const ARMBaseRegisterInfo*>(MF.getTarget().getRegisterInfo());
1132 if (!RegInfo->canRealignStack(MF))
1135 // We always spill contiguous d-registers starting from d8. Count how many
1136 // needs spilling. The register allocator will almost always use the
1137 // callee-saved registers in order, but it can happen that there are holes in
1138 // the range. Registers above the hole will be spilled to the standard DPRCS
1140 MachineRegisterInfo &MRI = MF.getRegInfo();
1141 unsigned NumSpills = 0;
1142 for (; NumSpills < 8; ++NumSpills)
1143 if (!MRI.isPhysRegUsed(ARM::D8 + NumSpills))
1146 // Don't do this for just one d-register. It's not worth it.
1150 // Spill the first NumSpills D-registers after realigning the stack.
1151 MF.getInfo<ARMFunctionInfo>()->setNumAlignedDPRCS2Regs(NumSpills);
1153 // A scratch register is required for the vst1 / vld1 instructions.
1154 MF.getRegInfo().setPhysRegUsed(ARM::R4);
1158 ARMFrameLowering::processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
1159 RegScavenger *RS) const {
1160 // This tells PEI to spill the FP as if it is any other callee-save register
1161 // to take advantage the eliminateFrameIndex machinery. This also ensures it
1162 // is spilled in the order specified by getCalleeSavedRegs() to make it easier
1163 // to combine multiple loads / stores.
1164 bool CanEliminateFrame = true;
1165 bool CS1Spilled = false;
1166 bool LRSpilled = false;
1167 unsigned NumGPRSpills = 0;
1168 SmallVector<unsigned, 4> UnspilledCS1GPRs;
1169 SmallVector<unsigned, 4> UnspilledCS2GPRs;
1170 const ARMBaseRegisterInfo *RegInfo =
1171 static_cast<const ARMBaseRegisterInfo*>(MF.getTarget().getRegisterInfo());
1172 const ARMBaseInstrInfo &TII =
1173 *static_cast<const ARMBaseInstrInfo*>(MF.getTarget().getInstrInfo());
1174 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1175 MachineFrameInfo *MFI = MF.getFrameInfo();
1176 MachineRegisterInfo &MRI = MF.getRegInfo();
1177 unsigned FramePtr = RegInfo->getFrameRegister(MF);
1179 // Spill R4 if Thumb2 function requires stack realignment - it will be used as
1180 // scratch register. Also spill R4 if Thumb2 function has varsized objects,
1181 // since it's not always possible to restore sp from fp in a single
1183 // FIXME: It will be better just to find spare register here.
1184 if (AFI->isThumb2Function() &&
1185 (MFI->hasVarSizedObjects() || RegInfo->needsStackRealignment(MF)))
1186 MRI.setPhysRegUsed(ARM::R4);
1188 if (AFI->isThumb1OnlyFunction()) {
1189 // Spill LR if Thumb1 function uses variable length argument lists.
1190 if (AFI->getArgRegsSaveSize() > 0)
1191 MRI.setPhysRegUsed(ARM::LR);
1193 // Spill R4 if Thumb1 epilogue has to restore SP from FP. We don't know
1194 // for sure what the stack size will be, but for this, an estimate is good
1195 // enough. If there anything changes it, it'll be a spill, which implies
1196 // we've used all the registers and so R4 is already used, so not marking
1197 // it here will be OK.
1198 // FIXME: It will be better just to find spare register here.
1199 unsigned StackSize = MFI->estimateStackSize(MF);
1200 if (MFI->hasVarSizedObjects() || StackSize > 508)
1201 MRI.setPhysRegUsed(ARM::R4);
1204 // See if we can spill vector registers to aligned stack.
1205 checkNumAlignedDPRCS2Regs(MF);
1207 // Spill the BasePtr if it's used.
1208 if (RegInfo->hasBasePointer(MF))
1209 MRI.setPhysRegUsed(RegInfo->getBaseRegister());
1211 // Don't spill FP if the frame can be eliminated. This is determined
1212 // by scanning the callee-save registers to see if any is used.
1213 const uint16_t *CSRegs = RegInfo->getCalleeSavedRegs(&MF);
1214 for (unsigned i = 0; CSRegs[i]; ++i) {
1215 unsigned Reg = CSRegs[i];
1216 bool Spilled = false;
1217 if (MRI.isPhysRegUsed(Reg)) {
1219 CanEliminateFrame = false;
1222 if (!ARM::GPRRegClass.contains(Reg))
1228 if (!STI.isTargetIOS()) {
1235 // Keep track if LR and any of R4, R5, R6, and R7 is spilled.
1240 case ARM::R0: case ARM::R1:
1241 case ARM::R2: case ARM::R3:
1242 case ARM::R4: case ARM::R5:
1243 case ARM::R6: case ARM::R7:
1250 if (!STI.isTargetIOS()) {
1251 UnspilledCS1GPRs.push_back(Reg);
1256 case ARM::R0: case ARM::R1:
1257 case ARM::R2: case ARM::R3:
1258 case ARM::R4: case ARM::R5:
1259 case ARM::R6: case ARM::R7:
1261 UnspilledCS1GPRs.push_back(Reg);
1264 UnspilledCS2GPRs.push_back(Reg);
1270 bool ForceLRSpill = false;
1271 if (!LRSpilled && AFI->isThumb1OnlyFunction()) {
1272 unsigned FnSize = GetFunctionSizeInBytes(MF, TII);
1273 // Force LR to be spilled if the Thumb function size is > 2048. This enables
1274 // use of BL to implement far jump. If it turns out that it's not needed
1275 // then the branch fix up path will undo it.
1276 if (FnSize >= (1 << 11)) {
1277 CanEliminateFrame = false;
1278 ForceLRSpill = true;
1282 // If any of the stack slot references may be out of range of an immediate
1283 // offset, make sure a register (or a spill slot) is available for the
1284 // register scavenger. Note that if we're indexing off the frame pointer, the
1285 // effective stack size is 4 bytes larger since the FP points to the stack
1286 // slot of the previous FP. Also, if we have variable sized objects in the
1287 // function, stack slot references will often be negative, and some of
1288 // our instructions are positive-offset only, so conservatively consider
1289 // that case to want a spill slot (or register) as well. Similarly, if
1290 // the function adjusts the stack pointer during execution and the
1291 // adjustments aren't already part of our stack size estimate, our offset
1292 // calculations may be off, so be conservative.
1293 // FIXME: We could add logic to be more precise about negative offsets
1294 // and which instructions will need a scratch register for them. Is it
1295 // worth the effort and added fragility?
1298 (MFI->estimateStackSize(MF) +
1299 ((hasFP(MF) && AFI->hasStackFrame()) ? 4:0) >=
1300 estimateRSStackSizeLimit(MF, this)))
1301 || MFI->hasVarSizedObjects()
1302 || (MFI->adjustsStack() && !canSimplifyCallFramePseudos(MF));
1304 bool ExtraCSSpill = false;
1305 if (BigStack || !CanEliminateFrame || RegInfo->cannotEliminateFrame(MF)) {
1306 AFI->setHasStackFrame(true);
1308 // If LR is not spilled, but at least one of R4, R5, R6, and R7 is spilled.
1309 // Spill LR as well so we can fold BX_RET to the registers restore (LDM).
1310 if (!LRSpilled && CS1Spilled) {
1311 MRI.setPhysRegUsed(ARM::LR);
1313 SmallVectorImpl<unsigned>::iterator LRPos;
1314 LRPos = std::find(UnspilledCS1GPRs.begin(), UnspilledCS1GPRs.end(),
1316 if (LRPos != UnspilledCS1GPRs.end())
1317 UnspilledCS1GPRs.erase(LRPos);
1319 ForceLRSpill = false;
1320 ExtraCSSpill = true;
1324 MRI.setPhysRegUsed(FramePtr);
1328 // If stack and double are 8-byte aligned and we are spilling an odd number
1329 // of GPRs, spill one extra callee save GPR so we won't have to pad between
1330 // the integer and double callee save areas.
1331 unsigned TargetAlign = getStackAlignment();
1332 if (TargetAlign == 8 && (NumGPRSpills & 1)) {
1333 if (CS1Spilled && !UnspilledCS1GPRs.empty()) {
1334 for (unsigned i = 0, e = UnspilledCS1GPRs.size(); i != e; ++i) {
1335 unsigned Reg = UnspilledCS1GPRs[i];
1336 // Don't spill high register if the function is thumb1
1337 if (!AFI->isThumb1OnlyFunction() ||
1338 isARMLowRegister(Reg) || Reg == ARM::LR) {
1339 MRI.setPhysRegUsed(Reg);
1340 if (!MRI.isReserved(Reg))
1341 ExtraCSSpill = true;
1345 } else if (!UnspilledCS2GPRs.empty() && !AFI->isThumb1OnlyFunction()) {
1346 unsigned Reg = UnspilledCS2GPRs.front();
1347 MRI.setPhysRegUsed(Reg);
1348 if (!MRI.isReserved(Reg))
1349 ExtraCSSpill = true;
1353 // Estimate if we might need to scavenge a register at some point in order
1354 // to materialize a stack offset. If so, either spill one additional
1355 // callee-saved register or reserve a special spill slot to facilitate
1356 // register scavenging. Thumb1 needs a spill slot for stack pointer
1357 // adjustments also, even when the frame itself is small.
1358 if (BigStack && !ExtraCSSpill) {
1359 // If any non-reserved CS register isn't spilled, just spill one or two
1360 // extra. That should take care of it!
1361 unsigned NumExtras = TargetAlign / 4;
1362 SmallVector<unsigned, 2> Extras;
1363 while (NumExtras && !UnspilledCS1GPRs.empty()) {
1364 unsigned Reg = UnspilledCS1GPRs.back();
1365 UnspilledCS1GPRs.pop_back();
1366 if (!MRI.isReserved(Reg) &&
1367 (!AFI->isThumb1OnlyFunction() || isARMLowRegister(Reg) ||
1369 Extras.push_back(Reg);
1373 // For non-Thumb1 functions, also check for hi-reg CS registers
1374 if (!AFI->isThumb1OnlyFunction()) {
1375 while (NumExtras && !UnspilledCS2GPRs.empty()) {
1376 unsigned Reg = UnspilledCS2GPRs.back();
1377 UnspilledCS2GPRs.pop_back();
1378 if (!MRI.isReserved(Reg)) {
1379 Extras.push_back(Reg);
1384 if (Extras.size() && NumExtras == 0) {
1385 for (unsigned i = 0, e = Extras.size(); i != e; ++i) {
1386 MRI.setPhysRegUsed(Extras[i]);
1388 } else if (!AFI->isThumb1OnlyFunction()) {
1389 // note: Thumb1 functions spill to R12, not the stack. Reserve a slot
1390 // closest to SP or frame pointer.
1391 const TargetRegisterClass *RC = &ARM::GPRRegClass;
1392 RS->addScavengingFrameIndex(MFI->CreateStackObject(RC->getSize(),
1400 MRI.setPhysRegUsed(ARM::LR);
1401 AFI->setLRIsSpilledForFarJump(true);
1406 void ARMFrameLowering::
1407 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
1408 MachineBasicBlock::iterator I) const {
1409 const ARMBaseInstrInfo &TII =
1410 *static_cast<const ARMBaseInstrInfo*>(MF.getTarget().getInstrInfo());
1411 if (!hasReservedCallFrame(MF)) {
1412 // If we have alloca, convert as follows:
1413 // ADJCALLSTACKDOWN -> sub, sp, sp, amount
1414 // ADJCALLSTACKUP -> add, sp, sp, amount
1415 MachineInstr *Old = I;
1416 DebugLoc dl = Old->getDebugLoc();
1417 unsigned Amount = Old->getOperand(0).getImm();
1419 // We need to keep the stack aligned properly. To do this, we round the
1420 // amount of space needed for the outgoing arguments up to the next
1421 // alignment boundary.
1422 unsigned Align = getStackAlignment();
1423 Amount = (Amount+Align-1)/Align*Align;
1425 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1426 assert(!AFI->isThumb1OnlyFunction() &&
1427 "This eliminateCallFramePseudoInstr does not support Thumb1!");
1428 bool isARM = !AFI->isThumbFunction();
1430 // Replace the pseudo instruction with a new instruction...
1431 unsigned Opc = Old->getOpcode();
1432 int PIdx = Old->findFirstPredOperandIdx();
1433 ARMCC::CondCodes Pred = (PIdx == -1)
1434 ? ARMCC::AL : (ARMCC::CondCodes)Old->getOperand(PIdx).getImm();
1435 if (Opc == ARM::ADJCALLSTACKDOWN || Opc == ARM::tADJCALLSTACKDOWN) {
1436 // Note: PredReg is operand 2 for ADJCALLSTACKDOWN.
1437 unsigned PredReg = Old->getOperand(2).getReg();
1438 emitSPUpdate(isARM, MBB, I, dl, TII, -Amount, MachineInstr::NoFlags,
1441 // Note: PredReg is operand 3 for ADJCALLSTACKUP.
1442 unsigned PredReg = Old->getOperand(3).getReg();
1443 assert(Opc == ARM::ADJCALLSTACKUP || Opc == ARM::tADJCALLSTACKUP);
1444 emitSPUpdate(isARM, MBB, I, dl, TII, Amount, MachineInstr::NoFlags,