1 //===-- ARMFastISel.cpp - ARM FastISel implementation ---------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the ARM-specific support for the FastISel class. Some
11 // of the target-specific code is generated by tablegen in the file
12 // ARMGenFastISel.inc, which is #included here.
14 //===----------------------------------------------------------------------===//
17 #include "ARMBaseInstrInfo.h"
18 #include "ARMRegisterInfo.h"
19 #include "ARMTargetMachine.h"
20 #include "ARMSubtarget.h"
21 #include "llvm/CallingConv.h"
22 #include "llvm/DerivedTypes.h"
23 #include "llvm/GlobalVariable.h"
24 #include "llvm/Instructions.h"
25 #include "llvm/IntrinsicInst.h"
26 #include "llvm/CodeGen/Analysis.h"
27 #include "llvm/CodeGen/FastISel.h"
28 #include "llvm/CodeGen/FunctionLoweringInfo.h"
29 #include "llvm/CodeGen/MachineInstrBuilder.h"
30 #include "llvm/CodeGen/MachineModuleInfo.h"
31 #include "llvm/CodeGen/MachineConstantPool.h"
32 #include "llvm/CodeGen/MachineFrameInfo.h"
33 #include "llvm/CodeGen/MachineRegisterInfo.h"
34 #include "llvm/Support/CallSite.h"
35 #include "llvm/Support/CommandLine.h"
36 #include "llvm/Support/ErrorHandling.h"
37 #include "llvm/Support/GetElementPtrTypeIterator.h"
38 #include "llvm/Target/TargetData.h"
39 #include "llvm/Target/TargetInstrInfo.h"
40 #include "llvm/Target/TargetLowering.h"
41 #include "llvm/Target/TargetMachine.h"
42 #include "llvm/Target/TargetOptions.h"
46 EnableARMFastISel("arm-fast-isel",
47 cl::desc("Turn on experimental ARM fast-isel support"),
48 cl::init(false), cl::Hidden);
52 class ARMFastISel : public FastISel {
54 /// Subtarget - Keep a pointer to the ARMSubtarget around so that we can
55 /// make the right decision when generating code for different targets.
56 const ARMSubtarget *Subtarget;
57 const TargetMachine &TM;
58 const TargetInstrInfo &TII;
59 const TargetLowering &TLI;
60 const ARMFunctionInfo *AFI;
62 // Convenience variable to avoid checking all the time.
66 explicit ARMFastISel(FunctionLoweringInfo &funcInfo)
68 TM(funcInfo.MF->getTarget()),
69 TII(*TM.getInstrInfo()),
70 TLI(*TM.getTargetLowering()) {
71 Subtarget = &TM.getSubtarget<ARMSubtarget>();
72 AFI = funcInfo.MF->getInfo<ARMFunctionInfo>();
73 isThumb = AFI->isThumbFunction();
76 // Code from FastISel.cpp.
77 virtual unsigned FastEmitInst_(unsigned MachineInstOpcode,
78 const TargetRegisterClass *RC);
79 virtual unsigned FastEmitInst_r(unsigned MachineInstOpcode,
80 const TargetRegisterClass *RC,
81 unsigned Op0, bool Op0IsKill);
82 virtual unsigned FastEmitInst_rr(unsigned MachineInstOpcode,
83 const TargetRegisterClass *RC,
84 unsigned Op0, bool Op0IsKill,
85 unsigned Op1, bool Op1IsKill);
86 virtual unsigned FastEmitInst_ri(unsigned MachineInstOpcode,
87 const TargetRegisterClass *RC,
88 unsigned Op0, bool Op0IsKill,
90 virtual unsigned FastEmitInst_rf(unsigned MachineInstOpcode,
91 const TargetRegisterClass *RC,
92 unsigned Op0, bool Op0IsKill,
93 const ConstantFP *FPImm);
94 virtual unsigned FastEmitInst_i(unsigned MachineInstOpcode,
95 const TargetRegisterClass *RC,
97 virtual unsigned FastEmitInst_rri(unsigned MachineInstOpcode,
98 const TargetRegisterClass *RC,
99 unsigned Op0, bool Op0IsKill,
100 unsigned Op1, bool Op1IsKill,
102 virtual unsigned FastEmitInst_extractsubreg(MVT RetVT,
103 unsigned Op0, bool Op0IsKill,
106 // Backend specific FastISel code.
107 virtual bool TargetSelectInstruction(const Instruction *I);
108 virtual unsigned TargetMaterializeConstant(const Constant *C);
110 #include "ARMGenFastISel.inc"
112 // Instruction selection routines.
113 virtual bool ARMSelectLoad(const Instruction *I);
114 virtual bool ARMSelectStore(const Instruction *I);
115 virtual bool ARMSelectBranch(const Instruction *I);
116 virtual bool ARMSelectCmp(const Instruction *I);
117 virtual bool ARMSelectFPExt(const Instruction *I);
118 virtual bool ARMSelectFPTrunc(const Instruction *I);
119 virtual bool ARMSelectBinaryOp(const Instruction *I, unsigned ISDOpcode);
120 virtual bool ARMSelectSIToFP(const Instruction *I);
121 virtual bool ARMSelectFPToSI(const Instruction *I);
125 bool isTypeLegal(const Type *Ty, EVT &VT);
126 bool isLoadTypeLegal(const Type *Ty, EVT &VT);
127 bool ARMEmitLoad(EVT VT, unsigned &ResultReg, unsigned Reg, int Offset);
128 bool ARMEmitStore(EVT VT, unsigned SrcReg, unsigned Reg, int Offset);
129 bool ARMLoadAlloca(const Instruction *I, EVT VT);
130 bool ARMStoreAlloca(const Instruction *I, unsigned SrcReg, EVT VT);
131 bool ARMComputeRegOffset(const Value *Obj, unsigned &Reg, int &Offset);
132 unsigned ARMMaterializeFP(const ConstantFP *CFP, EVT VT);
133 unsigned ARMMaterializeInt(const Constant *C);
134 unsigned ARMMoveToFPReg(EVT VT, unsigned SrcReg);
135 unsigned ARMMoveToIntReg(EVT VT, unsigned SrcReg);
137 bool DefinesOptionalPredicate(MachineInstr *MI, bool *CPSR);
138 const MachineInstrBuilder &AddOptionalDefs(const MachineInstrBuilder &MIB);
141 } // end anonymous namespace
143 // #include "ARMGenCallingConv.inc"
145 // DefinesOptionalPredicate - This is different from DefinesPredicate in that
146 // we don't care about implicit defs here, just places we'll need to add a
147 // default CCReg argument. Sets CPSR if we're setting CPSR instead of CCR.
148 bool ARMFastISel::DefinesOptionalPredicate(MachineInstr *MI, bool *CPSR) {
149 const TargetInstrDesc &TID = MI->getDesc();
150 if (!TID.hasOptionalDef())
153 // Look to see if our OptionalDef is defining CPSR or CCR.
154 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
155 const MachineOperand &MO = MI->getOperand(i);
156 if (!MO.isReg() || !MO.isDef()) continue;
157 if (MO.getReg() == ARM::CPSR)
163 // If the machine is predicable go ahead and add the predicate operands, if
164 // it needs default CC operands add those.
165 const MachineInstrBuilder &
166 ARMFastISel::AddOptionalDefs(const MachineInstrBuilder &MIB) {
167 MachineInstr *MI = &*MIB;
169 // Do we use a predicate?
170 if (TII.isPredicable(MI))
173 // Do we optionally set a predicate? Preds is size > 0 iff the predicate
174 // defines CPSR. All other OptionalDefines in ARM are the CCR register.
176 if (DefinesOptionalPredicate(MI, &CPSR)) {
185 unsigned ARMFastISel::FastEmitInst_(unsigned MachineInstOpcode,
186 const TargetRegisterClass* RC) {
187 unsigned ResultReg = createResultReg(RC);
188 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
190 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg));
194 unsigned ARMFastISel::FastEmitInst_r(unsigned MachineInstOpcode,
195 const TargetRegisterClass *RC,
196 unsigned Op0, bool Op0IsKill) {
197 unsigned ResultReg = createResultReg(RC);
198 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
200 if (II.getNumDefs() >= 1)
201 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
202 .addReg(Op0, Op0IsKill * RegState::Kill));
204 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
205 .addReg(Op0, Op0IsKill * RegState::Kill));
206 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
207 TII.get(TargetOpcode::COPY), ResultReg)
208 .addReg(II.ImplicitDefs[0]));
213 unsigned ARMFastISel::FastEmitInst_rr(unsigned MachineInstOpcode,
214 const TargetRegisterClass *RC,
215 unsigned Op0, bool Op0IsKill,
216 unsigned Op1, bool Op1IsKill) {
217 unsigned ResultReg = createResultReg(RC);
218 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
220 if (II.getNumDefs() >= 1)
221 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
222 .addReg(Op0, Op0IsKill * RegState::Kill)
223 .addReg(Op1, Op1IsKill * RegState::Kill));
225 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
226 .addReg(Op0, Op0IsKill * RegState::Kill)
227 .addReg(Op1, Op1IsKill * RegState::Kill));
228 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
229 TII.get(TargetOpcode::COPY), ResultReg)
230 .addReg(II.ImplicitDefs[0]));
235 unsigned ARMFastISel::FastEmitInst_ri(unsigned MachineInstOpcode,
236 const TargetRegisterClass *RC,
237 unsigned Op0, bool Op0IsKill,
239 unsigned ResultReg = createResultReg(RC);
240 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
242 if (II.getNumDefs() >= 1)
243 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
244 .addReg(Op0, Op0IsKill * RegState::Kill)
247 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
248 .addReg(Op0, Op0IsKill * RegState::Kill)
250 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
251 TII.get(TargetOpcode::COPY), ResultReg)
252 .addReg(II.ImplicitDefs[0]));
257 unsigned ARMFastISel::FastEmitInst_rf(unsigned MachineInstOpcode,
258 const TargetRegisterClass *RC,
259 unsigned Op0, bool Op0IsKill,
260 const ConstantFP *FPImm) {
261 unsigned ResultReg = createResultReg(RC);
262 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
264 if (II.getNumDefs() >= 1)
265 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
266 .addReg(Op0, Op0IsKill * RegState::Kill)
269 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
270 .addReg(Op0, Op0IsKill * RegState::Kill)
272 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
273 TII.get(TargetOpcode::COPY), ResultReg)
274 .addReg(II.ImplicitDefs[0]));
279 unsigned ARMFastISel::FastEmitInst_rri(unsigned MachineInstOpcode,
280 const TargetRegisterClass *RC,
281 unsigned Op0, bool Op0IsKill,
282 unsigned Op1, bool Op1IsKill,
284 unsigned ResultReg = createResultReg(RC);
285 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
287 if (II.getNumDefs() >= 1)
288 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
289 .addReg(Op0, Op0IsKill * RegState::Kill)
290 .addReg(Op1, Op1IsKill * RegState::Kill)
293 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
294 .addReg(Op0, Op0IsKill * RegState::Kill)
295 .addReg(Op1, Op1IsKill * RegState::Kill)
297 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
298 TII.get(TargetOpcode::COPY), ResultReg)
299 .addReg(II.ImplicitDefs[0]));
304 unsigned ARMFastISel::FastEmitInst_i(unsigned MachineInstOpcode,
305 const TargetRegisterClass *RC,
307 unsigned ResultReg = createResultReg(RC);
308 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
310 if (II.getNumDefs() >= 1)
311 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
314 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
316 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
317 TII.get(TargetOpcode::COPY), ResultReg)
318 .addReg(II.ImplicitDefs[0]));
323 unsigned ARMFastISel::FastEmitInst_extractsubreg(MVT RetVT,
324 unsigned Op0, bool Op0IsKill,
326 unsigned ResultReg = createResultReg(TLI.getRegClassFor(RetVT));
327 assert(TargetRegisterInfo::isVirtualRegister(Op0) &&
328 "Cannot yet extract from physregs");
329 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt,
330 DL, TII.get(TargetOpcode::COPY), ResultReg)
331 .addReg(Op0, getKillRegState(Op0IsKill), Idx));
335 unsigned ARMFastISel::ARMMoveToFPReg(EVT VT, unsigned SrcReg) {
336 // Don't worry about 64-bit now.
337 if (VT.getSimpleVT().SimpleTy == MVT::f64) return 0;
339 unsigned MoveReg = createResultReg(TLI.getRegClassFor(VT));
340 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
341 TII.get(ARM::VMOVRS), MoveReg)
346 unsigned ARMFastISel::ARMMoveToIntReg(EVT VT, unsigned SrcReg) {
347 // Don't worry about 64-bit now.
348 if (VT.getSimpleVT().SimpleTy == MVT::i64) return 0;
350 // If we have a floating point constant we expect it in a floating point
352 unsigned MoveReg = createResultReg(TLI.getRegClassFor(VT));
353 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
354 TII.get(ARM::VMOVSR), MoveReg)
359 // For double width floating point we need to materialize two constants
360 // (the high and the low) into integer registers then use a move to get
361 // the combined constant into an FP reg.
362 unsigned ARMFastISel::ARMMaterializeFP(const ConstantFP *CFP, EVT VT) {
363 const APFloat Val = CFP->getValueAPF();
364 bool is64bit = VT.getSimpleVT().SimpleTy == MVT::f64;
366 // This checks to see if we can use VFP3 instructions to materialize
367 // a constant, otherwise we have to go through the constant pool.
368 if (TLI.isFPImmLegal(Val, VT)) {
369 unsigned Opc = is64bit ? ARM::FCONSTD : ARM::FCONSTS;
370 unsigned DestReg = createResultReg(TLI.getRegClassFor(VT));
371 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc),
377 // Require VFP2 for this.
378 if (!Subtarget->hasVFP2()) return false;
380 // MachineConstantPool wants an explicit alignment.
381 unsigned Align = TD.getPrefTypeAlignment(CFP->getType());
383 // TODO: Figure out if this is correct.
384 Align = TD.getTypeAllocSize(CFP->getType());
386 unsigned Idx = MCP.getConstantPoolIndex(cast<Constant>(CFP), Align);
387 unsigned DestReg = createResultReg(TLI.getRegClassFor(VT));
388 unsigned Opc = is64bit ? ARM::VLDRD : ARM::VLDRS;
390 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc))
391 .addReg(DestReg).addConstantPoolIndex(Idx)
396 unsigned ARMFastISel::ARMMaterializeInt(const Constant *C) {
397 // MachineConstantPool wants an explicit alignment.
398 unsigned Align = TD.getPrefTypeAlignment(C->getType());
400 // TODO: Figure out if this is correct.
401 Align = TD.getTypeAllocSize(C->getType());
403 unsigned Idx = MCP.getConstantPoolIndex(C, Align);
405 unsigned DestReg = createResultReg(TLI.getRegClassFor(MVT::i32));
407 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
408 TII.get(ARM::t2LDRpci))
409 .addReg(DestReg).addConstantPoolIndex(Idx));
411 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
413 .addReg(DestReg).addConstantPoolIndex(Idx)
414 .addReg(0).addImm(0));
419 unsigned ARMFastISel::TargetMaterializeConstant(const Constant *C) {
420 EVT VT = TLI.getValueType(C->getType(), true);
422 // Only handle simple types.
423 if (!VT.isSimple()) return 0;
425 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(C))
426 return ARMMaterializeFP(CFP, VT);
427 return ARMMaterializeInt(C);
430 bool ARMFastISel::isTypeLegal(const Type *Ty, EVT &VT) {
431 VT = TLI.getValueType(Ty, true);
433 // Only handle simple types.
434 if (VT == MVT::Other || !VT.isSimple()) return false;
436 // Handle all legal types, i.e. a register that will directly hold this
438 return TLI.isTypeLegal(VT);
441 bool ARMFastISel::isLoadTypeLegal(const Type *Ty, EVT &VT) {
442 if (isTypeLegal(Ty, VT)) return true;
444 // If this is a type than can be sign or zero-extended to a basic operation
445 // go ahead and accept it now.
446 if (VT == MVT::i8 || VT == MVT::i16)
452 // Computes the Reg+Offset to get to an object.
453 bool ARMFastISel::ARMComputeRegOffset(const Value *Obj, unsigned &Reg,
455 // Some boilerplate from the X86 FastISel.
456 const User *U = NULL;
457 unsigned Opcode = Instruction::UserOp1;
458 if (const Instruction *I = dyn_cast<Instruction>(Obj)) {
459 // Don't walk into other basic blocks; it's possible we haven't
460 // visited them yet, so the instructions may not yet be assigned
461 // virtual registers.
462 if (FuncInfo.MBBMap[I->getParent()] != FuncInfo.MBB)
465 Opcode = I->getOpcode();
467 } else if (const ConstantExpr *C = dyn_cast<ConstantExpr>(Obj)) {
468 Opcode = C->getOpcode();
472 if (const PointerType *Ty = dyn_cast<PointerType>(Obj->getType()))
473 if (Ty->getAddressSpace() > 255)
474 // Fast instruction selection doesn't support the special
480 //errs() << "Failing Opcode is: " << *Op1 << "\n";
482 case Instruction::Alloca: {
483 assert(false && "Alloca should have been handled earlier!");
488 if (const GlobalValue *GV = dyn_cast<GlobalValue>(Obj)) {
489 //errs() << "Failing GV is: " << GV << "\n";
494 // Try to get this in a register if nothing else has worked.
495 Reg = getRegForValue(Obj);
496 if (Reg == 0) return false;
498 // Since the offset may be too large for the load instruction
499 // get the reg+offset into a register.
500 // TODO: Verify the additions work, otherwise we'll need to add the
501 // offset instead of 0 to the instructions and do all sorts of operand
503 // TODO: Optimize this somewhat.
505 ARMCC::CondCodes Pred = ARMCC::AL;
506 unsigned PredReg = 0;
509 emitARMRegPlusImmediate(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
510 Reg, Reg, Offset, Pred, PredReg,
511 static_cast<const ARMBaseInstrInfo&>(TII));
513 assert(AFI->isThumb2Function());
514 emitT2RegPlusImmediate(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
515 Reg, Reg, Offset, Pred, PredReg,
516 static_cast<const ARMBaseInstrInfo&>(TII));
523 bool ARMFastISel::ARMLoadAlloca(const Instruction *I, EVT VT) {
524 Value *Op0 = I->getOperand(0);
526 // Verify it's an alloca.
527 if (const AllocaInst *AI = dyn_cast<AllocaInst>(Op0)) {
528 DenseMap<const AllocaInst*, int>::iterator SI =
529 FuncInfo.StaticAllocaMap.find(AI);
531 if (SI != FuncInfo.StaticAllocaMap.end()) {
532 TargetRegisterClass* RC = TLI.getRegClassFor(VT);
533 unsigned ResultReg = createResultReg(RC);
534 TII.loadRegFromStackSlot(*FuncInfo.MBB, *FuncInfo.InsertPt,
535 ResultReg, SI->second, RC,
536 TM.getRegisterInfo());
537 UpdateValueMap(I, ResultReg);
544 bool ARMFastISel::ARMEmitLoad(EVT VT, unsigned &ResultReg,
545 unsigned Reg, int Offset) {
547 assert(VT.isSimple() && "Non-simple types are invalid here!");
550 switch (VT.getSimpleVT().SimpleTy) {
552 assert(false && "Trying to emit for an unhandled type!");
555 Opc = isThumb ? ARM::tLDRH : ARM::LDRH;
559 Opc = isThumb ? ARM::tLDRB : ARM::LDRB;
563 Opc = isThumb ? ARM::tLDR : ARM::LDR;
567 ResultReg = createResultReg(TLI.getRegClassFor(VT));
569 // TODO: Fix the Addressing modes so that these can share some code.
570 // Since this is a Thumb1 load this will work in Thumb1 or 2 mode.
572 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
573 TII.get(Opc), ResultReg)
574 .addReg(Reg).addImm(Offset).addReg(0));
576 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
577 TII.get(Opc), ResultReg)
578 .addReg(Reg).addReg(0).addImm(Offset));
582 bool ARMFastISel::ARMStoreAlloca(const Instruction *I, unsigned SrcReg, EVT VT){
583 Value *Op1 = I->getOperand(1);
585 // Verify it's an alloca.
586 if (const AllocaInst *AI = dyn_cast<AllocaInst>(Op1)) {
587 DenseMap<const AllocaInst*, int>::iterator SI =
588 FuncInfo.StaticAllocaMap.find(AI);
590 if (SI != FuncInfo.StaticAllocaMap.end()) {
591 TargetRegisterClass* RC = TLI.getRegClassFor(VT);
592 assert(SrcReg != 0 && "Nothing to store!");
593 TII.storeRegToStackSlot(*FuncInfo.MBB, *FuncInfo.InsertPt,
594 SrcReg, true /*isKill*/, SI->second, RC,
595 TM.getRegisterInfo());
602 bool ARMFastISel::ARMEmitStore(EVT VT, unsigned SrcReg,
603 unsigned DstReg, int Offset) {
605 switch (VT.getSimpleVT().SimpleTy) {
606 default: return false;
608 case MVT::i8: StrOpc = isThumb ? ARM::tSTRB : ARM::STRB; break;
609 case MVT::i16: StrOpc = isThumb ? ARM::tSTRH : ARM::STRH; break;
610 case MVT::i32: StrOpc = isThumb ? ARM::tSTR : ARM::STR; break;
612 if (!Subtarget->hasVFP2()) return false;
616 if (!Subtarget->hasVFP2()) return false;
622 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
623 TII.get(StrOpc), SrcReg)
624 .addReg(DstReg).addImm(Offset).addReg(0));
626 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
627 TII.get(StrOpc), SrcReg)
628 .addReg(DstReg).addReg(0).addImm(Offset));
633 bool ARMFastISel::ARMSelectStore(const Instruction *I) {
634 Value *Op0 = I->getOperand(0);
637 // Yay type legalization
639 if (!isLoadTypeLegal(I->getOperand(0)->getType(), VT))
642 // Get the value to be stored into a register.
643 SrcReg = getRegForValue(Op0);
647 // If we're an alloca we know we have a frame index and can emit the store
649 if (ARMStoreAlloca(I, SrcReg, VT))
652 // Our register and offset with innocuous defaults.
656 // See if we can handle this as Reg + Offset
657 if (!ARMComputeRegOffset(I->getOperand(1), Reg, Offset))
660 if (!ARMEmitStore(VT, SrcReg, Reg, Offset /* 0 */)) return false;
665 bool ARMFastISel::ARMSelectLoad(const Instruction *I) {
666 // Verify we have a legal type before going any further.
668 if (!isLoadTypeLegal(I->getType(), VT))
671 // If we're an alloca we know we have a frame index and can emit the load
672 // directly in short order.
673 if (ARMLoadAlloca(I, VT))
676 // Our register and offset with innocuous defaults.
680 // See if we can handle this as Reg + Offset
681 if (!ARMComputeRegOffset(I->getOperand(0), Reg, Offset))
685 if (!ARMEmitLoad(VT, ResultReg, Reg, Offset /* 0 */)) return false;
687 UpdateValueMap(I, ResultReg);
691 bool ARMFastISel::ARMSelectBranch(const Instruction *I) {
692 const BranchInst *BI = cast<BranchInst>(I);
693 MachineBasicBlock *TBB = FuncInfo.MBBMap[BI->getSuccessor(0)];
694 MachineBasicBlock *FBB = FuncInfo.MBBMap[BI->getSuccessor(1)];
696 // Simple branch support.
697 unsigned CondReg = getRegForValue(BI->getCondition());
698 if (CondReg == 0) return false;
700 unsigned CmpOpc = isThumb ? ARM::t2CMPrr : ARM::CMPrr;
701 unsigned BrOpc = isThumb ? ARM::t2Bcc : ARM::Bcc;
702 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(CmpOpc))
703 .addReg(CondReg).addReg(CondReg));
704 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(BrOpc))
705 .addMBB(TBB).addImm(ARMCC::NE).addReg(ARM::CPSR);
706 FastEmitBranch(FBB, DL);
707 FuncInfo.MBB->addSuccessor(TBB);
711 bool ARMFastISel::ARMSelectCmp(const Instruction *I) {
712 const CmpInst *CI = cast<CmpInst>(I);
715 const Type *Ty = CI->getOperand(0)->getType();
716 if (!isTypeLegal(Ty, VT))
719 bool isFloat = (Ty->isDoubleTy() || Ty->isFloatTy());
720 if (isFloat && !Subtarget->hasVFP2())
724 switch (VT.getSimpleVT().SimpleTy) {
725 default: return false;
726 // TODO: Verify compares.
728 CmpOpc = ARM::VCMPES;
731 CmpOpc = ARM::VCMPED;
734 CmpOpc = isThumb ? ARM::t2CMPrr : ARM::CMPrr;
738 unsigned Arg1 = getRegForValue(CI->getOperand(0));
739 if (Arg1 == 0) return false;
741 unsigned Arg2 = getRegForValue(CI->getOperand(1));
742 if (Arg2 == 0) return false;
744 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(CmpOpc))
745 .addReg(Arg1).addReg(Arg2));
747 // For floating point we need to move the result to a register we can
748 // actually do something with.
750 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
751 TII.get(ARM::FMSTAT)));
753 // TODO: How to update the value map when there's no result reg?
757 bool ARMFastISel::ARMSelectFPExt(const Instruction *I) {
758 // Make sure we have VFP and that we're extending float to double.
759 if (!Subtarget->hasVFP2()) return false;
761 Value *V = I->getOperand(0);
762 if (!I->getType()->isDoubleTy() ||
763 !V->getType()->isFloatTy()) return false;
765 unsigned Op = getRegForValue(V);
766 if (Op == 0) return false;
768 unsigned Result = createResultReg(ARM::DPRRegisterClass);
770 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
771 TII.get(ARM::VCVTDS), Result)
773 UpdateValueMap(I, Result);
777 bool ARMFastISel::ARMSelectFPTrunc(const Instruction *I) {
778 // Make sure we have VFP and that we're truncating double to float.
779 if (!Subtarget->hasVFP2()) return false;
781 Value *V = I->getOperand(0);
782 if (!I->getType()->isFloatTy() ||
783 !V->getType()->isDoubleTy()) return false;
785 unsigned Op = getRegForValue(V);
786 if (Op == 0) return false;
788 unsigned Result = createResultReg(ARM::SPRRegisterClass);
790 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
791 TII.get(ARM::VCVTSD), Result)
793 UpdateValueMap(I, Result);
797 bool ARMFastISel::ARMSelectSIToFP(const Instruction *I) {
798 // Make sure we have VFP.
799 if (!Subtarget->hasVFP2()) return false;
802 const Type *Ty = I->getType();
803 if (!isTypeLegal(Ty, DstVT))
806 unsigned Op = getRegForValue(I->getOperand(0));
807 if (Op == 0) return false;
809 // The conversion routine works on fp-reg to fp-reg.
810 unsigned FP = ARMMoveToFPReg(DstVT, Op);
811 if (FP == 0) return false;
814 if (Ty->isFloatTy()) Opc = ARM::VSITOS;
815 else if (Ty->isDoubleTy()) Opc = ARM::VSITOD;
818 unsigned ResultReg = createResultReg(TLI.getRegClassFor(DstVT));
819 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc),
822 UpdateValueMap(I, ResultReg);
826 bool ARMFastISel::ARMSelectFPToSI(const Instruction *I) {
827 // Make sure we have VFP.
828 if (!Subtarget->hasVFP2()) return false;
831 const Type *RetTy = I->getType();
832 if (!isTypeLegal(RetTy, VT))
835 unsigned Op = getRegForValue(I->getOperand(0));
836 if (Op == 0) return false;
839 const Type *OpTy = I->getOperand(0)->getType();
840 if (OpTy->isFloatTy()) Opc = ARM::VTOSIZS;
841 else if (OpTy->isDoubleTy()) Opc = ARM::VTOSIZD;
843 EVT OpVT = TLI.getValueType(OpTy, true);
845 unsigned ResultReg = createResultReg(TLI.getRegClassFor(OpVT));
846 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc),
850 // This result needs to be in an integer register, but the conversion only
851 // takes place in fp-regs.
852 unsigned IntReg = ARMMoveToIntReg(VT, ResultReg);
853 if (IntReg == 0) return false;
855 UpdateValueMap(I, IntReg);
859 bool ARMFastISel::ARMSelectBinaryOp(const Instruction *I, unsigned ISDOpcode) {
860 EVT VT = TLI.getValueType(I->getType(), true);
862 // We can get here in the case when we want to use NEON for our fp
863 // operations, but can't figure out how to. Just use the vfp instructions
865 // FIXME: It'd be nice to use NEON instructions.
866 const Type *Ty = I->getType();
867 bool isFloat = (Ty->isDoubleTy() || Ty->isFloatTy());
868 if (isFloat && !Subtarget->hasVFP2())
871 unsigned Op1 = getRegForValue(I->getOperand(0));
872 if (Op1 == 0) return false;
874 unsigned Op2 = getRegForValue(I->getOperand(1));
875 if (Op2 == 0) return false;
878 bool is64bit = VT.getSimpleVT().SimpleTy == MVT::f64 ||
879 VT.getSimpleVT().SimpleTy == MVT::i64;
881 default: return false;
883 Opc = is64bit ? ARM::VADDD : ARM::VADDS;
886 Opc = is64bit ? ARM::VSUBD : ARM::VSUBS;
889 Opc = is64bit ? ARM::VMULD : ARM::VMULS;
892 unsigned ResultReg = createResultReg(TLI.getRegClassFor(VT));
893 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
894 TII.get(Opc), ResultReg)
895 .addReg(Op1).addReg(Op2));
896 UpdateValueMap(I, ResultReg);
900 // TODO: SoftFP support.
901 bool ARMFastISel::TargetSelectInstruction(const Instruction *I) {
902 // No Thumb-1 for now.
903 if (isThumb && !AFI->isThumb2Function()) return false;
905 switch (I->getOpcode()) {
906 case Instruction::Load:
907 return ARMSelectLoad(I);
908 case Instruction::Store:
909 return ARMSelectStore(I);
910 case Instruction::Br:
911 return ARMSelectBranch(I);
912 case Instruction::ICmp:
913 case Instruction::FCmp:
914 return ARMSelectCmp(I);
915 case Instruction::FPExt:
916 return ARMSelectFPExt(I);
917 case Instruction::FPTrunc:
918 return ARMSelectFPTrunc(I);
919 case Instruction::SIToFP:
920 return ARMSelectSIToFP(I);
921 case Instruction::FPToSI:
922 return ARMSelectFPToSI(I);
923 case Instruction::FAdd:
924 return ARMSelectBinaryOp(I, ISD::FADD);
925 case Instruction::FSub:
926 return ARMSelectBinaryOp(I, ISD::FSUB);
927 case Instruction::FMul:
928 return ARMSelectBinaryOp(I, ISD::FMUL);
935 llvm::FastISel *ARM::createFastISel(FunctionLoweringInfo &funcInfo) {
936 if (EnableARMFastISel) return new ARMFastISel(funcInfo);