1 //===-- ARMFastISel.cpp - ARM FastISel implementation ---------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the ARM-specific support for the FastISel class. Some
11 // of the target-specific code is generated by tablegen in the file
12 // ARMGenFastISel.inc, which is #included here.
14 //===----------------------------------------------------------------------===//
17 #include "ARMBaseRegisterInfo.h"
18 #include "ARMCallingConv.h"
19 #include "ARMConstantPoolValue.h"
20 #include "ARMISelLowering.h"
21 #include "ARMMachineFunctionInfo.h"
22 #include "ARMSubtarget.h"
23 #include "MCTargetDesc/ARMAddressingModes.h"
24 #include "llvm/ADT/STLExtras.h"
25 #include "llvm/CodeGen/Analysis.h"
26 #include "llvm/CodeGen/FastISel.h"
27 #include "llvm/CodeGen/FunctionLoweringInfo.h"
28 #include "llvm/CodeGen/MachineConstantPool.h"
29 #include "llvm/CodeGen/MachineFrameInfo.h"
30 #include "llvm/CodeGen/MachineInstrBuilder.h"
31 #include "llvm/CodeGen/MachineMemOperand.h"
32 #include "llvm/CodeGen/MachineModuleInfo.h"
33 #include "llvm/CodeGen/MachineRegisterInfo.h"
34 #include "llvm/IR/CallSite.h"
35 #include "llvm/IR/CallingConv.h"
36 #include "llvm/IR/DataLayout.h"
37 #include "llvm/IR/DerivedTypes.h"
38 #include "llvm/IR/GetElementPtrTypeIterator.h"
39 #include "llvm/IR/GlobalVariable.h"
40 #include "llvm/IR/Instructions.h"
41 #include "llvm/IR/IntrinsicInst.h"
42 #include "llvm/IR/Module.h"
43 #include "llvm/IR/Operator.h"
44 #include "llvm/Support/CommandLine.h"
45 #include "llvm/Support/ErrorHandling.h"
46 #include "llvm/Target/TargetInstrInfo.h"
47 #include "llvm/Target/TargetLowering.h"
48 #include "llvm/Target/TargetMachine.h"
49 #include "llvm/Target/TargetOptions.h"
54 // All possible address modes, plus some.
55 typedef struct Address {
68 // Innocuous defaults for our address.
70 : BaseType(RegBase), Offset(0) {
75 class ARMFastISel final : public FastISel {
77 /// Subtarget - Keep a pointer to the ARMSubtarget around so that we can
78 /// make the right decision when generating code for different targets.
79 const ARMSubtarget *Subtarget;
81 const TargetMachine &TM;
82 const TargetInstrInfo &TII;
83 const TargetLowering &TLI;
86 // Convenience variables to avoid some queries.
91 explicit ARMFastISel(FunctionLoweringInfo &funcInfo,
92 const TargetLibraryInfo *libInfo)
93 : FastISel(funcInfo, libInfo),
95 &static_cast<const ARMSubtarget &>(funcInfo.MF->getSubtarget())),
96 M(const_cast<Module &>(*funcInfo.Fn->getParent())),
97 TM(funcInfo.MF->getTarget()), TII(*Subtarget->getInstrInfo()),
98 TLI(*Subtarget->getTargetLowering()) {
99 AFI = funcInfo.MF->getInfo<ARMFunctionInfo>();
100 isThumb2 = AFI->isThumbFunction();
101 Context = &funcInfo.Fn->getContext();
104 // Code from FastISel.cpp.
106 unsigned fastEmitInst_r(unsigned MachineInstOpcode,
107 const TargetRegisterClass *RC,
108 unsigned Op0, bool Op0IsKill);
109 unsigned fastEmitInst_rr(unsigned MachineInstOpcode,
110 const TargetRegisterClass *RC,
111 unsigned Op0, bool Op0IsKill,
112 unsigned Op1, bool Op1IsKill);
113 unsigned fastEmitInst_rrr(unsigned MachineInstOpcode,
114 const TargetRegisterClass *RC,
115 unsigned Op0, bool Op0IsKill,
116 unsigned Op1, bool Op1IsKill,
117 unsigned Op2, bool Op2IsKill);
118 unsigned fastEmitInst_ri(unsigned MachineInstOpcode,
119 const TargetRegisterClass *RC,
120 unsigned Op0, bool Op0IsKill,
122 unsigned fastEmitInst_rri(unsigned MachineInstOpcode,
123 const TargetRegisterClass *RC,
124 unsigned Op0, bool Op0IsKill,
125 unsigned Op1, bool Op1IsKill,
127 unsigned fastEmitInst_i(unsigned MachineInstOpcode,
128 const TargetRegisterClass *RC,
131 // Backend specific FastISel code.
133 bool fastSelectInstruction(const Instruction *I) override;
134 unsigned fastMaterializeConstant(const Constant *C) override;
135 unsigned fastMaterializeAlloca(const AllocaInst *AI) override;
136 bool tryToFoldLoadIntoMI(MachineInstr *MI, unsigned OpNo,
137 const LoadInst *LI) override;
138 bool fastLowerArguments() override;
140 #include "ARMGenFastISel.inc"
142 // Instruction selection routines.
144 bool SelectLoad(const Instruction *I);
145 bool SelectStore(const Instruction *I);
146 bool SelectBranch(const Instruction *I);
147 bool SelectIndirectBr(const Instruction *I);
148 bool SelectCmp(const Instruction *I);
149 bool SelectFPExt(const Instruction *I);
150 bool SelectFPTrunc(const Instruction *I);
151 bool SelectBinaryIntOp(const Instruction *I, unsigned ISDOpcode);
152 bool SelectBinaryFPOp(const Instruction *I, unsigned ISDOpcode);
153 bool SelectIToFP(const Instruction *I, bool isSigned);
154 bool SelectFPToI(const Instruction *I, bool isSigned);
155 bool SelectDiv(const Instruction *I, bool isSigned);
156 bool SelectRem(const Instruction *I, bool isSigned);
157 bool SelectCall(const Instruction *I, const char *IntrMemName);
158 bool SelectIntrinsicCall(const IntrinsicInst &I);
159 bool SelectSelect(const Instruction *I);
160 bool SelectRet(const Instruction *I);
161 bool SelectTrunc(const Instruction *I);
162 bool SelectIntExt(const Instruction *I);
163 bool SelectShift(const Instruction *I, ARM_AM::ShiftOpc ShiftTy);
167 bool isTypeLegal(Type *Ty, MVT &VT);
168 bool isLoadTypeLegal(Type *Ty, MVT &VT);
169 bool ARMEmitCmp(const Value *Src1Value, const Value *Src2Value,
171 bool ARMEmitLoad(MVT VT, unsigned &ResultReg, Address &Addr,
172 unsigned Alignment = 0, bool isZExt = true,
173 bool allocReg = true);
174 bool ARMEmitStore(MVT VT, unsigned SrcReg, Address &Addr,
175 unsigned Alignment = 0);
176 bool ARMComputeAddress(const Value *Obj, Address &Addr);
177 void ARMSimplifyAddress(Address &Addr, MVT VT, bool useAM3);
178 bool ARMIsMemCpySmall(uint64_t Len);
179 bool ARMTryEmitSmallMemCpy(Address Dest, Address Src, uint64_t Len,
181 unsigned ARMEmitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, bool isZExt);
182 unsigned ARMMaterializeFP(const ConstantFP *CFP, MVT VT);
183 unsigned ARMMaterializeInt(const Constant *C, MVT VT);
184 unsigned ARMMaterializeGV(const GlobalValue *GV, MVT VT);
185 unsigned ARMMoveToFPReg(MVT VT, unsigned SrcReg);
186 unsigned ARMMoveToIntReg(MVT VT, unsigned SrcReg);
187 unsigned ARMSelectCallOp(bool UseReg);
188 unsigned ARMLowerPICELF(const GlobalValue *GV, unsigned Align, MVT VT);
190 const TargetLowering *getTargetLowering() { return &TLI; }
192 // Call handling routines.
194 CCAssignFn *CCAssignFnForCall(CallingConv::ID CC,
197 bool ProcessCallArgs(SmallVectorImpl<Value*> &Args,
198 SmallVectorImpl<unsigned> &ArgRegs,
199 SmallVectorImpl<MVT> &ArgVTs,
200 SmallVectorImpl<ISD::ArgFlagsTy> &ArgFlags,
201 SmallVectorImpl<unsigned> &RegArgs,
205 unsigned getLibcallReg(const Twine &Name);
206 bool FinishCall(MVT RetVT, SmallVectorImpl<unsigned> &UsedRegs,
207 const Instruction *I, CallingConv::ID CC,
208 unsigned &NumBytes, bool isVarArg);
209 bool ARMEmitLibcall(const Instruction *I, RTLIB::Libcall Call);
211 // OptionalDef handling routines.
213 bool isARMNEONPred(const MachineInstr *MI);
214 bool DefinesOptionalPredicate(MachineInstr *MI, bool *CPSR);
215 const MachineInstrBuilder &AddOptionalDefs(const MachineInstrBuilder &MIB);
216 void AddLoadStoreOperands(MVT VT, Address &Addr,
217 const MachineInstrBuilder &MIB,
218 unsigned Flags, bool useAM3);
221 } // end anonymous namespace
223 #include "ARMGenCallingConv.inc"
225 // DefinesOptionalPredicate - This is different from DefinesPredicate in that
226 // we don't care about implicit defs here, just places we'll need to add a
227 // default CCReg argument. Sets CPSR if we're setting CPSR instead of CCR.
228 bool ARMFastISel::DefinesOptionalPredicate(MachineInstr *MI, bool *CPSR) {
229 if (!MI->hasOptionalDef())
232 // Look to see if our OptionalDef is defining CPSR or CCR.
233 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
234 const MachineOperand &MO = MI->getOperand(i);
235 if (!MO.isReg() || !MO.isDef()) continue;
236 if (MO.getReg() == ARM::CPSR)
242 bool ARMFastISel::isARMNEONPred(const MachineInstr *MI) {
243 const MCInstrDesc &MCID = MI->getDesc();
245 // If we're a thumb2 or not NEON function we'll be handled via isPredicable.
246 if ((MCID.TSFlags & ARMII::DomainMask) != ARMII::DomainNEON ||
247 AFI->isThumb2Function())
248 return MI->isPredicable();
250 for (unsigned i = 0, e = MCID.getNumOperands(); i != e; ++i)
251 if (MCID.OpInfo[i].isPredicate())
257 // If the machine is predicable go ahead and add the predicate operands, if
258 // it needs default CC operands add those.
259 // TODO: If we want to support thumb1 then we'll need to deal with optional
260 // CPSR defs that need to be added before the remaining operands. See s_cc_out
261 // for descriptions why.
262 const MachineInstrBuilder &
263 ARMFastISel::AddOptionalDefs(const MachineInstrBuilder &MIB) {
264 MachineInstr *MI = &*MIB;
266 // Do we use a predicate? or...
267 // Are we NEON in ARM mode and have a predicate operand? If so, I know
268 // we're not predicable but add it anyways.
269 if (isARMNEONPred(MI))
272 // Do we optionally set a predicate? Preds is size > 0 iff the predicate
273 // defines CPSR. All other OptionalDefines in ARM are the CCR register.
275 if (DefinesOptionalPredicate(MI, &CPSR)) {
284 unsigned ARMFastISel::fastEmitInst_r(unsigned MachineInstOpcode,
285 const TargetRegisterClass *RC,
286 unsigned Op0, bool Op0IsKill) {
287 unsigned ResultReg = createResultReg(RC);
288 const MCInstrDesc &II = TII.get(MachineInstOpcode);
290 // Make sure the input operand is sufficiently constrained to be legal
291 // for this instruction.
292 Op0 = constrainOperandRegClass(II, Op0, 1);
293 if (II.getNumDefs() >= 1) {
294 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II,
295 ResultReg).addReg(Op0, Op0IsKill * RegState::Kill));
297 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II)
298 .addReg(Op0, Op0IsKill * RegState::Kill));
299 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
300 TII.get(TargetOpcode::COPY), ResultReg)
301 .addReg(II.ImplicitDefs[0]));
306 unsigned ARMFastISel::fastEmitInst_rr(unsigned MachineInstOpcode,
307 const TargetRegisterClass *RC,
308 unsigned Op0, bool Op0IsKill,
309 unsigned Op1, bool Op1IsKill) {
310 unsigned ResultReg = createResultReg(RC);
311 const MCInstrDesc &II = TII.get(MachineInstOpcode);
313 // Make sure the input operands are sufficiently constrained to be legal
314 // for this instruction.
315 Op0 = constrainOperandRegClass(II, Op0, 1);
316 Op1 = constrainOperandRegClass(II, Op1, 2);
318 if (II.getNumDefs() >= 1) {
320 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg)
321 .addReg(Op0, Op0IsKill * RegState::Kill)
322 .addReg(Op1, Op1IsKill * RegState::Kill));
324 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II)
325 .addReg(Op0, Op0IsKill * RegState::Kill)
326 .addReg(Op1, Op1IsKill * RegState::Kill));
327 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
328 TII.get(TargetOpcode::COPY), ResultReg)
329 .addReg(II.ImplicitDefs[0]));
334 unsigned ARMFastISel::fastEmitInst_rrr(unsigned MachineInstOpcode,
335 const TargetRegisterClass *RC,
336 unsigned Op0, bool Op0IsKill,
337 unsigned Op1, bool Op1IsKill,
338 unsigned Op2, bool Op2IsKill) {
339 unsigned ResultReg = createResultReg(RC);
340 const MCInstrDesc &II = TII.get(MachineInstOpcode);
342 // Make sure the input operands are sufficiently constrained to be legal
343 // for this instruction.
344 Op0 = constrainOperandRegClass(II, Op0, 1);
345 Op1 = constrainOperandRegClass(II, Op1, 2);
346 Op2 = constrainOperandRegClass(II, Op1, 3);
348 if (II.getNumDefs() >= 1) {
350 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg)
351 .addReg(Op0, Op0IsKill * RegState::Kill)
352 .addReg(Op1, Op1IsKill * RegState::Kill)
353 .addReg(Op2, Op2IsKill * RegState::Kill));
355 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II)
356 .addReg(Op0, Op0IsKill * RegState::Kill)
357 .addReg(Op1, Op1IsKill * RegState::Kill)
358 .addReg(Op2, Op2IsKill * RegState::Kill));
359 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
360 TII.get(TargetOpcode::COPY), ResultReg)
361 .addReg(II.ImplicitDefs[0]));
366 unsigned ARMFastISel::fastEmitInst_ri(unsigned MachineInstOpcode,
367 const TargetRegisterClass *RC,
368 unsigned Op0, bool Op0IsKill,
370 unsigned ResultReg = createResultReg(RC);
371 const MCInstrDesc &II = TII.get(MachineInstOpcode);
373 // Make sure the input operand is sufficiently constrained to be legal
374 // for this instruction.
375 Op0 = constrainOperandRegClass(II, Op0, 1);
376 if (II.getNumDefs() >= 1) {
378 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg)
379 .addReg(Op0, Op0IsKill * RegState::Kill)
382 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II)
383 .addReg(Op0, Op0IsKill * RegState::Kill)
385 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
386 TII.get(TargetOpcode::COPY), ResultReg)
387 .addReg(II.ImplicitDefs[0]));
392 unsigned ARMFastISel::fastEmitInst_rri(unsigned MachineInstOpcode,
393 const TargetRegisterClass *RC,
394 unsigned Op0, bool Op0IsKill,
395 unsigned Op1, bool Op1IsKill,
397 unsigned ResultReg = createResultReg(RC);
398 const MCInstrDesc &II = TII.get(MachineInstOpcode);
400 // Make sure the input operands are sufficiently constrained to be legal
401 // for this instruction.
402 Op0 = constrainOperandRegClass(II, Op0, 1);
403 Op1 = constrainOperandRegClass(II, Op1, 2);
404 if (II.getNumDefs() >= 1) {
406 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg)
407 .addReg(Op0, Op0IsKill * RegState::Kill)
408 .addReg(Op1, Op1IsKill * RegState::Kill)
411 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II)
412 .addReg(Op0, Op0IsKill * RegState::Kill)
413 .addReg(Op1, Op1IsKill * RegState::Kill)
415 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
416 TII.get(TargetOpcode::COPY), ResultReg)
417 .addReg(II.ImplicitDefs[0]));
422 unsigned ARMFastISel::fastEmitInst_i(unsigned MachineInstOpcode,
423 const TargetRegisterClass *RC,
425 unsigned ResultReg = createResultReg(RC);
426 const MCInstrDesc &II = TII.get(MachineInstOpcode);
428 if (II.getNumDefs() >= 1) {
429 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II,
430 ResultReg).addImm(Imm));
432 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II)
434 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
435 TII.get(TargetOpcode::COPY), ResultReg)
436 .addReg(II.ImplicitDefs[0]));
441 // TODO: Don't worry about 64-bit now, but when this is fixed remove the
442 // checks from the various callers.
443 unsigned ARMFastISel::ARMMoveToFPReg(MVT VT, unsigned SrcReg) {
444 if (VT == MVT::f64) return 0;
446 unsigned MoveReg = createResultReg(TLI.getRegClassFor(VT));
447 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
448 TII.get(ARM::VMOVSR), MoveReg)
453 unsigned ARMFastISel::ARMMoveToIntReg(MVT VT, unsigned SrcReg) {
454 if (VT == MVT::i64) return 0;
456 unsigned MoveReg = createResultReg(TLI.getRegClassFor(VT));
457 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
458 TII.get(ARM::VMOVRS), MoveReg)
463 // For double width floating point we need to materialize two constants
464 // (the high and the low) into integer registers then use a move to get
465 // the combined constant into an FP reg.
466 unsigned ARMFastISel::ARMMaterializeFP(const ConstantFP *CFP, MVT VT) {
467 const APFloat Val = CFP->getValueAPF();
468 bool is64bit = VT == MVT::f64;
470 // This checks to see if we can use VFP3 instructions to materialize
471 // a constant, otherwise we have to go through the constant pool.
472 if (TLI.isFPImmLegal(Val, VT)) {
476 Imm = ARM_AM::getFP64Imm(Val);
479 Imm = ARM_AM::getFP32Imm(Val);
482 unsigned DestReg = createResultReg(TLI.getRegClassFor(VT));
483 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
484 TII.get(Opc), DestReg).addImm(Imm));
488 // Require VFP2 for loading fp constants.
489 if (!Subtarget->hasVFP2()) return false;
491 // MachineConstantPool wants an explicit alignment.
492 unsigned Align = DL.getPrefTypeAlignment(CFP->getType());
494 // TODO: Figure out if this is correct.
495 Align = DL.getTypeAllocSize(CFP->getType());
497 unsigned Idx = MCP.getConstantPoolIndex(cast<Constant>(CFP), Align);
498 unsigned DestReg = createResultReg(TLI.getRegClassFor(VT));
499 unsigned Opc = is64bit ? ARM::VLDRD : ARM::VLDRS;
501 // The extra reg is for addrmode5.
503 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), DestReg)
504 .addConstantPoolIndex(Idx)
509 unsigned ARMFastISel::ARMMaterializeInt(const Constant *C, MVT VT) {
511 if (VT != MVT::i32 && VT != MVT::i16 && VT != MVT::i8 && VT != MVT::i1)
514 // If we can do this in a single instruction without a constant pool entry
516 const ConstantInt *CI = cast<ConstantInt>(C);
517 if (Subtarget->hasV6T2Ops() && isUInt<16>(CI->getZExtValue())) {
518 unsigned Opc = isThumb2 ? ARM::t2MOVi16 : ARM::MOVi16;
519 const TargetRegisterClass *RC = isThumb2 ? &ARM::rGPRRegClass :
521 unsigned ImmReg = createResultReg(RC);
522 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
523 TII.get(Opc), ImmReg)
524 .addImm(CI->getZExtValue()));
528 // Use MVN to emit negative constants.
529 if (VT == MVT::i32 && Subtarget->hasV6T2Ops() && CI->isNegative()) {
530 unsigned Imm = (unsigned)~(CI->getSExtValue());
531 bool UseImm = isThumb2 ? (ARM_AM::getT2SOImmVal(Imm) != -1) :
532 (ARM_AM::getSOImmVal(Imm) != -1);
534 unsigned Opc = isThumb2 ? ARM::t2MVNi : ARM::MVNi;
535 const TargetRegisterClass *RC = isThumb2 ? &ARM::rGPRRegClass :
537 unsigned ImmReg = createResultReg(RC);
538 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
539 TII.get(Opc), ImmReg)
545 unsigned ResultReg = 0;
546 if (Subtarget->useMovt(*FuncInfo.MF))
547 ResultReg = fastEmit_i(VT, VT, ISD::Constant, CI->getZExtValue());
552 // Load from constant pool. For now 32-bit only.
556 // MachineConstantPool wants an explicit alignment.
557 unsigned Align = DL.getPrefTypeAlignment(C->getType());
559 // TODO: Figure out if this is correct.
560 Align = DL.getTypeAllocSize(C->getType());
562 unsigned Idx = MCP.getConstantPoolIndex(C, Align);
563 ResultReg = createResultReg(TLI.getRegClassFor(VT));
565 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
566 TII.get(ARM::t2LDRpci), ResultReg)
567 .addConstantPoolIndex(Idx));
569 // The extra immediate is for addrmode2.
570 ResultReg = constrainOperandRegClass(TII.get(ARM::LDRcp), ResultReg, 0);
571 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
572 TII.get(ARM::LDRcp), ResultReg)
573 .addConstantPoolIndex(Idx)
579 unsigned ARMFastISel::ARMMaterializeGV(const GlobalValue *GV, MVT VT) {
580 // For now 32-bit only.
581 if (VT != MVT::i32) return 0;
583 Reloc::Model RelocM = TM.getRelocationModel();
584 bool IsIndirect = Subtarget->GVIsIndirectSymbol(GV, RelocM);
585 const TargetRegisterClass *RC = isThumb2 ? &ARM::rGPRRegClass
587 unsigned DestReg = createResultReg(RC);
589 // FastISel TLS support on non-MachO is broken, punt to SelectionDAG.
590 const GlobalVariable *GVar = dyn_cast<GlobalVariable>(GV);
591 bool IsThreadLocal = GVar && GVar->isThreadLocal();
592 if (!Subtarget->isTargetMachO() && IsThreadLocal) return 0;
594 // Use movw+movt when possible, it avoids constant pool entries.
595 // Non-darwin targets only support static movt relocations in FastISel.
596 if (Subtarget->useMovt(*FuncInfo.MF) &&
597 (Subtarget->isTargetMachO() || RelocM == Reloc::Static)) {
599 unsigned char TF = 0;
600 if (Subtarget->isTargetMachO())
601 TF = ARMII::MO_NONLAZY;
605 Opc = isThumb2 ? ARM::t2MOV_ga_pcrel : ARM::MOV_ga_pcrel;
608 Opc = isThumb2 ? ARM::t2MOVi32imm : ARM::MOVi32imm;
611 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
612 TII.get(Opc), DestReg).addGlobalAddress(GV, 0, TF));
614 // MachineConstantPool wants an explicit alignment.
615 unsigned Align = DL.getPrefTypeAlignment(GV->getType());
617 // TODO: Figure out if this is correct.
618 Align = DL.getTypeAllocSize(GV->getType());
621 if (Subtarget->isTargetELF() && RelocM == Reloc::PIC_)
622 return ARMLowerPICELF(GV, Align, VT);
625 unsigned PCAdj = (RelocM != Reloc::PIC_) ? 0 :
626 (Subtarget->isThumb() ? 4 : 8);
627 unsigned Id = AFI->createPICLabelUId();
628 ARMConstantPoolValue *CPV = ARMConstantPoolConstant::Create(GV, Id,
631 unsigned Idx = MCP.getConstantPoolIndex(CPV, Align);
634 MachineInstrBuilder MIB;
636 unsigned Opc = (RelocM!=Reloc::PIC_) ? ARM::t2LDRpci : ARM::t2LDRpci_pic;
637 MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc),
638 DestReg).addConstantPoolIndex(Idx);
639 if (RelocM == Reloc::PIC_)
641 AddOptionalDefs(MIB);
643 // The extra immediate is for addrmode2.
644 DestReg = constrainOperandRegClass(TII.get(ARM::LDRcp), DestReg, 0);
645 MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
646 TII.get(ARM::LDRcp), DestReg)
647 .addConstantPoolIndex(Idx)
649 AddOptionalDefs(MIB);
651 if (RelocM == Reloc::PIC_) {
652 unsigned Opc = IsIndirect ? ARM::PICLDR : ARM::PICADD;
653 unsigned NewDestReg = createResultReg(TLI.getRegClassFor(VT));
655 MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt,
656 DbgLoc, TII.get(Opc), NewDestReg)
659 AddOptionalDefs(MIB);
666 MachineInstrBuilder MIB;
667 unsigned NewDestReg = createResultReg(TLI.getRegClassFor(VT));
669 MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
670 TII.get(ARM::t2LDRi12), NewDestReg)
674 MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
675 TII.get(ARM::LDRi12), NewDestReg)
678 DestReg = NewDestReg;
679 AddOptionalDefs(MIB);
685 unsigned ARMFastISel::fastMaterializeConstant(const Constant *C) {
686 EVT CEVT = TLI.getValueType(DL, C->getType(), true);
688 // Only handle simple types.
689 if (!CEVT.isSimple()) return 0;
690 MVT VT = CEVT.getSimpleVT();
692 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(C))
693 return ARMMaterializeFP(CFP, VT);
694 else if (const GlobalValue *GV = dyn_cast<GlobalValue>(C))
695 return ARMMaterializeGV(GV, VT);
696 else if (isa<ConstantInt>(C))
697 return ARMMaterializeInt(C, VT);
702 // TODO: unsigned ARMFastISel::TargetMaterializeFloatZero(const ConstantFP *CF);
704 unsigned ARMFastISel::fastMaterializeAlloca(const AllocaInst *AI) {
705 // Don't handle dynamic allocas.
706 if (!FuncInfo.StaticAllocaMap.count(AI)) return 0;
709 if (!isLoadTypeLegal(AI->getType(), VT)) return 0;
711 DenseMap<const AllocaInst*, int>::iterator SI =
712 FuncInfo.StaticAllocaMap.find(AI);
714 // This will get lowered later into the correct offsets and registers
715 // via rewriteXFrameIndex.
716 if (SI != FuncInfo.StaticAllocaMap.end()) {
717 unsigned Opc = isThumb2 ? ARM::t2ADDri : ARM::ADDri;
718 const TargetRegisterClass* RC = TLI.getRegClassFor(VT);
719 unsigned ResultReg = createResultReg(RC);
720 ResultReg = constrainOperandRegClass(TII.get(Opc), ResultReg, 0);
722 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
723 TII.get(Opc), ResultReg)
724 .addFrameIndex(SI->second)
732 bool ARMFastISel::isTypeLegal(Type *Ty, MVT &VT) {
733 EVT evt = TLI.getValueType(DL, Ty, true);
735 // Only handle simple types.
736 if (evt == MVT::Other || !evt.isSimple()) return false;
737 VT = evt.getSimpleVT();
739 // Handle all legal types, i.e. a register that will directly hold this
741 return TLI.isTypeLegal(VT);
744 bool ARMFastISel::isLoadTypeLegal(Type *Ty, MVT &VT) {
745 if (isTypeLegal(Ty, VT)) return true;
747 // If this is a type than can be sign or zero-extended to a basic operation
748 // go ahead and accept it now.
749 if (VT == MVT::i1 || VT == MVT::i8 || VT == MVT::i16)
755 // Computes the address to get to an object.
756 bool ARMFastISel::ARMComputeAddress(const Value *Obj, Address &Addr) {
757 // Some boilerplate from the X86 FastISel.
758 const User *U = nullptr;
759 unsigned Opcode = Instruction::UserOp1;
760 if (const Instruction *I = dyn_cast<Instruction>(Obj)) {
761 // Don't walk into other basic blocks unless the object is an alloca from
762 // another block, otherwise it may not have a virtual register assigned.
763 if (FuncInfo.StaticAllocaMap.count(static_cast<const AllocaInst *>(Obj)) ||
764 FuncInfo.MBBMap[I->getParent()] == FuncInfo.MBB) {
765 Opcode = I->getOpcode();
768 } else if (const ConstantExpr *C = dyn_cast<ConstantExpr>(Obj)) {
769 Opcode = C->getOpcode();
773 if (PointerType *Ty = dyn_cast<PointerType>(Obj->getType()))
774 if (Ty->getAddressSpace() > 255)
775 // Fast instruction selection doesn't support the special
782 case Instruction::BitCast:
783 // Look through bitcasts.
784 return ARMComputeAddress(U->getOperand(0), Addr);
785 case Instruction::IntToPtr:
786 // Look past no-op inttoptrs.
787 if (TLI.getValueType(DL, U->getOperand(0)->getType()) ==
788 TLI.getPointerTy(DL))
789 return ARMComputeAddress(U->getOperand(0), Addr);
791 case Instruction::PtrToInt:
792 // Look past no-op ptrtoints.
793 if (TLI.getValueType(DL, U->getType()) == TLI.getPointerTy(DL))
794 return ARMComputeAddress(U->getOperand(0), Addr);
796 case Instruction::GetElementPtr: {
797 Address SavedAddr = Addr;
798 int TmpOffset = Addr.Offset;
800 // Iterate through the GEP folding the constants into offsets where
802 gep_type_iterator GTI = gep_type_begin(U);
803 for (User::const_op_iterator i = U->op_begin() + 1, e = U->op_end();
804 i != e; ++i, ++GTI) {
805 const Value *Op = *i;
806 if (StructType *STy = dyn_cast<StructType>(*GTI)) {
807 const StructLayout *SL = DL.getStructLayout(STy);
808 unsigned Idx = cast<ConstantInt>(Op)->getZExtValue();
809 TmpOffset += SL->getElementOffset(Idx);
811 uint64_t S = DL.getTypeAllocSize(GTI.getIndexedType());
813 if (const ConstantInt *CI = dyn_cast<ConstantInt>(Op)) {
814 // Constant-offset addressing.
815 TmpOffset += CI->getSExtValue() * S;
818 if (canFoldAddIntoGEP(U, Op)) {
819 // A compatible add with a constant operand. Fold the constant.
821 cast<ConstantInt>(cast<AddOperator>(Op)->getOperand(1));
822 TmpOffset += CI->getSExtValue() * S;
823 // Iterate on the other operand.
824 Op = cast<AddOperator>(Op)->getOperand(0);
828 goto unsupported_gep;
833 // Try to grab the base operand now.
834 Addr.Offset = TmpOffset;
835 if (ARMComputeAddress(U->getOperand(0), Addr)) return true;
837 // We failed, restore everything and try the other options.
843 case Instruction::Alloca: {
844 const AllocaInst *AI = cast<AllocaInst>(Obj);
845 DenseMap<const AllocaInst*, int>::iterator SI =
846 FuncInfo.StaticAllocaMap.find(AI);
847 if (SI != FuncInfo.StaticAllocaMap.end()) {
848 Addr.BaseType = Address::FrameIndexBase;
849 Addr.Base.FI = SI->second;
856 // Try to get this in a register if nothing else has worked.
857 if (Addr.Base.Reg == 0) Addr.Base.Reg = getRegForValue(Obj);
858 return Addr.Base.Reg != 0;
861 void ARMFastISel::ARMSimplifyAddress(Address &Addr, MVT VT, bool useAM3) {
862 bool needsLowering = false;
863 switch (VT.SimpleTy) {
864 default: llvm_unreachable("Unhandled load/store type!");
870 // Integer loads/stores handle 12-bit offsets.
871 needsLowering = ((Addr.Offset & 0xfff) != Addr.Offset);
872 // Handle negative offsets.
873 if (needsLowering && isThumb2)
874 needsLowering = !(Subtarget->hasV6T2Ops() && Addr.Offset < 0 &&
877 // ARM halfword load/stores and signed byte loads use +/-imm8 offsets.
878 needsLowering = (Addr.Offset > 255 || Addr.Offset < -255);
883 // Floating point operands handle 8-bit offsets.
884 needsLowering = ((Addr.Offset & 0xff) != Addr.Offset);
888 // If this is a stack pointer and the offset needs to be simplified then
889 // put the alloca address into a register, set the base type back to
890 // register and continue. This should almost never happen.
891 if (needsLowering && Addr.BaseType == Address::FrameIndexBase) {
892 const TargetRegisterClass *RC = isThumb2 ? &ARM::tGPRRegClass
894 unsigned ResultReg = createResultReg(RC);
895 unsigned Opc = isThumb2 ? ARM::t2ADDri : ARM::ADDri;
896 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
897 TII.get(Opc), ResultReg)
898 .addFrameIndex(Addr.Base.FI)
900 Addr.Base.Reg = ResultReg;
901 Addr.BaseType = Address::RegBase;
904 // Since the offset is too large for the load/store instruction
905 // get the reg+offset into a register.
907 Addr.Base.Reg = fastEmit_ri_(MVT::i32, ISD::ADD, Addr.Base.Reg,
908 /*Op0IsKill*/false, Addr.Offset, MVT::i32);
913 void ARMFastISel::AddLoadStoreOperands(MVT VT, Address &Addr,
914 const MachineInstrBuilder &MIB,
915 unsigned Flags, bool useAM3) {
916 // addrmode5 output depends on the selection dag addressing dividing the
917 // offset by 4 that it then later multiplies. Do this here as well.
918 if (VT.SimpleTy == MVT::f32 || VT.SimpleTy == MVT::f64)
921 // Frame base works a bit differently. Handle it separately.
922 if (Addr.BaseType == Address::FrameIndexBase) {
923 int FI = Addr.Base.FI;
924 int Offset = Addr.Offset;
925 MachineMemOperand *MMO =
926 FuncInfo.MF->getMachineMemOperand(
927 MachinePointerInfo::getFixedStack(FI, Offset),
929 MFI.getObjectSize(FI),
930 MFI.getObjectAlignment(FI));
931 // Now add the rest of the operands.
932 MIB.addFrameIndex(FI);
934 // ARM halfword load/stores and signed byte loads need an additional
937 signed Imm = (Addr.Offset < 0) ? (0x100 | -Addr.Offset) : Addr.Offset;
941 MIB.addImm(Addr.Offset);
943 MIB.addMemOperand(MMO);
945 // Now add the rest of the operands.
946 MIB.addReg(Addr.Base.Reg);
948 // ARM halfword load/stores and signed byte loads need an additional
951 signed Imm = (Addr.Offset < 0) ? (0x100 | -Addr.Offset) : Addr.Offset;
955 MIB.addImm(Addr.Offset);
958 AddOptionalDefs(MIB);
961 bool ARMFastISel::ARMEmitLoad(MVT VT, unsigned &ResultReg, Address &Addr,
962 unsigned Alignment, bool isZExt, bool allocReg) {
965 bool needVMOV = false;
966 const TargetRegisterClass *RC;
967 switch (VT.SimpleTy) {
968 // This is mostly going to be Neon/vector support.
969 default: return false;
973 if (Addr.Offset < 0 && Addr.Offset > -256 && Subtarget->hasV6T2Ops())
974 Opc = isZExt ? ARM::t2LDRBi8 : ARM::t2LDRSBi8;
976 Opc = isZExt ? ARM::t2LDRBi12 : ARM::t2LDRSBi12;
985 RC = isThumb2 ? &ARM::rGPRRegClass : &ARM::GPRnopcRegClass;
988 if (Alignment && Alignment < 2 && !Subtarget->allowsUnalignedMem())
992 if (Addr.Offset < 0 && Addr.Offset > -256 && Subtarget->hasV6T2Ops())
993 Opc = isZExt ? ARM::t2LDRHi8 : ARM::t2LDRSHi8;
995 Opc = isZExt ? ARM::t2LDRHi12 : ARM::t2LDRSHi12;
997 Opc = isZExt ? ARM::LDRH : ARM::LDRSH;
1000 RC = isThumb2 ? &ARM::rGPRRegClass : &ARM::GPRnopcRegClass;
1003 if (Alignment && Alignment < 4 && !Subtarget->allowsUnalignedMem())
1007 if (Addr.Offset < 0 && Addr.Offset > -256 && Subtarget->hasV6T2Ops())
1010 Opc = ARM::t2LDRi12;
1014 RC = isThumb2 ? &ARM::rGPRRegClass : &ARM::GPRnopcRegClass;
1017 if (!Subtarget->hasVFP2()) return false;
1018 // Unaligned loads need special handling. Floats require word-alignment.
1019 if (Alignment && Alignment < 4) {
1022 Opc = isThumb2 ? ARM::t2LDRi12 : ARM::LDRi12;
1023 RC = isThumb2 ? &ARM::rGPRRegClass : &ARM::GPRnopcRegClass;
1026 RC = TLI.getRegClassFor(VT);
1030 if (!Subtarget->hasVFP2()) return false;
1031 // FIXME: Unaligned loads need special handling. Doublewords require
1033 if (Alignment && Alignment < 4)
1037 RC = TLI.getRegClassFor(VT);
1040 // Simplify this down to something we can handle.
1041 ARMSimplifyAddress(Addr, VT, useAM3);
1043 // Create the base instruction, then add the operands.
1045 ResultReg = createResultReg(RC);
1046 assert (ResultReg > 255 && "Expected an allocated virtual register.");
1047 MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1048 TII.get(Opc), ResultReg);
1049 AddLoadStoreOperands(VT, Addr, MIB, MachineMemOperand::MOLoad, useAM3);
1051 // If we had an unaligned load of a float we've converted it to an regular
1052 // load. Now we must move from the GRP to the FP register.
1054 unsigned MoveReg = createResultReg(TLI.getRegClassFor(MVT::f32));
1055 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1056 TII.get(ARM::VMOVSR), MoveReg)
1057 .addReg(ResultReg));
1058 ResultReg = MoveReg;
1063 bool ARMFastISel::SelectLoad(const Instruction *I) {
1064 // Atomic loads need special handling.
1065 if (cast<LoadInst>(I)->isAtomic())
1068 // Verify we have a legal type before going any further.
1070 if (!isLoadTypeLegal(I->getType(), VT))
1073 // See if we can handle this address.
1075 if (!ARMComputeAddress(I->getOperand(0), Addr)) return false;
1078 if (!ARMEmitLoad(VT, ResultReg, Addr, cast<LoadInst>(I)->getAlignment()))
1080 updateValueMap(I, ResultReg);
1084 bool ARMFastISel::ARMEmitStore(MVT VT, unsigned SrcReg, Address &Addr,
1085 unsigned Alignment) {
1087 bool useAM3 = false;
1088 switch (VT.SimpleTy) {
1089 // This is mostly going to be Neon/vector support.
1090 default: return false;
1092 unsigned Res = createResultReg(isThumb2 ? &ARM::tGPRRegClass
1093 : &ARM::GPRRegClass);
1094 unsigned Opc = isThumb2 ? ARM::t2ANDri : ARM::ANDri;
1095 SrcReg = constrainOperandRegClass(TII.get(Opc), SrcReg, 1);
1096 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1098 .addReg(SrcReg).addImm(1));
1100 } // Fallthrough here.
1103 if (Addr.Offset < 0 && Addr.Offset > -256 && Subtarget->hasV6T2Ops())
1104 StrOpc = ARM::t2STRBi8;
1106 StrOpc = ARM::t2STRBi12;
1108 StrOpc = ARM::STRBi12;
1112 if (Alignment && Alignment < 2 && !Subtarget->allowsUnalignedMem())
1116 if (Addr.Offset < 0 && Addr.Offset > -256 && Subtarget->hasV6T2Ops())
1117 StrOpc = ARM::t2STRHi8;
1119 StrOpc = ARM::t2STRHi12;
1126 if (Alignment && Alignment < 4 && !Subtarget->allowsUnalignedMem())
1130 if (Addr.Offset < 0 && Addr.Offset > -256 && Subtarget->hasV6T2Ops())
1131 StrOpc = ARM::t2STRi8;
1133 StrOpc = ARM::t2STRi12;
1135 StrOpc = ARM::STRi12;
1139 if (!Subtarget->hasVFP2()) return false;
1140 // Unaligned stores need special handling. Floats require word-alignment.
1141 if (Alignment && Alignment < 4) {
1142 unsigned MoveReg = createResultReg(TLI.getRegClassFor(MVT::i32));
1143 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1144 TII.get(ARM::VMOVRS), MoveReg)
1148 StrOpc = isThumb2 ? ARM::t2STRi12 : ARM::STRi12;
1150 StrOpc = ARM::VSTRS;
1154 if (!Subtarget->hasVFP2()) return false;
1155 // FIXME: Unaligned stores need special handling. Doublewords require
1157 if (Alignment && Alignment < 4)
1160 StrOpc = ARM::VSTRD;
1163 // Simplify this down to something we can handle.
1164 ARMSimplifyAddress(Addr, VT, useAM3);
1166 // Create the base instruction, then add the operands.
1167 SrcReg = constrainOperandRegClass(TII.get(StrOpc), SrcReg, 0);
1168 MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1171 AddLoadStoreOperands(VT, Addr, MIB, MachineMemOperand::MOStore, useAM3);
1175 bool ARMFastISel::SelectStore(const Instruction *I) {
1176 Value *Op0 = I->getOperand(0);
1177 unsigned SrcReg = 0;
1179 // Atomic stores need special handling.
1180 if (cast<StoreInst>(I)->isAtomic())
1183 // Verify we have a legal type before going any further.
1185 if (!isLoadTypeLegal(I->getOperand(0)->getType(), VT))
1188 // Get the value to be stored into a register.
1189 SrcReg = getRegForValue(Op0);
1190 if (SrcReg == 0) return false;
1192 // See if we can handle this address.
1194 if (!ARMComputeAddress(I->getOperand(1), Addr))
1197 if (!ARMEmitStore(VT, SrcReg, Addr, cast<StoreInst>(I)->getAlignment()))
1202 static ARMCC::CondCodes getComparePred(CmpInst::Predicate Pred) {
1204 // Needs two compares...
1205 case CmpInst::FCMP_ONE:
1206 case CmpInst::FCMP_UEQ:
1208 // AL is our "false" for now. The other two need more compares.
1210 case CmpInst::ICMP_EQ:
1211 case CmpInst::FCMP_OEQ:
1213 case CmpInst::ICMP_SGT:
1214 case CmpInst::FCMP_OGT:
1216 case CmpInst::ICMP_SGE:
1217 case CmpInst::FCMP_OGE:
1219 case CmpInst::ICMP_UGT:
1220 case CmpInst::FCMP_UGT:
1222 case CmpInst::FCMP_OLT:
1224 case CmpInst::ICMP_ULE:
1225 case CmpInst::FCMP_OLE:
1227 case CmpInst::FCMP_ORD:
1229 case CmpInst::FCMP_UNO:
1231 case CmpInst::FCMP_UGE:
1233 case CmpInst::ICMP_SLT:
1234 case CmpInst::FCMP_ULT:
1236 case CmpInst::ICMP_SLE:
1237 case CmpInst::FCMP_ULE:
1239 case CmpInst::FCMP_UNE:
1240 case CmpInst::ICMP_NE:
1242 case CmpInst::ICMP_UGE:
1244 case CmpInst::ICMP_ULT:
1249 bool ARMFastISel::SelectBranch(const Instruction *I) {
1250 const BranchInst *BI = cast<BranchInst>(I);
1251 MachineBasicBlock *TBB = FuncInfo.MBBMap[BI->getSuccessor(0)];
1252 MachineBasicBlock *FBB = FuncInfo.MBBMap[BI->getSuccessor(1)];
1254 // Simple branch support.
1256 // If we can, avoid recomputing the compare - redoing it could lead to wonky
1258 if (const CmpInst *CI = dyn_cast<CmpInst>(BI->getCondition())) {
1259 if (CI->hasOneUse() && (CI->getParent() == I->getParent())) {
1261 // Get the compare predicate.
1262 // Try to take advantage of fallthrough opportunities.
1263 CmpInst::Predicate Predicate = CI->getPredicate();
1264 if (FuncInfo.MBB->isLayoutSuccessor(TBB)) {
1265 std::swap(TBB, FBB);
1266 Predicate = CmpInst::getInversePredicate(Predicate);
1269 ARMCC::CondCodes ARMPred = getComparePred(Predicate);
1271 // We may not handle every CC for now.
1272 if (ARMPred == ARMCC::AL) return false;
1274 // Emit the compare.
1275 if (!ARMEmitCmp(CI->getOperand(0), CI->getOperand(1), CI->isUnsigned()))
1278 unsigned BrOpc = isThumb2 ? ARM::t2Bcc : ARM::Bcc;
1279 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(BrOpc))
1280 .addMBB(TBB).addImm(ARMPred).addReg(ARM::CPSR);
1281 fastEmitBranch(FBB, DbgLoc);
1282 FuncInfo.MBB->addSuccessor(TBB);
1285 } else if (TruncInst *TI = dyn_cast<TruncInst>(BI->getCondition())) {
1287 if (TI->hasOneUse() && TI->getParent() == I->getParent() &&
1288 (isLoadTypeLegal(TI->getOperand(0)->getType(), SourceVT))) {
1289 unsigned TstOpc = isThumb2 ? ARM::t2TSTri : ARM::TSTri;
1290 unsigned OpReg = getRegForValue(TI->getOperand(0));
1291 OpReg = constrainOperandRegClass(TII.get(TstOpc), OpReg, 0);
1292 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1294 .addReg(OpReg).addImm(1));
1296 unsigned CCMode = ARMCC::NE;
1297 if (FuncInfo.MBB->isLayoutSuccessor(TBB)) {
1298 std::swap(TBB, FBB);
1302 unsigned BrOpc = isThumb2 ? ARM::t2Bcc : ARM::Bcc;
1303 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(BrOpc))
1304 .addMBB(TBB).addImm(CCMode).addReg(ARM::CPSR);
1306 fastEmitBranch(FBB, DbgLoc);
1307 FuncInfo.MBB->addSuccessor(TBB);
1310 } else if (const ConstantInt *CI =
1311 dyn_cast<ConstantInt>(BI->getCondition())) {
1312 uint64_t Imm = CI->getZExtValue();
1313 MachineBasicBlock *Target = (Imm == 0) ? FBB : TBB;
1314 fastEmitBranch(Target, DbgLoc);
1318 unsigned CmpReg = getRegForValue(BI->getCondition());
1319 if (CmpReg == 0) return false;
1321 // We've been divorced from our compare! Our block was split, and
1322 // now our compare lives in a predecessor block. We musn't
1323 // re-compare here, as the children of the compare aren't guaranteed
1324 // live across the block boundary (we *could* check for this).
1325 // Regardless, the compare has been done in the predecessor block,
1326 // and it left a value for us in a virtual register. Ergo, we test
1327 // the one-bit value left in the virtual register.
1328 unsigned TstOpc = isThumb2 ? ARM::t2TSTri : ARM::TSTri;
1329 CmpReg = constrainOperandRegClass(TII.get(TstOpc), CmpReg, 0);
1331 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(TstOpc))
1335 unsigned CCMode = ARMCC::NE;
1336 if (FuncInfo.MBB->isLayoutSuccessor(TBB)) {
1337 std::swap(TBB, FBB);
1341 unsigned BrOpc = isThumb2 ? ARM::t2Bcc : ARM::Bcc;
1342 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(BrOpc))
1343 .addMBB(TBB).addImm(CCMode).addReg(ARM::CPSR);
1344 fastEmitBranch(FBB, DbgLoc);
1345 FuncInfo.MBB->addSuccessor(TBB);
1349 bool ARMFastISel::SelectIndirectBr(const Instruction *I) {
1350 unsigned AddrReg = getRegForValue(I->getOperand(0));
1351 if (AddrReg == 0) return false;
1353 unsigned Opc = isThumb2 ? ARM::tBRIND : ARM::BX;
1354 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1355 TII.get(Opc)).addReg(AddrReg));
1357 const IndirectBrInst *IB = cast<IndirectBrInst>(I);
1358 for (unsigned i = 0, e = IB->getNumSuccessors(); i != e; ++i)
1359 FuncInfo.MBB->addSuccessor(FuncInfo.MBBMap[IB->getSuccessor(i)]);
1364 bool ARMFastISel::ARMEmitCmp(const Value *Src1Value, const Value *Src2Value,
1366 Type *Ty = Src1Value->getType();
1367 EVT SrcEVT = TLI.getValueType(DL, Ty, true);
1368 if (!SrcEVT.isSimple()) return false;
1369 MVT SrcVT = SrcEVT.getSimpleVT();
1371 bool isFloat = (Ty->isFloatTy() || Ty->isDoubleTy());
1372 if (isFloat && !Subtarget->hasVFP2())
1375 // Check to see if the 2nd operand is a constant that we can encode directly
1378 bool UseImm = false;
1379 bool isNegativeImm = false;
1380 // FIXME: At -O0 we don't have anything that canonicalizes operand order.
1381 // Thus, Src1Value may be a ConstantInt, but we're missing it.
1382 if (const ConstantInt *ConstInt = dyn_cast<ConstantInt>(Src2Value)) {
1383 if (SrcVT == MVT::i32 || SrcVT == MVT::i16 || SrcVT == MVT::i8 ||
1385 const APInt &CIVal = ConstInt->getValue();
1386 Imm = (isZExt) ? (int)CIVal.getZExtValue() : (int)CIVal.getSExtValue();
1387 // For INT_MIN/LONG_MIN (i.e., 0x80000000) we need to use a cmp, rather
1388 // then a cmn, because there is no way to represent 2147483648 as a
1389 // signed 32-bit int.
1390 if (Imm < 0 && Imm != (int)0x80000000) {
1391 isNegativeImm = true;
1394 UseImm = isThumb2 ? (ARM_AM::getT2SOImmVal(Imm) != -1) :
1395 (ARM_AM::getSOImmVal(Imm) != -1);
1397 } else if (const ConstantFP *ConstFP = dyn_cast<ConstantFP>(Src2Value)) {
1398 if (SrcVT == MVT::f32 || SrcVT == MVT::f64)
1399 if (ConstFP->isZero() && !ConstFP->isNegative())
1405 bool needsExt = false;
1406 switch (SrcVT.SimpleTy) {
1407 default: return false;
1408 // TODO: Verify compares.
1411 CmpOpc = UseImm ? ARM::VCMPEZS : ARM::VCMPES;
1415 CmpOpc = UseImm ? ARM::VCMPEZD : ARM::VCMPED;
1421 // Intentional fall-through.
1425 CmpOpc = ARM::t2CMPrr;
1427 CmpOpc = isNegativeImm ? ARM::t2CMNri : ARM::t2CMPri;
1430 CmpOpc = ARM::CMPrr;
1432 CmpOpc = isNegativeImm ? ARM::CMNri : ARM::CMPri;
1437 unsigned SrcReg1 = getRegForValue(Src1Value);
1438 if (SrcReg1 == 0) return false;
1440 unsigned SrcReg2 = 0;
1442 SrcReg2 = getRegForValue(Src2Value);
1443 if (SrcReg2 == 0) return false;
1446 // We have i1, i8, or i16, we need to either zero extend or sign extend.
1448 SrcReg1 = ARMEmitIntExt(SrcVT, SrcReg1, MVT::i32, isZExt);
1449 if (SrcReg1 == 0) return false;
1451 SrcReg2 = ARMEmitIntExt(SrcVT, SrcReg2, MVT::i32, isZExt);
1452 if (SrcReg2 == 0) return false;
1456 const MCInstrDesc &II = TII.get(CmpOpc);
1457 SrcReg1 = constrainOperandRegClass(II, SrcReg1, 0);
1459 SrcReg2 = constrainOperandRegClass(II, SrcReg2, 1);
1460 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II)
1461 .addReg(SrcReg1).addReg(SrcReg2));
1463 MachineInstrBuilder MIB;
1464 MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II)
1467 // Only add immediate for icmp as the immediate for fcmp is an implicit 0.0.
1470 AddOptionalDefs(MIB);
1473 // For floating point we need to move the result to a comparison register
1474 // that we can then use for branches.
1475 if (Ty->isFloatTy() || Ty->isDoubleTy())
1476 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1477 TII.get(ARM::FMSTAT)));
1481 bool ARMFastISel::SelectCmp(const Instruction *I) {
1482 const CmpInst *CI = cast<CmpInst>(I);
1484 // Get the compare predicate.
1485 ARMCC::CondCodes ARMPred = getComparePred(CI->getPredicate());
1487 // We may not handle every CC for now.
1488 if (ARMPred == ARMCC::AL) return false;
1490 // Emit the compare.
1491 if (!ARMEmitCmp(CI->getOperand(0), CI->getOperand(1), CI->isUnsigned()))
1494 // Now set a register based on the comparison. Explicitly set the predicates
1496 unsigned MovCCOpc = isThumb2 ? ARM::t2MOVCCi : ARM::MOVCCi;
1497 const TargetRegisterClass *RC = isThumb2 ? &ARM::rGPRRegClass
1498 : &ARM::GPRRegClass;
1499 unsigned DestReg = createResultReg(RC);
1500 Constant *Zero = ConstantInt::get(Type::getInt32Ty(*Context), 0);
1501 unsigned ZeroReg = fastMaterializeConstant(Zero);
1502 // ARMEmitCmp emits a FMSTAT when necessary, so it's always safe to use CPSR.
1503 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(MovCCOpc), DestReg)
1504 .addReg(ZeroReg).addImm(1)
1505 .addImm(ARMPred).addReg(ARM::CPSR);
1507 updateValueMap(I, DestReg);
1511 bool ARMFastISel::SelectFPExt(const Instruction *I) {
1512 // Make sure we have VFP and that we're extending float to double.
1513 if (!Subtarget->hasVFP2()) return false;
1515 Value *V = I->getOperand(0);
1516 if (!I->getType()->isDoubleTy() ||
1517 !V->getType()->isFloatTy()) return false;
1519 unsigned Op = getRegForValue(V);
1520 if (Op == 0) return false;
1522 unsigned Result = createResultReg(&ARM::DPRRegClass);
1523 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1524 TII.get(ARM::VCVTDS), Result)
1526 updateValueMap(I, Result);
1530 bool ARMFastISel::SelectFPTrunc(const Instruction *I) {
1531 // Make sure we have VFP and that we're truncating double to float.
1532 if (!Subtarget->hasVFP2()) return false;
1534 Value *V = I->getOperand(0);
1535 if (!(I->getType()->isFloatTy() &&
1536 V->getType()->isDoubleTy())) return false;
1538 unsigned Op = getRegForValue(V);
1539 if (Op == 0) return false;
1541 unsigned Result = createResultReg(&ARM::SPRRegClass);
1542 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1543 TII.get(ARM::VCVTSD), Result)
1545 updateValueMap(I, Result);
1549 bool ARMFastISel::SelectIToFP(const Instruction *I, bool isSigned) {
1550 // Make sure we have VFP.
1551 if (!Subtarget->hasVFP2()) return false;
1554 Type *Ty = I->getType();
1555 if (!isTypeLegal(Ty, DstVT))
1558 Value *Src = I->getOperand(0);
1559 EVT SrcEVT = TLI.getValueType(DL, Src->getType(), true);
1560 if (!SrcEVT.isSimple())
1562 MVT SrcVT = SrcEVT.getSimpleVT();
1563 if (SrcVT != MVT::i32 && SrcVT != MVT::i16 && SrcVT != MVT::i8)
1566 unsigned SrcReg = getRegForValue(Src);
1567 if (SrcReg == 0) return false;
1569 // Handle sign-extension.
1570 if (SrcVT == MVT::i16 || SrcVT == MVT::i8) {
1571 SrcReg = ARMEmitIntExt(SrcVT, SrcReg, MVT::i32,
1572 /*isZExt*/!isSigned);
1573 if (SrcReg == 0) return false;
1576 // The conversion routine works on fp-reg to fp-reg and the operand above
1577 // was an integer, move it to the fp registers if possible.
1578 unsigned FP = ARMMoveToFPReg(MVT::f32, SrcReg);
1579 if (FP == 0) return false;
1582 if (Ty->isFloatTy()) Opc = isSigned ? ARM::VSITOS : ARM::VUITOS;
1583 else if (Ty->isDoubleTy()) Opc = isSigned ? ARM::VSITOD : ARM::VUITOD;
1586 unsigned ResultReg = createResultReg(TLI.getRegClassFor(DstVT));
1587 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1588 TII.get(Opc), ResultReg).addReg(FP));
1589 updateValueMap(I, ResultReg);
1593 bool ARMFastISel::SelectFPToI(const Instruction *I, bool isSigned) {
1594 // Make sure we have VFP.
1595 if (!Subtarget->hasVFP2()) return false;
1598 Type *RetTy = I->getType();
1599 if (!isTypeLegal(RetTy, DstVT))
1602 unsigned Op = getRegForValue(I->getOperand(0));
1603 if (Op == 0) return false;
1606 Type *OpTy = I->getOperand(0)->getType();
1607 if (OpTy->isFloatTy()) Opc = isSigned ? ARM::VTOSIZS : ARM::VTOUIZS;
1608 else if (OpTy->isDoubleTy()) Opc = isSigned ? ARM::VTOSIZD : ARM::VTOUIZD;
1611 // f64->s32/u32 or f32->s32/u32 both need an intermediate f32 reg.
1612 unsigned ResultReg = createResultReg(TLI.getRegClassFor(MVT::f32));
1613 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1614 TII.get(Opc), ResultReg).addReg(Op));
1616 // This result needs to be in an integer register, but the conversion only
1617 // takes place in fp-regs.
1618 unsigned IntReg = ARMMoveToIntReg(DstVT, ResultReg);
1619 if (IntReg == 0) return false;
1621 updateValueMap(I, IntReg);
1625 bool ARMFastISel::SelectSelect(const Instruction *I) {
1627 if (!isTypeLegal(I->getType(), VT))
1630 // Things need to be register sized for register moves.
1631 if (VT != MVT::i32) return false;
1633 unsigned CondReg = getRegForValue(I->getOperand(0));
1634 if (CondReg == 0) return false;
1635 unsigned Op1Reg = getRegForValue(I->getOperand(1));
1636 if (Op1Reg == 0) return false;
1638 // Check to see if we can use an immediate in the conditional move.
1640 bool UseImm = false;
1641 bool isNegativeImm = false;
1642 if (const ConstantInt *ConstInt = dyn_cast<ConstantInt>(I->getOperand(2))) {
1643 assert (VT == MVT::i32 && "Expecting an i32.");
1644 Imm = (int)ConstInt->getValue().getZExtValue();
1646 isNegativeImm = true;
1649 UseImm = isThumb2 ? (ARM_AM::getT2SOImmVal(Imm) != -1) :
1650 (ARM_AM::getSOImmVal(Imm) != -1);
1653 unsigned Op2Reg = 0;
1655 Op2Reg = getRegForValue(I->getOperand(2));
1656 if (Op2Reg == 0) return false;
1659 unsigned TstOpc = isThumb2 ? ARM::t2TSTri : ARM::TSTri;
1660 CondReg = constrainOperandRegClass(TII.get(TstOpc), CondReg, 0);
1662 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(TstOpc))
1667 const TargetRegisterClass *RC;
1669 RC = isThumb2 ? &ARM::tGPRRegClass : &ARM::GPRRegClass;
1670 MovCCOpc = isThumb2 ? ARM::t2MOVCCr : ARM::MOVCCr;
1672 RC = isThumb2 ? &ARM::rGPRRegClass : &ARM::GPRRegClass;
1674 MovCCOpc = isThumb2 ? ARM::t2MOVCCi : ARM::MOVCCi;
1676 MovCCOpc = isThumb2 ? ARM::t2MVNCCi : ARM::MVNCCi;
1678 unsigned ResultReg = createResultReg(RC);
1680 Op2Reg = constrainOperandRegClass(TII.get(MovCCOpc), Op2Reg, 1);
1681 Op1Reg = constrainOperandRegClass(TII.get(MovCCOpc), Op1Reg, 2);
1682 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(MovCCOpc),
1689 Op1Reg = constrainOperandRegClass(TII.get(MovCCOpc), Op1Reg, 1);
1690 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(MovCCOpc),
1697 updateValueMap(I, ResultReg);
1701 bool ARMFastISel::SelectDiv(const Instruction *I, bool isSigned) {
1703 Type *Ty = I->getType();
1704 if (!isTypeLegal(Ty, VT))
1707 // If we have integer div support we should have selected this automagically.
1708 // In case we have a real miss go ahead and return false and we'll pick
1710 if (Subtarget->hasDivide()) return false;
1712 // Otherwise emit a libcall.
1713 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
1715 LC = isSigned ? RTLIB::SDIV_I8 : RTLIB::UDIV_I8;
1716 else if (VT == MVT::i16)
1717 LC = isSigned ? RTLIB::SDIV_I16 : RTLIB::UDIV_I16;
1718 else if (VT == MVT::i32)
1719 LC = isSigned ? RTLIB::SDIV_I32 : RTLIB::UDIV_I32;
1720 else if (VT == MVT::i64)
1721 LC = isSigned ? RTLIB::SDIV_I64 : RTLIB::UDIV_I64;
1722 else if (VT == MVT::i128)
1723 LC = isSigned ? RTLIB::SDIV_I128 : RTLIB::UDIV_I128;
1724 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported SDIV!");
1726 return ARMEmitLibcall(I, LC);
1729 bool ARMFastISel::SelectRem(const Instruction *I, bool isSigned) {
1731 Type *Ty = I->getType();
1732 if (!isTypeLegal(Ty, VT))
1735 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
1737 LC = isSigned ? RTLIB::SREM_I8 : RTLIB::UREM_I8;
1738 else if (VT == MVT::i16)
1739 LC = isSigned ? RTLIB::SREM_I16 : RTLIB::UREM_I16;
1740 else if (VT == MVT::i32)
1741 LC = isSigned ? RTLIB::SREM_I32 : RTLIB::UREM_I32;
1742 else if (VT == MVT::i64)
1743 LC = isSigned ? RTLIB::SREM_I64 : RTLIB::UREM_I64;
1744 else if (VT == MVT::i128)
1745 LC = isSigned ? RTLIB::SREM_I128 : RTLIB::UREM_I128;
1746 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported SREM!");
1748 return ARMEmitLibcall(I, LC);
1751 bool ARMFastISel::SelectBinaryIntOp(const Instruction *I, unsigned ISDOpcode) {
1752 EVT DestVT = TLI.getValueType(DL, I->getType(), true);
1754 // We can get here in the case when we have a binary operation on a non-legal
1755 // type and the target independent selector doesn't know how to handle it.
1756 if (DestVT != MVT::i16 && DestVT != MVT::i8 && DestVT != MVT::i1)
1760 switch (ISDOpcode) {
1761 default: return false;
1763 Opc = isThumb2 ? ARM::t2ADDrr : ARM::ADDrr;
1766 Opc = isThumb2 ? ARM::t2ORRrr : ARM::ORRrr;
1769 Opc = isThumb2 ? ARM::t2SUBrr : ARM::SUBrr;
1773 unsigned SrcReg1 = getRegForValue(I->getOperand(0));
1774 if (SrcReg1 == 0) return false;
1776 // TODO: Often the 2nd operand is an immediate, which can be encoded directly
1777 // in the instruction, rather then materializing the value in a register.
1778 unsigned SrcReg2 = getRegForValue(I->getOperand(1));
1779 if (SrcReg2 == 0) return false;
1781 unsigned ResultReg = createResultReg(&ARM::GPRnopcRegClass);
1782 SrcReg1 = constrainOperandRegClass(TII.get(Opc), SrcReg1, 1);
1783 SrcReg2 = constrainOperandRegClass(TII.get(Opc), SrcReg2, 2);
1784 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1785 TII.get(Opc), ResultReg)
1786 .addReg(SrcReg1).addReg(SrcReg2));
1787 updateValueMap(I, ResultReg);
1791 bool ARMFastISel::SelectBinaryFPOp(const Instruction *I, unsigned ISDOpcode) {
1792 EVT FPVT = TLI.getValueType(DL, I->getType(), true);
1793 if (!FPVT.isSimple()) return false;
1794 MVT VT = FPVT.getSimpleVT();
1796 // FIXME: Support vector types where possible.
1800 // We can get here in the case when we want to use NEON for our fp
1801 // operations, but can't figure out how to. Just use the vfp instructions
1803 // FIXME: It'd be nice to use NEON instructions.
1804 Type *Ty = I->getType();
1805 bool isFloat = (Ty->isDoubleTy() || Ty->isFloatTy());
1806 if (isFloat && !Subtarget->hasVFP2())
1810 bool is64bit = VT == MVT::f64 || VT == MVT::i64;
1811 switch (ISDOpcode) {
1812 default: return false;
1814 Opc = is64bit ? ARM::VADDD : ARM::VADDS;
1817 Opc = is64bit ? ARM::VSUBD : ARM::VSUBS;
1820 Opc = is64bit ? ARM::VMULD : ARM::VMULS;
1823 unsigned Op1 = getRegForValue(I->getOperand(0));
1824 if (Op1 == 0) return false;
1826 unsigned Op2 = getRegForValue(I->getOperand(1));
1827 if (Op2 == 0) return false;
1829 unsigned ResultReg = createResultReg(TLI.getRegClassFor(VT.SimpleTy));
1830 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1831 TII.get(Opc), ResultReg)
1832 .addReg(Op1).addReg(Op2));
1833 updateValueMap(I, ResultReg);
1837 // Call Handling Code
1839 // This is largely taken directly from CCAssignFnForNode
1840 // TODO: We may not support all of this.
1841 CCAssignFn *ARMFastISel::CCAssignFnForCall(CallingConv::ID CC,
1846 llvm_unreachable("Unsupported calling convention");
1847 case CallingConv::Fast:
1848 if (Subtarget->hasVFP2() && !isVarArg) {
1849 if (!Subtarget->isAAPCS_ABI())
1850 return (Return ? RetFastCC_ARM_APCS : FastCC_ARM_APCS);
1851 // For AAPCS ABI targets, just use VFP variant of the calling convention.
1852 return (Return ? RetCC_ARM_AAPCS_VFP : CC_ARM_AAPCS_VFP);
1855 case CallingConv::C:
1856 // Use target triple & subtarget features to do actual dispatch.
1857 if (Subtarget->isAAPCS_ABI()) {
1858 if (Subtarget->hasVFP2() &&
1859 TM.Options.FloatABIType == FloatABI::Hard && !isVarArg)
1860 return (Return ? RetCC_ARM_AAPCS_VFP: CC_ARM_AAPCS_VFP);
1862 return (Return ? RetCC_ARM_AAPCS: CC_ARM_AAPCS);
1864 return (Return ? RetCC_ARM_APCS: CC_ARM_APCS);
1865 case CallingConv::ARM_AAPCS_VFP:
1867 return (Return ? RetCC_ARM_AAPCS_VFP: CC_ARM_AAPCS_VFP);
1868 // Fall through to soft float variant, variadic functions don't
1869 // use hard floating point ABI.
1870 case CallingConv::ARM_AAPCS:
1871 return (Return ? RetCC_ARM_AAPCS: CC_ARM_AAPCS);
1872 case CallingConv::ARM_APCS:
1873 return (Return ? RetCC_ARM_APCS: CC_ARM_APCS);
1874 case CallingConv::GHC:
1876 llvm_unreachable("Can't return in GHC call convention");
1878 return CC_ARM_APCS_GHC;
1882 bool ARMFastISel::ProcessCallArgs(SmallVectorImpl<Value*> &Args,
1883 SmallVectorImpl<unsigned> &ArgRegs,
1884 SmallVectorImpl<MVT> &ArgVTs,
1885 SmallVectorImpl<ISD::ArgFlagsTy> &ArgFlags,
1886 SmallVectorImpl<unsigned> &RegArgs,
1890 SmallVector<CCValAssign, 16> ArgLocs;
1891 CCState CCInfo(CC, isVarArg, *FuncInfo.MF, ArgLocs, *Context);
1892 CCInfo.AnalyzeCallOperands(ArgVTs, ArgFlags,
1893 CCAssignFnForCall(CC, false, isVarArg));
1895 // Check that we can handle all of the arguments. If we can't, then bail out
1896 // now before we add code to the MBB.
1897 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1898 CCValAssign &VA = ArgLocs[i];
1899 MVT ArgVT = ArgVTs[VA.getValNo()];
1901 // We don't handle NEON/vector parameters yet.
1902 if (ArgVT.isVector() || ArgVT.getSizeInBits() > 64)
1905 // Now copy/store arg to correct locations.
1906 if (VA.isRegLoc() && !VA.needsCustom()) {
1908 } else if (VA.needsCustom()) {
1909 // TODO: We need custom lowering for vector (v2f64) args.
1910 if (VA.getLocVT() != MVT::f64 ||
1911 // TODO: Only handle register args for now.
1912 !VA.isRegLoc() || !ArgLocs[++i].isRegLoc())
1915 switch (ArgVT.SimpleTy) {
1924 if (!Subtarget->hasVFP2())
1928 if (!Subtarget->hasVFP2())
1935 // At the point, we are able to handle the call's arguments in fast isel.
1937 // Get a count of how many bytes are to be pushed on the stack.
1938 NumBytes = CCInfo.getNextStackOffset();
1940 // Issue CALLSEQ_START
1941 unsigned AdjStackDown = TII.getCallFrameSetupOpcode();
1942 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1943 TII.get(AdjStackDown))
1946 // Process the args.
1947 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1948 CCValAssign &VA = ArgLocs[i];
1949 const Value *ArgVal = Args[VA.getValNo()];
1950 unsigned Arg = ArgRegs[VA.getValNo()];
1951 MVT ArgVT = ArgVTs[VA.getValNo()];
1953 assert((!ArgVT.isVector() && ArgVT.getSizeInBits() <= 64) &&
1954 "We don't handle NEON/vector parameters yet.");
1956 // Handle arg promotion, etc.
1957 switch (VA.getLocInfo()) {
1958 case CCValAssign::Full: break;
1959 case CCValAssign::SExt: {
1960 MVT DestVT = VA.getLocVT();
1961 Arg = ARMEmitIntExt(ArgVT, Arg, DestVT, /*isZExt*/false);
1962 assert (Arg != 0 && "Failed to emit a sext");
1966 case CCValAssign::AExt:
1967 // Intentional fall-through. Handle AExt and ZExt.
1968 case CCValAssign::ZExt: {
1969 MVT DestVT = VA.getLocVT();
1970 Arg = ARMEmitIntExt(ArgVT, Arg, DestVT, /*isZExt*/true);
1971 assert (Arg != 0 && "Failed to emit a zext");
1975 case CCValAssign::BCvt: {
1976 unsigned BC = fastEmit_r(ArgVT, VA.getLocVT(), ISD::BITCAST, Arg,
1977 /*TODO: Kill=*/false);
1978 assert(BC != 0 && "Failed to emit a bitcast!");
1980 ArgVT = VA.getLocVT();
1983 default: llvm_unreachable("Unknown arg promotion!");
1986 // Now copy/store arg to correct locations.
1987 if (VA.isRegLoc() && !VA.needsCustom()) {
1988 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1989 TII.get(TargetOpcode::COPY), VA.getLocReg()).addReg(Arg);
1990 RegArgs.push_back(VA.getLocReg());
1991 } else if (VA.needsCustom()) {
1992 // TODO: We need custom lowering for vector (v2f64) args.
1993 assert(VA.getLocVT() == MVT::f64 &&
1994 "Custom lowering for v2f64 args not available");
1996 CCValAssign &NextVA = ArgLocs[++i];
1998 assert(VA.isRegLoc() && NextVA.isRegLoc() &&
1999 "We only handle register args!");
2001 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
2002 TII.get(ARM::VMOVRRD), VA.getLocReg())
2003 .addReg(NextVA.getLocReg(), RegState::Define)
2005 RegArgs.push_back(VA.getLocReg());
2006 RegArgs.push_back(NextVA.getLocReg());
2008 assert(VA.isMemLoc());
2009 // Need to store on the stack.
2011 // Don't emit stores for undef values.
2012 if (isa<UndefValue>(ArgVal))
2016 Addr.BaseType = Address::RegBase;
2017 Addr.Base.Reg = ARM::SP;
2018 Addr.Offset = VA.getLocMemOffset();
2020 bool EmitRet = ARMEmitStore(ArgVT, Arg, Addr); (void)EmitRet;
2021 assert(EmitRet && "Could not emit a store for argument!");
2028 bool ARMFastISel::FinishCall(MVT RetVT, SmallVectorImpl<unsigned> &UsedRegs,
2029 const Instruction *I, CallingConv::ID CC,
2030 unsigned &NumBytes, bool isVarArg) {
2031 // Issue CALLSEQ_END
2032 unsigned AdjStackUp = TII.getCallFrameDestroyOpcode();
2033 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
2034 TII.get(AdjStackUp))
2035 .addImm(NumBytes).addImm(0));
2037 // Now the return value.
2038 if (RetVT != MVT::isVoid) {
2039 SmallVector<CCValAssign, 16> RVLocs;
2040 CCState CCInfo(CC, isVarArg, *FuncInfo.MF, RVLocs, *Context);
2041 CCInfo.AnalyzeCallResult(RetVT, CCAssignFnForCall(CC, true, isVarArg));
2043 // Copy all of the result registers out of their specified physreg.
2044 if (RVLocs.size() == 2 && RetVT == MVT::f64) {
2045 // For this move we copy into two registers and then move into the
2046 // double fp reg we want.
2047 MVT DestVT = RVLocs[0].getValVT();
2048 const TargetRegisterClass* DstRC = TLI.getRegClassFor(DestVT);
2049 unsigned ResultReg = createResultReg(DstRC);
2050 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
2051 TII.get(ARM::VMOVDRR), ResultReg)
2052 .addReg(RVLocs[0].getLocReg())
2053 .addReg(RVLocs[1].getLocReg()));
2055 UsedRegs.push_back(RVLocs[0].getLocReg());
2056 UsedRegs.push_back(RVLocs[1].getLocReg());
2058 // Finally update the result.
2059 updateValueMap(I, ResultReg);
2061 assert(RVLocs.size() == 1 &&"Can't handle non-double multi-reg retvals!");
2062 MVT CopyVT = RVLocs[0].getValVT();
2064 // Special handling for extended integers.
2065 if (RetVT == MVT::i1 || RetVT == MVT::i8 || RetVT == MVT::i16)
2068 const TargetRegisterClass* DstRC = TLI.getRegClassFor(CopyVT);
2070 unsigned ResultReg = createResultReg(DstRC);
2071 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
2072 TII.get(TargetOpcode::COPY),
2073 ResultReg).addReg(RVLocs[0].getLocReg());
2074 UsedRegs.push_back(RVLocs[0].getLocReg());
2076 // Finally update the result.
2077 updateValueMap(I, ResultReg);
2084 bool ARMFastISel::SelectRet(const Instruction *I) {
2085 const ReturnInst *Ret = cast<ReturnInst>(I);
2086 const Function &F = *I->getParent()->getParent();
2088 if (!FuncInfo.CanLowerReturn)
2091 // Build a list of return value registers.
2092 SmallVector<unsigned, 4> RetRegs;
2094 CallingConv::ID CC = F.getCallingConv();
2095 if (Ret->getNumOperands() > 0) {
2096 SmallVector<ISD::OutputArg, 4> Outs;
2097 GetReturnInfo(F.getReturnType(), F.getAttributes(), Outs, TLI, DL);
2099 // Analyze operands of the call, assigning locations to each operand.
2100 SmallVector<CCValAssign, 16> ValLocs;
2101 CCState CCInfo(CC, F.isVarArg(), *FuncInfo.MF, ValLocs, I->getContext());
2102 CCInfo.AnalyzeReturn(Outs, CCAssignFnForCall(CC, true /* is Ret */,
2105 const Value *RV = Ret->getOperand(0);
2106 unsigned Reg = getRegForValue(RV);
2110 // Only handle a single return value for now.
2111 if (ValLocs.size() != 1)
2114 CCValAssign &VA = ValLocs[0];
2116 // Don't bother handling odd stuff for now.
2117 if (VA.getLocInfo() != CCValAssign::Full)
2119 // Only handle register returns for now.
2123 unsigned SrcReg = Reg + VA.getValNo();
2124 EVT RVEVT = TLI.getValueType(DL, RV->getType());
2125 if (!RVEVT.isSimple()) return false;
2126 MVT RVVT = RVEVT.getSimpleVT();
2127 MVT DestVT = VA.getValVT();
2128 // Special handling for extended integers.
2129 if (RVVT != DestVT) {
2130 if (RVVT != MVT::i1 && RVVT != MVT::i8 && RVVT != MVT::i16)
2133 assert(DestVT == MVT::i32 && "ARM should always ext to i32");
2135 // Perform extension if flagged as either zext or sext. Otherwise, do
2137 if (Outs[0].Flags.isZExt() || Outs[0].Flags.isSExt()) {
2138 SrcReg = ARMEmitIntExt(RVVT, SrcReg, DestVT, Outs[0].Flags.isZExt());
2139 if (SrcReg == 0) return false;
2144 unsigned DstReg = VA.getLocReg();
2145 const TargetRegisterClass* SrcRC = MRI.getRegClass(SrcReg);
2146 // Avoid a cross-class copy. This is very unlikely.
2147 if (!SrcRC->contains(DstReg))
2149 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
2150 TII.get(TargetOpcode::COPY), DstReg).addReg(SrcReg);
2152 // Add register to return instruction.
2153 RetRegs.push_back(VA.getLocReg());
2156 unsigned RetOpc = isThumb2 ? ARM::tBX_RET : ARM::BX_RET;
2157 MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
2159 AddOptionalDefs(MIB);
2160 for (unsigned i = 0, e = RetRegs.size(); i != e; ++i)
2161 MIB.addReg(RetRegs[i], RegState::Implicit);
2165 unsigned ARMFastISel::ARMSelectCallOp(bool UseReg) {
2167 return isThumb2 ? ARM::tBLXr : ARM::BLX;
2169 return isThumb2 ? ARM::tBL : ARM::BL;
2172 unsigned ARMFastISel::getLibcallReg(const Twine &Name) {
2173 // Manually compute the global's type to avoid building it when unnecessary.
2174 Type *GVTy = Type::getInt32PtrTy(*Context, /*AS=*/0);
2175 EVT LCREVT = TLI.getValueType(DL, GVTy);
2176 if (!LCREVT.isSimple()) return 0;
2178 GlobalValue *GV = new GlobalVariable(M, Type::getInt32Ty(*Context), false,
2179 GlobalValue::ExternalLinkage, nullptr,
2181 assert(GV->getType() == GVTy && "We miscomputed the type for the global!");
2182 return ARMMaterializeGV(GV, LCREVT.getSimpleVT());
2185 // A quick function that will emit a call for a named libcall in F with the
2186 // vector of passed arguments for the Instruction in I. We can assume that we
2187 // can emit a call for any libcall we can produce. This is an abridged version
2188 // of the full call infrastructure since we won't need to worry about things
2189 // like computed function pointers or strange arguments at call sites.
2190 // TODO: Try to unify this and the normal call bits for ARM, then try to unify
2192 bool ARMFastISel::ARMEmitLibcall(const Instruction *I, RTLIB::Libcall Call) {
2193 CallingConv::ID CC = TLI.getLibcallCallingConv(Call);
2195 // Handle *simple* calls for now.
2196 Type *RetTy = I->getType();
2198 if (RetTy->isVoidTy())
2199 RetVT = MVT::isVoid;
2200 else if (!isTypeLegal(RetTy, RetVT))
2203 // Can't handle non-double multi-reg retvals.
2204 if (RetVT != MVT::isVoid && RetVT != MVT::i32) {
2205 SmallVector<CCValAssign, 16> RVLocs;
2206 CCState CCInfo(CC, false, *FuncInfo.MF, RVLocs, *Context);
2207 CCInfo.AnalyzeCallResult(RetVT, CCAssignFnForCall(CC, true, false));
2208 if (RVLocs.size() >= 2 && RetVT != MVT::f64)
2212 // Set up the argument vectors.
2213 SmallVector<Value*, 8> Args;
2214 SmallVector<unsigned, 8> ArgRegs;
2215 SmallVector<MVT, 8> ArgVTs;
2216 SmallVector<ISD::ArgFlagsTy, 8> ArgFlags;
2217 Args.reserve(I->getNumOperands());
2218 ArgRegs.reserve(I->getNumOperands());
2219 ArgVTs.reserve(I->getNumOperands());
2220 ArgFlags.reserve(I->getNumOperands());
2221 for (unsigned i = 0; i < I->getNumOperands(); ++i) {
2222 Value *Op = I->getOperand(i);
2223 unsigned Arg = getRegForValue(Op);
2224 if (Arg == 0) return false;
2226 Type *ArgTy = Op->getType();
2228 if (!isTypeLegal(ArgTy, ArgVT)) return false;
2230 ISD::ArgFlagsTy Flags;
2231 unsigned OriginalAlignment = DL.getABITypeAlignment(ArgTy);
2232 Flags.setOrigAlign(OriginalAlignment);
2235 ArgRegs.push_back(Arg);
2236 ArgVTs.push_back(ArgVT);
2237 ArgFlags.push_back(Flags);
2240 // Handle the arguments now that we've gotten them.
2241 SmallVector<unsigned, 4> RegArgs;
2243 if (!ProcessCallArgs(Args, ArgRegs, ArgVTs, ArgFlags,
2244 RegArgs, CC, NumBytes, false))
2247 unsigned CalleeReg = 0;
2248 if (Subtarget->genLongCalls()) {
2249 CalleeReg = getLibcallReg(TLI.getLibcallName(Call));
2250 if (CalleeReg == 0) return false;
2254 unsigned CallOpc = ARMSelectCallOp(Subtarget->genLongCalls());
2255 MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt,
2256 DbgLoc, TII.get(CallOpc));
2257 // BL / BLX don't take a predicate, but tBL / tBLX do.
2259 AddDefaultPred(MIB);
2260 if (Subtarget->genLongCalls())
2261 MIB.addReg(CalleeReg);
2263 MIB.addExternalSymbol(TLI.getLibcallName(Call));
2265 // Add implicit physical register uses to the call.
2266 for (unsigned i = 0, e = RegArgs.size(); i != e; ++i)
2267 MIB.addReg(RegArgs[i], RegState::Implicit);
2269 // Add a register mask with the call-preserved registers.
2270 // Proper defs for return values will be added by setPhysRegsDeadExcept().
2271 MIB.addRegMask(TRI.getCallPreservedMask(*FuncInfo.MF, CC));
2273 // Finish off the call including any return values.
2274 SmallVector<unsigned, 4> UsedRegs;
2275 if (!FinishCall(RetVT, UsedRegs, I, CC, NumBytes, false)) return false;
2277 // Set all unused physreg defs as dead.
2278 static_cast<MachineInstr *>(MIB)->setPhysRegsDeadExcept(UsedRegs, TRI);
2283 bool ARMFastISel::SelectCall(const Instruction *I,
2284 const char *IntrMemName = nullptr) {
2285 const CallInst *CI = cast<CallInst>(I);
2286 const Value *Callee = CI->getCalledValue();
2288 // Can't handle inline asm.
2289 if (isa<InlineAsm>(Callee)) return false;
2291 // Allow SelectionDAG isel to handle tail calls.
2292 if (CI->isTailCall()) return false;
2294 // Check the calling convention.
2295 ImmutableCallSite CS(CI);
2296 CallingConv::ID CC = CS.getCallingConv();
2298 // TODO: Avoid some calling conventions?
2300 PointerType *PT = cast<PointerType>(CS.getCalledValue()->getType());
2301 FunctionType *FTy = cast<FunctionType>(PT->getElementType());
2302 bool isVarArg = FTy->isVarArg();
2304 // Handle *simple* calls for now.
2305 Type *RetTy = I->getType();
2307 if (RetTy->isVoidTy())
2308 RetVT = MVT::isVoid;
2309 else if (!isTypeLegal(RetTy, RetVT) && RetVT != MVT::i16 &&
2310 RetVT != MVT::i8 && RetVT != MVT::i1)
2313 // Can't handle non-double multi-reg retvals.
2314 if (RetVT != MVT::isVoid && RetVT != MVT::i1 && RetVT != MVT::i8 &&
2315 RetVT != MVT::i16 && RetVT != MVT::i32) {
2316 SmallVector<CCValAssign, 16> RVLocs;
2317 CCState CCInfo(CC, isVarArg, *FuncInfo.MF, RVLocs, *Context);
2318 CCInfo.AnalyzeCallResult(RetVT, CCAssignFnForCall(CC, true, isVarArg));
2319 if (RVLocs.size() >= 2 && RetVT != MVT::f64)
2323 // Set up the argument vectors.
2324 SmallVector<Value*, 8> Args;
2325 SmallVector<unsigned, 8> ArgRegs;
2326 SmallVector<MVT, 8> ArgVTs;
2327 SmallVector<ISD::ArgFlagsTy, 8> ArgFlags;
2328 unsigned arg_size = CS.arg_size();
2329 Args.reserve(arg_size);
2330 ArgRegs.reserve(arg_size);
2331 ArgVTs.reserve(arg_size);
2332 ArgFlags.reserve(arg_size);
2333 for (ImmutableCallSite::arg_iterator i = CS.arg_begin(), e = CS.arg_end();
2335 // If we're lowering a memory intrinsic instead of a regular call, skip the
2336 // last two arguments, which shouldn't be passed to the underlying function.
2337 if (IntrMemName && e-i <= 2)
2340 ISD::ArgFlagsTy Flags;
2341 unsigned AttrInd = i - CS.arg_begin() + 1;
2342 if (CS.paramHasAttr(AttrInd, Attribute::SExt))
2344 if (CS.paramHasAttr(AttrInd, Attribute::ZExt))
2347 // FIXME: Only handle *easy* calls for now.
2348 if (CS.paramHasAttr(AttrInd, Attribute::InReg) ||
2349 CS.paramHasAttr(AttrInd, Attribute::StructRet) ||
2350 CS.paramHasAttr(AttrInd, Attribute::Nest) ||
2351 CS.paramHasAttr(AttrInd, Attribute::ByVal))
2354 Type *ArgTy = (*i)->getType();
2356 if (!isTypeLegal(ArgTy, ArgVT) && ArgVT != MVT::i16 && ArgVT != MVT::i8 &&
2360 unsigned Arg = getRegForValue(*i);
2364 unsigned OriginalAlignment = DL.getABITypeAlignment(ArgTy);
2365 Flags.setOrigAlign(OriginalAlignment);
2368 ArgRegs.push_back(Arg);
2369 ArgVTs.push_back(ArgVT);
2370 ArgFlags.push_back(Flags);
2373 // Handle the arguments now that we've gotten them.
2374 SmallVector<unsigned, 4> RegArgs;
2376 if (!ProcessCallArgs(Args, ArgRegs, ArgVTs, ArgFlags,
2377 RegArgs, CC, NumBytes, isVarArg))
2380 bool UseReg = false;
2381 const GlobalValue *GV = dyn_cast<GlobalValue>(Callee);
2382 if (!GV || Subtarget->genLongCalls()) UseReg = true;
2384 unsigned CalleeReg = 0;
2387 CalleeReg = getLibcallReg(IntrMemName);
2389 CalleeReg = getRegForValue(Callee);
2391 if (CalleeReg == 0) return false;
2395 unsigned CallOpc = ARMSelectCallOp(UseReg);
2396 MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt,
2397 DbgLoc, TII.get(CallOpc));
2399 unsigned char OpFlags = 0;
2401 // Add MO_PLT for global address or external symbol in the PIC relocation
2403 if (Subtarget->isTargetELF() && TM.getRelocationModel() == Reloc::PIC_)
2404 OpFlags = ARMII::MO_PLT;
2406 // ARM calls don't take a predicate, but tBL / tBLX do.
2408 AddDefaultPred(MIB);
2410 MIB.addReg(CalleeReg);
2411 else if (!IntrMemName)
2412 MIB.addGlobalAddress(GV, 0, OpFlags);
2414 MIB.addExternalSymbol(IntrMemName, OpFlags);
2416 // Add implicit physical register uses to the call.
2417 for (unsigned i = 0, e = RegArgs.size(); i != e; ++i)
2418 MIB.addReg(RegArgs[i], RegState::Implicit);
2420 // Add a register mask with the call-preserved registers.
2421 // Proper defs for return values will be added by setPhysRegsDeadExcept().
2422 MIB.addRegMask(TRI.getCallPreservedMask(*FuncInfo.MF, CC));
2424 // Finish off the call including any return values.
2425 SmallVector<unsigned, 4> UsedRegs;
2426 if (!FinishCall(RetVT, UsedRegs, I, CC, NumBytes, isVarArg))
2429 // Set all unused physreg defs as dead.
2430 static_cast<MachineInstr *>(MIB)->setPhysRegsDeadExcept(UsedRegs, TRI);
2435 bool ARMFastISel::ARMIsMemCpySmall(uint64_t Len) {
2439 bool ARMFastISel::ARMTryEmitSmallMemCpy(Address Dest, Address Src,
2440 uint64_t Len, unsigned Alignment) {
2441 // Make sure we don't bloat code by inlining very large memcpy's.
2442 if (!ARMIsMemCpySmall(Len))
2447 if (!Alignment || Alignment >= 4) {
2453 assert (Len == 1 && "Expected a length of 1!");
2457 // Bound based on alignment.
2458 if (Len >= 2 && Alignment == 2)
2467 RV = ARMEmitLoad(VT, ResultReg, Src);
2468 assert (RV == true && "Should be able to handle this load.");
2469 RV = ARMEmitStore(VT, ResultReg, Dest);
2470 assert (RV == true && "Should be able to handle this store.");
2473 unsigned Size = VT.getSizeInBits()/8;
2475 Dest.Offset += Size;
2482 bool ARMFastISel::SelectIntrinsicCall(const IntrinsicInst &I) {
2483 // FIXME: Handle more intrinsics.
2484 switch (I.getIntrinsicID()) {
2485 default: return false;
2486 case Intrinsic::frameaddress: {
2487 MachineFrameInfo *MFI = FuncInfo.MF->getFrameInfo();
2488 MFI->setFrameAddressIsTaken(true);
2490 unsigned LdrOpc = isThumb2 ? ARM::t2LDRi12 : ARM::LDRi12;
2491 const TargetRegisterClass *RC = isThumb2 ? &ARM::tGPRRegClass
2492 : &ARM::GPRRegClass;
2494 const ARMBaseRegisterInfo *RegInfo =
2495 static_cast<const ARMBaseRegisterInfo *>(Subtarget->getRegisterInfo());
2496 unsigned FramePtr = RegInfo->getFrameRegister(*(FuncInfo.MF));
2497 unsigned SrcReg = FramePtr;
2499 // Recursively load frame address
2505 unsigned Depth = cast<ConstantInt>(I.getOperand(0))->getZExtValue();
2507 DestReg = createResultReg(RC);
2508 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
2509 TII.get(LdrOpc), DestReg)
2510 .addReg(SrcReg).addImm(0));
2513 updateValueMap(&I, SrcReg);
2516 case Intrinsic::memcpy:
2517 case Intrinsic::memmove: {
2518 const MemTransferInst &MTI = cast<MemTransferInst>(I);
2519 // Don't handle volatile.
2520 if (MTI.isVolatile())
2523 // Disable inlining for memmove before calls to ComputeAddress. Otherwise,
2524 // we would emit dead code because we don't currently handle memmoves.
2525 bool isMemCpy = (I.getIntrinsicID() == Intrinsic::memcpy);
2526 if (isa<ConstantInt>(MTI.getLength()) && isMemCpy) {
2527 // Small memcpy's are common enough that we want to do them without a call
2529 uint64_t Len = cast<ConstantInt>(MTI.getLength())->getZExtValue();
2530 if (ARMIsMemCpySmall(Len)) {
2532 if (!ARMComputeAddress(MTI.getRawDest(), Dest) ||
2533 !ARMComputeAddress(MTI.getRawSource(), Src))
2535 unsigned Alignment = MTI.getAlignment();
2536 if (ARMTryEmitSmallMemCpy(Dest, Src, Len, Alignment))
2541 if (!MTI.getLength()->getType()->isIntegerTy(32))
2544 if (MTI.getSourceAddressSpace() > 255 || MTI.getDestAddressSpace() > 255)
2547 const char *IntrMemName = isa<MemCpyInst>(I) ? "memcpy" : "memmove";
2548 return SelectCall(&I, IntrMemName);
2550 case Intrinsic::memset: {
2551 const MemSetInst &MSI = cast<MemSetInst>(I);
2552 // Don't handle volatile.
2553 if (MSI.isVolatile())
2556 if (!MSI.getLength()->getType()->isIntegerTy(32))
2559 if (MSI.getDestAddressSpace() > 255)
2562 return SelectCall(&I, "memset");
2564 case Intrinsic::trap: {
2565 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(
2566 Subtarget->useNaClTrap() ? ARM::TRAPNaCl : ARM::TRAP));
2572 bool ARMFastISel::SelectTrunc(const Instruction *I) {
2573 // The high bits for a type smaller than the register size are assumed to be
2575 Value *Op = I->getOperand(0);
2578 SrcVT = TLI.getValueType(DL, Op->getType(), true);
2579 DestVT = TLI.getValueType(DL, I->getType(), true);
2581 if (SrcVT != MVT::i32 && SrcVT != MVT::i16 && SrcVT != MVT::i8)
2583 if (DestVT != MVT::i16 && DestVT != MVT::i8 && DestVT != MVT::i1)
2586 unsigned SrcReg = getRegForValue(Op);
2587 if (!SrcReg) return false;
2589 // Because the high bits are undefined, a truncate doesn't generate
2591 updateValueMap(I, SrcReg);
2595 unsigned ARMFastISel::ARMEmitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT,
2597 if (DestVT != MVT::i32 && DestVT != MVT::i16 && DestVT != MVT::i8)
2599 if (SrcVT != MVT::i16 && SrcVT != MVT::i8 && SrcVT != MVT::i1)
2602 // Table of which combinations can be emitted as a single instruction,
2603 // and which will require two.
2604 static const uint8_t isSingleInstrTbl[3][2][2][2] = {
2606 // !hasV6Ops hasV6Ops !hasV6Ops hasV6Ops
2607 // ext: s z s z s z s z
2608 /* 1 */ { { { 0, 1 }, { 0, 1 } }, { { 0, 0 }, { 0, 1 } } },
2609 /* 8 */ { { { 0, 1 }, { 1, 1 } }, { { 0, 0 }, { 1, 1 } } },
2610 /* 16 */ { { { 0, 0 }, { 1, 1 } }, { { 0, 0 }, { 1, 1 } } }
2613 // Target registers for:
2614 // - For ARM can never be PC.
2615 // - For 16-bit Thumb are restricted to lower 8 registers.
2616 // - For 32-bit Thumb are restricted to non-SP and non-PC.
2617 static const TargetRegisterClass *RCTbl[2][2] = {
2618 // Instructions: Two Single
2619 /* ARM */ { &ARM::GPRnopcRegClass, &ARM::GPRnopcRegClass },
2620 /* Thumb */ { &ARM::tGPRRegClass, &ARM::rGPRRegClass }
2623 // Table governing the instruction(s) to be emitted.
2624 static const struct InstructionTable {
2626 uint32_t hasS : 1; // Some instructions have an S bit, always set it to 0.
2627 uint32_t Shift : 7; // For shift operand addressing mode, used by MOVsi.
2628 uint32_t Imm : 8; // All instructions have either a shift or a mask.
2629 } IT[2][2][3][2] = {
2630 { // Two instructions (first is left shift, second is in this table).
2631 { // ARM Opc S Shift Imm
2632 /* 1 bit sext */ { { ARM::MOVsi , 1, ARM_AM::asr , 31 },
2633 /* 1 bit zext */ { ARM::MOVsi , 1, ARM_AM::lsr , 31 } },
2634 /* 8 bit sext */ { { ARM::MOVsi , 1, ARM_AM::asr , 24 },
2635 /* 8 bit zext */ { ARM::MOVsi , 1, ARM_AM::lsr , 24 } },
2636 /* 16 bit sext */ { { ARM::MOVsi , 1, ARM_AM::asr , 16 },
2637 /* 16 bit zext */ { ARM::MOVsi , 1, ARM_AM::lsr , 16 } }
2639 { // Thumb Opc S Shift Imm
2640 /* 1 bit sext */ { { ARM::tASRri , 0, ARM_AM::no_shift, 31 },
2641 /* 1 bit zext */ { ARM::tLSRri , 0, ARM_AM::no_shift, 31 } },
2642 /* 8 bit sext */ { { ARM::tASRri , 0, ARM_AM::no_shift, 24 },
2643 /* 8 bit zext */ { ARM::tLSRri , 0, ARM_AM::no_shift, 24 } },
2644 /* 16 bit sext */ { { ARM::tASRri , 0, ARM_AM::no_shift, 16 },
2645 /* 16 bit zext */ { ARM::tLSRri , 0, ARM_AM::no_shift, 16 } }
2648 { // Single instruction.
2649 { // ARM Opc S Shift Imm
2650 /* 1 bit sext */ { { ARM::KILL , 0, ARM_AM::no_shift, 0 },
2651 /* 1 bit zext */ { ARM::ANDri , 1, ARM_AM::no_shift, 1 } },
2652 /* 8 bit sext */ { { ARM::SXTB , 0, ARM_AM::no_shift, 0 },
2653 /* 8 bit zext */ { ARM::ANDri , 1, ARM_AM::no_shift, 255 } },
2654 /* 16 bit sext */ { { ARM::SXTH , 0, ARM_AM::no_shift, 0 },
2655 /* 16 bit zext */ { ARM::UXTH , 0, ARM_AM::no_shift, 0 } }
2657 { // Thumb Opc S Shift Imm
2658 /* 1 bit sext */ { { ARM::KILL , 0, ARM_AM::no_shift, 0 },
2659 /* 1 bit zext */ { ARM::t2ANDri, 1, ARM_AM::no_shift, 1 } },
2660 /* 8 bit sext */ { { ARM::t2SXTB , 0, ARM_AM::no_shift, 0 },
2661 /* 8 bit zext */ { ARM::t2ANDri, 1, ARM_AM::no_shift, 255 } },
2662 /* 16 bit sext */ { { ARM::t2SXTH , 0, ARM_AM::no_shift, 0 },
2663 /* 16 bit zext */ { ARM::t2UXTH , 0, ARM_AM::no_shift, 0 } }
2668 unsigned SrcBits = SrcVT.getSizeInBits();
2669 unsigned DestBits = DestVT.getSizeInBits();
2671 assert((SrcBits < DestBits) && "can only extend to larger types");
2672 assert((DestBits == 32 || DestBits == 16 || DestBits == 8) &&
2673 "other sizes unimplemented");
2674 assert((SrcBits == 16 || SrcBits == 8 || SrcBits == 1) &&
2675 "other sizes unimplemented");
2677 bool hasV6Ops = Subtarget->hasV6Ops();
2678 unsigned Bitness = SrcBits / 8; // {1,8,16}=>{0,1,2}
2679 assert((Bitness < 3) && "sanity-check table bounds");
2681 bool isSingleInstr = isSingleInstrTbl[Bitness][isThumb2][hasV6Ops][isZExt];
2682 const TargetRegisterClass *RC = RCTbl[isThumb2][isSingleInstr];
2683 const InstructionTable *ITP = &IT[isSingleInstr][isThumb2][Bitness][isZExt];
2684 unsigned Opc = ITP->Opc;
2685 assert(ARM::KILL != Opc && "Invalid table entry");
2686 unsigned hasS = ITP->hasS;
2687 ARM_AM::ShiftOpc Shift = (ARM_AM::ShiftOpc) ITP->Shift;
2688 assert(((Shift == ARM_AM::no_shift) == (Opc != ARM::MOVsi)) &&
2689 "only MOVsi has shift operand addressing mode");
2690 unsigned Imm = ITP->Imm;
2692 // 16-bit Thumb instructions always set CPSR (unless they're in an IT block).
2693 bool setsCPSR = &ARM::tGPRRegClass == RC;
2694 unsigned LSLOpc = isThumb2 ? ARM::tLSLri : ARM::MOVsi;
2696 // MOVsi encodes shift and immediate in shift operand addressing mode.
2697 // The following condition has the same value when emitting two
2698 // instruction sequences: both are shifts.
2699 bool ImmIsSO = (Shift != ARM_AM::no_shift);
2701 // Either one or two instructions are emitted.
2702 // They're always of the form:
2704 // CPSR is set only by 16-bit Thumb instructions.
2705 // Predicate, if any, is AL.
2706 // S bit, if available, is always 0.
2707 // When two are emitted the first's result will feed as the second's input,
2708 // that value is then dead.
2709 unsigned NumInstrsEmitted = isSingleInstr ? 1 : 2;
2710 for (unsigned Instr = 0; Instr != NumInstrsEmitted; ++Instr) {
2711 ResultReg = createResultReg(RC);
2712 bool isLsl = (0 == Instr) && !isSingleInstr;
2713 unsigned Opcode = isLsl ? LSLOpc : Opc;
2714 ARM_AM::ShiftOpc ShiftAM = isLsl ? ARM_AM::lsl : Shift;
2715 unsigned ImmEnc = ImmIsSO ? ARM_AM::getSORegOpc(ShiftAM, Imm) : Imm;
2716 bool isKill = 1 == Instr;
2717 MachineInstrBuilder MIB = BuildMI(
2718 *FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opcode), ResultReg);
2720 MIB.addReg(ARM::CPSR, RegState::Define);
2721 SrcReg = constrainOperandRegClass(TII.get(Opcode), SrcReg, 1 + setsCPSR);
2722 AddDefaultPred(MIB.addReg(SrcReg, isKill * RegState::Kill).addImm(ImmEnc));
2725 // Second instruction consumes the first's result.
2732 bool ARMFastISel::SelectIntExt(const Instruction *I) {
2733 // On ARM, in general, integer casts don't involve legal types; this code
2734 // handles promotable integers.
2735 Type *DestTy = I->getType();
2736 Value *Src = I->getOperand(0);
2737 Type *SrcTy = Src->getType();
2739 bool isZExt = isa<ZExtInst>(I);
2740 unsigned SrcReg = getRegForValue(Src);
2741 if (!SrcReg) return false;
2743 EVT SrcEVT, DestEVT;
2744 SrcEVT = TLI.getValueType(DL, SrcTy, true);
2745 DestEVT = TLI.getValueType(DL, DestTy, true);
2746 if (!SrcEVT.isSimple()) return false;
2747 if (!DestEVT.isSimple()) return false;
2749 MVT SrcVT = SrcEVT.getSimpleVT();
2750 MVT DestVT = DestEVT.getSimpleVT();
2751 unsigned ResultReg = ARMEmitIntExt(SrcVT, SrcReg, DestVT, isZExt);
2752 if (ResultReg == 0) return false;
2753 updateValueMap(I, ResultReg);
2757 bool ARMFastISel::SelectShift(const Instruction *I,
2758 ARM_AM::ShiftOpc ShiftTy) {
2759 // We handle thumb2 mode by target independent selector
2760 // or SelectionDAG ISel.
2764 // Only handle i32 now.
2765 EVT DestVT = TLI.getValueType(DL, I->getType(), true);
2766 if (DestVT != MVT::i32)
2769 unsigned Opc = ARM::MOVsr;
2771 Value *Src2Value = I->getOperand(1);
2772 if (const ConstantInt *CI = dyn_cast<ConstantInt>(Src2Value)) {
2773 ShiftImm = CI->getZExtValue();
2775 // Fall back to selection DAG isel if the shift amount
2776 // is zero or greater than the width of the value type.
2777 if (ShiftImm == 0 || ShiftImm >=32)
2783 Value *Src1Value = I->getOperand(0);
2784 unsigned Reg1 = getRegForValue(Src1Value);
2785 if (Reg1 == 0) return false;
2788 if (Opc == ARM::MOVsr) {
2789 Reg2 = getRegForValue(Src2Value);
2790 if (Reg2 == 0) return false;
2793 unsigned ResultReg = createResultReg(&ARM::GPRnopcRegClass);
2794 if(ResultReg == 0) return false;
2796 MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
2797 TII.get(Opc), ResultReg)
2800 if (Opc == ARM::MOVsi)
2801 MIB.addImm(ARM_AM::getSORegOpc(ShiftTy, ShiftImm));
2802 else if (Opc == ARM::MOVsr) {
2804 MIB.addImm(ARM_AM::getSORegOpc(ShiftTy, 0));
2807 AddOptionalDefs(MIB);
2808 updateValueMap(I, ResultReg);
2812 // TODO: SoftFP support.
2813 bool ARMFastISel::fastSelectInstruction(const Instruction *I) {
2815 switch (I->getOpcode()) {
2816 case Instruction::Load:
2817 return SelectLoad(I);
2818 case Instruction::Store:
2819 return SelectStore(I);
2820 case Instruction::Br:
2821 return SelectBranch(I);
2822 case Instruction::IndirectBr:
2823 return SelectIndirectBr(I);
2824 case Instruction::ICmp:
2825 case Instruction::FCmp:
2826 return SelectCmp(I);
2827 case Instruction::FPExt:
2828 return SelectFPExt(I);
2829 case Instruction::FPTrunc:
2830 return SelectFPTrunc(I);
2831 case Instruction::SIToFP:
2832 return SelectIToFP(I, /*isSigned*/ true);
2833 case Instruction::UIToFP:
2834 return SelectIToFP(I, /*isSigned*/ false);
2835 case Instruction::FPToSI:
2836 return SelectFPToI(I, /*isSigned*/ true);
2837 case Instruction::FPToUI:
2838 return SelectFPToI(I, /*isSigned*/ false);
2839 case Instruction::Add:
2840 return SelectBinaryIntOp(I, ISD::ADD);
2841 case Instruction::Or:
2842 return SelectBinaryIntOp(I, ISD::OR);
2843 case Instruction::Sub:
2844 return SelectBinaryIntOp(I, ISD::SUB);
2845 case Instruction::FAdd:
2846 return SelectBinaryFPOp(I, ISD::FADD);
2847 case Instruction::FSub:
2848 return SelectBinaryFPOp(I, ISD::FSUB);
2849 case Instruction::FMul:
2850 return SelectBinaryFPOp(I, ISD::FMUL);
2851 case Instruction::SDiv:
2852 return SelectDiv(I, /*isSigned*/ true);
2853 case Instruction::UDiv:
2854 return SelectDiv(I, /*isSigned*/ false);
2855 case Instruction::SRem:
2856 return SelectRem(I, /*isSigned*/ true);
2857 case Instruction::URem:
2858 return SelectRem(I, /*isSigned*/ false);
2859 case Instruction::Call:
2860 if (const IntrinsicInst *II = dyn_cast<IntrinsicInst>(I))
2861 return SelectIntrinsicCall(*II);
2862 return SelectCall(I);
2863 case Instruction::Select:
2864 return SelectSelect(I);
2865 case Instruction::Ret:
2866 return SelectRet(I);
2867 case Instruction::Trunc:
2868 return SelectTrunc(I);
2869 case Instruction::ZExt:
2870 case Instruction::SExt:
2871 return SelectIntExt(I);
2872 case Instruction::Shl:
2873 return SelectShift(I, ARM_AM::lsl);
2874 case Instruction::LShr:
2875 return SelectShift(I, ARM_AM::lsr);
2876 case Instruction::AShr:
2877 return SelectShift(I, ARM_AM::asr);
2884 // This table describes sign- and zero-extend instructions which can be
2885 // folded into a preceding load. All of these extends have an immediate
2886 // (sometimes a mask and sometimes a shift) that's applied after
2888 const struct FoldableLoadExtendsStruct {
2889 uint16_t Opc[2]; // ARM, Thumb.
2890 uint8_t ExpectedImm;
2892 uint8_t ExpectedVT : 7;
2893 } FoldableLoadExtends[] = {
2894 { { ARM::SXTH, ARM::t2SXTH }, 0, 0, MVT::i16 },
2895 { { ARM::UXTH, ARM::t2UXTH }, 0, 1, MVT::i16 },
2896 { { ARM::ANDri, ARM::t2ANDri }, 255, 1, MVT::i8 },
2897 { { ARM::SXTB, ARM::t2SXTB }, 0, 0, MVT::i8 },
2898 { { ARM::UXTB, ARM::t2UXTB }, 0, 1, MVT::i8 }
2902 /// \brief The specified machine instr operand is a vreg, and that
2903 /// vreg is being provided by the specified load instruction. If possible,
2904 /// try to fold the load as an operand to the instruction, returning true if
2906 bool ARMFastISel::tryToFoldLoadIntoMI(MachineInstr *MI, unsigned OpNo,
2907 const LoadInst *LI) {
2908 // Verify we have a legal type before going any further.
2910 if (!isLoadTypeLegal(LI->getType(), VT))
2913 // Combine load followed by zero- or sign-extend.
2914 // ldrb r1, [r0] ldrb r1, [r0]
2916 // mov r3, r2 mov r3, r1
2917 if (MI->getNumOperands() < 3 || !MI->getOperand(2).isImm())
2919 const uint64_t Imm = MI->getOperand(2).getImm();
2923 for (unsigned i = 0, e = array_lengthof(FoldableLoadExtends);
2925 if (FoldableLoadExtends[i].Opc[isThumb2] == MI->getOpcode() &&
2926 (uint64_t)FoldableLoadExtends[i].ExpectedImm == Imm &&
2927 MVT((MVT::SimpleValueType)FoldableLoadExtends[i].ExpectedVT) == VT) {
2929 isZExt = FoldableLoadExtends[i].isZExt;
2932 if (!Found) return false;
2934 // See if we can handle this address.
2936 if (!ARMComputeAddress(LI->getOperand(0), Addr)) return false;
2938 unsigned ResultReg = MI->getOperand(0).getReg();
2939 if (!ARMEmitLoad(VT, ResultReg, Addr, LI->getAlignment(), isZExt, false))
2941 MI->eraseFromParent();
2945 unsigned ARMFastISel::ARMLowerPICELF(const GlobalValue *GV,
2946 unsigned Align, MVT VT) {
2947 bool UseGOTOFF = GV->hasLocalLinkage() || GV->hasHiddenVisibility();
2948 ARMConstantPoolConstant *CPV =
2949 ARMConstantPoolConstant::Create(GV, UseGOTOFF ? ARMCP::GOTOFF : ARMCP::GOT);
2950 unsigned Idx = MCP.getConstantPoolIndex(CPV, Align);
2953 unsigned DestReg1 = createResultReg(TLI.getRegClassFor(VT));
2956 DestReg1 = constrainOperandRegClass(TII.get(ARM::t2LDRpci), DestReg1, 0);
2957 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
2958 TII.get(ARM::t2LDRpci), DestReg1)
2959 .addConstantPoolIndex(Idx));
2960 Opc = UseGOTOFF ? ARM::t2ADDrr : ARM::t2LDRs;
2962 // The extra immediate is for addrmode2.
2963 DestReg1 = constrainOperandRegClass(TII.get(ARM::LDRcp), DestReg1, 0);
2964 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt,
2965 DbgLoc, TII.get(ARM::LDRcp), DestReg1)
2966 .addConstantPoolIndex(Idx).addImm(0));
2967 Opc = UseGOTOFF ? ARM::ADDrr : ARM::LDRrs;
2970 unsigned GlobalBaseReg = AFI->getGlobalBaseReg();
2971 if (GlobalBaseReg == 0) {
2972 GlobalBaseReg = MRI.createVirtualRegister(TLI.getRegClassFor(VT));
2973 AFI->setGlobalBaseReg(GlobalBaseReg);
2976 unsigned DestReg2 = createResultReg(TLI.getRegClassFor(VT));
2977 DestReg2 = constrainOperandRegClass(TII.get(Opc), DestReg2, 0);
2978 DestReg1 = constrainOperandRegClass(TII.get(Opc), DestReg1, 1);
2979 GlobalBaseReg = constrainOperandRegClass(TII.get(Opc), GlobalBaseReg, 2);
2980 MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt,
2981 DbgLoc, TII.get(Opc), DestReg2)
2983 .addReg(GlobalBaseReg);
2986 AddOptionalDefs(MIB);
2991 bool ARMFastISel::fastLowerArguments() {
2992 if (!FuncInfo.CanLowerReturn)
2995 const Function *F = FuncInfo.Fn;
2999 CallingConv::ID CC = F->getCallingConv();
3003 case CallingConv::Fast:
3004 case CallingConv::C:
3005 case CallingConv::ARM_AAPCS_VFP:
3006 case CallingConv::ARM_AAPCS:
3007 case CallingConv::ARM_APCS:
3011 // Only handle simple cases. i.e. Up to 4 i8/i16/i32 scalar arguments
3012 // which are passed in r0 - r3.
3014 for (Function::const_arg_iterator I = F->arg_begin(), E = F->arg_end();
3015 I != E; ++I, ++Idx) {
3019 if (F->getAttributes().hasAttribute(Idx, Attribute::InReg) ||
3020 F->getAttributes().hasAttribute(Idx, Attribute::StructRet) ||
3021 F->getAttributes().hasAttribute(Idx, Attribute::ByVal))
3024 Type *ArgTy = I->getType();
3025 if (ArgTy->isStructTy() || ArgTy->isArrayTy() || ArgTy->isVectorTy())
3028 EVT ArgVT = TLI.getValueType(DL, ArgTy);
3029 if (!ArgVT.isSimple()) return false;
3030 switch (ArgVT.getSimpleVT().SimpleTy) {
3041 static const uint16_t GPRArgRegs[] = {
3042 ARM::R0, ARM::R1, ARM::R2, ARM::R3
3045 const TargetRegisterClass *RC = &ARM::rGPRRegClass;
3047 for (Function::const_arg_iterator I = F->arg_begin(), E = F->arg_end();
3048 I != E; ++I, ++Idx) {
3049 unsigned SrcReg = GPRArgRegs[Idx];
3050 unsigned DstReg = FuncInfo.MF->addLiveIn(SrcReg, RC);
3051 // FIXME: Unfortunately it's necessary to emit a copy from the livein copy.
3052 // Without this, EmitLiveInCopies may eliminate the livein if its only
3053 // use is a bitcast (which isn't turned into an instruction).
3054 unsigned ResultReg = createResultReg(RC);
3055 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
3056 TII.get(TargetOpcode::COPY),
3057 ResultReg).addReg(DstReg, getKillRegState(true));
3058 updateValueMap(I, ResultReg);
3065 FastISel *ARM::createFastISel(FunctionLoweringInfo &funcInfo,
3066 const TargetLibraryInfo *libInfo) {
3067 if (funcInfo.MF->getSubtarget<ARMSubtarget>().useFastISel())
3068 return new ARMFastISel(funcInfo, libInfo);