1 //===-- ARMFastISel.cpp - ARM FastISel implementation ---------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the ARM-specific support for the FastISel class. Some
11 // of the target-specific code is generated by tablegen in the file
12 // ARMGenFastISel.inc, which is #included here.
14 //===----------------------------------------------------------------------===//
17 #include "ARMBaseInstrInfo.h"
18 #include "ARMCallingConv.h"
19 #include "ARMRegisterInfo.h"
20 #include "ARMTargetMachine.h"
21 #include "ARMSubtarget.h"
22 #include "ARMConstantPoolValue.h"
23 #include "llvm/CallingConv.h"
24 #include "llvm/DerivedTypes.h"
25 #include "llvm/GlobalVariable.h"
26 #include "llvm/Instructions.h"
27 #include "llvm/IntrinsicInst.h"
28 #include "llvm/Module.h"
29 #include "llvm/CodeGen/Analysis.h"
30 #include "llvm/CodeGen/FastISel.h"
31 #include "llvm/CodeGen/FunctionLoweringInfo.h"
32 #include "llvm/CodeGen/MachineInstrBuilder.h"
33 #include "llvm/CodeGen/MachineModuleInfo.h"
34 #include "llvm/CodeGen/MachineConstantPool.h"
35 #include "llvm/CodeGen/MachineFrameInfo.h"
36 #include "llvm/CodeGen/MachineMemOperand.h"
37 #include "llvm/CodeGen/MachineRegisterInfo.h"
38 #include "llvm/CodeGen/PseudoSourceValue.h"
39 #include "llvm/Support/CallSite.h"
40 #include "llvm/Support/CommandLine.h"
41 #include "llvm/Support/ErrorHandling.h"
42 #include "llvm/Support/GetElementPtrTypeIterator.h"
43 #include "llvm/Target/TargetData.h"
44 #include "llvm/Target/TargetInstrInfo.h"
45 #include "llvm/Target/TargetLowering.h"
46 #include "llvm/Target/TargetMachine.h"
47 #include "llvm/Target/TargetOptions.h"
51 DisableARMFastISel("disable-arm-fast-isel",
52 cl::desc("Turn off experimental ARM fast-isel support"),
53 cl::init(false), cl::Hidden);
57 class ARMFastISel : public FastISel {
59 /// Subtarget - Keep a pointer to the ARMSubtarget around so that we can
60 /// make the right decision when generating code for different targets.
61 const ARMSubtarget *Subtarget;
62 const TargetMachine &TM;
63 const TargetInstrInfo &TII;
64 const TargetLowering &TLI;
67 // Convenience variables to avoid some queries.
72 explicit ARMFastISel(FunctionLoweringInfo &funcInfo)
74 TM(funcInfo.MF->getTarget()),
75 TII(*TM.getInstrInfo()),
76 TLI(*TM.getTargetLowering()) {
77 Subtarget = &TM.getSubtarget<ARMSubtarget>();
78 AFI = funcInfo.MF->getInfo<ARMFunctionInfo>();
79 isThumb = AFI->isThumbFunction();
80 Context = &funcInfo.Fn->getContext();
83 // Code from FastISel.cpp.
84 virtual unsigned FastEmitInst_(unsigned MachineInstOpcode,
85 const TargetRegisterClass *RC);
86 virtual unsigned FastEmitInst_r(unsigned MachineInstOpcode,
87 const TargetRegisterClass *RC,
88 unsigned Op0, bool Op0IsKill);
89 virtual unsigned FastEmitInst_rr(unsigned MachineInstOpcode,
90 const TargetRegisterClass *RC,
91 unsigned Op0, bool Op0IsKill,
92 unsigned Op1, bool Op1IsKill);
93 virtual unsigned FastEmitInst_ri(unsigned MachineInstOpcode,
94 const TargetRegisterClass *RC,
95 unsigned Op0, bool Op0IsKill,
97 virtual unsigned FastEmitInst_rf(unsigned MachineInstOpcode,
98 const TargetRegisterClass *RC,
99 unsigned Op0, bool Op0IsKill,
100 const ConstantFP *FPImm);
101 virtual unsigned FastEmitInst_i(unsigned MachineInstOpcode,
102 const TargetRegisterClass *RC,
104 virtual unsigned FastEmitInst_rri(unsigned MachineInstOpcode,
105 const TargetRegisterClass *RC,
106 unsigned Op0, bool Op0IsKill,
107 unsigned Op1, bool Op1IsKill,
109 virtual unsigned FastEmitInst_extractsubreg(MVT RetVT,
110 unsigned Op0, bool Op0IsKill,
113 // Backend specific FastISel code.
114 virtual bool TargetSelectInstruction(const Instruction *I);
115 virtual unsigned TargetMaterializeConstant(const Constant *C);
116 virtual unsigned TargetMaterializeAlloca(const AllocaInst *AI);
118 #include "ARMGenFastISel.inc"
120 // Instruction selection routines.
122 virtual bool SelectLoad(const Instruction *I);
123 virtual bool SelectStore(const Instruction *I);
124 virtual bool SelectBranch(const Instruction *I);
125 virtual bool SelectCmp(const Instruction *I);
126 virtual bool SelectFPExt(const Instruction *I);
127 virtual bool SelectFPTrunc(const Instruction *I);
128 virtual bool SelectBinaryOp(const Instruction *I, unsigned ISDOpcode);
129 virtual bool SelectSIToFP(const Instruction *I);
130 virtual bool SelectFPToSI(const Instruction *I);
131 virtual bool SelectSDiv(const Instruction *I);
132 virtual bool SelectSRem(const Instruction *I);
133 virtual bool SelectCall(const Instruction *I);
134 virtual bool SelectSelect(const Instruction *I);
138 bool isTypeLegal(const Type *Ty, EVT &VT);
139 bool isLoadTypeLegal(const Type *Ty, EVT &VT);
140 bool ARMEmitLoad(EVT VT, unsigned &ResultReg, unsigned Base, int Offset);
141 bool ARMEmitStore(EVT VT, unsigned SrcReg, unsigned Base, int Offset);
142 bool ARMComputeRegOffset(const Value *Obj, unsigned &Base, int &Offset);
143 void ARMSimplifyRegOffset(unsigned &Base, int &Offset, EVT VT);
144 unsigned ARMMaterializeFP(const ConstantFP *CFP, EVT VT);
145 unsigned ARMMaterializeInt(const Constant *C, EVT VT);
146 unsigned ARMMaterializeGV(const GlobalValue *GV, EVT VT);
147 unsigned ARMMoveToFPReg(EVT VT, unsigned SrcReg);
148 unsigned ARMMoveToIntReg(EVT VT, unsigned SrcReg);
150 // Call handling routines.
152 bool FastEmitExtend(ISD::NodeType Opc, EVT DstVT, unsigned Src, EVT SrcVT,
153 unsigned &ResultReg);
154 CCAssignFn *CCAssignFnForCall(CallingConv::ID CC, bool Return);
155 bool ProcessCallArgs(SmallVectorImpl<Value*> &Args,
156 SmallVectorImpl<unsigned> &ArgRegs,
157 SmallVectorImpl<EVT> &ArgVTs,
158 SmallVectorImpl<ISD::ArgFlagsTy> &ArgFlags,
159 SmallVectorImpl<unsigned> &RegArgs,
162 bool FinishCall(EVT RetVT, SmallVectorImpl<unsigned> &UsedRegs,
163 const Instruction *I, CallingConv::ID CC,
165 bool ARMEmitLibcall(const Instruction *I, RTLIB::Libcall Call);
167 // OptionalDef handling routines.
169 bool DefinesOptionalPredicate(MachineInstr *MI, bool *CPSR);
170 const MachineInstrBuilder &AddOptionalDefs(const MachineInstrBuilder &MIB);
173 } // end anonymous namespace
175 #include "ARMGenCallingConv.inc"
177 // DefinesOptionalPredicate - This is different from DefinesPredicate in that
178 // we don't care about implicit defs here, just places we'll need to add a
179 // default CCReg argument. Sets CPSR if we're setting CPSR instead of CCR.
180 bool ARMFastISel::DefinesOptionalPredicate(MachineInstr *MI, bool *CPSR) {
181 const TargetInstrDesc &TID = MI->getDesc();
182 if (!TID.hasOptionalDef())
185 // Look to see if our OptionalDef is defining CPSR or CCR.
186 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
187 const MachineOperand &MO = MI->getOperand(i);
188 if (!MO.isReg() || !MO.isDef()) continue;
189 if (MO.getReg() == ARM::CPSR)
195 // If the machine is predicable go ahead and add the predicate operands, if
196 // it needs default CC operands add those.
197 const MachineInstrBuilder &
198 ARMFastISel::AddOptionalDefs(const MachineInstrBuilder &MIB) {
199 MachineInstr *MI = &*MIB;
201 // Do we use a predicate?
202 if (TII.isPredicable(MI))
205 // Do we optionally set a predicate? Preds is size > 0 iff the predicate
206 // defines CPSR. All other OptionalDefines in ARM are the CCR register.
208 if (DefinesOptionalPredicate(MI, &CPSR)) {
217 unsigned ARMFastISel::FastEmitInst_(unsigned MachineInstOpcode,
218 const TargetRegisterClass* RC) {
219 unsigned ResultReg = createResultReg(RC);
220 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
222 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg));
226 unsigned ARMFastISel::FastEmitInst_r(unsigned MachineInstOpcode,
227 const TargetRegisterClass *RC,
228 unsigned Op0, bool Op0IsKill) {
229 unsigned ResultReg = createResultReg(RC);
230 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
232 if (II.getNumDefs() >= 1)
233 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
234 .addReg(Op0, Op0IsKill * RegState::Kill));
236 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
237 .addReg(Op0, Op0IsKill * RegState::Kill));
238 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
239 TII.get(TargetOpcode::COPY), ResultReg)
240 .addReg(II.ImplicitDefs[0]));
245 unsigned ARMFastISel::FastEmitInst_rr(unsigned MachineInstOpcode,
246 const TargetRegisterClass *RC,
247 unsigned Op0, bool Op0IsKill,
248 unsigned Op1, bool Op1IsKill) {
249 unsigned ResultReg = createResultReg(RC);
250 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
252 if (II.getNumDefs() >= 1)
253 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
254 .addReg(Op0, Op0IsKill * RegState::Kill)
255 .addReg(Op1, Op1IsKill * RegState::Kill));
257 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
258 .addReg(Op0, Op0IsKill * RegState::Kill)
259 .addReg(Op1, Op1IsKill * RegState::Kill));
260 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
261 TII.get(TargetOpcode::COPY), ResultReg)
262 .addReg(II.ImplicitDefs[0]));
267 unsigned ARMFastISel::FastEmitInst_ri(unsigned MachineInstOpcode,
268 const TargetRegisterClass *RC,
269 unsigned Op0, bool Op0IsKill,
271 unsigned ResultReg = createResultReg(RC);
272 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
274 if (II.getNumDefs() >= 1)
275 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
276 .addReg(Op0, Op0IsKill * RegState::Kill)
279 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
280 .addReg(Op0, Op0IsKill * RegState::Kill)
282 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
283 TII.get(TargetOpcode::COPY), ResultReg)
284 .addReg(II.ImplicitDefs[0]));
289 unsigned ARMFastISel::FastEmitInst_rf(unsigned MachineInstOpcode,
290 const TargetRegisterClass *RC,
291 unsigned Op0, bool Op0IsKill,
292 const ConstantFP *FPImm) {
293 unsigned ResultReg = createResultReg(RC);
294 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
296 if (II.getNumDefs() >= 1)
297 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
298 .addReg(Op0, Op0IsKill * RegState::Kill)
301 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
302 .addReg(Op0, Op0IsKill * RegState::Kill)
304 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
305 TII.get(TargetOpcode::COPY), ResultReg)
306 .addReg(II.ImplicitDefs[0]));
311 unsigned ARMFastISel::FastEmitInst_rri(unsigned MachineInstOpcode,
312 const TargetRegisterClass *RC,
313 unsigned Op0, bool Op0IsKill,
314 unsigned Op1, bool Op1IsKill,
316 unsigned ResultReg = createResultReg(RC);
317 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
319 if (II.getNumDefs() >= 1)
320 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
321 .addReg(Op0, Op0IsKill * RegState::Kill)
322 .addReg(Op1, Op1IsKill * RegState::Kill)
325 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
326 .addReg(Op0, Op0IsKill * RegState::Kill)
327 .addReg(Op1, Op1IsKill * RegState::Kill)
329 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
330 TII.get(TargetOpcode::COPY), ResultReg)
331 .addReg(II.ImplicitDefs[0]));
336 unsigned ARMFastISel::FastEmitInst_i(unsigned MachineInstOpcode,
337 const TargetRegisterClass *RC,
339 unsigned ResultReg = createResultReg(RC);
340 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
342 if (II.getNumDefs() >= 1)
343 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
346 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
348 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
349 TII.get(TargetOpcode::COPY), ResultReg)
350 .addReg(II.ImplicitDefs[0]));
355 unsigned ARMFastISel::FastEmitInst_extractsubreg(MVT RetVT,
356 unsigned Op0, bool Op0IsKill,
358 unsigned ResultReg = createResultReg(TLI.getRegClassFor(RetVT));
359 assert(TargetRegisterInfo::isVirtualRegister(Op0) &&
360 "Cannot yet extract from physregs");
361 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt,
362 DL, TII.get(TargetOpcode::COPY), ResultReg)
363 .addReg(Op0, getKillRegState(Op0IsKill), Idx));
367 // TODO: Don't worry about 64-bit now, but when this is fixed remove the
368 // checks from the various callers.
369 unsigned ARMFastISel::ARMMoveToFPReg(EVT VT, unsigned SrcReg) {
370 if (VT.getSimpleVT().SimpleTy == MVT::f64) return 0;
372 unsigned MoveReg = createResultReg(TLI.getRegClassFor(VT));
373 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
374 TII.get(ARM::VMOVRS), MoveReg)
379 unsigned ARMFastISel::ARMMoveToIntReg(EVT VT, unsigned SrcReg) {
380 if (VT.getSimpleVT().SimpleTy == MVT::i64) return 0;
382 unsigned MoveReg = createResultReg(TLI.getRegClassFor(VT));
383 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
384 TII.get(ARM::VMOVSR), MoveReg)
389 // For double width floating point we need to materialize two constants
390 // (the high and the low) into integer registers then use a move to get
391 // the combined constant into an FP reg.
392 unsigned ARMFastISel::ARMMaterializeFP(const ConstantFP *CFP, EVT VT) {
393 const APFloat Val = CFP->getValueAPF();
394 bool is64bit = VT.getSimpleVT().SimpleTy == MVT::f64;
396 // This checks to see if we can use VFP3 instructions to materialize
397 // a constant, otherwise we have to go through the constant pool.
398 if (TLI.isFPImmLegal(Val, VT)) {
399 unsigned Opc = is64bit ? ARM::FCONSTD : ARM::FCONSTS;
400 unsigned DestReg = createResultReg(TLI.getRegClassFor(VT));
401 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc),
407 // Require VFP2 for loading fp constants.
408 if (!Subtarget->hasVFP2()) return false;
410 // MachineConstantPool wants an explicit alignment.
411 unsigned Align = TD.getPrefTypeAlignment(CFP->getType());
413 // TODO: Figure out if this is correct.
414 Align = TD.getTypeAllocSize(CFP->getType());
416 unsigned Idx = MCP.getConstantPoolIndex(cast<Constant>(CFP), Align);
417 unsigned DestReg = createResultReg(TLI.getRegClassFor(VT));
418 unsigned Opc = is64bit ? ARM::VLDRD : ARM::VLDRS;
420 // The extra reg is for addrmode5.
421 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc),
423 .addConstantPoolIndex(Idx)
428 unsigned ARMFastISel::ARMMaterializeInt(const Constant *C, EVT VT) {
430 // For now 32-bit only.
431 if (VT.getSimpleVT().SimpleTy != MVT::i32) return false;
433 // MachineConstantPool wants an explicit alignment.
434 unsigned Align = TD.getPrefTypeAlignment(C->getType());
436 // TODO: Figure out if this is correct.
437 Align = TD.getTypeAllocSize(C->getType());
439 unsigned Idx = MCP.getConstantPoolIndex(C, Align);
440 unsigned DestReg = createResultReg(TLI.getRegClassFor(VT));
443 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
444 TII.get(ARM::t2LDRpci), DestReg)
445 .addConstantPoolIndex(Idx));
447 // The extra reg and immediate are for addrmode2.
448 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
449 TII.get(ARM::LDRcp), DestReg)
450 .addConstantPoolIndex(Idx)
451 .addReg(0).addImm(0));
456 unsigned ARMFastISel::ARMMaterializeGV(const GlobalValue *GV, EVT VT) {
457 // For now 32-bit only.
458 if (VT.getSimpleVT().SimpleTy != MVT::i32) return 0;
460 Reloc::Model RelocM = TM.getRelocationModel();
462 // TODO: No external globals for now.
463 if (Subtarget->GVIsIndirectSymbol(GV, RelocM)) return 0;
465 // TODO: Need more magic for ARM PIC.
466 if (!isThumb && (RelocM == Reloc::PIC_)) return 0;
468 // MachineConstantPool wants an explicit alignment.
469 unsigned Align = TD.getPrefTypeAlignment(GV->getType());
471 // TODO: Figure out if this is correct.
472 Align = TD.getTypeAllocSize(GV->getType());
476 unsigned PCAdj = (RelocM != Reloc::PIC_) ? 0 : (Subtarget->isThumb() ? 4 : 8);
477 unsigned Id = AFI->createConstPoolEntryUId();
478 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(GV, Id,
479 ARMCP::CPValue, PCAdj);
480 unsigned Idx = MCP.getConstantPoolIndex(CPV, Align);
483 MachineInstrBuilder MIB;
484 unsigned DestReg = createResultReg(TLI.getRegClassFor(VT));
486 unsigned Opc = (RelocM != Reloc::PIC_) ? ARM::t2LDRpci : ARM::t2LDRpci_pic;
487 MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc), DestReg)
488 .addConstantPoolIndex(Idx);
489 if (RelocM == Reloc::PIC_)
492 // The extra reg and immediate are for addrmode2.
493 MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(ARM::LDRcp),
495 .addConstantPoolIndex(Idx)
496 .addReg(0).addImm(0);
498 AddOptionalDefs(MIB);
502 unsigned ARMFastISel::TargetMaterializeConstant(const Constant *C) {
503 EVT VT = TLI.getValueType(C->getType(), true);
505 // Only handle simple types.
506 if (!VT.isSimple()) return 0;
508 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(C))
509 return ARMMaterializeFP(CFP, VT);
510 else if (const GlobalValue *GV = dyn_cast<GlobalValue>(C))
511 return ARMMaterializeGV(GV, VT);
512 else if (isa<ConstantInt>(C))
513 return ARMMaterializeInt(C, VT);
518 unsigned ARMFastISel::TargetMaterializeAlloca(const AllocaInst *AI) {
519 // Don't handle dynamic allocas.
520 if (!FuncInfo.StaticAllocaMap.count(AI)) return 0;
523 if (!isLoadTypeLegal(AI->getType(), VT)) return false;
525 DenseMap<const AllocaInst*, int>::iterator SI =
526 FuncInfo.StaticAllocaMap.find(AI);
528 // This will get lowered later into the correct offsets and registers
529 // via rewriteXFrameIndex.
530 if (SI != FuncInfo.StaticAllocaMap.end()) {
531 TargetRegisterClass* RC = TLI.getRegClassFor(VT);
532 unsigned ResultReg = createResultReg(RC);
533 unsigned Opc = isThumb ? ARM::t2ADDri : ARM::ADDri;
534 AddOptionalDefs(BuildMI(*FuncInfo.MBB, *FuncInfo.InsertPt, DL,
535 TII.get(Opc), ResultReg)
536 .addFrameIndex(SI->second)
544 bool ARMFastISel::isTypeLegal(const Type *Ty, EVT &VT) {
545 VT = TLI.getValueType(Ty, true);
547 // Only handle simple types.
548 if (VT == MVT::Other || !VT.isSimple()) return false;
550 // Handle all legal types, i.e. a register that will directly hold this
552 return TLI.isTypeLegal(VT);
555 bool ARMFastISel::isLoadTypeLegal(const Type *Ty, EVT &VT) {
556 if (isTypeLegal(Ty, VT)) return true;
558 // If this is a type than can be sign or zero-extended to a basic operation
559 // go ahead and accept it now.
560 if (VT == MVT::i8 || VT == MVT::i16)
566 // Computes the Reg+Offset to get to an object.
567 bool ARMFastISel::ARMComputeRegOffset(const Value *Obj, unsigned &Base,
569 // Some boilerplate from the X86 FastISel.
570 const User *U = NULL;
571 unsigned Opcode = Instruction::UserOp1;
572 if (const Instruction *I = dyn_cast<Instruction>(Obj)) {
573 // Don't walk into other basic blocks; it's possible we haven't
574 // visited them yet, so the instructions may not yet be assigned
575 // virtual registers.
576 if (FuncInfo.MBBMap[I->getParent()] != FuncInfo.MBB)
578 Opcode = I->getOpcode();
580 } else if (const ConstantExpr *C = dyn_cast<ConstantExpr>(Obj)) {
581 Opcode = C->getOpcode();
585 if (const PointerType *Ty = dyn_cast<PointerType>(Obj->getType()))
586 if (Ty->getAddressSpace() > 255)
587 // Fast instruction selection doesn't support the special
594 case Instruction::BitCast: {
595 // Look through bitcasts.
596 return ARMComputeRegOffset(U->getOperand(0), Base, Offset);
598 case Instruction::IntToPtr: {
599 // Look past no-op inttoptrs.
600 if (TLI.getValueType(U->getOperand(0)->getType()) == TLI.getPointerTy())
601 return ARMComputeRegOffset(U->getOperand(0), Base, Offset);
604 case Instruction::PtrToInt: {
605 // Look past no-op ptrtoints.
606 if (TLI.getValueType(U->getType()) == TLI.getPointerTy())
607 return ARMComputeRegOffset(U->getOperand(0), Base, Offset);
610 case Instruction::GetElementPtr: {
611 int SavedOffset = Offset;
612 unsigned SavedBase = Base;
613 int TmpOffset = Offset;
615 // Iterate through the GEP folding the constants into offsets where
617 gep_type_iterator GTI = gep_type_begin(U);
618 for (User::const_op_iterator i = U->op_begin() + 1, e = U->op_end();
619 i != e; ++i, ++GTI) {
620 const Value *Op = *i;
621 if (const StructType *STy = dyn_cast<StructType>(*GTI)) {
622 const StructLayout *SL = TD.getStructLayout(STy);
623 unsigned Idx = cast<ConstantInt>(Op)->getZExtValue();
624 TmpOffset += SL->getElementOffset(Idx);
626 uint64_t S = TD.getTypeAllocSize(GTI.getIndexedType());
627 SmallVector<const Value *, 4> Worklist;
628 Worklist.push_back(Op);
630 Op = Worklist.pop_back_val();
631 if (const ConstantInt *CI = dyn_cast<ConstantInt>(Op)) {
632 // Constant-offset addressing.
633 TmpOffset += CI->getSExtValue() * S;
634 } else if (isa<AddOperator>(Op) &&
635 isa<ConstantInt>(cast<AddOperator>(Op)->getOperand(1))) {
636 // An add with a constant operand. Fold the constant.
638 cast<ConstantInt>(cast<AddOperator>(Op)->getOperand(1));
639 TmpOffset += CI->getSExtValue() * S;
640 // Add the other operand back to the work list.
641 Worklist.push_back(cast<AddOperator>(Op)->getOperand(0));
643 goto unsupported_gep;
644 } while (!Worklist.empty());
648 // Try to grab the base operand now.
650 if (ARMComputeRegOffset(U->getOperand(0), Base, Offset)) return true;
652 // We failed, restore everything and try the other options.
653 Offset = SavedOffset;
659 case Instruction::Alloca: {
660 const AllocaInst *AI = cast<AllocaInst>(Obj);
661 unsigned Reg = TargetMaterializeAlloca(AI);
663 if (Reg == 0) return false;
670 // Materialize the global variable's address into a reg which can
671 // then be used later to load the variable.
672 if (const GlobalValue *GV = dyn_cast<GlobalValue>(Obj)) {
673 unsigned Tmp = ARMMaterializeGV(GV, TLI.getValueType(Obj->getType()));
674 if (Tmp == 0) return false;
680 // Try to get this in a register if nothing else has worked.
681 if (Base == 0) Base = getRegForValue(Obj);
685 void ARMFastISel::ARMSimplifyRegOffset(unsigned &Base, int &Offset, EVT VT) {
687 assert(VT.isSimple() && "Non-simple types are invalid here!");
689 bool needsLowering = false;
690 switch (VT.getSimpleVT().SimpleTy) {
692 assert(false && "Unhandled load/store type!");
697 // Integer loads/stores handle 12-bit offsets.
698 needsLowering = ((Offset & 0xfff) != Offset);
702 // Floating point operands handle 8-bit offsets.
703 needsLowering = ((Offset & 0xff) != Offset);
707 // Since the offset is too large for the load/store instruction
708 // get the reg+offset into a register.
710 ARMCC::CondCodes Pred = ARMCC::AL;
711 unsigned PredReg = 0;
713 TargetRegisterClass *RC = isThumb ? ARM::tGPRRegisterClass :
714 ARM::GPRRegisterClass;
715 unsigned BaseReg = createResultReg(RC);
718 emitARMRegPlusImmediate(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
719 BaseReg, Base, Offset, Pred, PredReg,
720 static_cast<const ARMBaseInstrInfo&>(TII));
722 assert(AFI->isThumb2Function());
723 emitT2RegPlusImmediate(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
724 BaseReg, Base, Offset, Pred, PredReg,
725 static_cast<const ARMBaseInstrInfo&>(TII));
732 bool ARMFastISel::ARMEmitLoad(EVT VT, unsigned &ResultReg,
733 unsigned Base, int Offset) {
735 assert(VT.isSimple() && "Non-simple types are invalid here!");
737 TargetRegisterClass *RC;
738 bool isFloat = false;
739 switch (VT.getSimpleVT().SimpleTy) {
741 // This is mostly going to be Neon/vector support.
744 Opc = isThumb ? ARM::t2LDRHi12 : ARM::LDRH;
745 RC = ARM::GPRRegisterClass;
748 Opc = isThumb ? ARM::t2LDRBi12 : ARM::LDRB;
749 RC = ARM::GPRRegisterClass;
752 Opc = isThumb ? ARM::t2LDRi12 : ARM::LDR;
753 RC = ARM::GPRRegisterClass;
757 RC = TLI.getRegClassFor(VT);
762 RC = TLI.getRegClassFor(VT);
767 ResultReg = createResultReg(RC);
769 ARMSimplifyRegOffset(Base, Offset, VT);
771 // addrmode5 output depends on the selection dag addressing dividing the
772 // offset by 4 that it then later multiplies. Do this here as well.
776 // The thumb and floating point instructions both take 2 operands, ARM takes
778 if (isFloat || isThumb)
779 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
780 TII.get(Opc), ResultReg)
781 .addReg(Base).addImm(Offset));
783 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
784 TII.get(Opc), ResultReg)
785 .addReg(Base).addReg(0).addImm(Offset));
789 bool ARMFastISel::SelectLoad(const Instruction *I) {
790 // Verify we have a legal type before going any further.
792 if (!isLoadTypeLegal(I->getType(), VT))
795 // Our register and offset with innocuous defaults.
799 // See if we can handle this as Reg + Offset
800 if (!ARMComputeRegOffset(I->getOperand(0), Base, Offset))
804 if (!ARMEmitLoad(VT, ResultReg, Base, Offset)) return false;
806 UpdateValueMap(I, ResultReg);
810 bool ARMFastISel::ARMEmitStore(EVT VT, unsigned SrcReg,
811 unsigned Base, int Offset) {
813 bool isFloat = false;
814 switch (VT.getSimpleVT().SimpleTy) {
815 default: return false;
818 StrOpc = isThumb ? ARM::t2STRBi12 : ARM::STRB;
821 StrOpc = isThumb ? ARM::t2STRHi12 : ARM::STRH;
824 StrOpc = isThumb ? ARM::t2STRi12 : ARM::STR;
827 if (!Subtarget->hasVFP2()) return false;
832 if (!Subtarget->hasVFP2()) return false;
838 ARMSimplifyRegOffset(Base, Offset, VT);
840 // addrmode5 output depends on the selection dag addressing dividing the
841 // offset by 4 that it then later multiplies. Do this here as well.
845 // The thumb addressing mode has operands swapped from the arm addressing
846 // mode, the floating point one only has two operands.
847 if (isFloat || isThumb)
848 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
850 .addReg(SrcReg).addReg(Base).addImm(Offset));
852 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
854 .addReg(SrcReg).addReg(Base).addReg(0).addImm(Offset));
859 bool ARMFastISel::SelectStore(const Instruction *I) {
860 Value *Op0 = I->getOperand(0);
863 // Yay type legalization
865 if (!isLoadTypeLegal(I->getOperand(0)->getType(), VT))
868 // Get the value to be stored into a register.
869 SrcReg = getRegForValue(Op0);
873 // Our register and offset with innocuous defaults.
877 // See if we can handle this as Reg + Offset
878 if (!ARMComputeRegOffset(I->getOperand(1), Base, Offset))
881 if (!ARMEmitStore(VT, SrcReg, Base, Offset)) return false;
886 static ARMCC::CondCodes getComparePred(CmpInst::Predicate Pred) {
888 // Needs two compares...
889 case CmpInst::FCMP_ONE:
890 case CmpInst::FCMP_UEQ:
892 assert(false && "Unhandled CmpInst::Predicate!");
894 case CmpInst::ICMP_EQ:
895 case CmpInst::FCMP_OEQ:
897 case CmpInst::ICMP_SGT:
898 case CmpInst::FCMP_OGT:
900 case CmpInst::ICMP_SGE:
901 case CmpInst::FCMP_OGE:
903 case CmpInst::ICMP_UGT:
904 case CmpInst::FCMP_UGT:
906 case CmpInst::FCMP_OLT:
908 case CmpInst::ICMP_ULE:
909 case CmpInst::FCMP_OLE:
911 case CmpInst::FCMP_ORD:
913 case CmpInst::FCMP_UNO:
915 case CmpInst::FCMP_UGE:
917 case CmpInst::ICMP_SLT:
918 case CmpInst::FCMP_ULT:
920 case CmpInst::ICMP_SLE:
921 case CmpInst::FCMP_ULE:
923 case CmpInst::FCMP_UNE:
924 case CmpInst::ICMP_NE:
926 case CmpInst::ICMP_UGE:
928 case CmpInst::ICMP_ULT:
933 bool ARMFastISel::SelectBranch(const Instruction *I) {
934 const BranchInst *BI = cast<BranchInst>(I);
935 MachineBasicBlock *TBB = FuncInfo.MBBMap[BI->getSuccessor(0)];
936 MachineBasicBlock *FBB = FuncInfo.MBBMap[BI->getSuccessor(1)];
938 // Simple branch support.
939 // TODO: Try to avoid the re-computation in some places.
940 unsigned CondReg = getRegForValue(BI->getCondition());
941 if (CondReg == 0) return false;
943 // Re-set the flags just in case.
944 unsigned CmpOpc = isThumb ? ARM::t2CMPri : ARM::CMPri;
945 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(CmpOpc))
946 .addReg(CondReg).addImm(1));
948 unsigned BrOpc = isThumb ? ARM::t2Bcc : ARM::Bcc;
949 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(BrOpc))
950 .addMBB(TBB).addImm(ARMCC::EQ).addReg(ARM::CPSR);
951 FastEmitBranch(FBB, DL);
952 FuncInfo.MBB->addSuccessor(TBB);
956 bool ARMFastISel::SelectCmp(const Instruction *I) {
957 const CmpInst *CI = cast<CmpInst>(I);
960 const Type *Ty = CI->getOperand(0)->getType();
961 if (!isTypeLegal(Ty, VT))
964 bool isFloat = (Ty->isDoubleTy() || Ty->isFloatTy());
965 if (isFloat && !Subtarget->hasVFP2())
970 switch (VT.getSimpleVT().SimpleTy) {
971 default: return false;
972 // TODO: Verify compares.
974 CmpOpc = ARM::VCMPES;
975 CondReg = ARM::FPSCR;
978 CmpOpc = ARM::VCMPED;
979 CondReg = ARM::FPSCR;
982 CmpOpc = isThumb ? ARM::t2CMPrr : ARM::CMPrr;
987 // Get the compare predicate.
988 ARMCC::CondCodes ARMPred = getComparePred(CI->getPredicate());
990 // We may not handle every CC for now.
991 if (ARMPred == ARMCC::AL) return false;
993 unsigned Arg1 = getRegForValue(CI->getOperand(0));
994 if (Arg1 == 0) return false;
996 unsigned Arg2 = getRegForValue(CI->getOperand(1));
997 if (Arg2 == 0) return false;
999 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(CmpOpc))
1000 .addReg(Arg1).addReg(Arg2));
1002 // For floating point we need to move the result to a comparison register
1003 // that we can then use for branches.
1005 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1006 TII.get(ARM::FMSTAT)));
1008 // Now set a register based on the comparison. Explicitly set the predicates
1010 unsigned MovCCOpc = isThumb ? ARM::t2MOVCCi : ARM::MOVCCi;
1011 TargetRegisterClass *RC = isThumb ? ARM::rGPRRegisterClass
1012 : ARM::GPRRegisterClass;
1013 unsigned DestReg = createResultReg(RC);
1015 = ConstantInt::get(Type::getInt32Ty(*Context), 0);
1016 unsigned ZeroReg = TargetMaterializeConstant(Zero);
1017 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(MovCCOpc), DestReg)
1018 .addReg(ZeroReg).addImm(1)
1019 .addImm(ARMPred).addReg(CondReg);
1021 UpdateValueMap(I, DestReg);
1025 bool ARMFastISel::SelectFPExt(const Instruction *I) {
1026 // Make sure we have VFP and that we're extending float to double.
1027 if (!Subtarget->hasVFP2()) return false;
1029 Value *V = I->getOperand(0);
1030 if (!I->getType()->isDoubleTy() ||
1031 !V->getType()->isFloatTy()) return false;
1033 unsigned Op = getRegForValue(V);
1034 if (Op == 0) return false;
1036 unsigned Result = createResultReg(ARM::DPRRegisterClass);
1037 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1038 TII.get(ARM::VCVTDS), Result)
1040 UpdateValueMap(I, Result);
1044 bool ARMFastISel::SelectFPTrunc(const Instruction *I) {
1045 // Make sure we have VFP and that we're truncating double to float.
1046 if (!Subtarget->hasVFP2()) return false;
1048 Value *V = I->getOperand(0);
1049 if (!(I->getType()->isFloatTy() &&
1050 V->getType()->isDoubleTy())) return false;
1052 unsigned Op = getRegForValue(V);
1053 if (Op == 0) return false;
1055 unsigned Result = createResultReg(ARM::SPRRegisterClass);
1056 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1057 TII.get(ARM::VCVTSD), Result)
1059 UpdateValueMap(I, Result);
1063 bool ARMFastISel::SelectSIToFP(const Instruction *I) {
1064 // Make sure we have VFP.
1065 if (!Subtarget->hasVFP2()) return false;
1068 const Type *Ty = I->getType();
1069 if (!isTypeLegal(Ty, DstVT))
1072 unsigned Op = getRegForValue(I->getOperand(0));
1073 if (Op == 0) return false;
1075 // The conversion routine works on fp-reg to fp-reg and the operand above
1076 // was an integer, move it to the fp registers if possible.
1077 unsigned FP = ARMMoveToFPReg(MVT::f32, Op);
1078 if (FP == 0) return false;
1081 if (Ty->isFloatTy()) Opc = ARM::VSITOS;
1082 else if (Ty->isDoubleTy()) Opc = ARM::VSITOD;
1085 unsigned ResultReg = createResultReg(TLI.getRegClassFor(DstVT));
1086 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc),
1089 UpdateValueMap(I, ResultReg);
1093 bool ARMFastISel::SelectFPToSI(const Instruction *I) {
1094 // Make sure we have VFP.
1095 if (!Subtarget->hasVFP2()) return false;
1098 const Type *RetTy = I->getType();
1099 if (!isTypeLegal(RetTy, DstVT))
1102 unsigned Op = getRegForValue(I->getOperand(0));
1103 if (Op == 0) return false;
1106 const Type *OpTy = I->getOperand(0)->getType();
1107 if (OpTy->isFloatTy()) Opc = ARM::VTOSIZS;
1108 else if (OpTy->isDoubleTy()) Opc = ARM::VTOSIZD;
1111 // f64->s32 or f32->s32 both need an intermediate f32 reg.
1112 unsigned ResultReg = createResultReg(TLI.getRegClassFor(MVT::f32));
1113 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc),
1117 // This result needs to be in an integer register, but the conversion only
1118 // takes place in fp-regs.
1119 unsigned IntReg = ARMMoveToIntReg(DstVT, ResultReg);
1120 if (IntReg == 0) return false;
1122 UpdateValueMap(I, IntReg);
1126 bool ARMFastISel::SelectSelect(const Instruction *I) {
1127 EVT VT = TLI.getValueType(I->getType(), /*HandleUnknown=*/true);
1128 if (VT == MVT::Other || !isTypeLegal(I->getType(), VT))
1131 // Things need to be register sized for register moves.
1132 if (VT.getSimpleVT().SimpleTy != MVT::i32) return false;
1133 const TargetRegisterClass *RC = TLI.getRegClassFor(VT);
1135 unsigned CondReg = getRegForValue(I->getOperand(0));
1136 if (CondReg == 0) return false;
1137 unsigned Op1Reg = getRegForValue(I->getOperand(1));
1138 if (Op1Reg == 0) return false;
1139 unsigned Op2Reg = getRegForValue(I->getOperand(2));
1140 if (Op2Reg == 0) return false;
1142 unsigned CmpOpc = isThumb ? ARM::t2TSTri : ARM::TSTri;
1143 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(CmpOpc))
1144 .addReg(CondReg).addImm(1));
1145 unsigned ResultReg = createResultReg(RC);
1146 unsigned MovCCOpc = isThumb ? ARM::t2MOVCCr : ARM::MOVCCr;
1147 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(MovCCOpc), ResultReg)
1148 .addReg(Op1Reg).addReg(Op2Reg)
1149 .addImm(ARMCC::EQ).addReg(ARM::CPSR);
1150 UpdateValueMap(I, ResultReg);
1154 bool ARMFastISel::SelectSDiv(const Instruction *I) {
1156 const Type *Ty = I->getType();
1157 if (!isTypeLegal(Ty, VT))
1160 // If we have integer div support we should have selected this automagically.
1161 // In case we have a real miss go ahead and return false and we'll pick
1163 if (Subtarget->hasDivide()) return false;
1165 // Otherwise emit a libcall.
1166 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
1168 LC = RTLIB::SDIV_I8;
1169 else if (VT == MVT::i16)
1170 LC = RTLIB::SDIV_I16;
1171 else if (VT == MVT::i32)
1172 LC = RTLIB::SDIV_I32;
1173 else if (VT == MVT::i64)
1174 LC = RTLIB::SDIV_I64;
1175 else if (VT == MVT::i128)
1176 LC = RTLIB::SDIV_I128;
1177 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported SDIV!");
1179 return ARMEmitLibcall(I, LC);
1182 bool ARMFastISel::SelectSRem(const Instruction *I) {
1184 const Type *Ty = I->getType();
1185 if (!isTypeLegal(Ty, VT))
1188 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
1190 LC = RTLIB::SREM_I8;
1191 else if (VT == MVT::i16)
1192 LC = RTLIB::SREM_I16;
1193 else if (VT == MVT::i32)
1194 LC = RTLIB::SREM_I32;
1195 else if (VT == MVT::i64)
1196 LC = RTLIB::SREM_I64;
1197 else if (VT == MVT::i128)
1198 LC = RTLIB::SREM_I128;
1199 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported SREM!");
1201 return ARMEmitLibcall(I, LC);
1204 bool ARMFastISel::SelectBinaryOp(const Instruction *I, unsigned ISDOpcode) {
1205 EVT VT = TLI.getValueType(I->getType(), true);
1207 // We can get here in the case when we want to use NEON for our fp
1208 // operations, but can't figure out how to. Just use the vfp instructions
1210 // FIXME: It'd be nice to use NEON instructions.
1211 const Type *Ty = I->getType();
1212 bool isFloat = (Ty->isDoubleTy() || Ty->isFloatTy());
1213 if (isFloat && !Subtarget->hasVFP2())
1216 unsigned Op1 = getRegForValue(I->getOperand(0));
1217 if (Op1 == 0) return false;
1219 unsigned Op2 = getRegForValue(I->getOperand(1));
1220 if (Op2 == 0) return false;
1223 bool is64bit = VT.getSimpleVT().SimpleTy == MVT::f64 ||
1224 VT.getSimpleVT().SimpleTy == MVT::i64;
1225 switch (ISDOpcode) {
1226 default: return false;
1228 Opc = is64bit ? ARM::VADDD : ARM::VADDS;
1231 Opc = is64bit ? ARM::VSUBD : ARM::VSUBS;
1234 Opc = is64bit ? ARM::VMULD : ARM::VMULS;
1237 unsigned ResultReg = createResultReg(TLI.getRegClassFor(VT));
1238 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1239 TII.get(Opc), ResultReg)
1240 .addReg(Op1).addReg(Op2));
1241 UpdateValueMap(I, ResultReg);
1245 // Call Handling Code
1247 bool ARMFastISel::FastEmitExtend(ISD::NodeType Opc, EVT DstVT, unsigned Src,
1248 EVT SrcVT, unsigned &ResultReg) {
1249 unsigned RR = FastEmit_r(SrcVT.getSimpleVT(), DstVT.getSimpleVT(), Opc,
1250 Src, /*TODO: Kill=*/false);
1259 // This is largely taken directly from CCAssignFnForNode - we don't support
1260 // varargs in FastISel so that part has been removed.
1261 // TODO: We may not support all of this.
1262 CCAssignFn *ARMFastISel::CCAssignFnForCall(CallingConv::ID CC, bool Return) {
1265 llvm_unreachable("Unsupported calling convention");
1266 case CallingConv::C:
1267 case CallingConv::Fast:
1268 // Use target triple & subtarget features to do actual dispatch.
1269 if (Subtarget->isAAPCS_ABI()) {
1270 if (Subtarget->hasVFP2() &&
1271 FloatABIType == FloatABI::Hard)
1272 return (Return ? RetCC_ARM_AAPCS_VFP: CC_ARM_AAPCS_VFP);
1274 return (Return ? RetCC_ARM_AAPCS: CC_ARM_AAPCS);
1276 return (Return ? RetCC_ARM_APCS: CC_ARM_APCS);
1277 case CallingConv::ARM_AAPCS_VFP:
1278 return (Return ? RetCC_ARM_AAPCS_VFP: CC_ARM_AAPCS_VFP);
1279 case CallingConv::ARM_AAPCS:
1280 return (Return ? RetCC_ARM_AAPCS: CC_ARM_AAPCS);
1281 case CallingConv::ARM_APCS:
1282 return (Return ? RetCC_ARM_APCS: CC_ARM_APCS);
1286 bool ARMFastISel::ProcessCallArgs(SmallVectorImpl<Value*> &Args,
1287 SmallVectorImpl<unsigned> &ArgRegs,
1288 SmallVectorImpl<EVT> &ArgVTs,
1289 SmallVectorImpl<ISD::ArgFlagsTy> &ArgFlags,
1290 SmallVectorImpl<unsigned> &RegArgs,
1292 unsigned &NumBytes) {
1293 SmallVector<CCValAssign, 16> ArgLocs;
1294 CCState CCInfo(CC, false, TM, ArgLocs, *Context);
1295 CCInfo.AnalyzeCallOperands(ArgVTs, ArgFlags, CCAssignFnForCall(CC, false));
1297 // Get a count of how many bytes are to be pushed on the stack.
1298 NumBytes = CCInfo.getNextStackOffset();
1300 // Issue CALLSEQ_START
1301 unsigned AdjStackDown = TM.getRegisterInfo()->getCallFrameSetupOpcode();
1302 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1303 TII.get(AdjStackDown))
1306 // Process the args.
1307 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1308 CCValAssign &VA = ArgLocs[i];
1309 unsigned Arg = ArgRegs[VA.getValNo()];
1310 EVT ArgVT = ArgVTs[VA.getValNo()];
1312 // Handle arg promotion, etc.
1313 switch (VA.getLocInfo()) {
1314 case CCValAssign::Full: break;
1315 case CCValAssign::SExt: {
1316 bool Emitted = FastEmitExtend(ISD::SIGN_EXTEND, VA.getLocVT(),
1318 assert(Emitted && "Failed to emit a sext!"); Emitted=Emitted;
1320 ArgVT = VA.getLocVT();
1323 case CCValAssign::ZExt: {
1324 bool Emitted = FastEmitExtend(ISD::ZERO_EXTEND, VA.getLocVT(),
1326 assert(Emitted && "Failed to emit a zext!"); Emitted=Emitted;
1328 ArgVT = VA.getLocVT();
1331 case CCValAssign::AExt: {
1332 // We don't handle NEON or f64 parameters yet.
1333 if (VA.getLocVT().isVector() && VA.getLocVT().getSizeInBits() >= 64)
1335 bool Emitted = FastEmitExtend(ISD::ANY_EXTEND, VA.getLocVT(),
1338 Emitted = FastEmitExtend(ISD::ZERO_EXTEND, VA.getLocVT(),
1341 Emitted = FastEmitExtend(ISD::SIGN_EXTEND, VA.getLocVT(),
1344 assert(Emitted && "Failed to emit a aext!"); Emitted=Emitted;
1345 ArgVT = VA.getLocVT();
1348 case CCValAssign::BCvt: {
1349 unsigned BC = FastEmit_r(ArgVT.getSimpleVT(),
1350 VA.getLocVT().getSimpleVT(),
1351 ISD::BIT_CONVERT, Arg, /*TODO: Kill=*/false);
1352 assert(BC != 0 && "Failed to emit a bitcast!");
1354 ArgVT = VA.getLocVT();
1357 default: llvm_unreachable("Unknown arg promotion!");
1360 // Now copy/store arg to correct locations.
1361 if (VA.isRegLoc() && !VA.needsCustom()) {
1362 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY),
1365 RegArgs.push_back(VA.getLocReg());
1366 } else if (VA.needsCustom()) {
1367 // TODO: We need custom lowering for vector (v2f64) args.
1368 if (VA.getLocVT() != MVT::f64) return false;
1370 CCValAssign &NextVA = ArgLocs[++i];
1372 // TODO: Only handle register args for now.
1373 if(!(VA.isRegLoc() && NextVA.isRegLoc())) return false;
1375 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1376 TII.get(ARM::VMOVRRD), VA.getLocReg())
1377 .addReg(NextVA.getLocReg(), RegState::Define)
1379 RegArgs.push_back(VA.getLocReg());
1380 RegArgs.push_back(NextVA.getLocReg());
1382 assert(VA.isMemLoc());
1383 // Need to store on the stack.
1384 unsigned Base = ARM::SP;
1385 int Offset = VA.getLocMemOffset();
1387 if (!ARMEmitStore(ArgVT, Arg, Base, Offset)) return false;
1393 bool ARMFastISel::FinishCall(EVT RetVT, SmallVectorImpl<unsigned> &UsedRegs,
1394 const Instruction *I, CallingConv::ID CC,
1395 unsigned &NumBytes) {
1396 // Issue CALLSEQ_END
1397 unsigned AdjStackUp = TM.getRegisterInfo()->getCallFrameDestroyOpcode();
1398 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1399 TII.get(AdjStackUp))
1400 .addImm(NumBytes).addImm(0));
1402 // Now the return value.
1403 if (RetVT.getSimpleVT().SimpleTy != MVT::isVoid) {
1404 SmallVector<CCValAssign, 16> RVLocs;
1405 CCState CCInfo(CC, false, TM, RVLocs, *Context);
1406 CCInfo.AnalyzeCallResult(RetVT, CCAssignFnForCall(CC, true));
1408 // Copy all of the result registers out of their specified physreg.
1409 if (RVLocs.size() == 2 && RetVT.getSimpleVT().SimpleTy == MVT::f64) {
1410 // For this move we copy into two registers and then move into the
1411 // double fp reg we want.
1412 EVT DestVT = RVLocs[0].getValVT();
1413 TargetRegisterClass* DstRC = TLI.getRegClassFor(DestVT);
1414 unsigned ResultReg = createResultReg(DstRC);
1415 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1416 TII.get(ARM::VMOVDRR), ResultReg)
1417 .addReg(RVLocs[0].getLocReg())
1418 .addReg(RVLocs[1].getLocReg()));
1420 UsedRegs.push_back(RVLocs[0].getLocReg());
1421 UsedRegs.push_back(RVLocs[1].getLocReg());
1423 // Finally update the result.
1424 UpdateValueMap(I, ResultReg);
1426 assert(RVLocs.size() == 1 &&"Can't handle non-double multi-reg retvals!");
1427 EVT CopyVT = RVLocs[0].getValVT();
1428 TargetRegisterClass* DstRC = TLI.getRegClassFor(CopyVT);
1430 unsigned ResultReg = createResultReg(DstRC);
1431 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY),
1432 ResultReg).addReg(RVLocs[0].getLocReg());
1433 UsedRegs.push_back(RVLocs[0].getLocReg());
1435 // Finally update the result.
1436 UpdateValueMap(I, ResultReg);
1443 // A quick function that will emit a call for a named libcall in F with the
1444 // vector of passed arguments for the Instruction in I. We can assume that we
1445 // can emit a call for any libcall we can produce. This is an abridged version
1446 // of the full call infrastructure since we won't need to worry about things
1447 // like computed function pointers or strange arguments at call sites.
1448 // TODO: Try to unify this and the normal call bits for ARM, then try to unify
1450 bool ARMFastISel::ARMEmitLibcall(const Instruction *I, RTLIB::Libcall Call) {
1451 CallingConv::ID CC = TLI.getLibcallCallingConv(Call);
1453 // Handle *simple* calls for now.
1454 const Type *RetTy = I->getType();
1456 if (RetTy->isVoidTy())
1457 RetVT = MVT::isVoid;
1458 else if (!isTypeLegal(RetTy, RetVT))
1461 // For now we're using BLX etc on the assumption that we have v5t ops.
1462 if (!Subtarget->hasV5TOps()) return false;
1464 // Set up the argument vectors.
1465 SmallVector<Value*, 8> Args;
1466 SmallVector<unsigned, 8> ArgRegs;
1467 SmallVector<EVT, 8> ArgVTs;
1468 SmallVector<ISD::ArgFlagsTy, 8> ArgFlags;
1469 Args.reserve(I->getNumOperands());
1470 ArgRegs.reserve(I->getNumOperands());
1471 ArgVTs.reserve(I->getNumOperands());
1472 ArgFlags.reserve(I->getNumOperands());
1473 for (unsigned i = 0; i < I->getNumOperands(); ++i) {
1474 Value *Op = I->getOperand(i);
1475 unsigned Arg = getRegForValue(Op);
1476 if (Arg == 0) return false;
1478 const Type *ArgTy = Op->getType();
1480 if (!isTypeLegal(ArgTy, ArgVT)) return false;
1482 ISD::ArgFlagsTy Flags;
1483 unsigned OriginalAlignment = TD.getABITypeAlignment(ArgTy);
1484 Flags.setOrigAlign(OriginalAlignment);
1487 ArgRegs.push_back(Arg);
1488 ArgVTs.push_back(ArgVT);
1489 ArgFlags.push_back(Flags);
1492 // Handle the arguments now that we've gotten them.
1493 SmallVector<unsigned, 4> RegArgs;
1495 if (!ProcessCallArgs(Args, ArgRegs, ArgVTs, ArgFlags, RegArgs, CC, NumBytes))
1498 // Issue the call, BLXr9 for darwin, BLX otherwise. This uses V5 ops.
1499 // TODO: Turn this into the table of arm call ops.
1500 MachineInstrBuilder MIB;
1503 CallOpc = Subtarget->isTargetDarwin() ? ARM::tBLXi_r9 : ARM::tBLXi;
1505 CallOpc = Subtarget->isTargetDarwin() ? ARM::BLr9 : ARM::BL;
1506 MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(CallOpc))
1507 .addExternalSymbol(TLI.getLibcallName(Call));
1509 // Add implicit physical register uses to the call.
1510 for (unsigned i = 0, e = RegArgs.size(); i != e; ++i)
1511 MIB.addReg(RegArgs[i]);
1513 // Finish off the call including any return values.
1514 SmallVector<unsigned, 4> UsedRegs;
1515 if (!FinishCall(RetVT, UsedRegs, I, CC, NumBytes)) return false;
1517 // Set all unused physreg defs as dead.
1518 static_cast<MachineInstr *>(MIB)->setPhysRegsDeadExcept(UsedRegs, TRI);
1523 bool ARMFastISel::SelectCall(const Instruction *I) {
1524 const CallInst *CI = cast<CallInst>(I);
1525 const Value *Callee = CI->getCalledValue();
1527 // Can't handle inline asm or worry about intrinsics yet.
1528 if (isa<InlineAsm>(Callee) || isa<IntrinsicInst>(CI)) return false;
1530 // Only handle global variable Callees that are direct calls.
1531 const GlobalValue *GV = dyn_cast<GlobalValue>(Callee);
1532 if (!GV || Subtarget->GVIsIndirectSymbol(GV, TM.getRelocationModel()))
1535 // Check the calling convention.
1536 ImmutableCallSite CS(CI);
1537 CallingConv::ID CC = CS.getCallingConv();
1539 // TODO: Avoid some calling conventions?
1541 // Let SDISel handle vararg functions.
1542 const PointerType *PT = cast<PointerType>(CS.getCalledValue()->getType());
1543 const FunctionType *FTy = cast<FunctionType>(PT->getElementType());
1544 if (FTy->isVarArg())
1547 // Handle *simple* calls for now.
1548 const Type *RetTy = I->getType();
1550 if (RetTy->isVoidTy())
1551 RetVT = MVT::isVoid;
1552 else if (!isTypeLegal(RetTy, RetVT))
1555 // For now we're using BLX etc on the assumption that we have v5t ops.
1557 if (!Subtarget->hasV5TOps()) return false;
1559 // Set up the argument vectors.
1560 SmallVector<Value*, 8> Args;
1561 SmallVector<unsigned, 8> ArgRegs;
1562 SmallVector<EVT, 8> ArgVTs;
1563 SmallVector<ISD::ArgFlagsTy, 8> ArgFlags;
1564 Args.reserve(CS.arg_size());
1565 ArgRegs.reserve(CS.arg_size());
1566 ArgVTs.reserve(CS.arg_size());
1567 ArgFlags.reserve(CS.arg_size());
1568 for (ImmutableCallSite::arg_iterator i = CS.arg_begin(), e = CS.arg_end();
1570 unsigned Arg = getRegForValue(*i);
1574 ISD::ArgFlagsTy Flags;
1575 unsigned AttrInd = i - CS.arg_begin() + 1;
1576 if (CS.paramHasAttr(AttrInd, Attribute::SExt))
1578 if (CS.paramHasAttr(AttrInd, Attribute::ZExt))
1581 // FIXME: Only handle *easy* calls for now.
1582 if (CS.paramHasAttr(AttrInd, Attribute::InReg) ||
1583 CS.paramHasAttr(AttrInd, Attribute::StructRet) ||
1584 CS.paramHasAttr(AttrInd, Attribute::Nest) ||
1585 CS.paramHasAttr(AttrInd, Attribute::ByVal))
1588 const Type *ArgTy = (*i)->getType();
1590 if (!isTypeLegal(ArgTy, ArgVT))
1592 unsigned OriginalAlignment = TD.getABITypeAlignment(ArgTy);
1593 Flags.setOrigAlign(OriginalAlignment);
1596 ArgRegs.push_back(Arg);
1597 ArgVTs.push_back(ArgVT);
1598 ArgFlags.push_back(Flags);
1601 // Handle the arguments now that we've gotten them.
1602 SmallVector<unsigned, 4> RegArgs;
1604 if (!ProcessCallArgs(Args, ArgRegs, ArgVTs, ArgFlags, RegArgs, CC, NumBytes))
1607 // Issue the call, BLXr9 for darwin, BLX otherwise. This uses V5 ops.
1608 // TODO: Turn this into the table of arm call ops.
1609 MachineInstrBuilder MIB;
1612 CallOpc = Subtarget->isTargetDarwin() ? ARM::tBLXi_r9 : ARM::tBLXi;
1614 CallOpc = Subtarget->isTargetDarwin() ? ARM::BLr9 : ARM::BL;
1615 MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(CallOpc))
1616 .addGlobalAddress(GV, 0, 0);
1618 // Add implicit physical register uses to the call.
1619 for (unsigned i = 0, e = RegArgs.size(); i != e; ++i)
1620 MIB.addReg(RegArgs[i]);
1622 // Finish off the call including any return values.
1623 SmallVector<unsigned, 4> UsedRegs;
1624 if (!FinishCall(RetVT, UsedRegs, I, CC, NumBytes)) return false;
1626 // Set all unused physreg defs as dead.
1627 static_cast<MachineInstr *>(MIB)->setPhysRegsDeadExcept(UsedRegs, TRI);
1633 // TODO: SoftFP support.
1634 bool ARMFastISel::TargetSelectInstruction(const Instruction *I) {
1635 // No Thumb-1 for now.
1636 if (isThumb && !AFI->isThumb2Function()) return false;
1638 switch (I->getOpcode()) {
1639 case Instruction::Load:
1640 return SelectLoad(I);
1641 case Instruction::Store:
1642 return SelectStore(I);
1643 case Instruction::Br:
1644 return SelectBranch(I);
1645 case Instruction::ICmp:
1646 case Instruction::FCmp:
1647 return SelectCmp(I);
1648 case Instruction::FPExt:
1649 return SelectFPExt(I);
1650 case Instruction::FPTrunc:
1651 return SelectFPTrunc(I);
1652 case Instruction::SIToFP:
1653 return SelectSIToFP(I);
1654 case Instruction::FPToSI:
1655 return SelectFPToSI(I);
1656 case Instruction::FAdd:
1657 return SelectBinaryOp(I, ISD::FADD);
1658 case Instruction::FSub:
1659 return SelectBinaryOp(I, ISD::FSUB);
1660 case Instruction::FMul:
1661 return SelectBinaryOp(I, ISD::FMUL);
1662 case Instruction::SDiv:
1663 return SelectSDiv(I);
1664 case Instruction::SRem:
1665 return SelectSRem(I);
1666 case Instruction::Call:
1667 return SelectCall(I);
1668 case Instruction::Select:
1669 return SelectSelect(I);
1676 llvm::FastISel *ARM::createFastISel(FunctionLoweringInfo &funcInfo) {
1677 // Completely untested on non-darwin.
1678 const TargetMachine &TM = funcInfo.MF->getTarget();
1679 const ARMSubtarget *Subtarget = &TM.getSubtarget<ARMSubtarget>();
1680 if (Subtarget->isTargetDarwin() && !DisableARMFastISel)
1681 return new ARMFastISel(funcInfo);