1 //===-- ARMFastISel.cpp - ARM FastISel implementation ---------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the ARM-specific support for the FastISel class. Some
11 // of the target-specific code is generated by tablegen in the file
12 // ARMGenFastISel.inc, which is #included here.
14 //===----------------------------------------------------------------------===//
17 #include "ARMBaseInstrInfo.h"
18 #include "ARMCallingConv.h"
19 #include "ARMConstantPoolValue.h"
20 #include "ARMSubtarget.h"
21 #include "ARMTargetMachine.h"
22 #include "MCTargetDesc/ARMAddressingModes.h"
23 #include "llvm/ADT/STLExtras.h"
24 #include "llvm/CodeGen/Analysis.h"
25 #include "llvm/CodeGen/FastISel.h"
26 #include "llvm/CodeGen/FunctionLoweringInfo.h"
27 #include "llvm/CodeGen/MachineConstantPool.h"
28 #include "llvm/CodeGen/MachineFrameInfo.h"
29 #include "llvm/CodeGen/MachineInstrBuilder.h"
30 #include "llvm/CodeGen/MachineMemOperand.h"
31 #include "llvm/CodeGen/MachineModuleInfo.h"
32 #include "llvm/CodeGen/MachineRegisterInfo.h"
33 #include "llvm/IR/CallingConv.h"
34 #include "llvm/IR/DataLayout.h"
35 #include "llvm/IR/DerivedTypes.h"
36 #include "llvm/IR/GlobalVariable.h"
37 #include "llvm/IR/Instructions.h"
38 #include "llvm/IR/IntrinsicInst.h"
39 #include "llvm/IR/Module.h"
40 #include "llvm/IR/Operator.h"
41 #include "llvm/Support/CallSite.h"
42 #include "llvm/Support/CommandLine.h"
43 #include "llvm/Support/ErrorHandling.h"
44 #include "llvm/Support/GetElementPtrTypeIterator.h"
45 #include "llvm/Target/TargetInstrInfo.h"
46 #include "llvm/Target/TargetLowering.h"
47 #include "llvm/Target/TargetMachine.h"
48 #include "llvm/Target/TargetOptions.h"
51 extern cl::opt<bool> EnableARMLongCalls;
55 // All possible address modes, plus some.
56 typedef struct Address {
69 // Innocuous defaults for our address.
71 : BaseType(RegBase), Offset(0) {
76 class ARMFastISel : public FastISel {
78 /// Subtarget - Keep a pointer to the ARMSubtarget around so that we can
79 /// make the right decision when generating code for different targets.
80 const ARMSubtarget *Subtarget;
81 const TargetMachine &TM;
82 const TargetInstrInfo &TII;
83 const TargetLowering &TLI;
86 // Convenience variables to avoid some queries.
91 explicit ARMFastISel(FunctionLoweringInfo &funcInfo,
92 const TargetLibraryInfo *libInfo)
93 : FastISel(funcInfo, libInfo),
94 TM(funcInfo.MF->getTarget()),
95 TII(*TM.getInstrInfo()),
96 TLI(*TM.getTargetLowering()) {
97 Subtarget = &TM.getSubtarget<ARMSubtarget>();
98 AFI = funcInfo.MF->getInfo<ARMFunctionInfo>();
99 isThumb2 = AFI->isThumbFunction();
100 Context = &funcInfo.Fn->getContext();
103 // Code from FastISel.cpp.
105 unsigned FastEmitInst_(unsigned MachineInstOpcode,
106 const TargetRegisterClass *RC);
107 unsigned FastEmitInst_r(unsigned MachineInstOpcode,
108 const TargetRegisterClass *RC,
109 unsigned Op0, bool Op0IsKill);
110 unsigned FastEmitInst_rr(unsigned MachineInstOpcode,
111 const TargetRegisterClass *RC,
112 unsigned Op0, bool Op0IsKill,
113 unsigned Op1, bool Op1IsKill);
114 unsigned FastEmitInst_rrr(unsigned MachineInstOpcode,
115 const TargetRegisterClass *RC,
116 unsigned Op0, bool Op0IsKill,
117 unsigned Op1, bool Op1IsKill,
118 unsigned Op2, bool Op2IsKill);
119 unsigned FastEmitInst_ri(unsigned MachineInstOpcode,
120 const TargetRegisterClass *RC,
121 unsigned Op0, bool Op0IsKill,
123 unsigned FastEmitInst_rf(unsigned MachineInstOpcode,
124 const TargetRegisterClass *RC,
125 unsigned Op0, bool Op0IsKill,
126 const ConstantFP *FPImm);
127 unsigned FastEmitInst_rri(unsigned MachineInstOpcode,
128 const TargetRegisterClass *RC,
129 unsigned Op0, bool Op0IsKill,
130 unsigned Op1, bool Op1IsKill,
132 unsigned FastEmitInst_i(unsigned MachineInstOpcode,
133 const TargetRegisterClass *RC,
135 unsigned FastEmitInst_ii(unsigned MachineInstOpcode,
136 const TargetRegisterClass *RC,
137 uint64_t Imm1, uint64_t Imm2);
139 unsigned FastEmitInst_extractsubreg(MVT RetVT,
140 unsigned Op0, bool Op0IsKill,
143 // Backend specific FastISel code.
145 virtual bool TargetSelectInstruction(const Instruction *I);
146 virtual unsigned TargetMaterializeConstant(const Constant *C);
147 virtual unsigned TargetMaterializeAlloca(const AllocaInst *AI);
148 virtual bool tryToFoldLoadIntoMI(MachineInstr *MI, unsigned OpNo,
150 virtual bool FastLowerArguments();
152 #include "ARMGenFastISel.inc"
154 // Instruction selection routines.
156 bool SelectLoad(const Instruction *I);
157 bool SelectStore(const Instruction *I);
158 bool SelectBranch(const Instruction *I);
159 bool SelectIndirectBr(const Instruction *I);
160 bool SelectCmp(const Instruction *I);
161 bool SelectFPExt(const Instruction *I);
162 bool SelectFPTrunc(const Instruction *I);
163 bool SelectBinaryIntOp(const Instruction *I, unsigned ISDOpcode);
164 bool SelectBinaryFPOp(const Instruction *I, unsigned ISDOpcode);
165 bool SelectIToFP(const Instruction *I, bool isSigned);
166 bool SelectFPToI(const Instruction *I, bool isSigned);
167 bool SelectDiv(const Instruction *I, bool isSigned);
168 bool SelectRem(const Instruction *I, bool isSigned);
169 bool SelectCall(const Instruction *I, const char *IntrMemName);
170 bool SelectIntrinsicCall(const IntrinsicInst &I);
171 bool SelectSelect(const Instruction *I);
172 bool SelectRet(const Instruction *I);
173 bool SelectTrunc(const Instruction *I);
174 bool SelectIntExt(const Instruction *I);
175 bool SelectShift(const Instruction *I, ARM_AM::ShiftOpc ShiftTy);
179 unsigned constrainOperandRegClass(const MCInstrDesc &II, unsigned OpNum,
181 bool isTypeLegal(Type *Ty, MVT &VT);
182 bool isLoadTypeLegal(Type *Ty, MVT &VT);
183 bool ARMEmitCmp(const Value *Src1Value, const Value *Src2Value,
185 bool ARMEmitLoad(MVT VT, unsigned &ResultReg, Address &Addr,
186 unsigned Alignment = 0, bool isZExt = true,
187 bool allocReg = true);
188 bool ARMEmitStore(MVT VT, unsigned SrcReg, Address &Addr,
189 unsigned Alignment = 0);
190 bool ARMComputeAddress(const Value *Obj, Address &Addr);
191 void ARMSimplifyAddress(Address &Addr, MVT VT, bool useAM3);
192 bool ARMIsMemCpySmall(uint64_t Len);
193 bool ARMTryEmitSmallMemCpy(Address Dest, Address Src, uint64_t Len,
195 unsigned ARMEmitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, bool isZExt);
196 unsigned ARMMaterializeFP(const ConstantFP *CFP, MVT VT);
197 unsigned ARMMaterializeInt(const Constant *C, MVT VT);
198 unsigned ARMMaterializeGV(const GlobalValue *GV, MVT VT);
199 unsigned ARMMoveToFPReg(MVT VT, unsigned SrcReg);
200 unsigned ARMMoveToIntReg(MVT VT, unsigned SrcReg);
201 unsigned ARMSelectCallOp(bool UseReg);
202 unsigned ARMLowerPICELF(const GlobalValue *GV, unsigned Align, MVT VT);
204 // Call handling routines.
206 CCAssignFn *CCAssignFnForCall(CallingConv::ID CC,
209 bool ProcessCallArgs(SmallVectorImpl<Value*> &Args,
210 SmallVectorImpl<unsigned> &ArgRegs,
211 SmallVectorImpl<MVT> &ArgVTs,
212 SmallVectorImpl<ISD::ArgFlagsTy> &ArgFlags,
213 SmallVectorImpl<unsigned> &RegArgs,
217 unsigned getLibcallReg(const Twine &Name);
218 bool FinishCall(MVT RetVT, SmallVectorImpl<unsigned> &UsedRegs,
219 const Instruction *I, CallingConv::ID CC,
220 unsigned &NumBytes, bool isVarArg);
221 bool ARMEmitLibcall(const Instruction *I, RTLIB::Libcall Call);
223 // OptionalDef handling routines.
225 bool isARMNEONPred(const MachineInstr *MI);
226 bool DefinesOptionalPredicate(MachineInstr *MI, bool *CPSR);
227 const MachineInstrBuilder &AddOptionalDefs(const MachineInstrBuilder &MIB);
228 void AddLoadStoreOperands(MVT VT, Address &Addr,
229 const MachineInstrBuilder &MIB,
230 unsigned Flags, bool useAM3);
233 } // end anonymous namespace
235 #include "ARMGenCallingConv.inc"
237 // DefinesOptionalPredicate - This is different from DefinesPredicate in that
238 // we don't care about implicit defs here, just places we'll need to add a
239 // default CCReg argument. Sets CPSR if we're setting CPSR instead of CCR.
240 bool ARMFastISel::DefinesOptionalPredicate(MachineInstr *MI, bool *CPSR) {
241 if (!MI->hasOptionalDef())
244 // Look to see if our OptionalDef is defining CPSR or CCR.
245 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
246 const MachineOperand &MO = MI->getOperand(i);
247 if (!MO.isReg() || !MO.isDef()) continue;
248 if (MO.getReg() == ARM::CPSR)
254 bool ARMFastISel::isARMNEONPred(const MachineInstr *MI) {
255 const MCInstrDesc &MCID = MI->getDesc();
257 // If we're a thumb2 or not NEON function we'll be handled via isPredicable.
258 if ((MCID.TSFlags & ARMII::DomainMask) != ARMII::DomainNEON ||
259 AFI->isThumb2Function())
260 return MI->isPredicable();
262 for (unsigned i = 0, e = MCID.getNumOperands(); i != e; ++i)
263 if (MCID.OpInfo[i].isPredicate())
269 // If the machine is predicable go ahead and add the predicate operands, if
270 // it needs default CC operands add those.
271 // TODO: If we want to support thumb1 then we'll need to deal with optional
272 // CPSR defs that need to be added before the remaining operands. See s_cc_out
273 // for descriptions why.
274 const MachineInstrBuilder &
275 ARMFastISel::AddOptionalDefs(const MachineInstrBuilder &MIB) {
276 MachineInstr *MI = &*MIB;
278 // Do we use a predicate? or...
279 // Are we NEON in ARM mode and have a predicate operand? If so, I know
280 // we're not predicable but add it anyways.
281 if (isARMNEONPred(MI))
284 // Do we optionally set a predicate? Preds is size > 0 iff the predicate
285 // defines CPSR. All other OptionalDefines in ARM are the CCR register.
287 if (DefinesOptionalPredicate(MI, &CPSR)) {
296 unsigned ARMFastISel::constrainOperandRegClass(const MCInstrDesc &II,
297 unsigned Op, unsigned OpNum) {
298 if (TargetRegisterInfo::isVirtualRegister(Op)) {
299 const TargetRegisterClass *RegClass =
300 TII.getRegClass(II, OpNum, &TRI, *FuncInfo.MF);
301 if (!MRI.constrainRegClass(Op, RegClass)) {
302 // If it's not legal to COPY between the register classes, something
303 // has gone very wrong before we got here.
304 unsigned NewOp = createResultReg(RegClass);
305 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
306 TII.get(TargetOpcode::COPY), NewOp).addReg(Op));
313 unsigned ARMFastISel::FastEmitInst_(unsigned MachineInstOpcode,
314 const TargetRegisterClass* RC) {
315 unsigned ResultReg = createResultReg(RC);
316 const MCInstrDesc &II = TII.get(MachineInstOpcode);
318 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg));
322 unsigned ARMFastISel::FastEmitInst_r(unsigned MachineInstOpcode,
323 const TargetRegisterClass *RC,
324 unsigned Op0, bool Op0IsKill) {
325 unsigned ResultReg = createResultReg(RC);
326 const MCInstrDesc &II = TII.get(MachineInstOpcode);
328 // Make sure the input operand is sufficiently constrained to be legal
329 // for this instruction.
330 Op0 = constrainOperandRegClass(II, Op0, 1);
331 if (II.getNumDefs() >= 1) {
332 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
333 .addReg(Op0, Op0IsKill * RegState::Kill));
335 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
336 .addReg(Op0, Op0IsKill * RegState::Kill));
337 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
338 TII.get(TargetOpcode::COPY), ResultReg)
339 .addReg(II.ImplicitDefs[0]));
344 unsigned ARMFastISel::FastEmitInst_rr(unsigned MachineInstOpcode,
345 const TargetRegisterClass *RC,
346 unsigned Op0, bool Op0IsKill,
347 unsigned Op1, bool Op1IsKill) {
348 unsigned ResultReg = createResultReg(RC);
349 const MCInstrDesc &II = TII.get(MachineInstOpcode);
351 // Make sure the input operands are sufficiently constrained to be legal
352 // for this instruction.
353 Op0 = constrainOperandRegClass(II, Op0, 1);
354 Op1 = constrainOperandRegClass(II, Op1, 2);
356 if (II.getNumDefs() >= 1) {
357 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
358 .addReg(Op0, Op0IsKill * RegState::Kill)
359 .addReg(Op1, Op1IsKill * RegState::Kill));
361 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
362 .addReg(Op0, Op0IsKill * RegState::Kill)
363 .addReg(Op1, Op1IsKill * RegState::Kill));
364 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
365 TII.get(TargetOpcode::COPY), ResultReg)
366 .addReg(II.ImplicitDefs[0]));
371 unsigned ARMFastISel::FastEmitInst_rrr(unsigned MachineInstOpcode,
372 const TargetRegisterClass *RC,
373 unsigned Op0, bool Op0IsKill,
374 unsigned Op1, bool Op1IsKill,
375 unsigned Op2, bool Op2IsKill) {
376 unsigned ResultReg = createResultReg(RC);
377 const MCInstrDesc &II = TII.get(MachineInstOpcode);
379 // Make sure the input operands are sufficiently constrained to be legal
380 // for this instruction.
381 Op0 = constrainOperandRegClass(II, Op0, 1);
382 Op1 = constrainOperandRegClass(II, Op1, 2);
383 Op2 = constrainOperandRegClass(II, Op1, 3);
385 if (II.getNumDefs() >= 1) {
386 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
387 .addReg(Op0, Op0IsKill * RegState::Kill)
388 .addReg(Op1, Op1IsKill * RegState::Kill)
389 .addReg(Op2, Op2IsKill * RegState::Kill));
391 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
392 .addReg(Op0, Op0IsKill * RegState::Kill)
393 .addReg(Op1, Op1IsKill * RegState::Kill)
394 .addReg(Op2, Op2IsKill * RegState::Kill));
395 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
396 TII.get(TargetOpcode::COPY), ResultReg)
397 .addReg(II.ImplicitDefs[0]));
402 unsigned ARMFastISel::FastEmitInst_ri(unsigned MachineInstOpcode,
403 const TargetRegisterClass *RC,
404 unsigned Op0, bool Op0IsKill,
406 unsigned ResultReg = createResultReg(RC);
407 const MCInstrDesc &II = TII.get(MachineInstOpcode);
409 // Make sure the input operand is sufficiently constrained to be legal
410 // for this instruction.
411 Op0 = constrainOperandRegClass(II, Op0, 1);
412 if (II.getNumDefs() >= 1) {
413 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
414 .addReg(Op0, Op0IsKill * RegState::Kill)
417 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
418 .addReg(Op0, Op0IsKill * RegState::Kill)
420 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
421 TII.get(TargetOpcode::COPY), ResultReg)
422 .addReg(II.ImplicitDefs[0]));
427 unsigned ARMFastISel::FastEmitInst_rf(unsigned MachineInstOpcode,
428 const TargetRegisterClass *RC,
429 unsigned Op0, bool Op0IsKill,
430 const ConstantFP *FPImm) {
431 unsigned ResultReg = createResultReg(RC);
432 const MCInstrDesc &II = TII.get(MachineInstOpcode);
434 // Make sure the input operand is sufficiently constrained to be legal
435 // for this instruction.
436 Op0 = constrainOperandRegClass(II, Op0, 1);
437 if (II.getNumDefs() >= 1) {
438 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
439 .addReg(Op0, Op0IsKill * RegState::Kill)
442 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
443 .addReg(Op0, Op0IsKill * RegState::Kill)
445 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
446 TII.get(TargetOpcode::COPY), ResultReg)
447 .addReg(II.ImplicitDefs[0]));
452 unsigned ARMFastISel::FastEmitInst_rri(unsigned MachineInstOpcode,
453 const TargetRegisterClass *RC,
454 unsigned Op0, bool Op0IsKill,
455 unsigned Op1, bool Op1IsKill,
457 unsigned ResultReg = createResultReg(RC);
458 const MCInstrDesc &II = TII.get(MachineInstOpcode);
460 // Make sure the input operands are sufficiently constrained to be legal
461 // for this instruction.
462 Op0 = constrainOperandRegClass(II, Op0, 1);
463 Op1 = constrainOperandRegClass(II, Op1, 2);
464 if (II.getNumDefs() >= 1) {
465 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
466 .addReg(Op0, Op0IsKill * RegState::Kill)
467 .addReg(Op1, Op1IsKill * RegState::Kill)
470 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
471 .addReg(Op0, Op0IsKill * RegState::Kill)
472 .addReg(Op1, Op1IsKill * RegState::Kill)
474 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
475 TII.get(TargetOpcode::COPY), ResultReg)
476 .addReg(II.ImplicitDefs[0]));
481 unsigned ARMFastISel::FastEmitInst_i(unsigned MachineInstOpcode,
482 const TargetRegisterClass *RC,
484 unsigned ResultReg = createResultReg(RC);
485 const MCInstrDesc &II = TII.get(MachineInstOpcode);
487 if (II.getNumDefs() >= 1) {
488 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
491 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
493 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
494 TII.get(TargetOpcode::COPY), ResultReg)
495 .addReg(II.ImplicitDefs[0]));
500 unsigned ARMFastISel::FastEmitInst_ii(unsigned MachineInstOpcode,
501 const TargetRegisterClass *RC,
502 uint64_t Imm1, uint64_t Imm2) {
503 unsigned ResultReg = createResultReg(RC);
504 const MCInstrDesc &II = TII.get(MachineInstOpcode);
506 if (II.getNumDefs() >= 1) {
507 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
508 .addImm(Imm1).addImm(Imm2));
510 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
511 .addImm(Imm1).addImm(Imm2));
512 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
513 TII.get(TargetOpcode::COPY),
515 .addReg(II.ImplicitDefs[0]));
520 unsigned ARMFastISel::FastEmitInst_extractsubreg(MVT RetVT,
521 unsigned Op0, bool Op0IsKill,
523 unsigned ResultReg = createResultReg(TLI.getRegClassFor(RetVT));
524 assert(TargetRegisterInfo::isVirtualRegister(Op0) &&
525 "Cannot yet extract from physregs");
527 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt,
528 DL, TII.get(TargetOpcode::COPY), ResultReg)
529 .addReg(Op0, getKillRegState(Op0IsKill), Idx));
533 // TODO: Don't worry about 64-bit now, but when this is fixed remove the
534 // checks from the various callers.
535 unsigned ARMFastISel::ARMMoveToFPReg(MVT VT, unsigned SrcReg) {
536 if (VT == MVT::f64) return 0;
538 unsigned MoveReg = createResultReg(TLI.getRegClassFor(VT));
539 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
540 TII.get(ARM::VMOVSR), MoveReg)
545 unsigned ARMFastISel::ARMMoveToIntReg(MVT VT, unsigned SrcReg) {
546 if (VT == MVT::i64) return 0;
548 unsigned MoveReg = createResultReg(TLI.getRegClassFor(VT));
549 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
550 TII.get(ARM::VMOVRS), MoveReg)
555 // For double width floating point we need to materialize two constants
556 // (the high and the low) into integer registers then use a move to get
557 // the combined constant into an FP reg.
558 unsigned ARMFastISel::ARMMaterializeFP(const ConstantFP *CFP, MVT VT) {
559 const APFloat Val = CFP->getValueAPF();
560 bool is64bit = VT == MVT::f64;
562 // This checks to see if we can use VFP3 instructions to materialize
563 // a constant, otherwise we have to go through the constant pool.
564 if (TLI.isFPImmLegal(Val, VT)) {
568 Imm = ARM_AM::getFP64Imm(Val);
571 Imm = ARM_AM::getFP32Imm(Val);
574 unsigned DestReg = createResultReg(TLI.getRegClassFor(VT));
575 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc),
581 // Require VFP2 for loading fp constants.
582 if (!Subtarget->hasVFP2()) return false;
584 // MachineConstantPool wants an explicit alignment.
585 unsigned Align = TD.getPrefTypeAlignment(CFP->getType());
587 // TODO: Figure out if this is correct.
588 Align = TD.getTypeAllocSize(CFP->getType());
590 unsigned Idx = MCP.getConstantPoolIndex(cast<Constant>(CFP), Align);
591 unsigned DestReg = createResultReg(TLI.getRegClassFor(VT));
592 unsigned Opc = is64bit ? ARM::VLDRD : ARM::VLDRS;
594 // The extra reg is for addrmode5.
595 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc),
597 .addConstantPoolIndex(Idx)
602 unsigned ARMFastISel::ARMMaterializeInt(const Constant *C, MVT VT) {
604 if (VT != MVT::i32 && VT != MVT::i16 && VT != MVT::i8 && VT != MVT::i1)
607 // If we can do this in a single instruction without a constant pool entry
609 const ConstantInt *CI = cast<ConstantInt>(C);
610 if (Subtarget->hasV6T2Ops() && isUInt<16>(CI->getZExtValue())) {
611 unsigned Opc = isThumb2 ? ARM::t2MOVi16 : ARM::MOVi16;
612 const TargetRegisterClass *RC = isThumb2 ? &ARM::rGPRRegClass :
614 unsigned ImmReg = createResultReg(RC);
615 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
616 TII.get(Opc), ImmReg)
617 .addImm(CI->getZExtValue()));
621 // Use MVN to emit negative constants.
622 if (VT == MVT::i32 && Subtarget->hasV6T2Ops() && CI->isNegative()) {
623 unsigned Imm = (unsigned)~(CI->getSExtValue());
624 bool UseImm = isThumb2 ? (ARM_AM::getT2SOImmVal(Imm) != -1) :
625 (ARM_AM::getSOImmVal(Imm) != -1);
627 unsigned Opc = isThumb2 ? ARM::t2MVNi : ARM::MVNi;
628 unsigned ImmReg = createResultReg(TLI.getRegClassFor(MVT::i32));
629 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
630 TII.get(Opc), ImmReg)
636 // Load from constant pool. For now 32-bit only.
640 unsigned DestReg = createResultReg(TLI.getRegClassFor(VT));
642 // MachineConstantPool wants an explicit alignment.
643 unsigned Align = TD.getPrefTypeAlignment(C->getType());
645 // TODO: Figure out if this is correct.
646 Align = TD.getTypeAllocSize(C->getType());
648 unsigned Idx = MCP.getConstantPoolIndex(C, Align);
651 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
652 TII.get(ARM::t2LDRpci), DestReg)
653 .addConstantPoolIndex(Idx));
655 // The extra immediate is for addrmode2.
656 DestReg = constrainOperandRegClass(TII.get(ARM::LDRcp), DestReg, 0);
657 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
658 TII.get(ARM::LDRcp), DestReg)
659 .addConstantPoolIndex(Idx)
665 unsigned ARMFastISel::ARMMaterializeGV(const GlobalValue *GV, MVT VT) {
666 // For now 32-bit only.
667 if (VT != MVT::i32) return 0;
669 Reloc::Model RelocM = TM.getRelocationModel();
670 bool IsIndirect = Subtarget->GVIsIndirectSymbol(GV, RelocM);
671 const TargetRegisterClass *RC = isThumb2 ?
672 (const TargetRegisterClass*)&ARM::rGPRRegClass :
673 (const TargetRegisterClass*)&ARM::GPRRegClass;
674 unsigned DestReg = createResultReg(RC);
676 // FastISel TLS support on non-Darwin is broken, punt to SelectionDAG.
677 const GlobalVariable *GVar = dyn_cast<GlobalVariable>(GV);
678 bool IsThreadLocal = GVar && GVar->isThreadLocal();
679 if (!Subtarget->isTargetDarwin() && IsThreadLocal) return 0;
681 // Use movw+movt when possible, it avoids constant pool entries.
682 // Darwin targets don't support movt with Reloc::Static, see
683 // ARMTargetLowering::LowerGlobalAddressDarwin. Other targets only support
684 // static movt relocations.
685 if (Subtarget->useMovt() &&
686 Subtarget->isTargetDarwin() == (RelocM != Reloc::Static)) {
690 Opc = isThumb2 ? ARM::t2MOV_ga_pcrel : ARM::MOV_ga_pcrel;
692 case Reloc::DynamicNoPIC:
693 Opc = isThumb2 ? ARM::t2MOV_ga_dyn : ARM::MOV_ga_dyn;
696 Opc = isThumb2 ? ARM::t2MOVi32imm : ARM::MOVi32imm;
699 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc),
700 DestReg).addGlobalAddress(GV));
702 // MachineConstantPool wants an explicit alignment.
703 unsigned Align = TD.getPrefTypeAlignment(GV->getType());
705 // TODO: Figure out if this is correct.
706 Align = TD.getTypeAllocSize(GV->getType());
709 if (Subtarget->isTargetELF() && RelocM == Reloc::PIC_)
710 return ARMLowerPICELF(GV, Align, VT);
713 unsigned PCAdj = (RelocM != Reloc::PIC_) ? 0 :
714 (Subtarget->isThumb() ? 4 : 8);
715 unsigned Id = AFI->createPICLabelUId();
716 ARMConstantPoolValue *CPV = ARMConstantPoolConstant::Create(GV, Id,
719 unsigned Idx = MCP.getConstantPoolIndex(CPV, Align);
722 MachineInstrBuilder MIB;
724 unsigned Opc = (RelocM!=Reloc::PIC_) ? ARM::t2LDRpci : ARM::t2LDRpci_pic;
725 MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc), DestReg)
726 .addConstantPoolIndex(Idx);
727 if (RelocM == Reloc::PIC_)
729 AddOptionalDefs(MIB);
731 // The extra immediate is for addrmode2.
732 DestReg = constrainOperandRegClass(TII.get(ARM::LDRcp), DestReg, 0);
733 MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(ARM::LDRcp),
735 .addConstantPoolIndex(Idx)
737 AddOptionalDefs(MIB);
739 if (RelocM == Reloc::PIC_) {
740 unsigned Opc = IsIndirect ? ARM::PICLDR : ARM::PICADD;
741 unsigned NewDestReg = createResultReg(TLI.getRegClassFor(VT));
743 MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt,
744 DL, TII.get(Opc), NewDestReg)
747 AddOptionalDefs(MIB);
754 MachineInstrBuilder MIB;
755 unsigned NewDestReg = createResultReg(TLI.getRegClassFor(VT));
757 MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
758 TII.get(ARM::t2LDRi12), NewDestReg)
762 MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(ARM::LDRi12),
766 DestReg = NewDestReg;
767 AddOptionalDefs(MIB);
773 unsigned ARMFastISel::TargetMaterializeConstant(const Constant *C) {
774 EVT CEVT = TLI.getValueType(C->getType(), true);
776 // Only handle simple types.
777 if (!CEVT.isSimple()) return 0;
778 MVT VT = CEVT.getSimpleVT();
780 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(C))
781 return ARMMaterializeFP(CFP, VT);
782 else if (const GlobalValue *GV = dyn_cast<GlobalValue>(C))
783 return ARMMaterializeGV(GV, VT);
784 else if (isa<ConstantInt>(C))
785 return ARMMaterializeInt(C, VT);
790 // TODO: unsigned ARMFastISel::TargetMaterializeFloatZero(const ConstantFP *CF);
792 unsigned ARMFastISel::TargetMaterializeAlloca(const AllocaInst *AI) {
793 // Don't handle dynamic allocas.
794 if (!FuncInfo.StaticAllocaMap.count(AI)) return 0;
797 if (!isLoadTypeLegal(AI->getType(), VT)) return 0;
799 DenseMap<const AllocaInst*, int>::iterator SI =
800 FuncInfo.StaticAllocaMap.find(AI);
802 // This will get lowered later into the correct offsets and registers
803 // via rewriteXFrameIndex.
804 if (SI != FuncInfo.StaticAllocaMap.end()) {
805 const TargetRegisterClass* RC = TLI.getRegClassFor(VT);
806 unsigned ResultReg = createResultReg(RC);
807 unsigned Opc = isThumb2 ? ARM::t2ADDri : ARM::ADDri;
808 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
809 TII.get(Opc), ResultReg)
810 .addFrameIndex(SI->second)
818 bool ARMFastISel::isTypeLegal(Type *Ty, MVT &VT) {
819 EVT evt = TLI.getValueType(Ty, true);
821 // Only handle simple types.
822 if (evt == MVT::Other || !evt.isSimple()) return false;
823 VT = evt.getSimpleVT();
825 // Handle all legal types, i.e. a register that will directly hold this
827 return TLI.isTypeLegal(VT);
830 bool ARMFastISel::isLoadTypeLegal(Type *Ty, MVT &VT) {
831 if (isTypeLegal(Ty, VT)) return true;
833 // If this is a type than can be sign or zero-extended to a basic operation
834 // go ahead and accept it now.
835 if (VT == MVT::i1 || VT == MVT::i8 || VT == MVT::i16)
841 // Computes the address to get to an object.
842 bool ARMFastISel::ARMComputeAddress(const Value *Obj, Address &Addr) {
843 // Some boilerplate from the X86 FastISel.
844 const User *U = NULL;
845 unsigned Opcode = Instruction::UserOp1;
846 if (const Instruction *I = dyn_cast<Instruction>(Obj)) {
847 // Don't walk into other basic blocks unless the object is an alloca from
848 // another block, otherwise it may not have a virtual register assigned.
849 if (FuncInfo.StaticAllocaMap.count(static_cast<const AllocaInst *>(Obj)) ||
850 FuncInfo.MBBMap[I->getParent()] == FuncInfo.MBB) {
851 Opcode = I->getOpcode();
854 } else if (const ConstantExpr *C = dyn_cast<ConstantExpr>(Obj)) {
855 Opcode = C->getOpcode();
859 if (PointerType *Ty = dyn_cast<PointerType>(Obj->getType()))
860 if (Ty->getAddressSpace() > 255)
861 // Fast instruction selection doesn't support the special
868 case Instruction::BitCast:
869 // Look through bitcasts.
870 return ARMComputeAddress(U->getOperand(0), Addr);
871 case Instruction::IntToPtr:
872 // Look past no-op inttoptrs.
873 if (TLI.getValueType(U->getOperand(0)->getType()) == TLI.getPointerTy())
874 return ARMComputeAddress(U->getOperand(0), Addr);
876 case Instruction::PtrToInt:
877 // Look past no-op ptrtoints.
878 if (TLI.getValueType(U->getType()) == TLI.getPointerTy())
879 return ARMComputeAddress(U->getOperand(0), Addr);
881 case Instruction::GetElementPtr: {
882 Address SavedAddr = Addr;
883 int TmpOffset = Addr.Offset;
885 // Iterate through the GEP folding the constants into offsets where
887 gep_type_iterator GTI = gep_type_begin(U);
888 for (User::const_op_iterator i = U->op_begin() + 1, e = U->op_end();
889 i != e; ++i, ++GTI) {
890 const Value *Op = *i;
891 if (StructType *STy = dyn_cast<StructType>(*GTI)) {
892 const StructLayout *SL = TD.getStructLayout(STy);
893 unsigned Idx = cast<ConstantInt>(Op)->getZExtValue();
894 TmpOffset += SL->getElementOffset(Idx);
896 uint64_t S = TD.getTypeAllocSize(GTI.getIndexedType());
898 if (const ConstantInt *CI = dyn_cast<ConstantInt>(Op)) {
899 // Constant-offset addressing.
900 TmpOffset += CI->getSExtValue() * S;
903 if (isa<AddOperator>(Op) &&
904 (!isa<Instruction>(Op) ||
905 FuncInfo.MBBMap[cast<Instruction>(Op)->getParent()]
907 isa<ConstantInt>(cast<AddOperator>(Op)->getOperand(1))) {
908 // An add (in the same block) with a constant operand. Fold the
911 cast<ConstantInt>(cast<AddOperator>(Op)->getOperand(1));
912 TmpOffset += CI->getSExtValue() * S;
913 // Iterate on the other operand.
914 Op = cast<AddOperator>(Op)->getOperand(0);
918 goto unsupported_gep;
923 // Try to grab the base operand now.
924 Addr.Offset = TmpOffset;
925 if (ARMComputeAddress(U->getOperand(0), Addr)) return true;
927 // We failed, restore everything and try the other options.
933 case Instruction::Alloca: {
934 const AllocaInst *AI = cast<AllocaInst>(Obj);
935 DenseMap<const AllocaInst*, int>::iterator SI =
936 FuncInfo.StaticAllocaMap.find(AI);
937 if (SI != FuncInfo.StaticAllocaMap.end()) {
938 Addr.BaseType = Address::FrameIndexBase;
939 Addr.Base.FI = SI->second;
946 // Try to get this in a register if nothing else has worked.
947 if (Addr.Base.Reg == 0) Addr.Base.Reg = getRegForValue(Obj);
948 return Addr.Base.Reg != 0;
951 void ARMFastISel::ARMSimplifyAddress(Address &Addr, MVT VT, bool useAM3) {
952 bool needsLowering = false;
953 switch (VT.SimpleTy) {
954 default: llvm_unreachable("Unhandled load/store type!");
960 // Integer loads/stores handle 12-bit offsets.
961 needsLowering = ((Addr.Offset & 0xfff) != Addr.Offset);
962 // Handle negative offsets.
963 if (needsLowering && isThumb2)
964 needsLowering = !(Subtarget->hasV6T2Ops() && Addr.Offset < 0 &&
967 // ARM halfword load/stores and signed byte loads use +/-imm8 offsets.
968 needsLowering = (Addr.Offset > 255 || Addr.Offset < -255);
973 // Floating point operands handle 8-bit offsets.
974 needsLowering = ((Addr.Offset & 0xff) != Addr.Offset);
978 // If this is a stack pointer and the offset needs to be simplified then
979 // put the alloca address into a register, set the base type back to
980 // register and continue. This should almost never happen.
981 if (needsLowering && Addr.BaseType == Address::FrameIndexBase) {
982 const TargetRegisterClass *RC = isThumb2 ?
983 (const TargetRegisterClass*)&ARM::tGPRRegClass :
984 (const TargetRegisterClass*)&ARM::GPRRegClass;
985 unsigned ResultReg = createResultReg(RC);
986 unsigned Opc = isThumb2 ? ARM::t2ADDri : ARM::ADDri;
987 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
988 TII.get(Opc), ResultReg)
989 .addFrameIndex(Addr.Base.FI)
991 Addr.Base.Reg = ResultReg;
992 Addr.BaseType = Address::RegBase;
995 // Since the offset is too large for the load/store instruction
996 // get the reg+offset into a register.
998 Addr.Base.Reg = FastEmit_ri_(MVT::i32, ISD::ADD, Addr.Base.Reg,
999 /*Op0IsKill*/false, Addr.Offset, MVT::i32);
1004 void ARMFastISel::AddLoadStoreOperands(MVT VT, Address &Addr,
1005 const MachineInstrBuilder &MIB,
1006 unsigned Flags, bool useAM3) {
1007 // addrmode5 output depends on the selection dag addressing dividing the
1008 // offset by 4 that it then later multiplies. Do this here as well.
1009 if (VT.SimpleTy == MVT::f32 || VT.SimpleTy == MVT::f64)
1012 // Frame base works a bit differently. Handle it separately.
1013 if (Addr.BaseType == Address::FrameIndexBase) {
1014 int FI = Addr.Base.FI;
1015 int Offset = Addr.Offset;
1016 MachineMemOperand *MMO =
1017 FuncInfo.MF->getMachineMemOperand(
1018 MachinePointerInfo::getFixedStack(FI, Offset),
1020 MFI.getObjectSize(FI),
1021 MFI.getObjectAlignment(FI));
1022 // Now add the rest of the operands.
1023 MIB.addFrameIndex(FI);
1025 // ARM halfword load/stores and signed byte loads need an additional
1028 signed Imm = (Addr.Offset < 0) ? (0x100 | -Addr.Offset) : Addr.Offset;
1032 MIB.addImm(Addr.Offset);
1034 MIB.addMemOperand(MMO);
1036 // Now add the rest of the operands.
1037 MIB.addReg(Addr.Base.Reg);
1039 // ARM halfword load/stores and signed byte loads need an additional
1042 signed Imm = (Addr.Offset < 0) ? (0x100 | -Addr.Offset) : Addr.Offset;
1046 MIB.addImm(Addr.Offset);
1049 AddOptionalDefs(MIB);
1052 bool ARMFastISel::ARMEmitLoad(MVT VT, unsigned &ResultReg, Address &Addr,
1053 unsigned Alignment, bool isZExt, bool allocReg) {
1055 bool useAM3 = false;
1056 bool needVMOV = false;
1057 const TargetRegisterClass *RC;
1058 switch (VT.SimpleTy) {
1059 // This is mostly going to be Neon/vector support.
1060 default: return false;
1064 if (Addr.Offset < 0 && Addr.Offset > -256 && Subtarget->hasV6T2Ops())
1065 Opc = isZExt ? ARM::t2LDRBi8 : ARM::t2LDRSBi8;
1067 Opc = isZExt ? ARM::t2LDRBi12 : ARM::t2LDRSBi12;
1076 RC = isThumb2 ? &ARM::rGPRRegClass : &ARM::GPRnopcRegClass;
1079 if (Alignment && Alignment < 2 && !Subtarget->allowsUnalignedMem())
1083 if (Addr.Offset < 0 && Addr.Offset > -256 && Subtarget->hasV6T2Ops())
1084 Opc = isZExt ? ARM::t2LDRHi8 : ARM::t2LDRSHi8;
1086 Opc = isZExt ? ARM::t2LDRHi12 : ARM::t2LDRSHi12;
1088 Opc = isZExt ? ARM::LDRH : ARM::LDRSH;
1091 RC = isThumb2 ? &ARM::rGPRRegClass : &ARM::GPRnopcRegClass;
1094 if (Alignment && Alignment < 4 && !Subtarget->allowsUnalignedMem())
1098 if (Addr.Offset < 0 && Addr.Offset > -256 && Subtarget->hasV6T2Ops())
1101 Opc = ARM::t2LDRi12;
1105 RC = isThumb2 ? &ARM::rGPRRegClass : &ARM::GPRnopcRegClass;
1108 if (!Subtarget->hasVFP2()) return false;
1109 // Unaligned loads need special handling. Floats require word-alignment.
1110 if (Alignment && Alignment < 4) {
1113 Opc = isThumb2 ? ARM::t2LDRi12 : ARM::LDRi12;
1114 RC = isThumb2 ? &ARM::rGPRRegClass : &ARM::GPRnopcRegClass;
1117 RC = TLI.getRegClassFor(VT);
1121 if (!Subtarget->hasVFP2()) return false;
1122 // FIXME: Unaligned loads need special handling. Doublewords require
1124 if (Alignment && Alignment < 4)
1128 RC = TLI.getRegClassFor(VT);
1131 // Simplify this down to something we can handle.
1132 ARMSimplifyAddress(Addr, VT, useAM3);
1134 // Create the base instruction, then add the operands.
1136 ResultReg = createResultReg(RC);
1137 assert (ResultReg > 255 && "Expected an allocated virtual register.");
1138 MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1139 TII.get(Opc), ResultReg);
1140 AddLoadStoreOperands(VT, Addr, MIB, MachineMemOperand::MOLoad, useAM3);
1142 // If we had an unaligned load of a float we've converted it to an regular
1143 // load. Now we must move from the GRP to the FP register.
1145 unsigned MoveReg = createResultReg(TLI.getRegClassFor(MVT::f32));
1146 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1147 TII.get(ARM::VMOVSR), MoveReg)
1148 .addReg(ResultReg));
1149 ResultReg = MoveReg;
1154 bool ARMFastISel::SelectLoad(const Instruction *I) {
1155 // Atomic loads need special handling.
1156 if (cast<LoadInst>(I)->isAtomic())
1159 // Verify we have a legal type before going any further.
1161 if (!isLoadTypeLegal(I->getType(), VT))
1164 // See if we can handle this address.
1166 if (!ARMComputeAddress(I->getOperand(0), Addr)) return false;
1169 if (!ARMEmitLoad(VT, ResultReg, Addr, cast<LoadInst>(I)->getAlignment()))
1171 UpdateValueMap(I, ResultReg);
1175 bool ARMFastISel::ARMEmitStore(MVT VT, unsigned SrcReg, Address &Addr,
1176 unsigned Alignment) {
1178 bool useAM3 = false;
1179 switch (VT.SimpleTy) {
1180 // This is mostly going to be Neon/vector support.
1181 default: return false;
1183 unsigned Res = createResultReg(isThumb2 ?
1184 (const TargetRegisterClass*)&ARM::tGPRRegClass :
1185 (const TargetRegisterClass*)&ARM::GPRRegClass);
1186 unsigned Opc = isThumb2 ? ARM::t2ANDri : ARM::ANDri;
1187 SrcReg = constrainOperandRegClass(TII.get(Opc), SrcReg, 1);
1188 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1190 .addReg(SrcReg).addImm(1));
1192 } // Fallthrough here.
1195 if (Addr.Offset < 0 && Addr.Offset > -256 && Subtarget->hasV6T2Ops())
1196 StrOpc = ARM::t2STRBi8;
1198 StrOpc = ARM::t2STRBi12;
1200 StrOpc = ARM::STRBi12;
1204 if (Alignment && Alignment < 2 && !Subtarget->allowsUnalignedMem())
1208 if (Addr.Offset < 0 && Addr.Offset > -256 && Subtarget->hasV6T2Ops())
1209 StrOpc = ARM::t2STRHi8;
1211 StrOpc = ARM::t2STRHi12;
1218 if (Alignment && Alignment < 4 && !Subtarget->allowsUnalignedMem())
1222 if (Addr.Offset < 0 && Addr.Offset > -256 && Subtarget->hasV6T2Ops())
1223 StrOpc = ARM::t2STRi8;
1225 StrOpc = ARM::t2STRi12;
1227 StrOpc = ARM::STRi12;
1231 if (!Subtarget->hasVFP2()) return false;
1232 // Unaligned stores need special handling. Floats require word-alignment.
1233 if (Alignment && Alignment < 4) {
1234 unsigned MoveReg = createResultReg(TLI.getRegClassFor(MVT::i32));
1235 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1236 TII.get(ARM::VMOVRS), MoveReg)
1240 StrOpc = isThumb2 ? ARM::t2STRi12 : ARM::STRi12;
1242 StrOpc = ARM::VSTRS;
1246 if (!Subtarget->hasVFP2()) return false;
1247 // FIXME: Unaligned stores need special handling. Doublewords require
1249 if (Alignment && Alignment < 4)
1252 StrOpc = ARM::VSTRD;
1255 // Simplify this down to something we can handle.
1256 ARMSimplifyAddress(Addr, VT, useAM3);
1258 // Create the base instruction, then add the operands.
1259 SrcReg = constrainOperandRegClass(TII.get(StrOpc), SrcReg, 0);
1260 MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1263 AddLoadStoreOperands(VT, Addr, MIB, MachineMemOperand::MOStore, useAM3);
1267 bool ARMFastISel::SelectStore(const Instruction *I) {
1268 Value *Op0 = I->getOperand(0);
1269 unsigned SrcReg = 0;
1271 // Atomic stores need special handling.
1272 if (cast<StoreInst>(I)->isAtomic())
1275 // Verify we have a legal type before going any further.
1277 if (!isLoadTypeLegal(I->getOperand(0)->getType(), VT))
1280 // Get the value to be stored into a register.
1281 SrcReg = getRegForValue(Op0);
1282 if (SrcReg == 0) return false;
1284 // See if we can handle this address.
1286 if (!ARMComputeAddress(I->getOperand(1), Addr))
1289 if (!ARMEmitStore(VT, SrcReg, Addr, cast<StoreInst>(I)->getAlignment()))
1294 static ARMCC::CondCodes getComparePred(CmpInst::Predicate Pred) {
1296 // Needs two compares...
1297 case CmpInst::FCMP_ONE:
1298 case CmpInst::FCMP_UEQ:
1300 // AL is our "false" for now. The other two need more compares.
1302 case CmpInst::ICMP_EQ:
1303 case CmpInst::FCMP_OEQ:
1305 case CmpInst::ICMP_SGT:
1306 case CmpInst::FCMP_OGT:
1308 case CmpInst::ICMP_SGE:
1309 case CmpInst::FCMP_OGE:
1311 case CmpInst::ICMP_UGT:
1312 case CmpInst::FCMP_UGT:
1314 case CmpInst::FCMP_OLT:
1316 case CmpInst::ICMP_ULE:
1317 case CmpInst::FCMP_OLE:
1319 case CmpInst::FCMP_ORD:
1321 case CmpInst::FCMP_UNO:
1323 case CmpInst::FCMP_UGE:
1325 case CmpInst::ICMP_SLT:
1326 case CmpInst::FCMP_ULT:
1328 case CmpInst::ICMP_SLE:
1329 case CmpInst::FCMP_ULE:
1331 case CmpInst::FCMP_UNE:
1332 case CmpInst::ICMP_NE:
1334 case CmpInst::ICMP_UGE:
1336 case CmpInst::ICMP_ULT:
1341 bool ARMFastISel::SelectBranch(const Instruction *I) {
1342 const BranchInst *BI = cast<BranchInst>(I);
1343 MachineBasicBlock *TBB = FuncInfo.MBBMap[BI->getSuccessor(0)];
1344 MachineBasicBlock *FBB = FuncInfo.MBBMap[BI->getSuccessor(1)];
1346 // Simple branch support.
1348 // If we can, avoid recomputing the compare - redoing it could lead to wonky
1350 if (const CmpInst *CI = dyn_cast<CmpInst>(BI->getCondition())) {
1351 if (CI->hasOneUse() && (CI->getParent() == I->getParent())) {
1353 // Get the compare predicate.
1354 // Try to take advantage of fallthrough opportunities.
1355 CmpInst::Predicate Predicate = CI->getPredicate();
1356 if (FuncInfo.MBB->isLayoutSuccessor(TBB)) {
1357 std::swap(TBB, FBB);
1358 Predicate = CmpInst::getInversePredicate(Predicate);
1361 ARMCC::CondCodes ARMPred = getComparePred(Predicate);
1363 // We may not handle every CC for now.
1364 if (ARMPred == ARMCC::AL) return false;
1366 // Emit the compare.
1367 if (!ARMEmitCmp(CI->getOperand(0), CI->getOperand(1), CI->isUnsigned()))
1370 unsigned BrOpc = isThumb2 ? ARM::t2Bcc : ARM::Bcc;
1371 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(BrOpc))
1372 .addMBB(TBB).addImm(ARMPred).addReg(ARM::CPSR);
1373 FastEmitBranch(FBB, DL);
1374 FuncInfo.MBB->addSuccessor(TBB);
1377 } else if (TruncInst *TI = dyn_cast<TruncInst>(BI->getCondition())) {
1379 if (TI->hasOneUse() && TI->getParent() == I->getParent() &&
1380 (isLoadTypeLegal(TI->getOperand(0)->getType(), SourceVT))) {
1381 unsigned TstOpc = isThumb2 ? ARM::t2TSTri : ARM::TSTri;
1382 unsigned OpReg = getRegForValue(TI->getOperand(0));
1383 OpReg = constrainOperandRegClass(TII.get(TstOpc), OpReg, 0);
1384 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1386 .addReg(OpReg).addImm(1));
1388 unsigned CCMode = ARMCC::NE;
1389 if (FuncInfo.MBB->isLayoutSuccessor(TBB)) {
1390 std::swap(TBB, FBB);
1394 unsigned BrOpc = isThumb2 ? ARM::t2Bcc : ARM::Bcc;
1395 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(BrOpc))
1396 .addMBB(TBB).addImm(CCMode).addReg(ARM::CPSR);
1398 FastEmitBranch(FBB, DL);
1399 FuncInfo.MBB->addSuccessor(TBB);
1402 } else if (const ConstantInt *CI =
1403 dyn_cast<ConstantInt>(BI->getCondition())) {
1404 uint64_t Imm = CI->getZExtValue();
1405 MachineBasicBlock *Target = (Imm == 0) ? FBB : TBB;
1406 FastEmitBranch(Target, DL);
1410 unsigned CmpReg = getRegForValue(BI->getCondition());
1411 if (CmpReg == 0) return false;
1413 // We've been divorced from our compare! Our block was split, and
1414 // now our compare lives in a predecessor block. We musn't
1415 // re-compare here, as the children of the compare aren't guaranteed
1416 // live across the block boundary (we *could* check for this).
1417 // Regardless, the compare has been done in the predecessor block,
1418 // and it left a value for us in a virtual register. Ergo, we test
1419 // the one-bit value left in the virtual register.
1420 unsigned TstOpc = isThumb2 ? ARM::t2TSTri : ARM::TSTri;
1421 CmpReg = constrainOperandRegClass(TII.get(TstOpc), CmpReg, 0);
1422 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TstOpc))
1423 .addReg(CmpReg).addImm(1));
1425 unsigned CCMode = ARMCC::NE;
1426 if (FuncInfo.MBB->isLayoutSuccessor(TBB)) {
1427 std::swap(TBB, FBB);
1431 unsigned BrOpc = isThumb2 ? ARM::t2Bcc : ARM::Bcc;
1432 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(BrOpc))
1433 .addMBB(TBB).addImm(CCMode).addReg(ARM::CPSR);
1434 FastEmitBranch(FBB, DL);
1435 FuncInfo.MBB->addSuccessor(TBB);
1439 bool ARMFastISel::SelectIndirectBr(const Instruction *I) {
1440 unsigned AddrReg = getRegForValue(I->getOperand(0));
1441 if (AddrReg == 0) return false;
1443 unsigned Opc = isThumb2 ? ARM::tBRIND : ARM::BX;
1444 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc))
1447 const IndirectBrInst *IB = cast<IndirectBrInst>(I);
1448 for (unsigned i = 0, e = IB->getNumSuccessors(); i != e; ++i)
1449 FuncInfo.MBB->addSuccessor(FuncInfo.MBBMap[IB->getSuccessor(i)]);
1454 bool ARMFastISel::ARMEmitCmp(const Value *Src1Value, const Value *Src2Value,
1456 Type *Ty = Src1Value->getType();
1457 EVT SrcEVT = TLI.getValueType(Ty, true);
1458 if (!SrcEVT.isSimple()) return false;
1459 MVT SrcVT = SrcEVT.getSimpleVT();
1461 bool isFloat = (Ty->isFloatTy() || Ty->isDoubleTy());
1462 if (isFloat && !Subtarget->hasVFP2())
1465 // Check to see if the 2nd operand is a constant that we can encode directly
1468 bool UseImm = false;
1469 bool isNegativeImm = false;
1470 // FIXME: At -O0 we don't have anything that canonicalizes operand order.
1471 // Thus, Src1Value may be a ConstantInt, but we're missing it.
1472 if (const ConstantInt *ConstInt = dyn_cast<ConstantInt>(Src2Value)) {
1473 if (SrcVT == MVT::i32 || SrcVT == MVT::i16 || SrcVT == MVT::i8 ||
1475 const APInt &CIVal = ConstInt->getValue();
1476 Imm = (isZExt) ? (int)CIVal.getZExtValue() : (int)CIVal.getSExtValue();
1477 // For INT_MIN/LONG_MIN (i.e., 0x80000000) we need to use a cmp, rather
1478 // then a cmn, because there is no way to represent 2147483648 as a
1479 // signed 32-bit int.
1480 if (Imm < 0 && Imm != (int)0x80000000) {
1481 isNegativeImm = true;
1484 UseImm = isThumb2 ? (ARM_AM::getT2SOImmVal(Imm) != -1) :
1485 (ARM_AM::getSOImmVal(Imm) != -1);
1487 } else if (const ConstantFP *ConstFP = dyn_cast<ConstantFP>(Src2Value)) {
1488 if (SrcVT == MVT::f32 || SrcVT == MVT::f64)
1489 if (ConstFP->isZero() && !ConstFP->isNegative())
1495 bool needsExt = false;
1496 switch (SrcVT.SimpleTy) {
1497 default: return false;
1498 // TODO: Verify compares.
1501 CmpOpc = UseImm ? ARM::VCMPEZS : ARM::VCMPES;
1505 CmpOpc = UseImm ? ARM::VCMPEZD : ARM::VCMPED;
1511 // Intentional fall-through.
1515 CmpOpc = ARM::t2CMPrr;
1517 CmpOpc = isNegativeImm ? ARM::t2CMNri : ARM::t2CMPri;
1520 CmpOpc = ARM::CMPrr;
1522 CmpOpc = isNegativeImm ? ARM::CMNri : ARM::CMPri;
1527 unsigned SrcReg1 = getRegForValue(Src1Value);
1528 if (SrcReg1 == 0) return false;
1530 unsigned SrcReg2 = 0;
1532 SrcReg2 = getRegForValue(Src2Value);
1533 if (SrcReg2 == 0) return false;
1536 // We have i1, i8, or i16, we need to either zero extend or sign extend.
1538 SrcReg1 = ARMEmitIntExt(SrcVT, SrcReg1, MVT::i32, isZExt);
1539 if (SrcReg1 == 0) return false;
1541 SrcReg2 = ARMEmitIntExt(SrcVT, SrcReg2, MVT::i32, isZExt);
1542 if (SrcReg2 == 0) return false;
1546 const MCInstrDesc &II = TII.get(CmpOpc);
1547 SrcReg1 = constrainOperandRegClass(II, SrcReg1, 0);
1549 SrcReg2 = constrainOperandRegClass(II, SrcReg2, 1);
1550 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
1551 .addReg(SrcReg1).addReg(SrcReg2));
1553 MachineInstrBuilder MIB;
1554 MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
1557 // Only add immediate for icmp as the immediate for fcmp is an implicit 0.0.
1560 AddOptionalDefs(MIB);
1563 // For floating point we need to move the result to a comparison register
1564 // that we can then use for branches.
1565 if (Ty->isFloatTy() || Ty->isDoubleTy())
1566 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1567 TII.get(ARM::FMSTAT)));
1571 bool ARMFastISel::SelectCmp(const Instruction *I) {
1572 const CmpInst *CI = cast<CmpInst>(I);
1574 // Get the compare predicate.
1575 ARMCC::CondCodes ARMPred = getComparePred(CI->getPredicate());
1577 // We may not handle every CC for now.
1578 if (ARMPred == ARMCC::AL) return false;
1580 // Emit the compare.
1581 if (!ARMEmitCmp(CI->getOperand(0), CI->getOperand(1), CI->isUnsigned()))
1584 // Now set a register based on the comparison. Explicitly set the predicates
1586 unsigned MovCCOpc = isThumb2 ? ARM::t2MOVCCi : ARM::MOVCCi;
1587 const TargetRegisterClass *RC = isThumb2 ?
1588 (const TargetRegisterClass*)&ARM::rGPRRegClass :
1589 (const TargetRegisterClass*)&ARM::GPRRegClass;
1590 unsigned DestReg = createResultReg(RC);
1591 Constant *Zero = ConstantInt::get(Type::getInt32Ty(*Context), 0);
1592 unsigned ZeroReg = TargetMaterializeConstant(Zero);
1593 // ARMEmitCmp emits a FMSTAT when necessary, so it's always safe to use CPSR.
1594 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(MovCCOpc), DestReg)
1595 .addReg(ZeroReg).addImm(1)
1596 .addImm(ARMPred).addReg(ARM::CPSR);
1598 UpdateValueMap(I, DestReg);
1602 bool ARMFastISel::SelectFPExt(const Instruction *I) {
1603 // Make sure we have VFP and that we're extending float to double.
1604 if (!Subtarget->hasVFP2()) return false;
1606 Value *V = I->getOperand(0);
1607 if (!I->getType()->isDoubleTy() ||
1608 !V->getType()->isFloatTy()) return false;
1610 unsigned Op = getRegForValue(V);
1611 if (Op == 0) return false;
1613 unsigned Result = createResultReg(&ARM::DPRRegClass);
1614 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1615 TII.get(ARM::VCVTDS), Result)
1617 UpdateValueMap(I, Result);
1621 bool ARMFastISel::SelectFPTrunc(const Instruction *I) {
1622 // Make sure we have VFP and that we're truncating double to float.
1623 if (!Subtarget->hasVFP2()) return false;
1625 Value *V = I->getOperand(0);
1626 if (!(I->getType()->isFloatTy() &&
1627 V->getType()->isDoubleTy())) return false;
1629 unsigned Op = getRegForValue(V);
1630 if (Op == 0) return false;
1632 unsigned Result = createResultReg(&ARM::SPRRegClass);
1633 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1634 TII.get(ARM::VCVTSD), Result)
1636 UpdateValueMap(I, Result);
1640 bool ARMFastISel::SelectIToFP(const Instruction *I, bool isSigned) {
1641 // Make sure we have VFP.
1642 if (!Subtarget->hasVFP2()) return false;
1645 Type *Ty = I->getType();
1646 if (!isTypeLegal(Ty, DstVT))
1649 Value *Src = I->getOperand(0);
1650 EVT SrcEVT = TLI.getValueType(Src->getType(), true);
1651 if (!SrcEVT.isSimple())
1653 MVT SrcVT = SrcEVT.getSimpleVT();
1654 if (SrcVT != MVT::i32 && SrcVT != MVT::i16 && SrcVT != MVT::i8)
1657 unsigned SrcReg = getRegForValue(Src);
1658 if (SrcReg == 0) return false;
1660 // Handle sign-extension.
1661 if (SrcVT == MVT::i16 || SrcVT == MVT::i8) {
1662 SrcReg = ARMEmitIntExt(SrcVT, SrcReg, MVT::i32,
1663 /*isZExt*/!isSigned);
1664 if (SrcReg == 0) return false;
1667 // The conversion routine works on fp-reg to fp-reg and the operand above
1668 // was an integer, move it to the fp registers if possible.
1669 unsigned FP = ARMMoveToFPReg(MVT::f32, SrcReg);
1670 if (FP == 0) return false;
1673 if (Ty->isFloatTy()) Opc = isSigned ? ARM::VSITOS : ARM::VUITOS;
1674 else if (Ty->isDoubleTy()) Opc = isSigned ? ARM::VSITOD : ARM::VUITOD;
1677 unsigned ResultReg = createResultReg(TLI.getRegClassFor(DstVT));
1678 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc),
1681 UpdateValueMap(I, ResultReg);
1685 bool ARMFastISel::SelectFPToI(const Instruction *I, bool isSigned) {
1686 // Make sure we have VFP.
1687 if (!Subtarget->hasVFP2()) return false;
1690 Type *RetTy = I->getType();
1691 if (!isTypeLegal(RetTy, DstVT))
1694 unsigned Op = getRegForValue(I->getOperand(0));
1695 if (Op == 0) return false;
1698 Type *OpTy = I->getOperand(0)->getType();
1699 if (OpTy->isFloatTy()) Opc = isSigned ? ARM::VTOSIZS : ARM::VTOUIZS;
1700 else if (OpTy->isDoubleTy()) Opc = isSigned ? ARM::VTOSIZD : ARM::VTOUIZD;
1703 // f64->s32/u32 or f32->s32/u32 both need an intermediate f32 reg.
1704 unsigned ResultReg = createResultReg(TLI.getRegClassFor(MVT::f32));
1705 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc),
1709 // This result needs to be in an integer register, but the conversion only
1710 // takes place in fp-regs.
1711 unsigned IntReg = ARMMoveToIntReg(DstVT, ResultReg);
1712 if (IntReg == 0) return false;
1714 UpdateValueMap(I, IntReg);
1718 bool ARMFastISel::SelectSelect(const Instruction *I) {
1720 if (!isTypeLegal(I->getType(), VT))
1723 // Things need to be register sized for register moves.
1724 if (VT != MVT::i32) return false;
1726 unsigned CondReg = getRegForValue(I->getOperand(0));
1727 if (CondReg == 0) return false;
1728 unsigned Op1Reg = getRegForValue(I->getOperand(1));
1729 if (Op1Reg == 0) return false;
1731 // Check to see if we can use an immediate in the conditional move.
1733 bool UseImm = false;
1734 bool isNegativeImm = false;
1735 if (const ConstantInt *ConstInt = dyn_cast<ConstantInt>(I->getOperand(2))) {
1736 assert (VT == MVT::i32 && "Expecting an i32.");
1737 Imm = (int)ConstInt->getValue().getZExtValue();
1739 isNegativeImm = true;
1742 UseImm = isThumb2 ? (ARM_AM::getT2SOImmVal(Imm) != -1) :
1743 (ARM_AM::getSOImmVal(Imm) != -1);
1746 unsigned Op2Reg = 0;
1748 Op2Reg = getRegForValue(I->getOperand(2));
1749 if (Op2Reg == 0) return false;
1752 unsigned CmpOpc = isThumb2 ? ARM::t2CMPri : ARM::CMPri;
1753 CondReg = constrainOperandRegClass(TII.get(CmpOpc), CondReg, 0);
1754 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(CmpOpc))
1755 .addReg(CondReg).addImm(0));
1758 const TargetRegisterClass *RC;
1760 RC = isThumb2 ? &ARM::tGPRRegClass : &ARM::GPRRegClass;
1761 MovCCOpc = isThumb2 ? ARM::t2MOVCCr : ARM::MOVCCr;
1763 RC = isThumb2 ? &ARM::rGPRRegClass : &ARM::GPRRegClass;
1765 MovCCOpc = isThumb2 ? ARM::t2MOVCCi : ARM::MOVCCi;
1767 MovCCOpc = isThumb2 ? ARM::t2MVNCCi : ARM::MVNCCi;
1769 unsigned ResultReg = createResultReg(RC);
1771 Op2Reg = constrainOperandRegClass(TII.get(MovCCOpc), Op2Reg, 1);
1772 Op1Reg = constrainOperandRegClass(TII.get(MovCCOpc), Op1Reg, 2);
1773 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(MovCCOpc), ResultReg)
1774 .addReg(Op2Reg).addReg(Op1Reg).addImm(ARMCC::NE).addReg(ARM::CPSR);
1776 Op1Reg = constrainOperandRegClass(TII.get(MovCCOpc), Op1Reg, 1);
1777 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(MovCCOpc), ResultReg)
1778 .addReg(Op1Reg).addImm(Imm).addImm(ARMCC::EQ).addReg(ARM::CPSR);
1780 UpdateValueMap(I, ResultReg);
1784 bool ARMFastISel::SelectDiv(const Instruction *I, bool isSigned) {
1786 Type *Ty = I->getType();
1787 if (!isTypeLegal(Ty, VT))
1790 // If we have integer div support we should have selected this automagically.
1791 // In case we have a real miss go ahead and return false and we'll pick
1793 if (Subtarget->hasDivide()) return false;
1795 // Otherwise emit a libcall.
1796 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
1798 LC = isSigned ? RTLIB::SDIV_I8 : RTLIB::UDIV_I8;
1799 else if (VT == MVT::i16)
1800 LC = isSigned ? RTLIB::SDIV_I16 : RTLIB::UDIV_I16;
1801 else if (VT == MVT::i32)
1802 LC = isSigned ? RTLIB::SDIV_I32 : RTLIB::UDIV_I32;
1803 else if (VT == MVT::i64)
1804 LC = isSigned ? RTLIB::SDIV_I64 : RTLIB::UDIV_I64;
1805 else if (VT == MVT::i128)
1806 LC = isSigned ? RTLIB::SDIV_I128 : RTLIB::UDIV_I128;
1807 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported SDIV!");
1809 return ARMEmitLibcall(I, LC);
1812 bool ARMFastISel::SelectRem(const Instruction *I, bool isSigned) {
1814 Type *Ty = I->getType();
1815 if (!isTypeLegal(Ty, VT))
1818 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
1820 LC = isSigned ? RTLIB::SREM_I8 : RTLIB::UREM_I8;
1821 else if (VT == MVT::i16)
1822 LC = isSigned ? RTLIB::SREM_I16 : RTLIB::UREM_I16;
1823 else if (VT == MVT::i32)
1824 LC = isSigned ? RTLIB::SREM_I32 : RTLIB::UREM_I32;
1825 else if (VT == MVT::i64)
1826 LC = isSigned ? RTLIB::SREM_I64 : RTLIB::UREM_I64;
1827 else if (VT == MVT::i128)
1828 LC = isSigned ? RTLIB::SREM_I128 : RTLIB::UREM_I128;
1829 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported SREM!");
1831 return ARMEmitLibcall(I, LC);
1834 bool ARMFastISel::SelectBinaryIntOp(const Instruction *I, unsigned ISDOpcode) {
1835 EVT DestVT = TLI.getValueType(I->getType(), true);
1837 // We can get here in the case when we have a binary operation on a non-legal
1838 // type and the target independent selector doesn't know how to handle it.
1839 if (DestVT != MVT::i16 && DestVT != MVT::i8 && DestVT != MVT::i1)
1843 switch (ISDOpcode) {
1844 default: return false;
1846 Opc = isThumb2 ? ARM::t2ADDrr : ARM::ADDrr;
1849 Opc = isThumb2 ? ARM::t2ORRrr : ARM::ORRrr;
1852 Opc = isThumb2 ? ARM::t2SUBrr : ARM::SUBrr;
1856 unsigned SrcReg1 = getRegForValue(I->getOperand(0));
1857 if (SrcReg1 == 0) return false;
1859 // TODO: Often the 2nd operand is an immediate, which can be encoded directly
1860 // in the instruction, rather then materializing the value in a register.
1861 unsigned SrcReg2 = getRegForValue(I->getOperand(1));
1862 if (SrcReg2 == 0) return false;
1864 unsigned ResultReg = createResultReg(&ARM::GPRnopcRegClass);
1865 SrcReg1 = constrainOperandRegClass(TII.get(Opc), SrcReg1, 1);
1866 SrcReg2 = constrainOperandRegClass(TII.get(Opc), SrcReg2, 2);
1867 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1868 TII.get(Opc), ResultReg)
1869 .addReg(SrcReg1).addReg(SrcReg2));
1870 UpdateValueMap(I, ResultReg);
1874 bool ARMFastISel::SelectBinaryFPOp(const Instruction *I, unsigned ISDOpcode) {
1875 EVT FPVT = TLI.getValueType(I->getType(), true);
1876 if (!FPVT.isSimple()) return false;
1877 MVT VT = FPVT.getSimpleVT();
1879 // We can get here in the case when we want to use NEON for our fp
1880 // operations, but can't figure out how to. Just use the vfp instructions
1882 // FIXME: It'd be nice to use NEON instructions.
1883 Type *Ty = I->getType();
1884 bool isFloat = (Ty->isDoubleTy() || Ty->isFloatTy());
1885 if (isFloat && !Subtarget->hasVFP2())
1889 bool is64bit = VT == MVT::f64 || VT == MVT::i64;
1890 switch (ISDOpcode) {
1891 default: return false;
1893 Opc = is64bit ? ARM::VADDD : ARM::VADDS;
1896 Opc = is64bit ? ARM::VSUBD : ARM::VSUBS;
1899 Opc = is64bit ? ARM::VMULD : ARM::VMULS;
1902 unsigned Op1 = getRegForValue(I->getOperand(0));
1903 if (Op1 == 0) return false;
1905 unsigned Op2 = getRegForValue(I->getOperand(1));
1906 if (Op2 == 0) return false;
1908 unsigned ResultReg = createResultReg(TLI.getRegClassFor(VT.SimpleTy));
1909 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1910 TII.get(Opc), ResultReg)
1911 .addReg(Op1).addReg(Op2));
1912 UpdateValueMap(I, ResultReg);
1916 // Call Handling Code
1918 // This is largely taken directly from CCAssignFnForNode
1919 // TODO: We may not support all of this.
1920 CCAssignFn *ARMFastISel::CCAssignFnForCall(CallingConv::ID CC,
1925 llvm_unreachable("Unsupported calling convention");
1926 case CallingConv::Fast:
1927 if (Subtarget->hasVFP2() && !isVarArg) {
1928 if (!Subtarget->isAAPCS_ABI())
1929 return (Return ? RetFastCC_ARM_APCS : FastCC_ARM_APCS);
1930 // For AAPCS ABI targets, just use VFP variant of the calling convention.
1931 return (Return ? RetCC_ARM_AAPCS_VFP : CC_ARM_AAPCS_VFP);
1934 case CallingConv::C:
1935 // Use target triple & subtarget features to do actual dispatch.
1936 if (Subtarget->isAAPCS_ABI()) {
1937 if (Subtarget->hasVFP2() &&
1938 TM.Options.FloatABIType == FloatABI::Hard && !isVarArg)
1939 return (Return ? RetCC_ARM_AAPCS_VFP: CC_ARM_AAPCS_VFP);
1941 return (Return ? RetCC_ARM_AAPCS: CC_ARM_AAPCS);
1943 return (Return ? RetCC_ARM_APCS: CC_ARM_APCS);
1944 case CallingConv::ARM_AAPCS_VFP:
1946 return (Return ? RetCC_ARM_AAPCS_VFP: CC_ARM_AAPCS_VFP);
1947 // Fall through to soft float variant, variadic functions don't
1948 // use hard floating point ABI.
1949 case CallingConv::ARM_AAPCS:
1950 return (Return ? RetCC_ARM_AAPCS: CC_ARM_AAPCS);
1951 case CallingConv::ARM_APCS:
1952 return (Return ? RetCC_ARM_APCS: CC_ARM_APCS);
1953 case CallingConv::GHC:
1955 llvm_unreachable("Can't return in GHC call convention");
1957 return CC_ARM_APCS_GHC;
1961 bool ARMFastISel::ProcessCallArgs(SmallVectorImpl<Value*> &Args,
1962 SmallVectorImpl<unsigned> &ArgRegs,
1963 SmallVectorImpl<MVT> &ArgVTs,
1964 SmallVectorImpl<ISD::ArgFlagsTy> &ArgFlags,
1965 SmallVectorImpl<unsigned> &RegArgs,
1969 SmallVector<CCValAssign, 16> ArgLocs;
1970 CCState CCInfo(CC, isVarArg, *FuncInfo.MF, TM, ArgLocs, *Context);
1971 CCInfo.AnalyzeCallOperands(ArgVTs, ArgFlags,
1972 CCAssignFnForCall(CC, false, isVarArg));
1974 // Check that we can handle all of the arguments. If we can't, then bail out
1975 // now before we add code to the MBB.
1976 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1977 CCValAssign &VA = ArgLocs[i];
1978 MVT ArgVT = ArgVTs[VA.getValNo()];
1980 // We don't handle NEON/vector parameters yet.
1981 if (ArgVT.isVector() || ArgVT.getSizeInBits() > 64)
1984 // Now copy/store arg to correct locations.
1985 if (VA.isRegLoc() && !VA.needsCustom()) {
1987 } else if (VA.needsCustom()) {
1988 // TODO: We need custom lowering for vector (v2f64) args.
1989 if (VA.getLocVT() != MVT::f64 ||
1990 // TODO: Only handle register args for now.
1991 !VA.isRegLoc() || !ArgLocs[++i].isRegLoc())
1994 switch (ArgVT.SimpleTy) {
2003 if (!Subtarget->hasVFP2())
2007 if (!Subtarget->hasVFP2())
2014 // At the point, we are able to handle the call's arguments in fast isel.
2016 // Get a count of how many bytes are to be pushed on the stack.
2017 NumBytes = CCInfo.getNextStackOffset();
2019 // Issue CALLSEQ_START
2020 unsigned AdjStackDown = TII.getCallFrameSetupOpcode();
2021 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
2022 TII.get(AdjStackDown))
2025 // Process the args.
2026 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2027 CCValAssign &VA = ArgLocs[i];
2028 unsigned Arg = ArgRegs[VA.getValNo()];
2029 MVT ArgVT = ArgVTs[VA.getValNo()];
2031 assert((!ArgVT.isVector() && ArgVT.getSizeInBits() <= 64) &&
2032 "We don't handle NEON/vector parameters yet.");
2034 // Handle arg promotion, etc.
2035 switch (VA.getLocInfo()) {
2036 case CCValAssign::Full: break;
2037 case CCValAssign::SExt: {
2038 MVT DestVT = VA.getLocVT();
2039 Arg = ARMEmitIntExt(ArgVT, Arg, DestVT, /*isZExt*/false);
2040 assert (Arg != 0 && "Failed to emit a sext");
2044 case CCValAssign::AExt:
2045 // Intentional fall-through. Handle AExt and ZExt.
2046 case CCValAssign::ZExt: {
2047 MVT DestVT = VA.getLocVT();
2048 Arg = ARMEmitIntExt(ArgVT, Arg, DestVT, /*isZExt*/true);
2049 assert (Arg != 0 && "Failed to emit a zext");
2053 case CCValAssign::BCvt: {
2054 unsigned BC = FastEmit_r(ArgVT, VA.getLocVT(), ISD::BITCAST, Arg,
2055 /*TODO: Kill=*/false);
2056 assert(BC != 0 && "Failed to emit a bitcast!");
2058 ArgVT = VA.getLocVT();
2061 default: llvm_unreachable("Unknown arg promotion!");
2064 // Now copy/store arg to correct locations.
2065 if (VA.isRegLoc() && !VA.needsCustom()) {
2066 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY),
2069 RegArgs.push_back(VA.getLocReg());
2070 } else if (VA.needsCustom()) {
2071 // TODO: We need custom lowering for vector (v2f64) args.
2072 assert(VA.getLocVT() == MVT::f64 &&
2073 "Custom lowering for v2f64 args not available");
2075 CCValAssign &NextVA = ArgLocs[++i];
2077 assert(VA.isRegLoc() && NextVA.isRegLoc() &&
2078 "We only handle register args!");
2080 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
2081 TII.get(ARM::VMOVRRD), VA.getLocReg())
2082 .addReg(NextVA.getLocReg(), RegState::Define)
2084 RegArgs.push_back(VA.getLocReg());
2085 RegArgs.push_back(NextVA.getLocReg());
2087 assert(VA.isMemLoc());
2088 // Need to store on the stack.
2090 Addr.BaseType = Address::RegBase;
2091 Addr.Base.Reg = ARM::SP;
2092 Addr.Offset = VA.getLocMemOffset();
2094 bool EmitRet = ARMEmitStore(ArgVT, Arg, Addr); (void)EmitRet;
2095 assert(EmitRet && "Could not emit a store for argument!");
2102 bool ARMFastISel::FinishCall(MVT RetVT, SmallVectorImpl<unsigned> &UsedRegs,
2103 const Instruction *I, CallingConv::ID CC,
2104 unsigned &NumBytes, bool isVarArg) {
2105 // Issue CALLSEQ_END
2106 unsigned AdjStackUp = TII.getCallFrameDestroyOpcode();
2107 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
2108 TII.get(AdjStackUp))
2109 .addImm(NumBytes).addImm(0));
2111 // Now the return value.
2112 if (RetVT != MVT::isVoid) {
2113 SmallVector<CCValAssign, 16> RVLocs;
2114 CCState CCInfo(CC, isVarArg, *FuncInfo.MF, TM, RVLocs, *Context);
2115 CCInfo.AnalyzeCallResult(RetVT, CCAssignFnForCall(CC, true, isVarArg));
2117 // Copy all of the result registers out of their specified physreg.
2118 if (RVLocs.size() == 2 && RetVT == MVT::f64) {
2119 // For this move we copy into two registers and then move into the
2120 // double fp reg we want.
2121 MVT DestVT = RVLocs[0].getValVT();
2122 const TargetRegisterClass* DstRC = TLI.getRegClassFor(DestVT);
2123 unsigned ResultReg = createResultReg(DstRC);
2124 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
2125 TII.get(ARM::VMOVDRR), ResultReg)
2126 .addReg(RVLocs[0].getLocReg())
2127 .addReg(RVLocs[1].getLocReg()));
2129 UsedRegs.push_back(RVLocs[0].getLocReg());
2130 UsedRegs.push_back(RVLocs[1].getLocReg());
2132 // Finally update the result.
2133 UpdateValueMap(I, ResultReg);
2135 assert(RVLocs.size() == 1 &&"Can't handle non-double multi-reg retvals!");
2136 MVT CopyVT = RVLocs[0].getValVT();
2138 // Special handling for extended integers.
2139 if (RetVT == MVT::i1 || RetVT == MVT::i8 || RetVT == MVT::i16)
2142 const TargetRegisterClass* DstRC = TLI.getRegClassFor(CopyVT);
2144 unsigned ResultReg = createResultReg(DstRC);
2145 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY),
2146 ResultReg).addReg(RVLocs[0].getLocReg());
2147 UsedRegs.push_back(RVLocs[0].getLocReg());
2149 // Finally update the result.
2150 UpdateValueMap(I, ResultReg);
2157 bool ARMFastISel::SelectRet(const Instruction *I) {
2158 const ReturnInst *Ret = cast<ReturnInst>(I);
2159 const Function &F = *I->getParent()->getParent();
2161 if (!FuncInfo.CanLowerReturn)
2164 // Build a list of return value registers.
2165 SmallVector<unsigned, 4> RetRegs;
2167 CallingConv::ID CC = F.getCallingConv();
2168 if (Ret->getNumOperands() > 0) {
2169 SmallVector<ISD::OutputArg, 4> Outs;
2170 GetReturnInfo(F.getReturnType(), F.getAttributes(), Outs, TLI);
2172 // Analyze operands of the call, assigning locations to each operand.
2173 SmallVector<CCValAssign, 16> ValLocs;
2174 CCState CCInfo(CC, F.isVarArg(), *FuncInfo.MF, TM, ValLocs,I->getContext());
2175 CCInfo.AnalyzeReturn(Outs, CCAssignFnForCall(CC, true /* is Ret */,
2178 const Value *RV = Ret->getOperand(0);
2179 unsigned Reg = getRegForValue(RV);
2183 // Only handle a single return value for now.
2184 if (ValLocs.size() != 1)
2187 CCValAssign &VA = ValLocs[0];
2189 // Don't bother handling odd stuff for now.
2190 if (VA.getLocInfo() != CCValAssign::Full)
2192 // Only handle register returns for now.
2196 unsigned SrcReg = Reg + VA.getValNo();
2197 EVT RVEVT = TLI.getValueType(RV->getType());
2198 if (!RVEVT.isSimple()) return false;
2199 MVT RVVT = RVEVT.getSimpleVT();
2200 MVT DestVT = VA.getValVT();
2201 // Special handling for extended integers.
2202 if (RVVT != DestVT) {
2203 if (RVVT != MVT::i1 && RVVT != MVT::i8 && RVVT != MVT::i16)
2206 assert(DestVT == MVT::i32 && "ARM should always ext to i32");
2208 // Perform extension if flagged as either zext or sext. Otherwise, do
2210 if (Outs[0].Flags.isZExt() || Outs[0].Flags.isSExt()) {
2211 SrcReg = ARMEmitIntExt(RVVT, SrcReg, DestVT, Outs[0].Flags.isZExt());
2212 if (SrcReg == 0) return false;
2217 unsigned DstReg = VA.getLocReg();
2218 const TargetRegisterClass* SrcRC = MRI.getRegClass(SrcReg);
2219 // Avoid a cross-class copy. This is very unlikely.
2220 if (!SrcRC->contains(DstReg))
2222 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY),
2223 DstReg).addReg(SrcReg);
2225 // Add register to return instruction.
2226 RetRegs.push_back(VA.getLocReg());
2229 unsigned RetOpc = isThumb2 ? ARM::tBX_RET : ARM::BX_RET;
2230 MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
2232 AddOptionalDefs(MIB);
2233 for (unsigned i = 0, e = RetRegs.size(); i != e; ++i)
2234 MIB.addReg(RetRegs[i], RegState::Implicit);
2238 unsigned ARMFastISel::ARMSelectCallOp(bool UseReg) {
2240 return isThumb2 ? ARM::tBLXr : ARM::BLX;
2242 return isThumb2 ? ARM::tBL : ARM::BL;
2245 unsigned ARMFastISel::getLibcallReg(const Twine &Name) {
2246 // Manually compute the global's type to avoid building it when unnecessary.
2247 Type *GVTy = Type::getInt32PtrTy(*Context, /*AS=*/0);
2248 EVT LCREVT = TLI.getValueType(GVTy);
2249 if (!LCREVT.isSimple()) return 0;
2251 GlobalValue *GV = new GlobalVariable(Type::getInt32Ty(*Context), false,
2252 GlobalValue::ExternalLinkage, 0, Name);
2253 assert(GV->getType() == GVTy && "We miscomputed the type for the global!");
2254 return ARMMaterializeGV(GV, LCREVT.getSimpleVT());
2257 // A quick function that will emit a call for a named libcall in F with the
2258 // vector of passed arguments for the Instruction in I. We can assume that we
2259 // can emit a call for any libcall we can produce. This is an abridged version
2260 // of the full call infrastructure since we won't need to worry about things
2261 // like computed function pointers or strange arguments at call sites.
2262 // TODO: Try to unify this and the normal call bits for ARM, then try to unify
2264 bool ARMFastISel::ARMEmitLibcall(const Instruction *I, RTLIB::Libcall Call) {
2265 CallingConv::ID CC = TLI.getLibcallCallingConv(Call);
2267 // Handle *simple* calls for now.
2268 Type *RetTy = I->getType();
2270 if (RetTy->isVoidTy())
2271 RetVT = MVT::isVoid;
2272 else if (!isTypeLegal(RetTy, RetVT))
2275 // Can't handle non-double multi-reg retvals.
2276 if (RetVT != MVT::isVoid && RetVT != MVT::i32) {
2277 SmallVector<CCValAssign, 16> RVLocs;
2278 CCState CCInfo(CC, false, *FuncInfo.MF, TM, RVLocs, *Context);
2279 CCInfo.AnalyzeCallResult(RetVT, CCAssignFnForCall(CC, true, false));
2280 if (RVLocs.size() >= 2 && RetVT != MVT::f64)
2284 // Set up the argument vectors.
2285 SmallVector<Value*, 8> Args;
2286 SmallVector<unsigned, 8> ArgRegs;
2287 SmallVector<MVT, 8> ArgVTs;
2288 SmallVector<ISD::ArgFlagsTy, 8> ArgFlags;
2289 Args.reserve(I->getNumOperands());
2290 ArgRegs.reserve(I->getNumOperands());
2291 ArgVTs.reserve(I->getNumOperands());
2292 ArgFlags.reserve(I->getNumOperands());
2293 for (unsigned i = 0; i < I->getNumOperands(); ++i) {
2294 Value *Op = I->getOperand(i);
2295 unsigned Arg = getRegForValue(Op);
2296 if (Arg == 0) return false;
2298 Type *ArgTy = Op->getType();
2300 if (!isTypeLegal(ArgTy, ArgVT)) return false;
2302 ISD::ArgFlagsTy Flags;
2303 unsigned OriginalAlignment = TD.getABITypeAlignment(ArgTy);
2304 Flags.setOrigAlign(OriginalAlignment);
2307 ArgRegs.push_back(Arg);
2308 ArgVTs.push_back(ArgVT);
2309 ArgFlags.push_back(Flags);
2312 // Handle the arguments now that we've gotten them.
2313 SmallVector<unsigned, 4> RegArgs;
2315 if (!ProcessCallArgs(Args, ArgRegs, ArgVTs, ArgFlags,
2316 RegArgs, CC, NumBytes, false))
2319 unsigned CalleeReg = 0;
2320 if (EnableARMLongCalls) {
2321 CalleeReg = getLibcallReg(TLI.getLibcallName(Call));
2322 if (CalleeReg == 0) return false;
2326 unsigned CallOpc = ARMSelectCallOp(EnableARMLongCalls);
2327 MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt,
2328 DL, TII.get(CallOpc));
2329 // BL / BLX don't take a predicate, but tBL / tBLX do.
2331 AddDefaultPred(MIB);
2332 if (EnableARMLongCalls)
2333 MIB.addReg(CalleeReg);
2335 MIB.addExternalSymbol(TLI.getLibcallName(Call));
2337 // Add implicit physical register uses to the call.
2338 for (unsigned i = 0, e = RegArgs.size(); i != e; ++i)
2339 MIB.addReg(RegArgs[i], RegState::Implicit);
2341 // Add a register mask with the call-preserved registers.
2342 // Proper defs for return values will be added by setPhysRegsDeadExcept().
2343 MIB.addRegMask(TRI.getCallPreservedMask(CC));
2345 // Finish off the call including any return values.
2346 SmallVector<unsigned, 4> UsedRegs;
2347 if (!FinishCall(RetVT, UsedRegs, I, CC, NumBytes, false)) return false;
2349 // Set all unused physreg defs as dead.
2350 static_cast<MachineInstr *>(MIB)->setPhysRegsDeadExcept(UsedRegs, TRI);
2355 bool ARMFastISel::SelectCall(const Instruction *I,
2356 const char *IntrMemName = 0) {
2357 const CallInst *CI = cast<CallInst>(I);
2358 const Value *Callee = CI->getCalledValue();
2360 // Can't handle inline asm.
2361 if (isa<InlineAsm>(Callee)) return false;
2363 // Allow SelectionDAG isel to handle tail calls.
2364 if (CI->isTailCall()) return false;
2366 // Check the calling convention.
2367 ImmutableCallSite CS(CI);
2368 CallingConv::ID CC = CS.getCallingConv();
2370 // TODO: Avoid some calling conventions?
2372 PointerType *PT = cast<PointerType>(CS.getCalledValue()->getType());
2373 FunctionType *FTy = cast<FunctionType>(PT->getElementType());
2374 bool isVarArg = FTy->isVarArg();
2376 // Handle *simple* calls for now.
2377 Type *RetTy = I->getType();
2379 if (RetTy->isVoidTy())
2380 RetVT = MVT::isVoid;
2381 else if (!isTypeLegal(RetTy, RetVT) && RetVT != MVT::i16 &&
2382 RetVT != MVT::i8 && RetVT != MVT::i1)
2385 // Can't handle non-double multi-reg retvals.
2386 if (RetVT != MVT::isVoid && RetVT != MVT::i1 && RetVT != MVT::i8 &&
2387 RetVT != MVT::i16 && RetVT != MVT::i32) {
2388 SmallVector<CCValAssign, 16> RVLocs;
2389 CCState CCInfo(CC, isVarArg, *FuncInfo.MF, TM, RVLocs, *Context);
2390 CCInfo.AnalyzeCallResult(RetVT, CCAssignFnForCall(CC, true, isVarArg));
2391 if (RVLocs.size() >= 2 && RetVT != MVT::f64)
2395 // Set up the argument vectors.
2396 SmallVector<Value*, 8> Args;
2397 SmallVector<unsigned, 8> ArgRegs;
2398 SmallVector<MVT, 8> ArgVTs;
2399 SmallVector<ISD::ArgFlagsTy, 8> ArgFlags;
2400 unsigned arg_size = CS.arg_size();
2401 Args.reserve(arg_size);
2402 ArgRegs.reserve(arg_size);
2403 ArgVTs.reserve(arg_size);
2404 ArgFlags.reserve(arg_size);
2405 for (ImmutableCallSite::arg_iterator i = CS.arg_begin(), e = CS.arg_end();
2407 // If we're lowering a memory intrinsic instead of a regular call, skip the
2408 // last two arguments, which shouldn't be passed to the underlying function.
2409 if (IntrMemName && e-i <= 2)
2412 ISD::ArgFlagsTy Flags;
2413 unsigned AttrInd = i - CS.arg_begin() + 1;
2414 if (CS.paramHasAttr(AttrInd, Attribute::SExt))
2416 if (CS.paramHasAttr(AttrInd, Attribute::ZExt))
2419 // FIXME: Only handle *easy* calls for now.
2420 if (CS.paramHasAttr(AttrInd, Attribute::InReg) ||
2421 CS.paramHasAttr(AttrInd, Attribute::StructRet) ||
2422 CS.paramHasAttr(AttrInd, Attribute::Nest) ||
2423 CS.paramHasAttr(AttrInd, Attribute::ByVal))
2426 Type *ArgTy = (*i)->getType();
2428 if (!isTypeLegal(ArgTy, ArgVT) && ArgVT != MVT::i16 && ArgVT != MVT::i8 &&
2432 unsigned Arg = getRegForValue(*i);
2436 unsigned OriginalAlignment = TD.getABITypeAlignment(ArgTy);
2437 Flags.setOrigAlign(OriginalAlignment);
2440 ArgRegs.push_back(Arg);
2441 ArgVTs.push_back(ArgVT);
2442 ArgFlags.push_back(Flags);
2445 // Handle the arguments now that we've gotten them.
2446 SmallVector<unsigned, 4> RegArgs;
2448 if (!ProcessCallArgs(Args, ArgRegs, ArgVTs, ArgFlags,
2449 RegArgs, CC, NumBytes, isVarArg))
2452 bool UseReg = false;
2453 const GlobalValue *GV = dyn_cast<GlobalValue>(Callee);
2454 if (!GV || EnableARMLongCalls) UseReg = true;
2456 unsigned CalleeReg = 0;
2459 CalleeReg = getLibcallReg(IntrMemName);
2461 CalleeReg = getRegForValue(Callee);
2463 if (CalleeReg == 0) return false;
2467 unsigned CallOpc = ARMSelectCallOp(UseReg);
2468 MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt,
2469 DL, TII.get(CallOpc));
2471 unsigned char OpFlags = 0;
2473 // Add MO_PLT for global address or external symbol in the PIC relocation
2475 if (Subtarget->isTargetELF() && TM.getRelocationModel() == Reloc::PIC_)
2476 OpFlags = ARMII::MO_PLT;
2478 // ARM calls don't take a predicate, but tBL / tBLX do.
2480 AddDefaultPred(MIB);
2482 MIB.addReg(CalleeReg);
2483 else if (!IntrMemName)
2484 MIB.addGlobalAddress(GV, 0, OpFlags);
2486 MIB.addExternalSymbol(IntrMemName, OpFlags);
2488 // Add implicit physical register uses to the call.
2489 for (unsigned i = 0, e = RegArgs.size(); i != e; ++i)
2490 MIB.addReg(RegArgs[i], RegState::Implicit);
2492 // Add a register mask with the call-preserved registers.
2493 // Proper defs for return values will be added by setPhysRegsDeadExcept().
2494 MIB.addRegMask(TRI.getCallPreservedMask(CC));
2496 // Finish off the call including any return values.
2497 SmallVector<unsigned, 4> UsedRegs;
2498 if (!FinishCall(RetVT, UsedRegs, I, CC, NumBytes, isVarArg))
2501 // Set all unused physreg defs as dead.
2502 static_cast<MachineInstr *>(MIB)->setPhysRegsDeadExcept(UsedRegs, TRI);
2507 bool ARMFastISel::ARMIsMemCpySmall(uint64_t Len) {
2511 bool ARMFastISel::ARMTryEmitSmallMemCpy(Address Dest, Address Src,
2512 uint64_t Len, unsigned Alignment) {
2513 // Make sure we don't bloat code by inlining very large memcpy's.
2514 if (!ARMIsMemCpySmall(Len))
2519 if (!Alignment || Alignment >= 4) {
2525 assert (Len == 1 && "Expected a length of 1!");
2529 // Bound based on alignment.
2530 if (Len >= 2 && Alignment == 2)
2539 RV = ARMEmitLoad(VT, ResultReg, Src);
2540 assert (RV == true && "Should be able to handle this load.");
2541 RV = ARMEmitStore(VT, ResultReg, Dest);
2542 assert (RV == true && "Should be able to handle this store.");
2545 unsigned Size = VT.getSizeInBits()/8;
2547 Dest.Offset += Size;
2554 bool ARMFastISel::SelectIntrinsicCall(const IntrinsicInst &I) {
2555 // FIXME: Handle more intrinsics.
2556 switch (I.getIntrinsicID()) {
2557 default: return false;
2558 case Intrinsic::frameaddress: {
2559 MachineFrameInfo *MFI = FuncInfo.MF->getFrameInfo();
2560 MFI->setFrameAddressIsTaken(true);
2563 const TargetRegisterClass *RC;
2565 LdrOpc = ARM::t2LDRi12;
2566 RC = (const TargetRegisterClass*)&ARM::tGPRRegClass;
2568 LdrOpc = ARM::LDRi12;
2569 RC = (const TargetRegisterClass*)&ARM::GPRRegClass;
2572 const ARMBaseRegisterInfo *RegInfo =
2573 static_cast<const ARMBaseRegisterInfo*>(TM.getRegisterInfo());
2574 unsigned FramePtr = RegInfo->getFrameRegister(*(FuncInfo.MF));
2575 unsigned SrcReg = FramePtr;
2577 // Recursively load frame address
2583 unsigned Depth = cast<ConstantInt>(I.getOperand(0))->getZExtValue();
2585 DestReg = createResultReg(RC);
2586 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
2587 TII.get(LdrOpc), DestReg)
2588 .addReg(SrcReg).addImm(0));
2591 UpdateValueMap(&I, SrcReg);
2594 case Intrinsic::memcpy:
2595 case Intrinsic::memmove: {
2596 const MemTransferInst &MTI = cast<MemTransferInst>(I);
2597 // Don't handle volatile.
2598 if (MTI.isVolatile())
2601 // Disable inlining for memmove before calls to ComputeAddress. Otherwise,
2602 // we would emit dead code because we don't currently handle memmoves.
2603 bool isMemCpy = (I.getIntrinsicID() == Intrinsic::memcpy);
2604 if (isa<ConstantInt>(MTI.getLength()) && isMemCpy) {
2605 // Small memcpy's are common enough that we want to do them without a call
2607 uint64_t Len = cast<ConstantInt>(MTI.getLength())->getZExtValue();
2608 if (ARMIsMemCpySmall(Len)) {
2610 if (!ARMComputeAddress(MTI.getRawDest(), Dest) ||
2611 !ARMComputeAddress(MTI.getRawSource(), Src))
2613 unsigned Alignment = MTI.getAlignment();
2614 if (ARMTryEmitSmallMemCpy(Dest, Src, Len, Alignment))
2619 if (!MTI.getLength()->getType()->isIntegerTy(32))
2622 if (MTI.getSourceAddressSpace() > 255 || MTI.getDestAddressSpace() > 255)
2625 const char *IntrMemName = isa<MemCpyInst>(I) ? "memcpy" : "memmove";
2626 return SelectCall(&I, IntrMemName);
2628 case Intrinsic::memset: {
2629 const MemSetInst &MSI = cast<MemSetInst>(I);
2630 // Don't handle volatile.
2631 if (MSI.isVolatile())
2634 if (!MSI.getLength()->getType()->isIntegerTy(32))
2637 if (MSI.getDestAddressSpace() > 255)
2640 return SelectCall(&I, "memset");
2642 case Intrinsic::trap: {
2643 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(
2644 Subtarget->useNaClTrap() ? ARM::TRAPNaCl : ARM::TRAP));
2650 bool ARMFastISel::SelectTrunc(const Instruction *I) {
2651 // The high bits for a type smaller than the register size are assumed to be
2653 Value *Op = I->getOperand(0);
2656 SrcVT = TLI.getValueType(Op->getType(), true);
2657 DestVT = TLI.getValueType(I->getType(), true);
2659 if (SrcVT != MVT::i32 && SrcVT != MVT::i16 && SrcVT != MVT::i8)
2661 if (DestVT != MVT::i16 && DestVT != MVT::i8 && DestVT != MVT::i1)
2664 unsigned SrcReg = getRegForValue(Op);
2665 if (!SrcReg) return false;
2667 // Because the high bits are undefined, a truncate doesn't generate
2669 UpdateValueMap(I, SrcReg);
2673 unsigned ARMFastISel::ARMEmitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT,
2675 if (DestVT != MVT::i32 && DestVT != MVT::i16 && DestVT != MVT::i8)
2677 if (SrcVT != MVT::i16 && SrcVT != MVT::i8 && SrcVT != MVT::i1)
2680 // Table of which combinations can be emitted as a single instruction,
2681 // and which will require two.
2682 static const uint8_t isSingleInstrTbl[3][2][2][2] = {
2684 // !hasV6Ops hasV6Ops !hasV6Ops hasV6Ops
2685 // ext: s z s z s z s z
2686 /* 1 */ { { { 0, 1 }, { 0, 1 } }, { { 0, 0 }, { 0, 1 } } },
2687 /* 8 */ { { { 0, 1 }, { 1, 1 } }, { { 0, 0 }, { 1, 1 } } },
2688 /* 16 */ { { { 0, 0 }, { 1, 1 } }, { { 0, 0 }, { 1, 1 } } }
2691 // Target registers for:
2692 // - For ARM can never be PC.
2693 // - For 16-bit Thumb are restricted to lower 8 registers.
2694 // - For 32-bit Thumb are restricted to non-SP and non-PC.
2695 static const TargetRegisterClass *RCTbl[2][2] = {
2696 // Instructions: Two Single
2697 /* ARM */ { &ARM::GPRnopcRegClass, &ARM::GPRnopcRegClass },
2698 /* Thumb */ { &ARM::tGPRRegClass, &ARM::rGPRRegClass }
2701 // Table governing the instruction(s) to be emitted.
2702 static const struct InstructionTable {
2704 uint32_t hasS : 1; // Some instructions have an S bit, always set it to 0.
2705 uint32_t Shift : 7; // For shift operand addressing mode, used by MOVsi.
2706 uint32_t Imm : 8; // All instructions have either a shift or a mask.
2707 } IT[2][2][3][2] = {
2708 { // Two instructions (first is left shift, second is in this table).
2709 { // ARM Opc S Shift Imm
2710 /* 1 bit sext */ { { ARM::MOVsi , 1, ARM_AM::asr , 31 },
2711 /* 1 bit zext */ { ARM::MOVsi , 1, ARM_AM::lsr , 31 } },
2712 /* 8 bit sext */ { { ARM::MOVsi , 1, ARM_AM::asr , 24 },
2713 /* 8 bit zext */ { ARM::MOVsi , 1, ARM_AM::lsr , 24 } },
2714 /* 16 bit sext */ { { ARM::MOVsi , 1, ARM_AM::asr , 16 },
2715 /* 16 bit zext */ { ARM::MOVsi , 1, ARM_AM::lsr , 16 } }
2717 { // Thumb Opc S Shift Imm
2718 /* 1 bit sext */ { { ARM::tASRri , 0, ARM_AM::no_shift, 31 },
2719 /* 1 bit zext */ { ARM::tLSRri , 0, ARM_AM::no_shift, 31 } },
2720 /* 8 bit sext */ { { ARM::tASRri , 0, ARM_AM::no_shift, 24 },
2721 /* 8 bit zext */ { ARM::tLSRri , 0, ARM_AM::no_shift, 24 } },
2722 /* 16 bit sext */ { { ARM::tASRri , 0, ARM_AM::no_shift, 16 },
2723 /* 16 bit zext */ { ARM::tLSRri , 0, ARM_AM::no_shift, 16 } }
2726 { // Single instruction.
2727 { // ARM Opc S Shift Imm
2728 /* 1 bit sext */ { { ARM::KILL , 0, ARM_AM::no_shift, 0 },
2729 /* 1 bit zext */ { ARM::ANDri , 1, ARM_AM::no_shift, 1 } },
2730 /* 8 bit sext */ { { ARM::SXTB , 0, ARM_AM::no_shift, 0 },
2731 /* 8 bit zext */ { ARM::ANDri , 1, ARM_AM::no_shift, 255 } },
2732 /* 16 bit sext */ { { ARM::SXTH , 0, ARM_AM::no_shift, 0 },
2733 /* 16 bit zext */ { ARM::UXTH , 0, ARM_AM::no_shift, 0 } }
2735 { // Thumb Opc S Shift Imm
2736 /* 1 bit sext */ { { ARM::KILL , 0, ARM_AM::no_shift, 0 },
2737 /* 1 bit zext */ { ARM::t2ANDri, 1, ARM_AM::no_shift, 1 } },
2738 /* 8 bit sext */ { { ARM::t2SXTB , 0, ARM_AM::no_shift, 0 },
2739 /* 8 bit zext */ { ARM::t2ANDri, 1, ARM_AM::no_shift, 255 } },
2740 /* 16 bit sext */ { { ARM::t2SXTH , 0, ARM_AM::no_shift, 0 },
2741 /* 16 bit zext */ { ARM::t2UXTH , 0, ARM_AM::no_shift, 0 } }
2746 unsigned SrcBits = SrcVT.getSizeInBits();
2747 unsigned DestBits = DestVT.getSizeInBits();
2749 assert((SrcBits < DestBits) && "can only extend to larger types");
2750 assert((DestBits == 32 || DestBits == 16 || DestBits == 8) &&
2751 "other sizes unimplemented");
2752 assert((SrcBits == 16 || SrcBits == 8 || SrcBits == 1) &&
2753 "other sizes unimplemented");
2755 bool hasV6Ops = Subtarget->hasV6Ops();
2756 unsigned Bitness = SrcBits / 8; // {1,8,16}=>{0,1,2}
2757 assert((Bitness < 3) && "sanity-check table bounds");
2759 bool isSingleInstr = isSingleInstrTbl[Bitness][isThumb2][hasV6Ops][isZExt];
2760 const TargetRegisterClass *RC = RCTbl[isThumb2][isSingleInstr];
2761 const InstructionTable *ITP = &IT[isSingleInstr][isThumb2][Bitness][isZExt];
2762 unsigned Opc = ITP->Opc;
2763 assert(ARM::KILL != Opc && "Invalid table entry");
2764 unsigned hasS = ITP->hasS;
2765 ARM_AM::ShiftOpc Shift = (ARM_AM::ShiftOpc) ITP->Shift;
2766 assert(((Shift == ARM_AM::no_shift) == (Opc != ARM::MOVsi)) &&
2767 "only MOVsi has shift operand addressing mode");
2768 unsigned Imm = ITP->Imm;
2770 // 16-bit Thumb instructions always set CPSR (unless they're in an IT block).
2771 bool setsCPSR = &ARM::tGPRRegClass == RC;
2772 unsigned LSLOpc = isThumb2 ? ARM::tLSLri : ARM::MOVsi;
2774 // MOVsi encodes shift and immediate in shift operand addressing mode.
2775 // The following condition has the same value when emitting two
2776 // instruction sequences: both are shifts.
2777 bool ImmIsSO = (Shift != ARM_AM::no_shift);
2779 // Either one or two instructions are emitted.
2780 // They're always of the form:
2782 // CPSR is set only by 16-bit Thumb instructions.
2783 // Predicate, if any, is AL.
2784 // S bit, if available, is always 0.
2785 // When two are emitted the first's result will feed as the second's input,
2786 // that value is then dead.
2787 unsigned NumInstrsEmitted = isSingleInstr ? 1 : 2;
2788 for (unsigned Instr = 0; Instr != NumInstrsEmitted; ++Instr) {
2789 ResultReg = createResultReg(RC);
2790 bool isLsl = (0 == Instr) && !isSingleInstr;
2791 unsigned Opcode = isLsl ? LSLOpc : Opc;
2792 ARM_AM::ShiftOpc ShiftAM = isLsl ? ARM_AM::lsl : Shift;
2793 unsigned ImmEnc = ImmIsSO ? ARM_AM::getSORegOpc(ShiftAM, Imm) : Imm;
2794 bool isKill = 1 == Instr;
2795 MachineInstrBuilder MIB = BuildMI(
2796 *FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opcode), ResultReg);
2798 MIB.addReg(ARM::CPSR, RegState::Define);
2799 SrcReg = constrainOperandRegClass(TII.get(Opcode), SrcReg, 1 + setsCPSR);
2800 AddDefaultPred(MIB.addReg(SrcReg, isKill * RegState::Kill).addImm(ImmEnc));
2803 // Second instruction consumes the first's result.
2810 bool ARMFastISel::SelectIntExt(const Instruction *I) {
2811 // On ARM, in general, integer casts don't involve legal types; this code
2812 // handles promotable integers.
2813 Type *DestTy = I->getType();
2814 Value *Src = I->getOperand(0);
2815 Type *SrcTy = Src->getType();
2817 bool isZExt = isa<ZExtInst>(I);
2818 unsigned SrcReg = getRegForValue(Src);
2819 if (!SrcReg) return false;
2821 EVT SrcEVT, DestEVT;
2822 SrcEVT = TLI.getValueType(SrcTy, true);
2823 DestEVT = TLI.getValueType(DestTy, true);
2824 if (!SrcEVT.isSimple()) return false;
2825 if (!DestEVT.isSimple()) return false;
2827 MVT SrcVT = SrcEVT.getSimpleVT();
2828 MVT DestVT = DestEVT.getSimpleVT();
2829 unsigned ResultReg = ARMEmitIntExt(SrcVT, SrcReg, DestVT, isZExt);
2830 if (ResultReg == 0) return false;
2831 UpdateValueMap(I, ResultReg);
2835 bool ARMFastISel::SelectShift(const Instruction *I,
2836 ARM_AM::ShiftOpc ShiftTy) {
2837 // We handle thumb2 mode by target independent selector
2838 // or SelectionDAG ISel.
2842 // Only handle i32 now.
2843 EVT DestVT = TLI.getValueType(I->getType(), true);
2844 if (DestVT != MVT::i32)
2847 unsigned Opc = ARM::MOVsr;
2849 Value *Src2Value = I->getOperand(1);
2850 if (const ConstantInt *CI = dyn_cast<ConstantInt>(Src2Value)) {
2851 ShiftImm = CI->getZExtValue();
2853 // Fall back to selection DAG isel if the shift amount
2854 // is zero or greater than the width of the value type.
2855 if (ShiftImm == 0 || ShiftImm >=32)
2861 Value *Src1Value = I->getOperand(0);
2862 unsigned Reg1 = getRegForValue(Src1Value);
2863 if (Reg1 == 0) return false;
2866 if (Opc == ARM::MOVsr) {
2867 Reg2 = getRegForValue(Src2Value);
2868 if (Reg2 == 0) return false;
2871 unsigned ResultReg = createResultReg(&ARM::GPRnopcRegClass);
2872 if(ResultReg == 0) return false;
2874 MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
2875 TII.get(Opc), ResultReg)
2878 if (Opc == ARM::MOVsi)
2879 MIB.addImm(ARM_AM::getSORegOpc(ShiftTy, ShiftImm));
2880 else if (Opc == ARM::MOVsr) {
2882 MIB.addImm(ARM_AM::getSORegOpc(ShiftTy, 0));
2885 AddOptionalDefs(MIB);
2886 UpdateValueMap(I, ResultReg);
2890 // TODO: SoftFP support.
2891 bool ARMFastISel::TargetSelectInstruction(const Instruction *I) {
2893 switch (I->getOpcode()) {
2894 case Instruction::Load:
2895 return SelectLoad(I);
2896 case Instruction::Store:
2897 return SelectStore(I);
2898 case Instruction::Br:
2899 return SelectBranch(I);
2900 case Instruction::IndirectBr:
2901 return SelectIndirectBr(I);
2902 case Instruction::ICmp:
2903 case Instruction::FCmp:
2904 return SelectCmp(I);
2905 case Instruction::FPExt:
2906 return SelectFPExt(I);
2907 case Instruction::FPTrunc:
2908 return SelectFPTrunc(I);
2909 case Instruction::SIToFP:
2910 return SelectIToFP(I, /*isSigned*/ true);
2911 case Instruction::UIToFP:
2912 return SelectIToFP(I, /*isSigned*/ false);
2913 case Instruction::FPToSI:
2914 return SelectFPToI(I, /*isSigned*/ true);
2915 case Instruction::FPToUI:
2916 return SelectFPToI(I, /*isSigned*/ false);
2917 case Instruction::Add:
2918 return SelectBinaryIntOp(I, ISD::ADD);
2919 case Instruction::Or:
2920 return SelectBinaryIntOp(I, ISD::OR);
2921 case Instruction::Sub:
2922 return SelectBinaryIntOp(I, ISD::SUB);
2923 case Instruction::FAdd:
2924 return SelectBinaryFPOp(I, ISD::FADD);
2925 case Instruction::FSub:
2926 return SelectBinaryFPOp(I, ISD::FSUB);
2927 case Instruction::FMul:
2928 return SelectBinaryFPOp(I, ISD::FMUL);
2929 case Instruction::SDiv:
2930 return SelectDiv(I, /*isSigned*/ true);
2931 case Instruction::UDiv:
2932 return SelectDiv(I, /*isSigned*/ false);
2933 case Instruction::SRem:
2934 return SelectRem(I, /*isSigned*/ true);
2935 case Instruction::URem:
2936 return SelectRem(I, /*isSigned*/ false);
2937 case Instruction::Call:
2938 if (const IntrinsicInst *II = dyn_cast<IntrinsicInst>(I))
2939 return SelectIntrinsicCall(*II);
2940 return SelectCall(I);
2941 case Instruction::Select:
2942 return SelectSelect(I);
2943 case Instruction::Ret:
2944 return SelectRet(I);
2945 case Instruction::Trunc:
2946 return SelectTrunc(I);
2947 case Instruction::ZExt:
2948 case Instruction::SExt:
2949 return SelectIntExt(I);
2950 case Instruction::Shl:
2951 return SelectShift(I, ARM_AM::lsl);
2952 case Instruction::LShr:
2953 return SelectShift(I, ARM_AM::lsr);
2954 case Instruction::AShr:
2955 return SelectShift(I, ARM_AM::asr);
2962 // This table describes sign- and zero-extend instructions which can be
2963 // folded into a preceding load. All of these extends have an immediate
2964 // (sometimes a mask and sometimes a shift) that's applied after
2966 const struct FoldableLoadExtendsStruct {
2967 uint16_t Opc[2]; // ARM, Thumb.
2968 uint8_t ExpectedImm;
2970 uint8_t ExpectedVT : 7;
2971 } FoldableLoadExtends[] = {
2972 { { ARM::SXTH, ARM::t2SXTH }, 0, 0, MVT::i16 },
2973 { { ARM::UXTH, ARM::t2UXTH }, 0, 1, MVT::i16 },
2974 { { ARM::ANDri, ARM::t2ANDri }, 255, 1, MVT::i8 },
2975 { { ARM::SXTB, ARM::t2SXTB }, 0, 0, MVT::i8 },
2976 { { ARM::UXTB, ARM::t2UXTB }, 0, 1, MVT::i8 }
2980 /// \brief The specified machine instr operand is a vreg, and that
2981 /// vreg is being provided by the specified load instruction. If possible,
2982 /// try to fold the load as an operand to the instruction, returning true if
2984 bool ARMFastISel::tryToFoldLoadIntoMI(MachineInstr *MI, unsigned OpNo,
2985 const LoadInst *LI) {
2986 // Verify we have a legal type before going any further.
2988 if (!isLoadTypeLegal(LI->getType(), VT))
2991 // Combine load followed by zero- or sign-extend.
2992 // ldrb r1, [r0] ldrb r1, [r0]
2994 // mov r3, r2 mov r3, r1
2995 if (MI->getNumOperands() < 3 || !MI->getOperand(2).isImm())
2997 const uint64_t Imm = MI->getOperand(2).getImm();
3001 for (unsigned i = 0, e = array_lengthof(FoldableLoadExtends);
3003 if (FoldableLoadExtends[i].Opc[isThumb2] == MI->getOpcode() &&
3004 (uint64_t)FoldableLoadExtends[i].ExpectedImm == Imm &&
3005 MVT((MVT::SimpleValueType)FoldableLoadExtends[i].ExpectedVT) == VT) {
3007 isZExt = FoldableLoadExtends[i].isZExt;
3010 if (!Found) return false;
3012 // See if we can handle this address.
3014 if (!ARMComputeAddress(LI->getOperand(0), Addr)) return false;
3016 unsigned ResultReg = MI->getOperand(0).getReg();
3017 if (!ARMEmitLoad(VT, ResultReg, Addr, LI->getAlignment(), isZExt, false))
3019 MI->eraseFromParent();
3023 unsigned ARMFastISel::ARMLowerPICELF(const GlobalValue *GV,
3024 unsigned Align, MVT VT) {
3025 bool UseGOTOFF = GV->hasLocalLinkage() || GV->hasHiddenVisibility();
3026 ARMConstantPoolConstant *CPV =
3027 ARMConstantPoolConstant::Create(GV, UseGOTOFF ? ARMCP::GOTOFF : ARMCP::GOT);
3028 unsigned Idx = MCP.getConstantPoolIndex(CPV, Align);
3031 unsigned DestReg1 = createResultReg(TLI.getRegClassFor(VT));
3034 DestReg1 = constrainOperandRegClass(TII.get(ARM::t2LDRpci), DestReg1, 0);
3035 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
3036 TII.get(ARM::t2LDRpci), DestReg1)
3037 .addConstantPoolIndex(Idx));
3038 Opc = UseGOTOFF ? ARM::t2ADDrr : ARM::t2LDRs;
3040 // The extra immediate is for addrmode2.
3041 DestReg1 = constrainOperandRegClass(TII.get(ARM::LDRcp), DestReg1, 0);
3042 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt,
3043 DL, TII.get(ARM::LDRcp), DestReg1)
3044 .addConstantPoolIndex(Idx).addImm(0));
3045 Opc = UseGOTOFF ? ARM::ADDrr : ARM::LDRrs;
3048 unsigned GlobalBaseReg = AFI->getGlobalBaseReg();
3049 if (GlobalBaseReg == 0) {
3050 GlobalBaseReg = MRI.createVirtualRegister(TLI.getRegClassFor(VT));
3051 AFI->setGlobalBaseReg(GlobalBaseReg);
3054 unsigned DestReg2 = createResultReg(TLI.getRegClassFor(VT));
3055 DestReg2 = constrainOperandRegClass(TII.get(Opc), DestReg2, 0);
3056 DestReg1 = constrainOperandRegClass(TII.get(Opc), DestReg1, 1);
3057 GlobalBaseReg = constrainOperandRegClass(TII.get(Opc), GlobalBaseReg, 2);
3058 MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt,
3059 DL, TII.get(Opc), DestReg2)
3061 .addReg(GlobalBaseReg);
3064 AddOptionalDefs(MIB);
3069 bool ARMFastISel::FastLowerArguments() {
3070 if (!FuncInfo.CanLowerReturn)
3073 const Function *F = FuncInfo.Fn;
3077 CallingConv::ID CC = F->getCallingConv();
3081 case CallingConv::Fast:
3082 case CallingConv::C:
3083 case CallingConv::ARM_AAPCS_VFP:
3084 case CallingConv::ARM_AAPCS:
3085 case CallingConv::ARM_APCS:
3089 // Only handle simple cases. i.e. Up to 4 i8/i16/i32 scalar arguments
3090 // which are passed in r0 - r3.
3092 for (Function::const_arg_iterator I = F->arg_begin(), E = F->arg_end();
3093 I != E; ++I, ++Idx) {
3097 if (F->getAttributes().hasAttribute(Idx, Attribute::InReg) ||
3098 F->getAttributes().hasAttribute(Idx, Attribute::StructRet) ||
3099 F->getAttributes().hasAttribute(Idx, Attribute::ByVal))
3102 Type *ArgTy = I->getType();
3103 if (ArgTy->isStructTy() || ArgTy->isArrayTy() || ArgTy->isVectorTy())
3106 EVT ArgVT = TLI.getValueType(ArgTy);
3107 if (!ArgVT.isSimple()) return false;
3108 switch (ArgVT.getSimpleVT().SimpleTy) {
3119 static const uint16_t GPRArgRegs[] = {
3120 ARM::R0, ARM::R1, ARM::R2, ARM::R3
3123 const TargetRegisterClass *RC = &ARM::rGPRRegClass;
3125 for (Function::const_arg_iterator I = F->arg_begin(), E = F->arg_end();
3126 I != E; ++I, ++Idx) {
3127 unsigned SrcReg = GPRArgRegs[Idx];
3128 unsigned DstReg = FuncInfo.MF->addLiveIn(SrcReg, RC);
3129 // FIXME: Unfortunately it's necessary to emit a copy from the livein copy.
3130 // Without this, EmitLiveInCopies may eliminate the livein if its only
3131 // use is a bitcast (which isn't turned into an instruction).
3132 unsigned ResultReg = createResultReg(RC);
3133 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY),
3134 ResultReg).addReg(DstReg, getKillRegState(true));
3135 UpdateValueMap(I, ResultReg);
3142 FastISel *ARM::createFastISel(FunctionLoweringInfo &funcInfo,
3143 const TargetLibraryInfo *libInfo) {
3144 const TargetMachine &TM = funcInfo.MF->getTarget();
3146 const ARMSubtarget *Subtarget = &TM.getSubtarget<ARMSubtarget>();
3147 // Thumb2 support on iOS; ARM support on iOS, Linux and NaCl.
3148 bool UseFastISel = false;
3149 UseFastISel |= Subtarget->isTargetIOS() && !Subtarget->isThumb1Only();
3150 UseFastISel |= Subtarget->isTargetLinux() && !Subtarget->isThumb();
3151 UseFastISel |= Subtarget->isTargetNaCl() && !Subtarget->isThumb();
3154 // iOS always has a FP for backtracking, force other targets
3155 // to keep their FP when doing FastISel. The emitted code is
3156 // currently superior, and in cases like test-suite's lencod
3157 // FastISel isn't quite correct when FP is eliminated.
3158 TM.Options.NoFramePointerElim = true;
3159 return new ARMFastISel(funcInfo, libInfo);