1 //===-- ARMFastISel.cpp - ARM FastISel implementation ---------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the ARM-specific support for the FastISel class. Some
11 // of the target-specific code is generated by tablegen in the file
12 // ARMGenFastISel.inc, which is #included here.
14 //===----------------------------------------------------------------------===//
17 #include "ARMBaseInstrInfo.h"
18 #include "ARMCallingConv.h"
19 #include "ARMRegisterInfo.h"
20 #include "ARMTargetMachine.h"
21 #include "ARMSubtarget.h"
22 #include "ARMConstantPoolValue.h"
23 #include "llvm/CallingConv.h"
24 #include "llvm/DerivedTypes.h"
25 #include "llvm/GlobalVariable.h"
26 #include "llvm/Instructions.h"
27 #include "llvm/IntrinsicInst.h"
28 #include "llvm/Module.h"
29 #include "llvm/CodeGen/Analysis.h"
30 #include "llvm/CodeGen/FastISel.h"
31 #include "llvm/CodeGen/FunctionLoweringInfo.h"
32 #include "llvm/CodeGen/MachineInstrBuilder.h"
33 #include "llvm/CodeGen/MachineModuleInfo.h"
34 #include "llvm/CodeGen/MachineConstantPool.h"
35 #include "llvm/CodeGen/MachineFrameInfo.h"
36 #include "llvm/CodeGen/MachineMemOperand.h"
37 #include "llvm/CodeGen/MachineRegisterInfo.h"
38 #include "llvm/CodeGen/PseudoSourceValue.h"
39 #include "llvm/Support/CallSite.h"
40 #include "llvm/Support/CommandLine.h"
41 #include "llvm/Support/ErrorHandling.h"
42 #include "llvm/Support/GetElementPtrTypeIterator.h"
43 #include "llvm/Target/TargetData.h"
44 #include "llvm/Target/TargetInstrInfo.h"
45 #include "llvm/Target/TargetLowering.h"
46 #include "llvm/Target/TargetMachine.h"
47 #include "llvm/Target/TargetOptions.h"
51 EnableARMFastISel("arm-fast-isel",
52 cl::desc("Turn on experimental ARM fast-isel support"),
53 cl::init(false), cl::Hidden);
57 class ARMFastISel : public FastISel {
59 typedef struct AddrBase {
64 /// Subtarget - Keep a pointer to the ARMSubtarget around so that we can
65 /// make the right decision when generating code for different targets.
66 const ARMSubtarget *Subtarget;
67 const TargetMachine &TM;
68 const TargetInstrInfo &TII;
69 const TargetLowering &TLI;
72 // Convenience variables to avoid some queries.
77 explicit ARMFastISel(FunctionLoweringInfo &funcInfo)
79 TM(funcInfo.MF->getTarget()),
80 TII(*TM.getInstrInfo()),
81 TLI(*TM.getTargetLowering()) {
82 Subtarget = &TM.getSubtarget<ARMSubtarget>();
83 AFI = funcInfo.MF->getInfo<ARMFunctionInfo>();
84 isThumb = AFI->isThumbFunction();
85 Context = &funcInfo.Fn->getContext();
88 // Code from FastISel.cpp.
89 virtual unsigned FastEmitInst_(unsigned MachineInstOpcode,
90 const TargetRegisterClass *RC);
91 virtual unsigned FastEmitInst_r(unsigned MachineInstOpcode,
92 const TargetRegisterClass *RC,
93 unsigned Op0, bool Op0IsKill);
94 virtual unsigned FastEmitInst_rr(unsigned MachineInstOpcode,
95 const TargetRegisterClass *RC,
96 unsigned Op0, bool Op0IsKill,
97 unsigned Op1, bool Op1IsKill);
98 virtual unsigned FastEmitInst_ri(unsigned MachineInstOpcode,
99 const TargetRegisterClass *RC,
100 unsigned Op0, bool Op0IsKill,
102 virtual unsigned FastEmitInst_rf(unsigned MachineInstOpcode,
103 const TargetRegisterClass *RC,
104 unsigned Op0, bool Op0IsKill,
105 const ConstantFP *FPImm);
106 virtual unsigned FastEmitInst_i(unsigned MachineInstOpcode,
107 const TargetRegisterClass *RC,
109 virtual unsigned FastEmitInst_rri(unsigned MachineInstOpcode,
110 const TargetRegisterClass *RC,
111 unsigned Op0, bool Op0IsKill,
112 unsigned Op1, bool Op1IsKill,
114 virtual unsigned FastEmitInst_extractsubreg(MVT RetVT,
115 unsigned Op0, bool Op0IsKill,
118 // Backend specific FastISel code.
119 virtual bool TargetSelectInstruction(const Instruction *I);
120 virtual unsigned TargetMaterializeConstant(const Constant *C);
121 virtual unsigned TargetMaterializeAlloca(const AllocaInst *AI);
123 #include "ARMGenFastISel.inc"
125 // Instruction selection routines.
127 virtual bool SelectLoad(const Instruction *I);
128 virtual bool SelectStore(const Instruction *I);
129 virtual bool SelectBranch(const Instruction *I);
130 virtual bool SelectCmp(const Instruction *I);
131 virtual bool SelectFPExt(const Instruction *I);
132 virtual bool SelectFPTrunc(const Instruction *I);
133 virtual bool SelectBinaryOp(const Instruction *I, unsigned ISDOpcode);
134 virtual bool SelectSIToFP(const Instruction *I);
135 virtual bool SelectFPToSI(const Instruction *I);
136 virtual bool SelectSDiv(const Instruction *I);
137 virtual bool SelectSRem(const Instruction *I);
138 virtual bool SelectCall(const Instruction *I);
139 virtual bool SelectSelect(const Instruction *I);
143 bool isTypeLegal(const Type *Ty, EVT &VT);
144 bool isLoadTypeLegal(const Type *Ty, EVT &VT);
145 bool ARMEmitLoad(EVT VT, unsigned &ResultReg, AddrBase Base, int Offset);
146 bool ARMEmitStore(EVT VT, unsigned SrcReg, AddrBase Base, int Offset);
147 bool ARMComputeRegOffset(const Value *Obj, AddrBase &Base, int &Offset);
148 void ARMSimplifyRegOffset(AddrBase &Base, int &Offset, EVT VT);
149 unsigned ARMMaterializeFP(const ConstantFP *CFP, EVT VT);
150 unsigned ARMMaterializeInt(const Constant *C, EVT VT);
151 unsigned ARMMaterializeGV(const GlobalValue *GV, EVT VT);
152 unsigned ARMMoveToFPReg(EVT VT, unsigned SrcReg);
153 unsigned ARMMoveToIntReg(EVT VT, unsigned SrcReg);
155 // Call handling routines.
157 CCAssignFn *CCAssignFnForCall(CallingConv::ID CC, bool Return);
158 bool ProcessCallArgs(SmallVectorImpl<Value*> &Args,
159 SmallVectorImpl<unsigned> &ArgRegs,
160 SmallVectorImpl<EVT> &ArgVTs,
161 SmallVectorImpl<ISD::ArgFlagsTy> &ArgFlags,
162 SmallVectorImpl<unsigned> &RegArgs,
165 bool FinishCall(EVT RetVT, SmallVectorImpl<unsigned> &UsedRegs,
166 const Instruction *I, CallingConv::ID CC,
168 bool ARMEmitLibcall(const Instruction *I, RTLIB::Libcall Call);
170 // OptionalDef handling routines.
172 bool DefinesOptionalPredicate(MachineInstr *MI, bool *CPSR);
173 const MachineInstrBuilder &AddOptionalDefs(const MachineInstrBuilder &MIB);
176 } // end anonymous namespace
178 #include "ARMGenCallingConv.inc"
180 // DefinesOptionalPredicate - This is different from DefinesPredicate in that
181 // we don't care about implicit defs here, just places we'll need to add a
182 // default CCReg argument. Sets CPSR if we're setting CPSR instead of CCR.
183 bool ARMFastISel::DefinesOptionalPredicate(MachineInstr *MI, bool *CPSR) {
184 const TargetInstrDesc &TID = MI->getDesc();
185 if (!TID.hasOptionalDef())
188 // Look to see if our OptionalDef is defining CPSR or CCR.
189 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
190 const MachineOperand &MO = MI->getOperand(i);
191 if (!MO.isReg() || !MO.isDef()) continue;
192 if (MO.getReg() == ARM::CPSR)
198 // If the machine is predicable go ahead and add the predicate operands, if
199 // it needs default CC operands add those.
200 const MachineInstrBuilder &
201 ARMFastISel::AddOptionalDefs(const MachineInstrBuilder &MIB) {
202 MachineInstr *MI = &*MIB;
204 // Do we use a predicate?
205 if (TII.isPredicable(MI))
208 // Do we optionally set a predicate? Preds is size > 0 iff the predicate
209 // defines CPSR. All other OptionalDefines in ARM are the CCR register.
211 if (DefinesOptionalPredicate(MI, &CPSR)) {
220 unsigned ARMFastISel::FastEmitInst_(unsigned MachineInstOpcode,
221 const TargetRegisterClass* RC) {
222 unsigned ResultReg = createResultReg(RC);
223 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
225 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg));
229 unsigned ARMFastISel::FastEmitInst_r(unsigned MachineInstOpcode,
230 const TargetRegisterClass *RC,
231 unsigned Op0, bool Op0IsKill) {
232 unsigned ResultReg = createResultReg(RC);
233 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
235 if (II.getNumDefs() >= 1)
236 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
237 .addReg(Op0, Op0IsKill * RegState::Kill));
239 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
240 .addReg(Op0, Op0IsKill * RegState::Kill));
241 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
242 TII.get(TargetOpcode::COPY), ResultReg)
243 .addReg(II.ImplicitDefs[0]));
248 unsigned ARMFastISel::FastEmitInst_rr(unsigned MachineInstOpcode,
249 const TargetRegisterClass *RC,
250 unsigned Op0, bool Op0IsKill,
251 unsigned Op1, bool Op1IsKill) {
252 unsigned ResultReg = createResultReg(RC);
253 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
255 if (II.getNumDefs() >= 1)
256 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
257 .addReg(Op0, Op0IsKill * RegState::Kill)
258 .addReg(Op1, Op1IsKill * RegState::Kill));
260 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
261 .addReg(Op0, Op0IsKill * RegState::Kill)
262 .addReg(Op1, Op1IsKill * RegState::Kill));
263 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
264 TII.get(TargetOpcode::COPY), ResultReg)
265 .addReg(II.ImplicitDefs[0]));
270 unsigned ARMFastISel::FastEmitInst_ri(unsigned MachineInstOpcode,
271 const TargetRegisterClass *RC,
272 unsigned Op0, bool Op0IsKill,
274 unsigned ResultReg = createResultReg(RC);
275 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
277 if (II.getNumDefs() >= 1)
278 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
279 .addReg(Op0, Op0IsKill * RegState::Kill)
282 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
283 .addReg(Op0, Op0IsKill * RegState::Kill)
285 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
286 TII.get(TargetOpcode::COPY), ResultReg)
287 .addReg(II.ImplicitDefs[0]));
292 unsigned ARMFastISel::FastEmitInst_rf(unsigned MachineInstOpcode,
293 const TargetRegisterClass *RC,
294 unsigned Op0, bool Op0IsKill,
295 const ConstantFP *FPImm) {
296 unsigned ResultReg = createResultReg(RC);
297 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
299 if (II.getNumDefs() >= 1)
300 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
301 .addReg(Op0, Op0IsKill * RegState::Kill)
304 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
305 .addReg(Op0, Op0IsKill * RegState::Kill)
307 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
308 TII.get(TargetOpcode::COPY), ResultReg)
309 .addReg(II.ImplicitDefs[0]));
314 unsigned ARMFastISel::FastEmitInst_rri(unsigned MachineInstOpcode,
315 const TargetRegisterClass *RC,
316 unsigned Op0, bool Op0IsKill,
317 unsigned Op1, bool Op1IsKill,
319 unsigned ResultReg = createResultReg(RC);
320 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
322 if (II.getNumDefs() >= 1)
323 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
324 .addReg(Op0, Op0IsKill * RegState::Kill)
325 .addReg(Op1, Op1IsKill * RegState::Kill)
328 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
329 .addReg(Op0, Op0IsKill * RegState::Kill)
330 .addReg(Op1, Op1IsKill * RegState::Kill)
332 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
333 TII.get(TargetOpcode::COPY), ResultReg)
334 .addReg(II.ImplicitDefs[0]));
339 unsigned ARMFastISel::FastEmitInst_i(unsigned MachineInstOpcode,
340 const TargetRegisterClass *RC,
342 unsigned ResultReg = createResultReg(RC);
343 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
345 if (II.getNumDefs() >= 1)
346 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
349 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
351 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
352 TII.get(TargetOpcode::COPY), ResultReg)
353 .addReg(II.ImplicitDefs[0]));
358 unsigned ARMFastISel::FastEmitInst_extractsubreg(MVT RetVT,
359 unsigned Op0, bool Op0IsKill,
361 unsigned ResultReg = createResultReg(TLI.getRegClassFor(RetVT));
362 assert(TargetRegisterInfo::isVirtualRegister(Op0) &&
363 "Cannot yet extract from physregs");
364 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt,
365 DL, TII.get(TargetOpcode::COPY), ResultReg)
366 .addReg(Op0, getKillRegState(Op0IsKill), Idx));
370 // TODO: Don't worry about 64-bit now, but when this is fixed remove the
371 // checks from the various callers.
372 unsigned ARMFastISel::ARMMoveToFPReg(EVT VT, unsigned SrcReg) {
373 if (VT.getSimpleVT().SimpleTy == MVT::f64) return 0;
375 unsigned MoveReg = createResultReg(TLI.getRegClassFor(VT));
376 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
377 TII.get(ARM::VMOVRS), MoveReg)
382 unsigned ARMFastISel::ARMMoveToIntReg(EVT VT, unsigned SrcReg) {
383 if (VT.getSimpleVT().SimpleTy == MVT::i64) return 0;
385 unsigned MoveReg = createResultReg(TLI.getRegClassFor(VT));
386 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
387 TII.get(ARM::VMOVSR), MoveReg)
392 // For double width floating point we need to materialize two constants
393 // (the high and the low) into integer registers then use a move to get
394 // the combined constant into an FP reg.
395 unsigned ARMFastISel::ARMMaterializeFP(const ConstantFP *CFP, EVT VT) {
396 const APFloat Val = CFP->getValueAPF();
397 bool is64bit = VT.getSimpleVT().SimpleTy == MVT::f64;
399 // This checks to see if we can use VFP3 instructions to materialize
400 // a constant, otherwise we have to go through the constant pool.
401 if (TLI.isFPImmLegal(Val, VT)) {
402 unsigned Opc = is64bit ? ARM::FCONSTD : ARM::FCONSTS;
403 unsigned DestReg = createResultReg(TLI.getRegClassFor(VT));
404 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc),
410 // Require VFP2 for loading fp constants.
411 if (!Subtarget->hasVFP2()) return false;
413 // MachineConstantPool wants an explicit alignment.
414 unsigned Align = TD.getPrefTypeAlignment(CFP->getType());
416 // TODO: Figure out if this is correct.
417 Align = TD.getTypeAllocSize(CFP->getType());
419 unsigned Idx = MCP.getConstantPoolIndex(cast<Constant>(CFP), Align);
420 unsigned DestReg = createResultReg(TLI.getRegClassFor(VT));
421 unsigned Opc = is64bit ? ARM::VLDRD : ARM::VLDRS;
423 // The extra reg is for addrmode5.
424 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc),
426 .addConstantPoolIndex(Idx)
431 unsigned ARMFastISel::ARMMaterializeInt(const Constant *C, EVT VT) {
433 // For now 32-bit only.
434 if (VT.getSimpleVT().SimpleTy != MVT::i32) return false;
436 // MachineConstantPool wants an explicit alignment.
437 unsigned Align = TD.getPrefTypeAlignment(C->getType());
439 // TODO: Figure out if this is correct.
440 Align = TD.getTypeAllocSize(C->getType());
442 unsigned Idx = MCP.getConstantPoolIndex(C, Align);
443 unsigned DestReg = createResultReg(TLI.getRegClassFor(VT));
446 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
447 TII.get(ARM::t2LDRpci), DestReg)
448 .addConstantPoolIndex(Idx));
450 // The extra reg and immediate are for addrmode2.
451 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
452 TII.get(ARM::LDRcp), DestReg)
453 .addConstantPoolIndex(Idx)
454 .addReg(0).addImm(0));
459 unsigned ARMFastISel::ARMMaterializeGV(const GlobalValue *GV, EVT VT) {
460 // For now 32-bit only.
461 if (VT.getSimpleVT().SimpleTy != MVT::i32) return 0;
463 Reloc::Model RelocM = TM.getRelocationModel();
465 // TODO: No external globals for now.
466 if (Subtarget->GVIsIndirectSymbol(GV, RelocM)) return 0;
468 // TODO: Need more magic for ARM PIC.
469 if (!isThumb && (RelocM == Reloc::PIC_)) return 0;
471 // MachineConstantPool wants an explicit alignment.
472 unsigned Align = TD.getPrefTypeAlignment(GV->getType());
474 // TODO: Figure out if this is correct.
475 Align = TD.getTypeAllocSize(GV->getType());
479 unsigned PCAdj = (RelocM != Reloc::PIC_) ? 0 : (Subtarget->isThumb() ? 4 : 8);
480 unsigned Id = AFI->createConstPoolEntryUId();
481 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(GV, Id,
482 ARMCP::CPValue, PCAdj);
483 unsigned Idx = MCP.getConstantPoolIndex(CPV, Align);
486 MachineInstrBuilder MIB;
487 unsigned DestReg = createResultReg(TLI.getRegClassFor(VT));
489 unsigned Opc = (RelocM != Reloc::PIC_) ? ARM::t2LDRpci : ARM::t2LDRpci_pic;
490 MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc), DestReg)
491 .addConstantPoolIndex(Idx);
492 if (RelocM == Reloc::PIC_)
495 // The extra reg and immediate are for addrmode2.
496 MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(ARM::LDRcp),
498 .addConstantPoolIndex(Idx)
499 .addReg(0).addImm(0);
501 AddOptionalDefs(MIB);
505 unsigned ARMFastISel::TargetMaterializeConstant(const Constant *C) {
506 EVT VT = TLI.getValueType(C->getType(), true);
508 // Only handle simple types.
509 if (!VT.isSimple()) return 0;
511 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(C))
512 return ARMMaterializeFP(CFP, VT);
513 else if (const GlobalValue *GV = dyn_cast<GlobalValue>(C))
514 return ARMMaterializeGV(GV, VT);
515 else if (isa<ConstantInt>(C))
516 return ARMMaterializeInt(C, VT);
521 unsigned ARMFastISel::TargetMaterializeAlloca(const AllocaInst *AI) {
522 // Don't handle dynamic allocas.
523 if (!FuncInfo.StaticAllocaMap.count(AI)) return 0;
526 if (!isTypeLegal(AI->getType(), VT)) return false;
528 DenseMap<const AllocaInst*, int>::iterator SI =
529 FuncInfo.StaticAllocaMap.find(AI);
531 // This will get lowered later into the correct offsets and registers
532 // via rewriteXFrameIndex.
533 if (SI != FuncInfo.StaticAllocaMap.end()) {
534 TargetRegisterClass* RC = TLI.getRegClassFor(VT);
535 unsigned ResultReg = createResultReg(RC);
536 unsigned Opc = isThumb ? ARM::t2ADDri : ARM::ADDri;
537 AddOptionalDefs(BuildMI(*FuncInfo.MBB, *FuncInfo.InsertPt, DL,
538 TII.get(Opc), ResultReg)
539 .addFrameIndex(SI->second)
547 bool ARMFastISel::isTypeLegal(const Type *Ty, EVT &VT) {
548 VT = TLI.getValueType(Ty, true);
550 // Only handle simple types.
551 if (VT == MVT::Other || !VT.isSimple()) return false;
553 // Handle all legal types, i.e. a register that will directly hold this
555 return TLI.isTypeLegal(VT);
558 bool ARMFastISel::isLoadTypeLegal(const Type *Ty, EVT &VT) {
559 if (isTypeLegal(Ty, VT)) return true;
561 // If this is a type than can be sign or zero-extended to a basic operation
562 // go ahead and accept it now.
563 if (VT == MVT::i8 || VT == MVT::i16)
569 // Computes the Reg+Offset to get to an object.
570 bool ARMFastISel::ARMComputeRegOffset(const Value *Obj, AddrBase &Base,
572 // Some boilerplate from the X86 FastISel.
573 const User *U = NULL;
574 unsigned Opcode = Instruction::UserOp1;
575 if (const Instruction *I = dyn_cast<Instruction>(Obj)) {
576 // Don't walk into other basic blocks; it's possible we haven't
577 // visited them yet, so the instructions may not yet be assigned
578 // virtual registers.
579 if (FuncInfo.MBBMap[I->getParent()] != FuncInfo.MBB)
581 Opcode = I->getOpcode();
583 } else if (const ConstantExpr *C = dyn_cast<ConstantExpr>(Obj)) {
584 Opcode = C->getOpcode();
588 if (const PointerType *Ty = dyn_cast<PointerType>(Obj->getType()))
589 if (Ty->getAddressSpace() > 255)
590 // Fast instruction selection doesn't support the special
597 case Instruction::BitCast: {
598 // Look through bitcasts.
599 return ARMComputeRegOffset(U->getOperand(0), Base, Offset);
601 case Instruction::IntToPtr: {
602 // Look past no-op inttoptrs.
603 if (TLI.getValueType(U->getOperand(0)->getType()) == TLI.getPointerTy())
604 return ARMComputeRegOffset(U->getOperand(0), Base, Offset);
607 case Instruction::PtrToInt: {
608 // Look past no-op ptrtoints.
609 if (TLI.getValueType(U->getType()) == TLI.getPointerTy())
610 return ARMComputeRegOffset(U->getOperand(0), Base, Offset);
613 case Instruction::GetElementPtr: {
614 int SavedOffset = Offset;
615 AddrBase SavedBase = Base;
616 int TmpOffset = Offset;
618 // Iterate through the GEP folding the constants into offsets where
620 gep_type_iterator GTI = gep_type_begin(U);
621 for (User::const_op_iterator i = U->op_begin() + 1, e = U->op_end();
622 i != e; ++i, ++GTI) {
623 const Value *Op = *i;
624 if (const StructType *STy = dyn_cast<StructType>(*GTI)) {
625 const StructLayout *SL = TD.getStructLayout(STy);
626 unsigned Idx = cast<ConstantInt>(Op)->getZExtValue();
627 TmpOffset += SL->getElementOffset(Idx);
629 uint64_t S = TD.getTypeAllocSize(GTI.getIndexedType());
630 SmallVector<const Value *, 4> Worklist;
631 Worklist.push_back(Op);
633 Op = Worklist.pop_back_val();
634 if (const ConstantInt *CI = dyn_cast<ConstantInt>(Op)) {
635 // Constant-offset addressing.
636 TmpOffset += CI->getSExtValue() * S;
637 } else if (isa<AddOperator>(Op) &&
638 isa<ConstantInt>(cast<AddOperator>(Op)->getOperand(1))) {
639 // An add with a constant operand. Fold the constant.
641 cast<ConstantInt>(cast<AddOperator>(Op)->getOperand(1));
642 TmpOffset += CI->getSExtValue() * S;
643 // Add the other operand back to the work list.
644 Worklist.push_back(cast<AddOperator>(Op)->getOperand(0));
646 goto unsupported_gep;
647 } while (!Worklist.empty());
651 // Try to grab the base operand now.
653 if (ARMComputeRegOffset(U->getOperand(0), Base, Offset)) return true;
655 // We failed, restore everything and try the other options.
656 Offset = SavedOffset;
662 case Instruction::Alloca: {
663 const AllocaInst *AI = cast<AllocaInst>(Obj);
664 unsigned Reg = TargetMaterializeAlloca(AI);
666 if (Reg == 0) return false;
673 // Materialize the global variable's address into a reg which can
674 // then be used later to load the variable.
675 if (const GlobalValue *GV = dyn_cast<GlobalValue>(Obj)) {
676 unsigned Tmp = ARMMaterializeGV(GV, TLI.getValueType(Obj->getType()));
677 if (Tmp == 0) return false;
683 // Try to get this in a register if nothing else has worked.
684 if (Base.Reg == 0) Base.Reg = getRegForValue(Obj);
685 return Base.Reg != 0;
688 void ARMFastISel::ARMSimplifyRegOffset(AddrBase &Base, int &Offset, EVT VT) {
690 // Since the offset may be too large for the load instruction
691 // get the reg+offset into a register.
692 if (Base.Reg != ARM::SP && Offset != 0) {
693 ARMCC::CondCodes Pred = ARMCC::AL;
694 unsigned PredReg = 0;
696 TargetRegisterClass *RC = isThumb ? ARM::tGPRRegisterClass :
697 ARM::GPRRegisterClass;
698 unsigned BaseReg = createResultReg(RC);
701 emitARMRegPlusImmediate(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
702 BaseReg, Base.Reg, Offset, Pred, PredReg,
703 static_cast<const ARMBaseInstrInfo&>(TII));
705 assert(AFI->isThumb2Function());
706 emitT2RegPlusImmediate(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
707 BaseReg, Base.Reg, Offset, Pred, PredReg,
708 static_cast<const ARMBaseInstrInfo&>(TII));
715 bool ARMFastISel::ARMEmitLoad(EVT VT, unsigned &ResultReg,
716 AddrBase Base, int Offset) {
718 assert(VT.isSimple() && "Non-simple types are invalid here!");
720 TargetRegisterClass *RC;
721 bool isFloat = false;
722 switch (VT.getSimpleVT().SimpleTy) {
724 // This is mostly going to be Neon/vector support.
727 Opc = isThumb ? ARM::t2LDRHi12 : ARM::LDRH;
728 RC = ARM::GPRRegisterClass;
732 Opc = isThumb ? ARM::t2LDRBi12 : ARM::LDRB;
733 RC = ARM::GPRRegisterClass;
737 Opc = isThumb ? ARM::t2LDRi12 : ARM::LDR;
738 RC = ARM::GPRRegisterClass;
742 RC = TLI.getRegClassFor(VT);
747 RC = TLI.getRegClassFor(VT);
752 ResultReg = createResultReg(RC);
754 // For now with the additions above the offset should be zero - thus we
755 // can always fit into an i12.
756 assert((Base.Reg == ARM::SP || Offset == 0) &&
757 "Offset not zero and not a stack load!");
759 if (Base.Reg == ARM::SP && Offset == 0)
760 TII.loadRegFromStackSlot(*FuncInfo.MBB, *FuncInfo.InsertPt,
761 ResultReg, Base.FrameIndex, RC,
762 TM.getRegisterInfo());
763 else if (Base.Reg == ARM::SP) {
764 // TODO: This won't work for NEON.
765 unsigned FI = Base.FrameIndex;
766 MachineMemOperand *MMO =
767 FuncInfo.MF->getMachineMemOperand(
768 MachinePointerInfo::getFixedStack(FI, Offset),
769 MachineMemOperand::MOLoad,
770 MFI.getObjectSize(FI),
771 MFI.getObjectAlignment(FI));
772 if (isFloat || isThumb)
773 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
774 TII.get(Opc), ResultReg)
775 .addFrameIndex(FI).addImm(Offset).addMemOperand(MMO));
777 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
778 TII.get(Opc), ResultReg)
779 .addFrameIndex(FI).addReg(0).addImm(Offset).addMemOperand(MMO));
781 // The thumb and floating point instructions both take 2 operands, ARM takes
783 else if (isFloat || isThumb)
784 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
785 TII.get(Opc), ResultReg)
786 .addReg(Base.Reg).addImm(Offset));
788 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
789 TII.get(Opc), ResultReg)
790 .addReg(Base.Reg).addReg(0).addImm(Offset));
794 bool ARMFastISel::SelectLoad(const Instruction *I) {
795 // Verify we have a legal type before going any further.
797 if (!isLoadTypeLegal(I->getType(), VT))
800 // Our register and offset with innocuous defaults.
801 AddrBase Base = { 0, 0 };
804 // See if we can handle this as Reg + Offset
805 if (!ARMComputeRegOffset(I->getOperand(0), Base, Offset))
808 ARMSimplifyRegOffset(Base, Offset, VT);
811 if (!ARMEmitLoad(VT, ResultReg, Base, Offset)) return false;
813 UpdateValueMap(I, ResultReg);
817 bool ARMFastISel::ARMEmitStore(EVT VT, unsigned SrcReg,
818 AddrBase Base, int Offset) {
820 bool isFloat = false;
821 // VT is set here only for use in the alloca stores below - those are promoted
822 // to reg size always.
823 switch (VT.getSimpleVT().SimpleTy) {
824 default: return false;
828 StrOpc = isThumb ? ARM::t2STRBi12 : ARM::STRB;
832 StrOpc = isThumb ? ARM::t2STRHi12 : ARM::STRH;
835 StrOpc = isThumb ? ARM::t2STRi12 : ARM::STR;
838 if (!Subtarget->hasVFP2()) return false;
843 if (!Subtarget->hasVFP2()) return false;
849 if (Base.Reg == ARM::SP && Offset == 0)
850 TII.storeRegToStackSlot(*FuncInfo.MBB, *FuncInfo.InsertPt,
851 SrcReg, true /*isKill*/, Base.FrameIndex,
852 TLI.getRegClassFor(VT), TM.getRegisterInfo());
853 else if (Base.Reg == ARM::SP) {
854 // TODO: This won't work for NEON.
855 unsigned FI = Base.FrameIndex;
856 MachineMemOperand *MMO =
857 FuncInfo.MF->getMachineMemOperand(
858 MachinePointerInfo::getFixedStack(FI, Offset),
859 MachineMemOperand::MOStore,
860 MFI.getObjectSize(FI),
861 MFI.getObjectAlignment(FI));
862 if (isFloat || isThumb)
863 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
865 .addReg(SrcReg, getKillRegState(true))
866 .addFrameIndex(FI).addImm(Offset).addMemOperand(MMO));
868 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
870 .addReg(SrcReg, getKillRegState(true))
871 .addFrameIndex(FI).addReg(0).addImm(Offset).addMemOperand(MMO));
873 // The thumb addressing mode has operands swapped from the arm addressing
874 // mode, the floating point one only has two operands.
875 else if (isFloat || isThumb)
876 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
878 .addReg(SrcReg).addReg(Base.Reg).addImm(Offset));
880 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
882 .addReg(SrcReg).addReg(Base.Reg).addReg(0).addImm(Offset));
887 bool ARMFastISel::SelectStore(const Instruction *I) {
888 Value *Op0 = I->getOperand(0);
891 // Yay type legalization
893 if (!isLoadTypeLegal(I->getOperand(0)->getType(), VT))
896 // Get the value to be stored into a register.
897 SrcReg = getRegForValue(Op0);
901 // Our register and offset with innocuous defaults.
902 AddrBase Base = { 0, 0 };
905 // See if we can handle this as Reg + Offset
906 if (!ARMComputeRegOffset(I->getOperand(1), Base, Offset))
909 ARMSimplifyRegOffset(Base, Offset, VT);
911 if (!ARMEmitStore(VT, SrcReg, Base, Offset)) return false;
916 static ARMCC::CondCodes getComparePred(CmpInst::Predicate Pred) {
918 // Needs two compares...
919 case CmpInst::FCMP_ONE:
920 case CmpInst::FCMP_UEQ:
922 assert(false && "Unhandled CmpInst::Predicate!");
924 case CmpInst::ICMP_EQ:
925 case CmpInst::FCMP_OEQ:
927 case CmpInst::ICMP_SGT:
928 case CmpInst::FCMP_OGT:
930 case CmpInst::ICMP_SGE:
931 case CmpInst::FCMP_OGE:
933 case CmpInst::ICMP_UGT:
934 case CmpInst::FCMP_UGT:
936 case CmpInst::FCMP_OLT:
938 case CmpInst::ICMP_ULE:
939 case CmpInst::FCMP_OLE:
941 case CmpInst::FCMP_ORD:
943 case CmpInst::FCMP_UNO:
945 case CmpInst::FCMP_UGE:
947 case CmpInst::ICMP_SLT:
948 case CmpInst::FCMP_ULT:
950 case CmpInst::ICMP_SLE:
951 case CmpInst::FCMP_ULE:
953 case CmpInst::FCMP_UNE:
954 case CmpInst::ICMP_NE:
956 case CmpInst::ICMP_UGE:
958 case CmpInst::ICMP_ULT:
963 bool ARMFastISel::SelectBranch(const Instruction *I) {
964 const BranchInst *BI = cast<BranchInst>(I);
965 MachineBasicBlock *TBB = FuncInfo.MBBMap[BI->getSuccessor(0)];
966 MachineBasicBlock *FBB = FuncInfo.MBBMap[BI->getSuccessor(1)];
968 // Simple branch support.
969 // TODO: Try to avoid the re-computation in some places.
970 unsigned CondReg = getRegForValue(BI->getCondition());
971 if (CondReg == 0) return false;
973 // Re-set the flags just in case.
974 unsigned CmpOpc = isThumb ? ARM::t2CMPri : ARM::CMPri;
975 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(CmpOpc))
976 .addReg(CondReg).addImm(1));
978 unsigned BrOpc = isThumb ? ARM::t2Bcc : ARM::Bcc;
979 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(BrOpc))
980 .addMBB(TBB).addImm(ARMCC::EQ).addReg(ARM::CPSR);
981 FastEmitBranch(FBB, DL);
982 FuncInfo.MBB->addSuccessor(TBB);
986 bool ARMFastISel::SelectCmp(const Instruction *I) {
987 const CmpInst *CI = cast<CmpInst>(I);
990 const Type *Ty = CI->getOperand(0)->getType();
991 if (!isTypeLegal(Ty, VT))
994 bool isFloat = (Ty->isDoubleTy() || Ty->isFloatTy());
995 if (isFloat && !Subtarget->hasVFP2())
1000 switch (VT.getSimpleVT().SimpleTy) {
1001 default: return false;
1002 // TODO: Verify compares.
1004 CmpOpc = ARM::VCMPES;
1005 CondReg = ARM::FPSCR;
1008 CmpOpc = ARM::VCMPED;
1009 CondReg = ARM::FPSCR;
1012 CmpOpc = isThumb ? ARM::t2CMPrr : ARM::CMPrr;
1013 CondReg = ARM::CPSR;
1017 // Get the compare predicate.
1018 ARMCC::CondCodes ARMPred = getComparePred(CI->getPredicate());
1020 // We may not handle every CC for now.
1021 if (ARMPred == ARMCC::AL) return false;
1023 unsigned Arg1 = getRegForValue(CI->getOperand(0));
1024 if (Arg1 == 0) return false;
1026 unsigned Arg2 = getRegForValue(CI->getOperand(1));
1027 if (Arg2 == 0) return false;
1029 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(CmpOpc))
1030 .addReg(Arg1).addReg(Arg2));
1032 // For floating point we need to move the result to a comparison register
1033 // that we can then use for branches.
1035 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1036 TII.get(ARM::FMSTAT)));
1038 // Now set a register based on the comparison. Explicitly set the predicates
1040 unsigned MovCCOpc = isThumb ? ARM::t2MOVCCi : ARM::MOVCCi;
1041 TargetRegisterClass *RC = isThumb ? ARM::rGPRRegisterClass
1042 : ARM::GPRRegisterClass;
1043 unsigned DestReg = createResultReg(RC);
1045 = ConstantInt::get(Type::getInt32Ty(*Context), 0);
1046 unsigned ZeroReg = TargetMaterializeConstant(Zero);
1047 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(MovCCOpc), DestReg)
1048 .addReg(ZeroReg).addImm(1)
1049 .addImm(ARMPred).addReg(CondReg);
1051 UpdateValueMap(I, DestReg);
1055 bool ARMFastISel::SelectFPExt(const Instruction *I) {
1056 // Make sure we have VFP and that we're extending float to double.
1057 if (!Subtarget->hasVFP2()) return false;
1059 Value *V = I->getOperand(0);
1060 if (!I->getType()->isDoubleTy() ||
1061 !V->getType()->isFloatTy()) return false;
1063 unsigned Op = getRegForValue(V);
1064 if (Op == 0) return false;
1066 unsigned Result = createResultReg(ARM::DPRRegisterClass);
1067 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1068 TII.get(ARM::VCVTDS), Result)
1070 UpdateValueMap(I, Result);
1074 bool ARMFastISel::SelectFPTrunc(const Instruction *I) {
1075 // Make sure we have VFP and that we're truncating double to float.
1076 if (!Subtarget->hasVFP2()) return false;
1078 Value *V = I->getOperand(0);
1079 if (!(I->getType()->isFloatTy() &&
1080 V->getType()->isDoubleTy())) return false;
1082 unsigned Op = getRegForValue(V);
1083 if (Op == 0) return false;
1085 unsigned Result = createResultReg(ARM::SPRRegisterClass);
1086 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1087 TII.get(ARM::VCVTSD), Result)
1089 UpdateValueMap(I, Result);
1093 bool ARMFastISel::SelectSIToFP(const Instruction *I) {
1094 // Make sure we have VFP.
1095 if (!Subtarget->hasVFP2()) return false;
1098 const Type *Ty = I->getType();
1099 if (!isTypeLegal(Ty, DstVT))
1102 unsigned Op = getRegForValue(I->getOperand(0));
1103 if (Op == 0) return false;
1105 // The conversion routine works on fp-reg to fp-reg and the operand above
1106 // was an integer, move it to the fp registers if possible.
1107 unsigned FP = ARMMoveToFPReg(MVT::f32, Op);
1108 if (FP == 0) return false;
1111 if (Ty->isFloatTy()) Opc = ARM::VSITOS;
1112 else if (Ty->isDoubleTy()) Opc = ARM::VSITOD;
1115 unsigned ResultReg = createResultReg(TLI.getRegClassFor(DstVT));
1116 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc),
1119 UpdateValueMap(I, ResultReg);
1123 bool ARMFastISel::SelectFPToSI(const Instruction *I) {
1124 // Make sure we have VFP.
1125 if (!Subtarget->hasVFP2()) return false;
1128 const Type *RetTy = I->getType();
1129 if (!isTypeLegal(RetTy, DstVT))
1132 unsigned Op = getRegForValue(I->getOperand(0));
1133 if (Op == 0) return false;
1136 const Type *OpTy = I->getOperand(0)->getType();
1137 if (OpTy->isFloatTy()) Opc = ARM::VTOSIZS;
1138 else if (OpTy->isDoubleTy()) Opc = ARM::VTOSIZD;
1141 // f64->s32 or f32->s32 both need an intermediate f32 reg.
1142 unsigned ResultReg = createResultReg(TLI.getRegClassFor(MVT::f32));
1143 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc),
1147 // This result needs to be in an integer register, but the conversion only
1148 // takes place in fp-regs.
1149 unsigned IntReg = ARMMoveToIntReg(DstVT, ResultReg);
1150 if (IntReg == 0) return false;
1152 UpdateValueMap(I, IntReg);
1156 bool ARMFastISel::SelectSelect(const Instruction *I) {
1157 EVT VT = TLI.getValueType(I->getType(), /*HandleUnknown=*/true);
1158 if (VT == MVT::Other || !isTypeLegal(I->getType(), VT))
1161 // Things need to be register sized for register moves.
1162 if (VT.getSimpleVT().SimpleTy != MVT::i32) return false;
1163 const TargetRegisterClass *RC = TLI.getRegClassFor(VT);
1165 unsigned CondReg = getRegForValue(I->getOperand(0));
1166 if (CondReg == 0) return false;
1167 unsigned Op1Reg = getRegForValue(I->getOperand(1));
1168 if (Op1Reg == 0) return false;
1169 unsigned Op2Reg = getRegForValue(I->getOperand(2));
1170 if (Op2Reg == 0) return false;
1172 unsigned CmpOpc = isThumb ? ARM::t2TSTri : ARM::TSTri;
1173 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(CmpOpc))
1174 .addReg(CondReg).addImm(1));
1175 unsigned ResultReg = createResultReg(RC);
1176 unsigned MovCCOpc = isThumb ? ARM::t2MOVCCr : ARM::MOVCCr;
1177 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(MovCCOpc), ResultReg)
1178 .addReg(Op1Reg).addReg(Op2Reg)
1179 .addImm(ARMCC::EQ).addReg(ARM::CPSR);
1180 UpdateValueMap(I, ResultReg);
1184 bool ARMFastISel::SelectSDiv(const Instruction *I) {
1186 const Type *Ty = I->getType();
1187 if (!isTypeLegal(Ty, VT))
1190 // If we have integer div support we should have selected this automagically.
1191 // In case we have a real miss go ahead and return false and we'll pick
1193 if (Subtarget->hasDivide()) return false;
1195 // Otherwise emit a libcall.
1196 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
1198 LC = RTLIB::SDIV_I8;
1199 else if (VT == MVT::i16)
1200 LC = RTLIB::SDIV_I16;
1201 else if (VT == MVT::i32)
1202 LC = RTLIB::SDIV_I32;
1203 else if (VT == MVT::i64)
1204 LC = RTLIB::SDIV_I64;
1205 else if (VT == MVT::i128)
1206 LC = RTLIB::SDIV_I128;
1207 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported SDIV!");
1209 return ARMEmitLibcall(I, LC);
1212 bool ARMFastISel::SelectSRem(const Instruction *I) {
1214 const Type *Ty = I->getType();
1215 if (!isTypeLegal(Ty, VT))
1218 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
1220 LC = RTLIB::SREM_I8;
1221 else if (VT == MVT::i16)
1222 LC = RTLIB::SREM_I16;
1223 else if (VT == MVT::i32)
1224 LC = RTLIB::SREM_I32;
1225 else if (VT == MVT::i64)
1226 LC = RTLIB::SREM_I64;
1227 else if (VT == MVT::i128)
1228 LC = RTLIB::SREM_I128;
1229 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported SREM!");
1231 return ARMEmitLibcall(I, LC);
1234 bool ARMFastISel::SelectBinaryOp(const Instruction *I, unsigned ISDOpcode) {
1235 EVT VT = TLI.getValueType(I->getType(), true);
1237 // We can get here in the case when we want to use NEON for our fp
1238 // operations, but can't figure out how to. Just use the vfp instructions
1240 // FIXME: It'd be nice to use NEON instructions.
1241 const Type *Ty = I->getType();
1242 bool isFloat = (Ty->isDoubleTy() || Ty->isFloatTy());
1243 if (isFloat && !Subtarget->hasVFP2())
1246 unsigned Op1 = getRegForValue(I->getOperand(0));
1247 if (Op1 == 0) return false;
1249 unsigned Op2 = getRegForValue(I->getOperand(1));
1250 if (Op2 == 0) return false;
1253 bool is64bit = VT.getSimpleVT().SimpleTy == MVT::f64 ||
1254 VT.getSimpleVT().SimpleTy == MVT::i64;
1255 switch (ISDOpcode) {
1256 default: return false;
1258 Opc = is64bit ? ARM::VADDD : ARM::VADDS;
1261 Opc = is64bit ? ARM::VSUBD : ARM::VSUBS;
1264 Opc = is64bit ? ARM::VMULD : ARM::VMULS;
1267 unsigned ResultReg = createResultReg(TLI.getRegClassFor(VT));
1268 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1269 TII.get(Opc), ResultReg)
1270 .addReg(Op1).addReg(Op2));
1271 UpdateValueMap(I, ResultReg);
1275 // Call Handling Code
1277 // This is largely taken directly from CCAssignFnForNode - we don't support
1278 // varargs in FastISel so that part has been removed.
1279 // TODO: We may not support all of this.
1280 CCAssignFn *ARMFastISel::CCAssignFnForCall(CallingConv::ID CC, bool Return) {
1283 llvm_unreachable("Unsupported calling convention");
1284 case CallingConv::C:
1285 case CallingConv::Fast:
1286 // Use target triple & subtarget features to do actual dispatch.
1287 if (Subtarget->isAAPCS_ABI()) {
1288 if (Subtarget->hasVFP2() &&
1289 FloatABIType == FloatABI::Hard)
1290 return (Return ? RetCC_ARM_AAPCS_VFP: CC_ARM_AAPCS_VFP);
1292 return (Return ? RetCC_ARM_AAPCS: CC_ARM_AAPCS);
1294 return (Return ? RetCC_ARM_APCS: CC_ARM_APCS);
1295 case CallingConv::ARM_AAPCS_VFP:
1296 return (Return ? RetCC_ARM_AAPCS_VFP: CC_ARM_AAPCS_VFP);
1297 case CallingConv::ARM_AAPCS:
1298 return (Return ? RetCC_ARM_AAPCS: CC_ARM_AAPCS);
1299 case CallingConv::ARM_APCS:
1300 return (Return ? RetCC_ARM_APCS: CC_ARM_APCS);
1304 bool ARMFastISel::ProcessCallArgs(SmallVectorImpl<Value*> &Args,
1305 SmallVectorImpl<unsigned> &ArgRegs,
1306 SmallVectorImpl<EVT> &ArgVTs,
1307 SmallVectorImpl<ISD::ArgFlagsTy> &ArgFlags,
1308 SmallVectorImpl<unsigned> &RegArgs,
1310 unsigned &NumBytes) {
1311 SmallVector<CCValAssign, 16> ArgLocs;
1312 CCState CCInfo(CC, false, TM, ArgLocs, *Context);
1313 CCInfo.AnalyzeCallOperands(ArgVTs, ArgFlags, CCAssignFnForCall(CC, false));
1315 // Get a count of how many bytes are to be pushed on the stack.
1316 NumBytes = CCInfo.getNextStackOffset();
1318 // Issue CALLSEQ_START
1319 unsigned AdjStackDown = TM.getRegisterInfo()->getCallFrameSetupOpcode();
1320 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1321 TII.get(AdjStackDown))
1324 // Process the args.
1325 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1326 CCValAssign &VA = ArgLocs[i];
1327 unsigned Arg = ArgRegs[VA.getValNo()];
1328 EVT ArgVT = ArgVTs[VA.getValNo()];
1330 // Handle arg promotion, etc.
1331 switch (VA.getLocInfo()) {
1332 case CCValAssign::Full: break;
1334 // TODO: Handle arg promotion.
1338 // Now copy/store arg to correct locations.
1339 // TODO: We need custom lowering for f64 args.
1340 if (VA.isRegLoc() && !VA.needsCustom()) {
1341 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY),
1344 RegArgs.push_back(VA.getLocReg());
1354 bool ARMFastISel::FinishCall(EVT RetVT, SmallVectorImpl<unsigned> &UsedRegs,
1355 const Instruction *I, CallingConv::ID CC,
1356 unsigned &NumBytes) {
1357 // Issue CALLSEQ_END
1358 unsigned AdjStackUp = TM.getRegisterInfo()->getCallFrameDestroyOpcode();
1359 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1360 TII.get(AdjStackUp))
1361 .addImm(NumBytes).addImm(0));
1363 // Now the return value.
1364 if (RetVT.getSimpleVT().SimpleTy != MVT::isVoid) {
1365 SmallVector<CCValAssign, 16> RVLocs;
1366 CCState CCInfo(CC, false, TM, RVLocs, *Context);
1367 CCInfo.AnalyzeCallResult(RetVT, CCAssignFnForCall(CC, true));
1369 // Copy all of the result registers out of their specified physreg.
1370 if (RVLocs.size() == 2 && RetVT.getSimpleVT().SimpleTy == MVT::f64) {
1371 // For this move we copy into two registers and then move into the
1372 // double fp reg we want.
1373 // TODO: Are the copies necessary?
1374 TargetRegisterClass *CopyRC = TLI.getRegClassFor(MVT::i32);
1375 unsigned Copy1 = createResultReg(CopyRC);
1376 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY),
1377 Copy1).addReg(RVLocs[0].getLocReg());
1378 UsedRegs.push_back(RVLocs[0].getLocReg());
1380 unsigned Copy2 = createResultReg(CopyRC);
1381 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY),
1382 Copy2).addReg(RVLocs[1].getLocReg());
1383 UsedRegs.push_back(RVLocs[1].getLocReg());
1385 EVT DestVT = RVLocs[0].getValVT();
1386 TargetRegisterClass* DstRC = TLI.getRegClassFor(DestVT);
1387 unsigned ResultReg = createResultReg(DstRC);
1388 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1389 TII.get(ARM::VMOVDRR), ResultReg)
1390 .addReg(Copy1).addReg(Copy2));
1392 // Finally update the result.
1393 UpdateValueMap(I, ResultReg);
1395 assert(RVLocs.size() == 1 &&"Can't handle non-double multi-reg retvals!");
1396 EVT CopyVT = RVLocs[0].getValVT();
1397 TargetRegisterClass* DstRC = TLI.getRegClassFor(CopyVT);
1399 unsigned ResultReg = createResultReg(DstRC);
1400 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY),
1401 ResultReg).addReg(RVLocs[0].getLocReg());
1402 UsedRegs.push_back(RVLocs[0].getLocReg());
1404 // Finally update the result.
1405 UpdateValueMap(I, ResultReg);
1412 // A quick function that will emit a call for a named libcall in F with the
1413 // vector of passed arguments for the Instruction in I. We can assume that we
1414 // can emit a call for any libcall we can produce. This is an abridged version
1415 // of the full call infrastructure since we won't need to worry about things
1416 // like computed function pointers or strange arguments at call sites.
1417 // TODO: Try to unify this and the normal call bits for ARM, then try to unify
1419 bool ARMFastISel::ARMEmitLibcall(const Instruction *I, RTLIB::Libcall Call) {
1420 CallingConv::ID CC = TLI.getLibcallCallingConv(Call);
1422 // Handle *simple* calls for now.
1423 const Type *RetTy = I->getType();
1425 if (RetTy->isVoidTy())
1426 RetVT = MVT::isVoid;
1427 else if (!isTypeLegal(RetTy, RetVT))
1430 // For now we're using BLX etc on the assumption that we have v5t ops.
1431 if (!Subtarget->hasV5TOps()) return false;
1433 // Set up the argument vectors.
1434 SmallVector<Value*, 8> Args;
1435 SmallVector<unsigned, 8> ArgRegs;
1436 SmallVector<EVT, 8> ArgVTs;
1437 SmallVector<ISD::ArgFlagsTy, 8> ArgFlags;
1438 Args.reserve(I->getNumOperands());
1439 ArgRegs.reserve(I->getNumOperands());
1440 ArgVTs.reserve(I->getNumOperands());
1441 ArgFlags.reserve(I->getNumOperands());
1442 for (unsigned i = 0; i < I->getNumOperands(); ++i) {
1443 Value *Op = I->getOperand(i);
1444 unsigned Arg = getRegForValue(Op);
1445 if (Arg == 0) return false;
1447 const Type *ArgTy = Op->getType();
1449 if (!isTypeLegal(ArgTy, ArgVT)) return false;
1451 ISD::ArgFlagsTy Flags;
1452 unsigned OriginalAlignment = TD.getABITypeAlignment(ArgTy);
1453 Flags.setOrigAlign(OriginalAlignment);
1456 ArgRegs.push_back(Arg);
1457 ArgVTs.push_back(ArgVT);
1458 ArgFlags.push_back(Flags);
1461 // Handle the arguments now that we've gotten them.
1462 SmallVector<unsigned, 4> RegArgs;
1464 if (!ProcessCallArgs(Args, ArgRegs, ArgVTs, ArgFlags, RegArgs, CC, NumBytes))
1467 // Issue the call, BLXr9 for darwin, BLX otherwise. This uses V5 ops.
1468 // TODO: Turn this into the table of arm call ops.
1469 MachineInstrBuilder MIB;
1472 CallOpc = Subtarget->isTargetDarwin() ? ARM::tBLXi_r9 : ARM::tBLXi;
1474 CallOpc = Subtarget->isTargetDarwin() ? ARM::BLr9 : ARM::BL;
1475 MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(CallOpc))
1476 .addExternalSymbol(TLI.getLibcallName(Call));
1478 // Add implicit physical register uses to the call.
1479 for (unsigned i = 0, e = RegArgs.size(); i != e; ++i)
1480 MIB.addReg(RegArgs[i]);
1482 // Finish off the call including any return values.
1483 SmallVector<unsigned, 4> UsedRegs;
1484 if (!FinishCall(RetVT, UsedRegs, I, CC, NumBytes)) return false;
1486 // Set all unused physreg defs as dead.
1487 static_cast<MachineInstr *>(MIB)->setPhysRegsDeadExcept(UsedRegs, TRI);
1492 bool ARMFastISel::SelectCall(const Instruction *I) {
1493 const CallInst *CI = cast<CallInst>(I);
1494 const Value *Callee = CI->getCalledValue();
1496 // Can't handle inline asm or worry about intrinsics yet.
1497 if (isa<InlineAsm>(Callee) || isa<IntrinsicInst>(CI)) return false;
1499 // Only handle global variable Callees that are direct calls.
1500 const GlobalValue *GV = dyn_cast<GlobalValue>(Callee);
1501 if (!GV || Subtarget->GVIsIndirectSymbol(GV, TM.getRelocationModel()))
1504 // Check the calling convention.
1505 ImmutableCallSite CS(CI);
1506 CallingConv::ID CC = CS.getCallingConv();
1507 // TODO: Avoid some calling conventions?
1508 if (CC != CallingConv::C) {
1509 // errs() << "Can't handle calling convention: " << CC << "\n";
1513 // Let SDISel handle vararg functions.
1514 const PointerType *PT = cast<PointerType>(CS.getCalledValue()->getType());
1515 const FunctionType *FTy = cast<FunctionType>(PT->getElementType());
1516 if (FTy->isVarArg())
1519 // Handle *simple* calls for now.
1520 const Type *RetTy = I->getType();
1522 if (RetTy->isVoidTy())
1523 RetVT = MVT::isVoid;
1524 else if (!isTypeLegal(RetTy, RetVT))
1527 // For now we're using BLX etc on the assumption that we have v5t ops.
1529 if (!Subtarget->hasV5TOps()) return false;
1531 // Set up the argument vectors.
1532 SmallVector<Value*, 8> Args;
1533 SmallVector<unsigned, 8> ArgRegs;
1534 SmallVector<EVT, 8> ArgVTs;
1535 SmallVector<ISD::ArgFlagsTy, 8> ArgFlags;
1536 Args.reserve(CS.arg_size());
1537 ArgRegs.reserve(CS.arg_size());
1538 ArgVTs.reserve(CS.arg_size());
1539 ArgFlags.reserve(CS.arg_size());
1540 for (ImmutableCallSite::arg_iterator i = CS.arg_begin(), e = CS.arg_end();
1542 unsigned Arg = getRegForValue(*i);
1546 ISD::ArgFlagsTy Flags;
1547 unsigned AttrInd = i - CS.arg_begin() + 1;
1548 if (CS.paramHasAttr(AttrInd, Attribute::SExt))
1550 if (CS.paramHasAttr(AttrInd, Attribute::ZExt))
1553 // FIXME: Only handle *easy* calls for now.
1554 if (CS.paramHasAttr(AttrInd, Attribute::InReg) ||
1555 CS.paramHasAttr(AttrInd, Attribute::StructRet) ||
1556 CS.paramHasAttr(AttrInd, Attribute::Nest) ||
1557 CS.paramHasAttr(AttrInd, Attribute::ByVal))
1560 const Type *ArgTy = (*i)->getType();
1562 if (!isTypeLegal(ArgTy, ArgVT))
1564 unsigned OriginalAlignment = TD.getABITypeAlignment(ArgTy);
1565 Flags.setOrigAlign(OriginalAlignment);
1568 ArgRegs.push_back(Arg);
1569 ArgVTs.push_back(ArgVT);
1570 ArgFlags.push_back(Flags);
1573 // Handle the arguments now that we've gotten them.
1574 SmallVector<unsigned, 4> RegArgs;
1576 if (!ProcessCallArgs(Args, ArgRegs, ArgVTs, ArgFlags, RegArgs, CC, NumBytes))
1579 // Issue the call, BLXr9 for darwin, BLX otherwise. This uses V5 ops.
1580 // TODO: Turn this into the table of arm call ops.
1581 MachineInstrBuilder MIB;
1584 CallOpc = Subtarget->isTargetDarwin() ? ARM::tBLXi_r9 : ARM::tBLXi;
1586 CallOpc = Subtarget->isTargetDarwin() ? ARM::BLr9 : ARM::BL;
1587 MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(CallOpc))
1588 .addGlobalAddress(GV, 0, 0);
1590 // Add implicit physical register uses to the call.
1591 for (unsigned i = 0, e = RegArgs.size(); i != e; ++i)
1592 MIB.addReg(RegArgs[i]);
1594 // Finish off the call including any return values.
1595 SmallVector<unsigned, 4> UsedRegs;
1596 if (!FinishCall(RetVT, UsedRegs, I, CC, NumBytes)) return false;
1598 // Set all unused physreg defs as dead.
1599 static_cast<MachineInstr *>(MIB)->setPhysRegsDeadExcept(UsedRegs, TRI);
1605 // TODO: SoftFP support.
1606 bool ARMFastISel::TargetSelectInstruction(const Instruction *I) {
1607 // No Thumb-1 for now.
1608 if (isThumb && !AFI->isThumb2Function()) return false;
1610 switch (I->getOpcode()) {
1611 case Instruction::Load:
1612 return SelectLoad(I);
1613 case Instruction::Store:
1614 return SelectStore(I);
1615 case Instruction::Br:
1616 return SelectBranch(I);
1617 case Instruction::ICmp:
1618 case Instruction::FCmp:
1619 return SelectCmp(I);
1620 case Instruction::FPExt:
1621 return SelectFPExt(I);
1622 case Instruction::FPTrunc:
1623 return SelectFPTrunc(I);
1624 case Instruction::SIToFP:
1625 return SelectSIToFP(I);
1626 case Instruction::FPToSI:
1627 return SelectFPToSI(I);
1628 case Instruction::FAdd:
1629 return SelectBinaryOp(I, ISD::FADD);
1630 case Instruction::FSub:
1631 return SelectBinaryOp(I, ISD::FSUB);
1632 case Instruction::FMul:
1633 return SelectBinaryOp(I, ISD::FMUL);
1634 case Instruction::SDiv:
1635 return SelectSDiv(I);
1636 case Instruction::SRem:
1637 return SelectSRem(I);
1638 case Instruction::Call:
1639 return SelectCall(I);
1640 case Instruction::Select:
1641 return SelectSelect(I);
1648 llvm::FastISel *ARM::createFastISel(FunctionLoweringInfo &funcInfo) {
1649 // Completely untested on non-darwin.
1650 const TargetMachine &TM = funcInfo.MF->getTarget();
1651 const ARMSubtarget *Subtarget = &TM.getSubtarget<ARMSubtarget>();
1652 if (Subtarget->isTargetDarwin() && EnableARMFastISel)
1653 return new ARMFastISel(funcInfo);