1 //===-- ARMFastISel.cpp - ARM FastISel implementation ---------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the ARM-specific support for the FastISel class. Some
11 // of the target-specific code is generated by tablegen in the file
12 // ARMGenFastISel.inc, which is #included here.
14 //===----------------------------------------------------------------------===//
17 #include "ARMBaseInstrInfo.h"
18 #include "ARMCallingConv.h"
19 #include "ARMRegisterInfo.h"
20 #include "ARMTargetMachine.h"
21 #include "ARMSubtarget.h"
22 #include "ARMConstantPoolValue.h"
23 #include "llvm/CallingConv.h"
24 #include "llvm/DerivedTypes.h"
25 #include "llvm/GlobalVariable.h"
26 #include "llvm/Instructions.h"
27 #include "llvm/IntrinsicInst.h"
28 #include "llvm/Module.h"
29 #include "llvm/CodeGen/Analysis.h"
30 #include "llvm/CodeGen/FastISel.h"
31 #include "llvm/CodeGen/FunctionLoweringInfo.h"
32 #include "llvm/CodeGen/MachineInstrBuilder.h"
33 #include "llvm/CodeGen/MachineModuleInfo.h"
34 #include "llvm/CodeGen/MachineConstantPool.h"
35 #include "llvm/CodeGen/MachineFrameInfo.h"
36 #include "llvm/CodeGen/MachineRegisterInfo.h"
37 #include "llvm/Support/CallSite.h"
38 #include "llvm/Support/CommandLine.h"
39 #include "llvm/Support/ErrorHandling.h"
40 #include "llvm/Support/GetElementPtrTypeIterator.h"
41 #include "llvm/Target/TargetData.h"
42 #include "llvm/Target/TargetInstrInfo.h"
43 #include "llvm/Target/TargetLowering.h"
44 #include "llvm/Target/TargetMachine.h"
45 #include "llvm/Target/TargetOptions.h"
49 EnableARMFastISel("arm-fast-isel",
50 cl::desc("Turn on experimental ARM fast-isel support"),
51 cl::init(false), cl::Hidden);
55 class ARMFastISel : public FastISel {
57 typedef struct AddrBase {
62 /// Subtarget - Keep a pointer to the ARMSubtarget around so that we can
63 /// make the right decision when generating code for different targets.
64 const ARMSubtarget *Subtarget;
65 const TargetMachine &TM;
66 const TargetInstrInfo &TII;
67 const TargetLowering &TLI;
70 // Convenience variables to avoid some queries.
75 explicit ARMFastISel(FunctionLoweringInfo &funcInfo)
77 TM(funcInfo.MF->getTarget()),
78 TII(*TM.getInstrInfo()),
79 TLI(*TM.getTargetLowering()) {
80 Subtarget = &TM.getSubtarget<ARMSubtarget>();
81 AFI = funcInfo.MF->getInfo<ARMFunctionInfo>();
82 isThumb = AFI->isThumbFunction();
83 Context = &funcInfo.Fn->getContext();
86 // Code from FastISel.cpp.
87 virtual unsigned FastEmitInst_(unsigned MachineInstOpcode,
88 const TargetRegisterClass *RC);
89 virtual unsigned FastEmitInst_r(unsigned MachineInstOpcode,
90 const TargetRegisterClass *RC,
91 unsigned Op0, bool Op0IsKill);
92 virtual unsigned FastEmitInst_rr(unsigned MachineInstOpcode,
93 const TargetRegisterClass *RC,
94 unsigned Op0, bool Op0IsKill,
95 unsigned Op1, bool Op1IsKill);
96 virtual unsigned FastEmitInst_ri(unsigned MachineInstOpcode,
97 const TargetRegisterClass *RC,
98 unsigned Op0, bool Op0IsKill,
100 virtual unsigned FastEmitInst_rf(unsigned MachineInstOpcode,
101 const TargetRegisterClass *RC,
102 unsigned Op0, bool Op0IsKill,
103 const ConstantFP *FPImm);
104 virtual unsigned FastEmitInst_i(unsigned MachineInstOpcode,
105 const TargetRegisterClass *RC,
107 virtual unsigned FastEmitInst_rri(unsigned MachineInstOpcode,
108 const TargetRegisterClass *RC,
109 unsigned Op0, bool Op0IsKill,
110 unsigned Op1, bool Op1IsKill,
112 virtual unsigned FastEmitInst_extractsubreg(MVT RetVT,
113 unsigned Op0, bool Op0IsKill,
116 // Backend specific FastISel code.
117 virtual bool TargetSelectInstruction(const Instruction *I);
118 virtual unsigned TargetMaterializeConstant(const Constant *C);
119 virtual unsigned TargetMaterializeAlloca(const AllocaInst *AI);
121 #include "ARMGenFastISel.inc"
123 // Instruction selection routines.
125 virtual bool SelectLoad(const Instruction *I);
126 virtual bool SelectStore(const Instruction *I);
127 virtual bool SelectBranch(const Instruction *I);
128 virtual bool SelectCmp(const Instruction *I);
129 virtual bool SelectFPExt(const Instruction *I);
130 virtual bool SelectFPTrunc(const Instruction *I);
131 virtual bool SelectBinaryOp(const Instruction *I, unsigned ISDOpcode);
132 virtual bool SelectSIToFP(const Instruction *I);
133 virtual bool SelectFPToSI(const Instruction *I);
134 virtual bool SelectSDiv(const Instruction *I);
135 virtual bool SelectSRem(const Instruction *I);
136 virtual bool SelectCall(const Instruction *I);
137 virtual bool SelectSelect(const Instruction *I);
141 bool isTypeLegal(const Type *Ty, EVT &VT);
142 bool isLoadTypeLegal(const Type *Ty, EVT &VT);
143 bool ARMEmitLoad(EVT VT, unsigned &ResultReg, AddrBase Base, int Offset);
144 bool ARMEmitStore(EVT VT, unsigned SrcReg, AddrBase Base, int Offset);
145 bool ARMComputeRegOffset(const Value *Obj, AddrBase &Base, int &Offset);
146 void ARMSimplifyRegOffset(AddrBase &Base, int &Offset, EVT VT);
147 unsigned ARMMaterializeFP(const ConstantFP *CFP, EVT VT);
148 unsigned ARMMaterializeInt(const Constant *C, EVT VT);
149 unsigned ARMMaterializeGV(const GlobalValue *GV, EVT VT);
150 unsigned ARMMoveToFPReg(EVT VT, unsigned SrcReg);
151 unsigned ARMMoveToIntReg(EVT VT, unsigned SrcReg);
153 // Call handling routines.
155 CCAssignFn *CCAssignFnForCall(CallingConv::ID CC, bool Return);
156 bool ProcessCallArgs(SmallVectorImpl<Value*> &Args,
157 SmallVectorImpl<unsigned> &ArgRegs,
158 SmallVectorImpl<EVT> &ArgVTs,
159 SmallVectorImpl<ISD::ArgFlagsTy> &ArgFlags,
160 SmallVectorImpl<unsigned> &RegArgs,
163 bool FinishCall(EVT RetVT, SmallVectorImpl<unsigned> &UsedRegs,
164 const Instruction *I, CallingConv::ID CC,
166 bool ARMEmitLibcall(const Instruction *I, RTLIB::Libcall Call);
168 // OptionalDef handling routines.
170 bool DefinesOptionalPredicate(MachineInstr *MI, bool *CPSR);
171 const MachineInstrBuilder &AddOptionalDefs(const MachineInstrBuilder &MIB);
174 } // end anonymous namespace
176 #include "ARMGenCallingConv.inc"
178 // DefinesOptionalPredicate - This is different from DefinesPredicate in that
179 // we don't care about implicit defs here, just places we'll need to add a
180 // default CCReg argument. Sets CPSR if we're setting CPSR instead of CCR.
181 bool ARMFastISel::DefinesOptionalPredicate(MachineInstr *MI, bool *CPSR) {
182 const TargetInstrDesc &TID = MI->getDesc();
183 if (!TID.hasOptionalDef())
186 // Look to see if our OptionalDef is defining CPSR or CCR.
187 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
188 const MachineOperand &MO = MI->getOperand(i);
189 if (!MO.isReg() || !MO.isDef()) continue;
190 if (MO.getReg() == ARM::CPSR)
196 // If the machine is predicable go ahead and add the predicate operands, if
197 // it needs default CC operands add those.
198 const MachineInstrBuilder &
199 ARMFastISel::AddOptionalDefs(const MachineInstrBuilder &MIB) {
200 MachineInstr *MI = &*MIB;
202 // Do we use a predicate?
203 if (TII.isPredicable(MI))
206 // Do we optionally set a predicate? Preds is size > 0 iff the predicate
207 // defines CPSR. All other OptionalDefines in ARM are the CCR register.
209 if (DefinesOptionalPredicate(MI, &CPSR)) {
218 unsigned ARMFastISel::FastEmitInst_(unsigned MachineInstOpcode,
219 const TargetRegisterClass* RC) {
220 unsigned ResultReg = createResultReg(RC);
221 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
223 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg));
227 unsigned ARMFastISel::FastEmitInst_r(unsigned MachineInstOpcode,
228 const TargetRegisterClass *RC,
229 unsigned Op0, bool Op0IsKill) {
230 unsigned ResultReg = createResultReg(RC);
231 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
233 if (II.getNumDefs() >= 1)
234 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
235 .addReg(Op0, Op0IsKill * RegState::Kill));
237 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
238 .addReg(Op0, Op0IsKill * RegState::Kill));
239 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
240 TII.get(TargetOpcode::COPY), ResultReg)
241 .addReg(II.ImplicitDefs[0]));
246 unsigned ARMFastISel::FastEmitInst_rr(unsigned MachineInstOpcode,
247 const TargetRegisterClass *RC,
248 unsigned Op0, bool Op0IsKill,
249 unsigned Op1, bool Op1IsKill) {
250 unsigned ResultReg = createResultReg(RC);
251 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
253 if (II.getNumDefs() >= 1)
254 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
255 .addReg(Op0, Op0IsKill * RegState::Kill)
256 .addReg(Op1, Op1IsKill * RegState::Kill));
258 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
259 .addReg(Op0, Op0IsKill * RegState::Kill)
260 .addReg(Op1, Op1IsKill * RegState::Kill));
261 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
262 TII.get(TargetOpcode::COPY), ResultReg)
263 .addReg(II.ImplicitDefs[0]));
268 unsigned ARMFastISel::FastEmitInst_ri(unsigned MachineInstOpcode,
269 const TargetRegisterClass *RC,
270 unsigned Op0, bool Op0IsKill,
272 unsigned ResultReg = createResultReg(RC);
273 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
275 if (II.getNumDefs() >= 1)
276 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
277 .addReg(Op0, Op0IsKill * RegState::Kill)
280 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
281 .addReg(Op0, Op0IsKill * RegState::Kill)
283 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
284 TII.get(TargetOpcode::COPY), ResultReg)
285 .addReg(II.ImplicitDefs[0]));
290 unsigned ARMFastISel::FastEmitInst_rf(unsigned MachineInstOpcode,
291 const TargetRegisterClass *RC,
292 unsigned Op0, bool Op0IsKill,
293 const ConstantFP *FPImm) {
294 unsigned ResultReg = createResultReg(RC);
295 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
297 if (II.getNumDefs() >= 1)
298 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
299 .addReg(Op0, Op0IsKill * RegState::Kill)
302 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
303 .addReg(Op0, Op0IsKill * RegState::Kill)
305 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
306 TII.get(TargetOpcode::COPY), ResultReg)
307 .addReg(II.ImplicitDefs[0]));
312 unsigned ARMFastISel::FastEmitInst_rri(unsigned MachineInstOpcode,
313 const TargetRegisterClass *RC,
314 unsigned Op0, bool Op0IsKill,
315 unsigned Op1, bool Op1IsKill,
317 unsigned ResultReg = createResultReg(RC);
318 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
320 if (II.getNumDefs() >= 1)
321 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
322 .addReg(Op0, Op0IsKill * RegState::Kill)
323 .addReg(Op1, Op1IsKill * RegState::Kill)
326 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
327 .addReg(Op0, Op0IsKill * RegState::Kill)
328 .addReg(Op1, Op1IsKill * RegState::Kill)
330 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
331 TII.get(TargetOpcode::COPY), ResultReg)
332 .addReg(II.ImplicitDefs[0]));
337 unsigned ARMFastISel::FastEmitInst_i(unsigned MachineInstOpcode,
338 const TargetRegisterClass *RC,
340 unsigned ResultReg = createResultReg(RC);
341 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
343 if (II.getNumDefs() >= 1)
344 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
347 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
349 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
350 TII.get(TargetOpcode::COPY), ResultReg)
351 .addReg(II.ImplicitDefs[0]));
356 unsigned ARMFastISel::FastEmitInst_extractsubreg(MVT RetVT,
357 unsigned Op0, bool Op0IsKill,
359 unsigned ResultReg = createResultReg(TLI.getRegClassFor(RetVT));
360 assert(TargetRegisterInfo::isVirtualRegister(Op0) &&
361 "Cannot yet extract from physregs");
362 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt,
363 DL, TII.get(TargetOpcode::COPY), ResultReg)
364 .addReg(Op0, getKillRegState(Op0IsKill), Idx));
368 // TODO: Don't worry about 64-bit now, but when this is fixed remove the
369 // checks from the various callers.
370 unsigned ARMFastISel::ARMMoveToFPReg(EVT VT, unsigned SrcReg) {
371 if (VT.getSimpleVT().SimpleTy == MVT::f64) return 0;
373 unsigned MoveReg = createResultReg(TLI.getRegClassFor(VT));
374 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
375 TII.get(ARM::VMOVRS), MoveReg)
380 unsigned ARMFastISel::ARMMoveToIntReg(EVT VT, unsigned SrcReg) {
381 if (VT.getSimpleVT().SimpleTy == MVT::i64) return 0;
383 unsigned MoveReg = createResultReg(TLI.getRegClassFor(VT));
384 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
385 TII.get(ARM::VMOVSR), MoveReg)
390 // For double width floating point we need to materialize two constants
391 // (the high and the low) into integer registers then use a move to get
392 // the combined constant into an FP reg.
393 unsigned ARMFastISel::ARMMaterializeFP(const ConstantFP *CFP, EVT VT) {
394 const APFloat Val = CFP->getValueAPF();
395 bool is64bit = VT.getSimpleVT().SimpleTy == MVT::f64;
397 // This checks to see if we can use VFP3 instructions to materialize
398 // a constant, otherwise we have to go through the constant pool.
399 if (TLI.isFPImmLegal(Val, VT)) {
400 unsigned Opc = is64bit ? ARM::FCONSTD : ARM::FCONSTS;
401 unsigned DestReg = createResultReg(TLI.getRegClassFor(VT));
402 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc),
408 // Require VFP2 for loading fp constants.
409 if (!Subtarget->hasVFP2()) return false;
411 // MachineConstantPool wants an explicit alignment.
412 unsigned Align = TD.getPrefTypeAlignment(CFP->getType());
414 // TODO: Figure out if this is correct.
415 Align = TD.getTypeAllocSize(CFP->getType());
417 unsigned Idx = MCP.getConstantPoolIndex(cast<Constant>(CFP), Align);
418 unsigned DestReg = createResultReg(TLI.getRegClassFor(VT));
419 unsigned Opc = is64bit ? ARM::VLDRD : ARM::VLDRS;
421 // The extra reg is for addrmode5.
422 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc),
424 .addConstantPoolIndex(Idx)
429 unsigned ARMFastISel::ARMMaterializeInt(const Constant *C, EVT VT) {
431 // For now 32-bit only.
432 if (VT.getSimpleVT().SimpleTy != MVT::i32) return false;
434 // MachineConstantPool wants an explicit alignment.
435 unsigned Align = TD.getPrefTypeAlignment(C->getType());
437 // TODO: Figure out if this is correct.
438 Align = TD.getTypeAllocSize(C->getType());
440 unsigned Idx = MCP.getConstantPoolIndex(C, Align);
441 unsigned DestReg = createResultReg(TLI.getRegClassFor(VT));
444 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
445 TII.get(ARM::t2LDRpci), DestReg)
446 .addConstantPoolIndex(Idx));
448 // The extra reg and immediate are for addrmode2.
449 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
450 TII.get(ARM::LDRcp), DestReg)
451 .addConstantPoolIndex(Idx)
452 .addReg(0).addImm(0));
457 unsigned ARMFastISel::ARMMaterializeGV(const GlobalValue *GV, EVT VT) {
458 // For now 32-bit only.
459 if (VT.getSimpleVT().SimpleTy != MVT::i32) return 0;
461 Reloc::Model RelocM = TM.getRelocationModel();
463 // TODO: No external globals for now.
464 if (Subtarget->GVIsIndirectSymbol(GV, RelocM)) return 0;
466 // TODO: Need more magic for ARM PIC.
467 if (!isThumb && (RelocM == Reloc::PIC_)) return 0;
469 // MachineConstantPool wants an explicit alignment.
470 unsigned Align = TD.getPrefTypeAlignment(GV->getType());
472 // TODO: Figure out if this is correct.
473 Align = TD.getTypeAllocSize(GV->getType());
477 unsigned PCAdj = (RelocM != Reloc::PIC_) ? 0 : (Subtarget->isThumb() ? 4 : 8);
478 unsigned Id = AFI->createConstPoolEntryUId();
479 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(GV, Id,
480 ARMCP::CPValue, PCAdj);
481 unsigned Idx = MCP.getConstantPoolIndex(CPV, Align);
484 MachineInstrBuilder MIB;
485 unsigned DestReg = createResultReg(TLI.getRegClassFor(VT));
487 unsigned Opc = (RelocM != Reloc::PIC_) ? ARM::t2LDRpci : ARM::t2LDRpci_pic;
488 MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc), DestReg)
489 .addConstantPoolIndex(Idx);
490 if (RelocM == Reloc::PIC_)
493 // The extra reg and immediate are for addrmode2.
494 MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(ARM::LDRcp),
496 .addConstantPoolIndex(Idx)
497 .addReg(0).addImm(0);
499 AddOptionalDefs(MIB);
503 unsigned ARMFastISel::TargetMaterializeConstant(const Constant *C) {
504 EVT VT = TLI.getValueType(C->getType(), true);
506 // Only handle simple types.
507 if (!VT.isSimple()) return 0;
509 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(C))
510 return ARMMaterializeFP(CFP, VT);
511 else if (const GlobalValue *GV = dyn_cast<GlobalValue>(C))
512 return ARMMaterializeGV(GV, VT);
513 else if (isa<ConstantInt>(C))
514 return ARMMaterializeInt(C, VT);
519 unsigned ARMFastISel::TargetMaterializeAlloca(const AllocaInst *AI) {
520 // Don't handle dynamic allocas.
521 if (!FuncInfo.StaticAllocaMap.count(AI)) return 0;
524 if (!isTypeLegal(AI->getType(), VT)) return false;
526 DenseMap<const AllocaInst*, int>::iterator SI =
527 FuncInfo.StaticAllocaMap.find(AI);
529 // This will get lowered later into the correct offsets and registers
530 // via rewriteXFrameIndex.
531 if (SI != FuncInfo.StaticAllocaMap.end()) {
532 TargetRegisterClass* RC = TLI.getRegClassFor(VT);
533 unsigned ResultReg = createResultReg(RC);
534 unsigned Opc = isThumb ? ARM::t2ADDri : ARM::ADDri;
535 AddOptionalDefs(BuildMI(*FuncInfo.MBB, *FuncInfo.InsertPt, DL,
536 TII.get(Opc), ResultReg)
537 .addFrameIndex(SI->second)
545 bool ARMFastISel::isTypeLegal(const Type *Ty, EVT &VT) {
546 VT = TLI.getValueType(Ty, true);
548 // Only handle simple types.
549 if (VT == MVT::Other || !VT.isSimple()) return false;
551 // Handle all legal types, i.e. a register that will directly hold this
553 return TLI.isTypeLegal(VT);
556 bool ARMFastISel::isLoadTypeLegal(const Type *Ty, EVT &VT) {
557 if (isTypeLegal(Ty, VT)) return true;
559 // If this is a type than can be sign or zero-extended to a basic operation
560 // go ahead and accept it now.
561 if (VT == MVT::i8 || VT == MVT::i16)
567 // Computes the Reg+Offset to get to an object.
568 bool ARMFastISel::ARMComputeRegOffset(const Value *Obj, AddrBase &Base,
570 // Some boilerplate from the X86 FastISel.
571 const User *U = NULL;
572 unsigned Opcode = Instruction::UserOp1;
573 if (const Instruction *I = dyn_cast<Instruction>(Obj)) {
574 // Don't walk into other basic blocks; it's possible we haven't
575 // visited them yet, so the instructions may not yet be assigned
576 // virtual registers.
577 if (FuncInfo.MBBMap[I->getParent()] != FuncInfo.MBB)
579 Opcode = I->getOpcode();
581 } else if (const ConstantExpr *C = dyn_cast<ConstantExpr>(Obj)) {
582 Opcode = C->getOpcode();
586 if (const PointerType *Ty = dyn_cast<PointerType>(Obj->getType()))
587 if (Ty->getAddressSpace() > 255)
588 // Fast instruction selection doesn't support the special
595 case Instruction::BitCast: {
596 // Look through bitcasts.
597 return ARMComputeRegOffset(U->getOperand(0), Base, Offset);
599 case Instruction::IntToPtr: {
600 // Look past no-op inttoptrs.
601 if (TLI.getValueType(U->getOperand(0)->getType()) == TLI.getPointerTy())
602 return ARMComputeRegOffset(U->getOperand(0), Base, Offset);
605 case Instruction::PtrToInt: {
606 // Look past no-op ptrtoints.
607 if (TLI.getValueType(U->getType()) == TLI.getPointerTy())
608 return ARMComputeRegOffset(U->getOperand(0), Base, Offset);
611 case Instruction::GetElementPtr: {
612 int SavedOffset = Offset;
613 AddrBase SavedBase = Base;
614 int TmpOffset = Offset;
616 // Iterate through the GEP folding the constants into offsets where
618 gep_type_iterator GTI = gep_type_begin(U);
619 for (User::const_op_iterator i = U->op_begin() + 1, e = U->op_end();
620 i != e; ++i, ++GTI) {
621 const Value *Op = *i;
622 if (const StructType *STy = dyn_cast<StructType>(*GTI)) {
623 const StructLayout *SL = TD.getStructLayout(STy);
624 unsigned Idx = cast<ConstantInt>(Op)->getZExtValue();
625 TmpOffset += SL->getElementOffset(Idx);
627 uint64_t S = TD.getTypeAllocSize(GTI.getIndexedType());
628 SmallVector<const Value *, 4> Worklist;
629 Worklist.push_back(Op);
631 Op = Worklist.pop_back_val();
632 if (const ConstantInt *CI = dyn_cast<ConstantInt>(Op)) {
633 // Constant-offset addressing.
634 TmpOffset += CI->getSExtValue() * S;
635 } else if (0 && isa<AddOperator>(Op) &&
636 isa<ConstantInt>(cast<AddOperator>(Op)->getOperand(1))) {
637 // An add with a constant operand. Fold the constant.
639 cast<ConstantInt>(cast<AddOperator>(Op)->getOperand(1));
640 TmpOffset += CI->getSExtValue() * S;
641 // Add the other operand back to the work list.
642 Worklist.push_back(cast<AddOperator>(Op)->getOperand(0));
644 goto unsupported_gep;
645 } while (!Worklist.empty());
649 // Try to grab the base operand now.
651 if (ARMComputeRegOffset(U->getOperand(0), Base, Offset)) return true;
653 // We failed, restore everything and try the other options.
654 Offset = SavedOffset;
660 case Instruction::Alloca: {
661 // TODO: Fix this to do intermediate loads, etc.
662 if (Offset != 0) return false;
664 const AllocaInst *AI = cast<AllocaInst>(Obj);
665 DenseMap<const AllocaInst*, int>::iterator SI =
666 FuncInfo.StaticAllocaMap.find(AI);
667 if (SI != FuncInfo.StaticAllocaMap.end()) {
669 Base.FrameIndex = SI->second;
672 // Don't handle dynamic allocas.
673 assert(!FuncInfo.StaticAllocaMap.count(cast<AllocaInst>(Obj)) &&
674 "Alloca should have been handled earlier!");
679 // Materialize the global variable's address into a reg which can
680 // then be used later to load the variable.
681 if (const GlobalValue *GV = dyn_cast<GlobalValue>(Obj)) {
682 unsigned Tmp = ARMMaterializeGV(GV, TLI.getValueType(Obj->getType()));
683 if (Tmp == 0) return false;
689 // Try to get this in a register if nothing else has worked.
690 if (Base.Reg == 0) Base.Reg = getRegForValue(Obj);
691 return Base.Reg != 0;
694 void ARMFastISel::ARMSimplifyRegOffset(AddrBase &Base, int &Offset, EVT VT) {
696 // Since the offset may be too large for the load instruction
697 // get the reg+offset into a register.
698 if (Base.Reg != ARM::SP && Offset != 0) {
699 ARMCC::CondCodes Pred = ARMCC::AL;
700 unsigned PredReg = 0;
702 TargetRegisterClass *RC = isThumb ? ARM::tGPRRegisterClass :
703 ARM::GPRRegisterClass;
704 unsigned BaseReg = createResultReg(RC);
707 emitARMRegPlusImmediate(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
708 BaseReg, Base.Reg, Offset, Pred, PredReg,
709 static_cast<const ARMBaseInstrInfo&>(TII));
711 assert(AFI->isThumb2Function());
712 emitT2RegPlusImmediate(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
713 BaseReg, Base.Reg, Offset, Pred, PredReg,
714 static_cast<const ARMBaseInstrInfo&>(TII));
721 bool ARMFastISel::ARMEmitLoad(EVT VT, unsigned &ResultReg,
722 AddrBase Base, int Offset) {
724 assert(VT.isSimple() && "Non-simple types are invalid here!");
726 TargetRegisterClass *RC;
727 bool isFloat = false;
728 switch (VT.getSimpleVT().SimpleTy) {
730 // This is mostly going to be Neon/vector support.
733 Opc = isThumb ? ARM::t2LDRHi8 : ARM::LDRH;
734 RC = ARM::GPRRegisterClass;
738 Opc = isThumb ? ARM::t2LDRBi8 : ARM::LDRB;
739 RC = ARM::GPRRegisterClass;
743 Opc = isThumb ? ARM::t2LDRi8 : ARM::LDR;
744 RC = ARM::GPRRegisterClass;
748 RC = TLI.getRegClassFor(VT);
753 RC = TLI.getRegClassFor(VT);
758 ResultReg = createResultReg(RC);
760 // For now with the additions above the offset should be zero - thus we
761 // can always fit into an i8.
762 assert((Base.Reg == ARM::SP || Offset == 0) &&
763 "Offset not zero and not a stack load!");
765 if (Base.Reg == ARM::SP && Offset == 0)
766 TII.loadRegFromStackSlot(*FuncInfo.MBB, *FuncInfo.InsertPt,
767 ResultReg, Base.FrameIndex, RC,
768 TM.getRegisterInfo());
769 // The thumb and floating point instructions both take 2 operands, ARM takes
771 else if (isFloat || isThumb)
772 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
773 TII.get(Opc), ResultReg)
774 .addReg(Base.Reg).addImm(Offset));
776 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
777 TII.get(Opc), ResultReg)
778 .addReg(Base.Reg).addReg(0).addImm(Offset));
782 bool ARMFastISel::SelectLoad(const Instruction *I) {
783 // Verify we have a legal type before going any further.
785 if (!isLoadTypeLegal(I->getType(), VT))
788 // Our register and offset with innocuous defaults.
789 AddrBase Base = { 0, 0 };
792 // See if we can handle this as Reg + Offset
793 if (!ARMComputeRegOffset(I->getOperand(0), Base, Offset))
796 ARMSimplifyRegOffset(Base, Offset, VT);
799 if (!ARMEmitLoad(VT, ResultReg, Base, Offset)) return false;
801 UpdateValueMap(I, ResultReg);
805 bool ARMFastISel::ARMEmitStore(EVT VT, unsigned SrcReg,
806 AddrBase Base, int Offset) {
808 bool isFloat = false;
809 // VT is set here only for use in the alloca stores below - those are promoted
810 // to reg size always.
811 switch (VT.getSimpleVT().SimpleTy) {
812 default: return false;
816 StrOpc = isThumb ? ARM::t2STRBi8 : ARM::STRB;
820 StrOpc = isThumb ? ARM::t2STRHi8 : ARM::STRH;
822 case MVT::i32: StrOpc = isThumb ? ARM::t2STRi8 : ARM::STR; break;
824 if (!Subtarget->hasVFP2()) return false;
829 if (!Subtarget->hasVFP2()) return false;
835 if (Base.Reg == ARM::SP && Offset == 0)
836 TII.storeRegToStackSlot(*FuncInfo.MBB, *FuncInfo.InsertPt,
837 SrcReg, true /*isKill*/, Base.FrameIndex,
838 TLI.getRegClassFor(VT), TM.getRegisterInfo());
839 // The thumb addressing mode has operands swapped from the arm addressing
840 // mode, the floating point one only has two operands.
841 else if (isFloat || isThumb)
842 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
844 .addReg(SrcReg).addReg(Base.Reg).addImm(Offset));
846 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
848 .addReg(SrcReg).addReg(Base.Reg).addReg(0).addImm(Offset));
853 bool ARMFastISel::SelectStore(const Instruction *I) {
854 Value *Op0 = I->getOperand(0);
857 // Yay type legalization
859 if (!isLoadTypeLegal(I->getOperand(0)->getType(), VT))
862 // Get the value to be stored into a register.
863 SrcReg = getRegForValue(Op0);
867 // Our register and offset with innocuous defaults.
868 AddrBase Base = { 0, 0 };
871 // See if we can handle this as Reg + Offset
872 if (!ARMComputeRegOffset(I->getOperand(1), Base, Offset))
875 ARMSimplifyRegOffset(Base, Offset, VT);
877 if (!ARMEmitStore(VT, SrcReg, Base, Offset)) return false;
882 static ARMCC::CondCodes getComparePred(CmpInst::Predicate Pred) {
884 // Needs two compares...
885 case CmpInst::FCMP_ONE:
886 case CmpInst::FCMP_UEQ:
888 assert(false && "Unhandled CmpInst::Predicate!");
890 case CmpInst::ICMP_EQ:
891 case CmpInst::FCMP_OEQ:
893 case CmpInst::ICMP_SGT:
894 case CmpInst::FCMP_OGT:
896 case CmpInst::ICMP_SGE:
897 case CmpInst::FCMP_OGE:
899 case CmpInst::ICMP_UGT:
900 case CmpInst::FCMP_UGT:
902 case CmpInst::FCMP_OLT:
904 case CmpInst::ICMP_ULE:
905 case CmpInst::FCMP_OLE:
907 case CmpInst::FCMP_ORD:
909 case CmpInst::FCMP_UNO:
911 case CmpInst::FCMP_UGE:
913 case CmpInst::ICMP_SLT:
914 case CmpInst::FCMP_ULT:
916 case CmpInst::ICMP_SLE:
917 case CmpInst::FCMP_ULE:
919 case CmpInst::FCMP_UNE:
920 case CmpInst::ICMP_NE:
922 case CmpInst::ICMP_UGE:
924 case CmpInst::ICMP_ULT:
929 bool ARMFastISel::SelectBranch(const Instruction *I) {
930 const BranchInst *BI = cast<BranchInst>(I);
931 MachineBasicBlock *TBB = FuncInfo.MBBMap[BI->getSuccessor(0)];
932 MachineBasicBlock *FBB = FuncInfo.MBBMap[BI->getSuccessor(1)];
934 // Simple branch support.
935 // TODO: Try to avoid the re-computation in some places.
936 unsigned CondReg = getRegForValue(BI->getCondition());
937 if (CondReg == 0) return false;
939 // Re-set the flags just in case.
940 unsigned CmpOpc = isThumb ? ARM::t2CMPri : ARM::CMPri;
941 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(CmpOpc))
942 .addReg(CondReg).addImm(1));
944 unsigned BrOpc = isThumb ? ARM::t2Bcc : ARM::Bcc;
945 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(BrOpc))
946 .addMBB(TBB).addImm(ARMCC::EQ).addReg(ARM::CPSR);
947 FastEmitBranch(FBB, DL);
948 FuncInfo.MBB->addSuccessor(TBB);
952 bool ARMFastISel::SelectCmp(const Instruction *I) {
953 const CmpInst *CI = cast<CmpInst>(I);
956 const Type *Ty = CI->getOperand(0)->getType();
957 if (!isTypeLegal(Ty, VT))
960 bool isFloat = (Ty->isDoubleTy() || Ty->isFloatTy());
961 if (isFloat && !Subtarget->hasVFP2())
966 switch (VT.getSimpleVT().SimpleTy) {
967 default: return false;
968 // TODO: Verify compares.
970 CmpOpc = ARM::VCMPES;
971 CondReg = ARM::FPSCR;
974 CmpOpc = ARM::VCMPED;
975 CondReg = ARM::FPSCR;
978 CmpOpc = isThumb ? ARM::t2CMPrr : ARM::CMPrr;
983 // Get the compare predicate.
984 ARMCC::CondCodes ARMPred = getComparePred(CI->getPredicate());
986 // We may not handle every CC for now.
987 if (ARMPred == ARMCC::AL) return false;
989 unsigned Arg1 = getRegForValue(CI->getOperand(0));
990 if (Arg1 == 0) return false;
992 unsigned Arg2 = getRegForValue(CI->getOperand(1));
993 if (Arg2 == 0) return false;
995 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(CmpOpc))
996 .addReg(Arg1).addReg(Arg2));
998 // For floating point we need to move the result to a comparison register
999 // that we can then use for branches.
1001 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1002 TII.get(ARM::FMSTAT)));
1004 // Now set a register based on the comparison. Explicitly set the predicates
1006 unsigned MovCCOpc = isThumb ? ARM::t2MOVCCi : ARM::MOVCCi;
1007 TargetRegisterClass *RC = isThumb ? ARM::rGPRRegisterClass
1008 : ARM::GPRRegisterClass;
1009 unsigned DestReg = createResultReg(RC);
1011 = ConstantInt::get(Type::getInt32Ty(*Context), 0);
1012 unsigned ZeroReg = TargetMaterializeConstant(Zero);
1013 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(MovCCOpc), DestReg)
1014 .addReg(ZeroReg).addImm(1)
1015 .addImm(ARMPred).addReg(CondReg);
1017 UpdateValueMap(I, DestReg);
1021 bool ARMFastISel::SelectFPExt(const Instruction *I) {
1022 // Make sure we have VFP and that we're extending float to double.
1023 if (!Subtarget->hasVFP2()) return false;
1025 Value *V = I->getOperand(0);
1026 if (!I->getType()->isDoubleTy() ||
1027 !V->getType()->isFloatTy()) return false;
1029 unsigned Op = getRegForValue(V);
1030 if (Op == 0) return false;
1032 unsigned Result = createResultReg(ARM::DPRRegisterClass);
1033 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1034 TII.get(ARM::VCVTDS), Result)
1036 UpdateValueMap(I, Result);
1040 bool ARMFastISel::SelectFPTrunc(const Instruction *I) {
1041 // Make sure we have VFP and that we're truncating double to float.
1042 if (!Subtarget->hasVFP2()) return false;
1044 Value *V = I->getOperand(0);
1045 if (!(I->getType()->isFloatTy() &&
1046 V->getType()->isDoubleTy())) return false;
1048 unsigned Op = getRegForValue(V);
1049 if (Op == 0) return false;
1051 unsigned Result = createResultReg(ARM::SPRRegisterClass);
1052 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1053 TII.get(ARM::VCVTSD), Result)
1055 UpdateValueMap(I, Result);
1059 bool ARMFastISel::SelectSIToFP(const Instruction *I) {
1060 // Make sure we have VFP.
1061 if (!Subtarget->hasVFP2()) return false;
1064 const Type *Ty = I->getType();
1065 if (!isTypeLegal(Ty, DstVT))
1068 unsigned Op = getRegForValue(I->getOperand(0));
1069 if (Op == 0) return false;
1071 // The conversion routine works on fp-reg to fp-reg and the operand above
1072 // was an integer, move it to the fp registers if possible.
1073 unsigned FP = ARMMoveToFPReg(MVT::f32, Op);
1074 if (FP == 0) return false;
1077 if (Ty->isFloatTy()) Opc = ARM::VSITOS;
1078 else if (Ty->isDoubleTy()) Opc = ARM::VSITOD;
1081 unsigned ResultReg = createResultReg(TLI.getRegClassFor(DstVT));
1082 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc),
1085 UpdateValueMap(I, ResultReg);
1089 bool ARMFastISel::SelectFPToSI(const Instruction *I) {
1090 // Make sure we have VFP.
1091 if (!Subtarget->hasVFP2()) return false;
1094 const Type *RetTy = I->getType();
1095 if (!isTypeLegal(RetTy, DstVT))
1098 unsigned Op = getRegForValue(I->getOperand(0));
1099 if (Op == 0) return false;
1102 const Type *OpTy = I->getOperand(0)->getType();
1103 if (OpTy->isFloatTy()) Opc = ARM::VTOSIZS;
1104 else if (OpTy->isDoubleTy()) Opc = ARM::VTOSIZD;
1107 // f64->s32 or f32->s32 both need an intermediate f32 reg.
1108 unsigned ResultReg = createResultReg(TLI.getRegClassFor(MVT::f32));
1109 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc),
1113 // This result needs to be in an integer register, but the conversion only
1114 // takes place in fp-regs.
1115 unsigned IntReg = ARMMoveToIntReg(DstVT, ResultReg);
1116 if (IntReg == 0) return false;
1118 UpdateValueMap(I, IntReg);
1122 bool ARMFastISel::SelectSelect(const Instruction *I) {
1123 EVT VT = TLI.getValueType(I->getType(), /*HandleUnknown=*/true);
1124 if (VT == MVT::Other || !isTypeLegal(I->getType(), VT))
1127 // Things need to be register sized for register moves.
1128 if (VT.getSimpleVT().SimpleTy != MVT::i32) return false;
1129 const TargetRegisterClass *RC = TLI.getRegClassFor(VT);
1131 unsigned CondReg = getRegForValue(I->getOperand(0));
1132 if (CondReg == 0) return false;
1133 unsigned Op1Reg = getRegForValue(I->getOperand(1));
1134 if (Op1Reg == 0) return false;
1135 unsigned Op2Reg = getRegForValue(I->getOperand(2));
1136 if (Op2Reg == 0) return false;
1138 unsigned CmpOpc = isThumb ? ARM::t2TSTri : ARM::TSTri;
1139 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(CmpOpc))
1140 .addReg(CondReg).addImm(1));
1141 unsigned ResultReg = createResultReg(RC);
1142 unsigned MovCCOpc = isThumb ? ARM::t2MOVCCr : ARM::MOVCCr;
1143 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(MovCCOpc), ResultReg)
1144 .addReg(Op1Reg).addReg(Op2Reg)
1145 .addImm(ARMCC::EQ).addReg(ARM::CPSR);
1146 UpdateValueMap(I, ResultReg);
1150 bool ARMFastISel::SelectSDiv(const Instruction *I) {
1152 const Type *Ty = I->getType();
1153 if (!isTypeLegal(Ty, VT))
1156 // If we have integer div support we should have selected this automagically.
1157 // In case we have a real miss go ahead and return false and we'll pick
1159 if (Subtarget->hasDivide()) return false;
1161 // Otherwise emit a libcall.
1162 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
1164 LC = RTLIB::SDIV_I8;
1165 else if (VT == MVT::i16)
1166 LC = RTLIB::SDIV_I16;
1167 else if (VT == MVT::i32)
1168 LC = RTLIB::SDIV_I32;
1169 else if (VT == MVT::i64)
1170 LC = RTLIB::SDIV_I64;
1171 else if (VT == MVT::i128)
1172 LC = RTLIB::SDIV_I128;
1173 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported SDIV!");
1175 return ARMEmitLibcall(I, LC);
1178 bool ARMFastISel::SelectSRem(const Instruction *I) {
1180 const Type *Ty = I->getType();
1181 if (!isTypeLegal(Ty, VT))
1184 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
1186 LC = RTLIB::SREM_I8;
1187 else if (VT == MVT::i16)
1188 LC = RTLIB::SREM_I16;
1189 else if (VT == MVT::i32)
1190 LC = RTLIB::SREM_I32;
1191 else if (VT == MVT::i64)
1192 LC = RTLIB::SREM_I64;
1193 else if (VT == MVT::i128)
1194 LC = RTLIB::SREM_I128;
1195 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported SREM!");
1197 return ARMEmitLibcall(I, LC);
1200 bool ARMFastISel::SelectBinaryOp(const Instruction *I, unsigned ISDOpcode) {
1201 EVT VT = TLI.getValueType(I->getType(), true);
1203 // We can get here in the case when we want to use NEON for our fp
1204 // operations, but can't figure out how to. Just use the vfp instructions
1206 // FIXME: It'd be nice to use NEON instructions.
1207 const Type *Ty = I->getType();
1208 bool isFloat = (Ty->isDoubleTy() || Ty->isFloatTy());
1209 if (isFloat && !Subtarget->hasVFP2())
1212 unsigned Op1 = getRegForValue(I->getOperand(0));
1213 if (Op1 == 0) return false;
1215 unsigned Op2 = getRegForValue(I->getOperand(1));
1216 if (Op2 == 0) return false;
1219 bool is64bit = VT.getSimpleVT().SimpleTy == MVT::f64 ||
1220 VT.getSimpleVT().SimpleTy == MVT::i64;
1221 switch (ISDOpcode) {
1222 default: return false;
1224 Opc = is64bit ? ARM::VADDD : ARM::VADDS;
1227 Opc = is64bit ? ARM::VSUBD : ARM::VSUBS;
1230 Opc = is64bit ? ARM::VMULD : ARM::VMULS;
1233 unsigned ResultReg = createResultReg(TLI.getRegClassFor(VT));
1234 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1235 TII.get(Opc), ResultReg)
1236 .addReg(Op1).addReg(Op2));
1237 UpdateValueMap(I, ResultReg);
1241 // Call Handling Code
1243 // This is largely taken directly from CCAssignFnForNode - we don't support
1244 // varargs in FastISel so that part has been removed.
1245 // TODO: We may not support all of this.
1246 CCAssignFn *ARMFastISel::CCAssignFnForCall(CallingConv::ID CC, bool Return) {
1249 llvm_unreachable("Unsupported calling convention");
1250 case CallingConv::C:
1251 case CallingConv::Fast:
1252 // Use target triple & subtarget features to do actual dispatch.
1253 if (Subtarget->isAAPCS_ABI()) {
1254 if (Subtarget->hasVFP2() &&
1255 FloatABIType == FloatABI::Hard)
1256 return (Return ? RetCC_ARM_AAPCS_VFP: CC_ARM_AAPCS_VFP);
1258 return (Return ? RetCC_ARM_AAPCS: CC_ARM_AAPCS);
1260 return (Return ? RetCC_ARM_APCS: CC_ARM_APCS);
1261 case CallingConv::ARM_AAPCS_VFP:
1262 return (Return ? RetCC_ARM_AAPCS_VFP: CC_ARM_AAPCS_VFP);
1263 case CallingConv::ARM_AAPCS:
1264 return (Return ? RetCC_ARM_AAPCS: CC_ARM_AAPCS);
1265 case CallingConv::ARM_APCS:
1266 return (Return ? RetCC_ARM_APCS: CC_ARM_APCS);
1270 bool ARMFastISel::ProcessCallArgs(SmallVectorImpl<Value*> &Args,
1271 SmallVectorImpl<unsigned> &ArgRegs,
1272 SmallVectorImpl<EVT> &ArgVTs,
1273 SmallVectorImpl<ISD::ArgFlagsTy> &ArgFlags,
1274 SmallVectorImpl<unsigned> &RegArgs,
1276 unsigned &NumBytes) {
1277 SmallVector<CCValAssign, 16> ArgLocs;
1278 CCState CCInfo(CC, false, TM, ArgLocs, *Context);
1279 CCInfo.AnalyzeCallOperands(ArgVTs, ArgFlags, CCAssignFnForCall(CC, false));
1281 // Get a count of how many bytes are to be pushed on the stack.
1282 NumBytes = CCInfo.getNextStackOffset();
1284 // Issue CALLSEQ_START
1285 unsigned AdjStackDown = TM.getRegisterInfo()->getCallFrameSetupOpcode();
1286 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1287 TII.get(AdjStackDown))
1290 // Process the args.
1291 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1292 CCValAssign &VA = ArgLocs[i];
1293 unsigned Arg = ArgRegs[VA.getValNo()];
1294 EVT ArgVT = ArgVTs[VA.getValNo()];
1296 // Handle arg promotion, etc.
1297 switch (VA.getLocInfo()) {
1298 case CCValAssign::Full: break;
1300 // TODO: Handle arg promotion.
1304 // Now copy/store arg to correct locations.
1305 // TODO: We need custom lowering for f64 args.
1306 if (VA.isRegLoc() && !VA.needsCustom()) {
1307 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY),
1310 RegArgs.push_back(VA.getLocReg());
1320 bool ARMFastISel::FinishCall(EVT RetVT, SmallVectorImpl<unsigned> &UsedRegs,
1321 const Instruction *I, CallingConv::ID CC,
1322 unsigned &NumBytes) {
1323 // Issue CALLSEQ_END
1324 unsigned AdjStackUp = TM.getRegisterInfo()->getCallFrameDestroyOpcode();
1325 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1326 TII.get(AdjStackUp))
1327 .addImm(NumBytes).addImm(0));
1329 // Now the return value.
1330 if (RetVT.getSimpleVT().SimpleTy != MVT::isVoid) {
1331 SmallVector<CCValAssign, 16> RVLocs;
1332 CCState CCInfo(CC, false, TM, RVLocs, *Context);
1333 CCInfo.AnalyzeCallResult(RetVT, CCAssignFnForCall(CC, true));
1335 // Copy all of the result registers out of their specified physreg.
1336 if (RVLocs.size() == 2 && RetVT.getSimpleVT().SimpleTy == MVT::f64) {
1337 // For this move we copy into two registers and then move into the
1338 // double fp reg we want.
1339 // TODO: Are the copies necessary?
1340 TargetRegisterClass *CopyRC = TLI.getRegClassFor(MVT::i32);
1341 unsigned Copy1 = createResultReg(CopyRC);
1342 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY),
1343 Copy1).addReg(RVLocs[0].getLocReg());
1344 UsedRegs.push_back(RVLocs[0].getLocReg());
1346 unsigned Copy2 = createResultReg(CopyRC);
1347 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY),
1348 Copy2).addReg(RVLocs[1].getLocReg());
1349 UsedRegs.push_back(RVLocs[1].getLocReg());
1351 EVT DestVT = RVLocs[0].getValVT();
1352 TargetRegisterClass* DstRC = TLI.getRegClassFor(DestVT);
1353 unsigned ResultReg = createResultReg(DstRC);
1354 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1355 TII.get(ARM::VMOVDRR), ResultReg)
1356 .addReg(Copy1).addReg(Copy2));
1358 // Finally update the result.
1359 UpdateValueMap(I, ResultReg);
1361 assert(RVLocs.size() == 1 &&"Can't handle non-double multi-reg retvals!");
1362 EVT CopyVT = RVLocs[0].getValVT();
1363 TargetRegisterClass* DstRC = TLI.getRegClassFor(CopyVT);
1365 unsigned ResultReg = createResultReg(DstRC);
1366 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY),
1367 ResultReg).addReg(RVLocs[0].getLocReg());
1368 UsedRegs.push_back(RVLocs[0].getLocReg());
1370 // Finally update the result.
1371 UpdateValueMap(I, ResultReg);
1378 // A quick function that will emit a call for a named libcall in F with the
1379 // vector of passed arguments for the Instruction in I. We can assume that we
1380 // can emit a call for any libcall we can produce. This is an abridged version
1381 // of the full call infrastructure since we won't need to worry about things
1382 // like computed function pointers or strange arguments at call sites.
1383 // TODO: Try to unify this and the normal call bits for ARM, then try to unify
1385 bool ARMFastISel::ARMEmitLibcall(const Instruction *I, RTLIB::Libcall Call) {
1386 CallingConv::ID CC = TLI.getLibcallCallingConv(Call);
1388 // Handle *simple* calls for now.
1389 const Type *RetTy = I->getType();
1391 if (RetTy->isVoidTy())
1392 RetVT = MVT::isVoid;
1393 else if (!isTypeLegal(RetTy, RetVT))
1396 // For now we're using BLX etc on the assumption that we have v5t ops.
1397 if (!Subtarget->hasV5TOps()) return false;
1399 // Set up the argument vectors.
1400 SmallVector<Value*, 8> Args;
1401 SmallVector<unsigned, 8> ArgRegs;
1402 SmallVector<EVT, 8> ArgVTs;
1403 SmallVector<ISD::ArgFlagsTy, 8> ArgFlags;
1404 Args.reserve(I->getNumOperands());
1405 ArgRegs.reserve(I->getNumOperands());
1406 ArgVTs.reserve(I->getNumOperands());
1407 ArgFlags.reserve(I->getNumOperands());
1408 for (unsigned i = 0; i < I->getNumOperands(); ++i) {
1409 Value *Op = I->getOperand(i);
1410 unsigned Arg = getRegForValue(Op);
1411 if (Arg == 0) return false;
1413 const Type *ArgTy = Op->getType();
1415 if (!isTypeLegal(ArgTy, ArgVT)) return false;
1417 ISD::ArgFlagsTy Flags;
1418 unsigned OriginalAlignment = TD.getABITypeAlignment(ArgTy);
1419 Flags.setOrigAlign(OriginalAlignment);
1422 ArgRegs.push_back(Arg);
1423 ArgVTs.push_back(ArgVT);
1424 ArgFlags.push_back(Flags);
1427 // Handle the arguments now that we've gotten them.
1428 SmallVector<unsigned, 4> RegArgs;
1430 if (!ProcessCallArgs(Args, ArgRegs, ArgVTs, ArgFlags, RegArgs, CC, NumBytes))
1433 // Issue the call, BLXr9 for darwin, BLX otherwise. This uses V5 ops.
1434 // TODO: Turn this into the table of arm call ops.
1435 MachineInstrBuilder MIB;
1438 CallOpc = Subtarget->isTargetDarwin() ? ARM::tBLXi_r9 : ARM::tBLXi;
1440 CallOpc = Subtarget->isTargetDarwin() ? ARM::BLr9 : ARM::BL;
1441 MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(CallOpc))
1442 .addExternalSymbol(TLI.getLibcallName(Call));
1444 // Add implicit physical register uses to the call.
1445 for (unsigned i = 0, e = RegArgs.size(); i != e; ++i)
1446 MIB.addReg(RegArgs[i]);
1448 // Finish off the call including any return values.
1449 SmallVector<unsigned, 4> UsedRegs;
1450 if (!FinishCall(RetVT, UsedRegs, I, CC, NumBytes)) return false;
1452 // Set all unused physreg defs as dead.
1453 static_cast<MachineInstr *>(MIB)->setPhysRegsDeadExcept(UsedRegs, TRI);
1458 bool ARMFastISel::SelectCall(const Instruction *I) {
1459 const CallInst *CI = cast<CallInst>(I);
1460 const Value *Callee = CI->getCalledValue();
1462 // Can't handle inline asm or worry about intrinsics yet.
1463 if (isa<InlineAsm>(Callee) || isa<IntrinsicInst>(CI)) return false;
1465 // Only handle global variable Callees that are direct calls.
1466 const GlobalValue *GV = dyn_cast<GlobalValue>(Callee);
1467 if (!GV || Subtarget->GVIsIndirectSymbol(GV, TM.getRelocationModel()))
1470 // Check the calling convention.
1471 ImmutableCallSite CS(CI);
1472 CallingConv::ID CC = CS.getCallingConv();
1473 // TODO: Avoid some calling conventions?
1474 if (CC != CallingConv::C) {
1475 // errs() << "Can't handle calling convention: " << CC << "\n";
1479 // Let SDISel handle vararg functions.
1480 const PointerType *PT = cast<PointerType>(CS.getCalledValue()->getType());
1481 const FunctionType *FTy = cast<FunctionType>(PT->getElementType());
1482 if (FTy->isVarArg())
1485 // Handle *simple* calls for now.
1486 const Type *RetTy = I->getType();
1488 if (RetTy->isVoidTy())
1489 RetVT = MVT::isVoid;
1490 else if (!isTypeLegal(RetTy, RetVT))
1493 // For now we're using BLX etc on the assumption that we have v5t ops.
1495 if (!Subtarget->hasV5TOps()) return false;
1497 // Set up the argument vectors.
1498 SmallVector<Value*, 8> Args;
1499 SmallVector<unsigned, 8> ArgRegs;
1500 SmallVector<EVT, 8> ArgVTs;
1501 SmallVector<ISD::ArgFlagsTy, 8> ArgFlags;
1502 Args.reserve(CS.arg_size());
1503 ArgRegs.reserve(CS.arg_size());
1504 ArgVTs.reserve(CS.arg_size());
1505 ArgFlags.reserve(CS.arg_size());
1506 for (ImmutableCallSite::arg_iterator i = CS.arg_begin(), e = CS.arg_end();
1508 unsigned Arg = getRegForValue(*i);
1512 ISD::ArgFlagsTy Flags;
1513 unsigned AttrInd = i - CS.arg_begin() + 1;
1514 if (CS.paramHasAttr(AttrInd, Attribute::SExt))
1516 if (CS.paramHasAttr(AttrInd, Attribute::ZExt))
1519 // FIXME: Only handle *easy* calls for now.
1520 if (CS.paramHasAttr(AttrInd, Attribute::InReg) ||
1521 CS.paramHasAttr(AttrInd, Attribute::StructRet) ||
1522 CS.paramHasAttr(AttrInd, Attribute::Nest) ||
1523 CS.paramHasAttr(AttrInd, Attribute::ByVal))
1526 const Type *ArgTy = (*i)->getType();
1528 if (!isTypeLegal(ArgTy, ArgVT))
1530 unsigned OriginalAlignment = TD.getABITypeAlignment(ArgTy);
1531 Flags.setOrigAlign(OriginalAlignment);
1534 ArgRegs.push_back(Arg);
1535 ArgVTs.push_back(ArgVT);
1536 ArgFlags.push_back(Flags);
1539 // Handle the arguments now that we've gotten them.
1540 SmallVector<unsigned, 4> RegArgs;
1542 if (!ProcessCallArgs(Args, ArgRegs, ArgVTs, ArgFlags, RegArgs, CC, NumBytes))
1545 // Issue the call, BLXr9 for darwin, BLX otherwise. This uses V5 ops.
1546 // TODO: Turn this into the table of arm call ops.
1547 MachineInstrBuilder MIB;
1550 CallOpc = Subtarget->isTargetDarwin() ? ARM::tBLXi_r9 : ARM::tBLXi;
1552 CallOpc = Subtarget->isTargetDarwin() ? ARM::BLr9 : ARM::BL;
1553 MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(CallOpc))
1554 .addGlobalAddress(GV, 0, 0);
1556 // Add implicit physical register uses to the call.
1557 for (unsigned i = 0, e = RegArgs.size(); i != e; ++i)
1558 MIB.addReg(RegArgs[i]);
1560 // Finish off the call including any return values.
1561 SmallVector<unsigned, 4> UsedRegs;
1562 if (!FinishCall(RetVT, UsedRegs, I, CC, NumBytes)) return false;
1564 // Set all unused physreg defs as dead.
1565 static_cast<MachineInstr *>(MIB)->setPhysRegsDeadExcept(UsedRegs, TRI);
1571 // TODO: SoftFP support.
1572 bool ARMFastISel::TargetSelectInstruction(const Instruction *I) {
1573 // No Thumb-1 for now.
1574 if (isThumb && !AFI->isThumb2Function()) return false;
1576 switch (I->getOpcode()) {
1577 case Instruction::Load:
1578 return SelectLoad(I);
1579 case Instruction::Store:
1580 return SelectStore(I);
1581 case Instruction::Br:
1582 return SelectBranch(I);
1583 case Instruction::ICmp:
1584 case Instruction::FCmp:
1585 return SelectCmp(I);
1586 case Instruction::FPExt:
1587 return SelectFPExt(I);
1588 case Instruction::FPTrunc:
1589 return SelectFPTrunc(I);
1590 case Instruction::SIToFP:
1591 return SelectSIToFP(I);
1592 case Instruction::FPToSI:
1593 return SelectFPToSI(I);
1594 case Instruction::FAdd:
1595 return SelectBinaryOp(I, ISD::FADD);
1596 case Instruction::FSub:
1597 return SelectBinaryOp(I, ISD::FSUB);
1598 case Instruction::FMul:
1599 return SelectBinaryOp(I, ISD::FMUL);
1600 case Instruction::SDiv:
1601 return SelectSDiv(I);
1602 case Instruction::SRem:
1603 return SelectSRem(I);
1604 case Instruction::Call:
1605 return SelectCall(I);
1606 case Instruction::Select:
1607 return SelectSelect(I);
1614 llvm::FastISel *ARM::createFastISel(FunctionLoweringInfo &funcInfo) {
1615 // Completely untested on non-darwin.
1616 const TargetMachine &TM = funcInfo.MF->getTarget();
1617 const ARMSubtarget *Subtarget = &TM.getSubtarget<ARMSubtarget>();
1618 if (Subtarget->isTargetDarwin() && EnableARMFastISel)
1619 return new ARMFastISel(funcInfo);