1 //===-- ARMExpandPseudoInsts.cpp - Expand pseudo instructions -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains a pass that expands pseudo instructions into target
11 // instructions to allow proper scheduling, if-conversion, and other late
12 // optimizations. This pass should be run after register allocation but before
13 // the post-regalloc scheduling pass.
15 //===----------------------------------------------------------------------===//
17 #define DEBUG_TYPE "arm-pseudo"
19 #include "ARMBaseInstrInfo.h"
20 #include "ARMBaseRegisterInfo.h"
21 #include "ARMConstantPoolValue.h"
22 #include "ARMMachineFunctionInfo.h"
23 #include "MCTargetDesc/ARMAddressingModes.h"
24 #include "llvm/CodeGen/MachineFrameInfo.h"
25 #include "llvm/CodeGen/MachineFunctionPass.h"
26 #include "llvm/CodeGen/MachineInstrBuilder.h"
27 #include "llvm/IR/GlobalValue.h"
28 #include "llvm/Support/CommandLine.h"
29 #include "llvm/Support/raw_ostream.h" // FIXME: for debug only. remove!
30 #include "llvm/Target/TargetFrameLowering.h"
31 #include "llvm/Target/TargetRegisterInfo.h"
35 VerifyARMPseudo("verify-arm-pseudo-expand", cl::Hidden,
36 cl::desc("Verify machine code after expanding ARM pseudos"));
39 class ARMExpandPseudo : public MachineFunctionPass {
42 ARMExpandPseudo() : MachineFunctionPass(ID) {}
44 const ARMBaseInstrInfo *TII;
45 const TargetRegisterInfo *TRI;
46 const ARMSubtarget *STI;
49 virtual bool runOnMachineFunction(MachineFunction &Fn);
51 virtual const char *getPassName() const {
52 return "ARM pseudo instruction expansion pass";
56 void TransferImpOps(MachineInstr &OldMI,
57 MachineInstrBuilder &UseMI, MachineInstrBuilder &DefMI);
58 bool ExpandMI(MachineBasicBlock &MBB,
59 MachineBasicBlock::iterator MBBI);
60 bool ExpandMBB(MachineBasicBlock &MBB);
61 void ExpandVLD(MachineBasicBlock::iterator &MBBI);
62 void ExpandVST(MachineBasicBlock::iterator &MBBI);
63 void ExpandLaneOp(MachineBasicBlock::iterator &MBBI);
64 void ExpandVTBL(MachineBasicBlock::iterator &MBBI,
65 unsigned Opc, bool IsExt);
66 void ExpandMOV32BitImm(MachineBasicBlock &MBB,
67 MachineBasicBlock::iterator &MBBI);
69 char ARMExpandPseudo::ID = 0;
72 /// TransferImpOps - Transfer implicit operands on the pseudo instruction to
73 /// the instructions created from the expansion.
74 void ARMExpandPseudo::TransferImpOps(MachineInstr &OldMI,
75 MachineInstrBuilder &UseMI,
76 MachineInstrBuilder &DefMI) {
77 const MCInstrDesc &Desc = OldMI.getDesc();
78 for (unsigned i = Desc.getNumOperands(), e = OldMI.getNumOperands();
80 const MachineOperand &MO = OldMI.getOperand(i);
81 assert(MO.isReg() && MO.getReg());
90 // Constants for register spacing in NEON load/store instructions.
91 // For quad-register load-lane and store-lane pseudo instructors, the
92 // spacing is initially assumed to be EvenDblSpc, and that is changed to
93 // OddDblSpc depending on the lane number operand.
100 // Entries for NEON load/store information table. The table is sorted by
101 // PseudoOpc for fast binary-search lookups.
102 struct NEONLdStTableEntry {
107 bool hasWritebackOperand;
108 uint8_t RegSpacing; // One of type NEONRegSpacing
109 uint8_t NumRegs; // D registers loaded or stored
110 uint8_t RegElts; // elements per D register; used for lane ops
111 // FIXME: Temporary flag to denote whether the real instruction takes
112 // a single register (like the encoding) or all of the registers in
113 // the list (like the asm syntax and the isel DAG). When all definitions
114 // are converted to take only the single encoded register, this will
116 bool copyAllListRegs;
118 // Comparison methods for binary search of the table.
119 bool operator<(const NEONLdStTableEntry &TE) const {
120 return PseudoOpc < TE.PseudoOpc;
122 friend bool operator<(const NEONLdStTableEntry &TE, unsigned PseudoOpc) {
123 return TE.PseudoOpc < PseudoOpc;
125 friend bool LLVM_ATTRIBUTE_UNUSED operator<(unsigned PseudoOpc,
126 const NEONLdStTableEntry &TE) {
127 return PseudoOpc < TE.PseudoOpc;
132 static const NEONLdStTableEntry NEONLdStTable[] = {
133 { ARM::VLD1LNq16Pseudo, ARM::VLD1LNd16, true, false, false, EvenDblSpc, 1, 4 ,true},
134 { ARM::VLD1LNq16Pseudo_UPD, ARM::VLD1LNd16_UPD, true, true, true, EvenDblSpc, 1, 4 ,true},
135 { ARM::VLD1LNq32Pseudo, ARM::VLD1LNd32, true, false, false, EvenDblSpc, 1, 2 ,true},
136 { ARM::VLD1LNq32Pseudo_UPD, ARM::VLD1LNd32_UPD, true, true, true, EvenDblSpc, 1, 2 ,true},
137 { ARM::VLD1LNq8Pseudo, ARM::VLD1LNd8, true, false, false, EvenDblSpc, 1, 8 ,true},
138 { ARM::VLD1LNq8Pseudo_UPD, ARM::VLD1LNd8_UPD, true, true, true, EvenDblSpc, 1, 8 ,true},
140 { ARM::VLD1d64QPseudo, ARM::VLD1d64Q, true, false, false, SingleSpc, 4, 1 ,false},
141 { ARM::VLD1d64QPseudoWB_fixed, ARM::VLD1d64Qwb_fixed, true, true, false, SingleSpc, 4, 1 ,false},
142 { ARM::VLD1d64TPseudo, ARM::VLD1d64T, true, false, false, SingleSpc, 3, 1 ,false},
143 { ARM::VLD1d64TPseudoWB_fixed, ARM::VLD1d64Twb_fixed, true, true, false, SingleSpc, 3, 1 ,false},
145 { ARM::VLD2LNd16Pseudo, ARM::VLD2LNd16, true, false, false, SingleSpc, 2, 4 ,true},
146 { ARM::VLD2LNd16Pseudo_UPD, ARM::VLD2LNd16_UPD, true, true, true, SingleSpc, 2, 4 ,true},
147 { ARM::VLD2LNd32Pseudo, ARM::VLD2LNd32, true, false, false, SingleSpc, 2, 2 ,true},
148 { ARM::VLD2LNd32Pseudo_UPD, ARM::VLD2LNd32_UPD, true, true, true, SingleSpc, 2, 2 ,true},
149 { ARM::VLD2LNd8Pseudo, ARM::VLD2LNd8, true, false, false, SingleSpc, 2, 8 ,true},
150 { ARM::VLD2LNd8Pseudo_UPD, ARM::VLD2LNd8_UPD, true, true, true, SingleSpc, 2, 8 ,true},
151 { ARM::VLD2LNq16Pseudo, ARM::VLD2LNq16, true, false, false, EvenDblSpc, 2, 4 ,true},
152 { ARM::VLD2LNq16Pseudo_UPD, ARM::VLD2LNq16_UPD, true, true, true, EvenDblSpc, 2, 4 ,true},
153 { ARM::VLD2LNq32Pseudo, ARM::VLD2LNq32, true, false, false, EvenDblSpc, 2, 2 ,true},
154 { ARM::VLD2LNq32Pseudo_UPD, ARM::VLD2LNq32_UPD, true, true, true, EvenDblSpc, 2, 2 ,true},
156 { ARM::VLD2q16Pseudo, ARM::VLD2q16, true, false, false, SingleSpc, 4, 4 ,false},
157 { ARM::VLD2q16PseudoWB_fixed, ARM::VLD2q16wb_fixed, true, true, false, SingleSpc, 4, 4 ,false},
158 { ARM::VLD2q16PseudoWB_register, ARM::VLD2q16wb_register, true, true, true, SingleSpc, 4, 4 ,false},
159 { ARM::VLD2q32Pseudo, ARM::VLD2q32, true, false, false, SingleSpc, 4, 2 ,false},
160 { ARM::VLD2q32PseudoWB_fixed, ARM::VLD2q32wb_fixed, true, true, false, SingleSpc, 4, 2 ,false},
161 { ARM::VLD2q32PseudoWB_register, ARM::VLD2q32wb_register, true, true, true, SingleSpc, 4, 2 ,false},
162 { ARM::VLD2q8Pseudo, ARM::VLD2q8, true, false, false, SingleSpc, 4, 8 ,false},
163 { ARM::VLD2q8PseudoWB_fixed, ARM::VLD2q8wb_fixed, true, true, false, SingleSpc, 4, 8 ,false},
164 { ARM::VLD2q8PseudoWB_register, ARM::VLD2q8wb_register, true, true, true, SingleSpc, 4, 8 ,false},
166 { ARM::VLD3DUPd16Pseudo, ARM::VLD3DUPd16, true, false, false, SingleSpc, 3, 4,true},
167 { ARM::VLD3DUPd16Pseudo_UPD, ARM::VLD3DUPd16_UPD, true, true, true, SingleSpc, 3, 4,true},
168 { ARM::VLD3DUPd32Pseudo, ARM::VLD3DUPd32, true, false, false, SingleSpc, 3, 2,true},
169 { ARM::VLD3DUPd32Pseudo_UPD, ARM::VLD3DUPd32_UPD, true, true, true, SingleSpc, 3, 2,true},
170 { ARM::VLD3DUPd8Pseudo, ARM::VLD3DUPd8, true, false, false, SingleSpc, 3, 8,true},
171 { ARM::VLD3DUPd8Pseudo_UPD, ARM::VLD3DUPd8_UPD, true, true, true, SingleSpc, 3, 8,true},
173 { ARM::VLD3LNd16Pseudo, ARM::VLD3LNd16, true, false, false, SingleSpc, 3, 4 ,true},
174 { ARM::VLD3LNd16Pseudo_UPD, ARM::VLD3LNd16_UPD, true, true, true, SingleSpc, 3, 4 ,true},
175 { ARM::VLD3LNd32Pseudo, ARM::VLD3LNd32, true, false, false, SingleSpc, 3, 2 ,true},
176 { ARM::VLD3LNd32Pseudo_UPD, ARM::VLD3LNd32_UPD, true, true, true, SingleSpc, 3, 2 ,true},
177 { ARM::VLD3LNd8Pseudo, ARM::VLD3LNd8, true, false, false, SingleSpc, 3, 8 ,true},
178 { ARM::VLD3LNd8Pseudo_UPD, ARM::VLD3LNd8_UPD, true, true, true, SingleSpc, 3, 8 ,true},
179 { ARM::VLD3LNq16Pseudo, ARM::VLD3LNq16, true, false, false, EvenDblSpc, 3, 4 ,true},
180 { ARM::VLD3LNq16Pseudo_UPD, ARM::VLD3LNq16_UPD, true, true, true, EvenDblSpc, 3, 4 ,true},
181 { ARM::VLD3LNq32Pseudo, ARM::VLD3LNq32, true, false, false, EvenDblSpc, 3, 2 ,true},
182 { ARM::VLD3LNq32Pseudo_UPD, ARM::VLD3LNq32_UPD, true, true, true, EvenDblSpc, 3, 2 ,true},
184 { ARM::VLD3d16Pseudo, ARM::VLD3d16, true, false, false, SingleSpc, 3, 4 ,true},
185 { ARM::VLD3d16Pseudo_UPD, ARM::VLD3d16_UPD, true, true, true, SingleSpc, 3, 4 ,true},
186 { ARM::VLD3d32Pseudo, ARM::VLD3d32, true, false, false, SingleSpc, 3, 2 ,true},
187 { ARM::VLD3d32Pseudo_UPD, ARM::VLD3d32_UPD, true, true, true, SingleSpc, 3, 2 ,true},
188 { ARM::VLD3d8Pseudo, ARM::VLD3d8, true, false, false, SingleSpc, 3, 8 ,true},
189 { ARM::VLD3d8Pseudo_UPD, ARM::VLD3d8_UPD, true, true, true, SingleSpc, 3, 8 ,true},
191 { ARM::VLD3q16Pseudo_UPD, ARM::VLD3q16_UPD, true, true, true, EvenDblSpc, 3, 4 ,true},
192 { ARM::VLD3q16oddPseudo, ARM::VLD3q16, true, false, false, OddDblSpc, 3, 4 ,true},
193 { ARM::VLD3q16oddPseudo_UPD, ARM::VLD3q16_UPD, true, true, true, OddDblSpc, 3, 4 ,true},
194 { ARM::VLD3q32Pseudo_UPD, ARM::VLD3q32_UPD, true, true, true, EvenDblSpc, 3, 2 ,true},
195 { ARM::VLD3q32oddPseudo, ARM::VLD3q32, true, false, false, OddDblSpc, 3, 2 ,true},
196 { ARM::VLD3q32oddPseudo_UPD, ARM::VLD3q32_UPD, true, true, true, OddDblSpc, 3, 2 ,true},
197 { ARM::VLD3q8Pseudo_UPD, ARM::VLD3q8_UPD, true, true, true, EvenDblSpc, 3, 8 ,true},
198 { ARM::VLD3q8oddPseudo, ARM::VLD3q8, true, false, false, OddDblSpc, 3, 8 ,true},
199 { ARM::VLD3q8oddPseudo_UPD, ARM::VLD3q8_UPD, true, true, true, OddDblSpc, 3, 8 ,true},
201 { ARM::VLD4DUPd16Pseudo, ARM::VLD4DUPd16, true, false, false, SingleSpc, 4, 4,true},
202 { ARM::VLD4DUPd16Pseudo_UPD, ARM::VLD4DUPd16_UPD, true, true, true, SingleSpc, 4, 4,true},
203 { ARM::VLD4DUPd32Pseudo, ARM::VLD4DUPd32, true, false, false, SingleSpc, 4, 2,true},
204 { ARM::VLD4DUPd32Pseudo_UPD, ARM::VLD4DUPd32_UPD, true, true, true, SingleSpc, 4, 2,true},
205 { ARM::VLD4DUPd8Pseudo, ARM::VLD4DUPd8, true, false, false, SingleSpc, 4, 8,true},
206 { ARM::VLD4DUPd8Pseudo_UPD, ARM::VLD4DUPd8_UPD, true, true, true, SingleSpc, 4, 8,true},
208 { ARM::VLD4LNd16Pseudo, ARM::VLD4LNd16, true, false, false, SingleSpc, 4, 4 ,true},
209 { ARM::VLD4LNd16Pseudo_UPD, ARM::VLD4LNd16_UPD, true, true, true, SingleSpc, 4, 4 ,true},
210 { ARM::VLD4LNd32Pseudo, ARM::VLD4LNd32, true, false, false, SingleSpc, 4, 2 ,true},
211 { ARM::VLD4LNd32Pseudo_UPD, ARM::VLD4LNd32_UPD, true, true, true, SingleSpc, 4, 2 ,true},
212 { ARM::VLD4LNd8Pseudo, ARM::VLD4LNd8, true, false, false, SingleSpc, 4, 8 ,true},
213 { ARM::VLD4LNd8Pseudo_UPD, ARM::VLD4LNd8_UPD, true, true, true, SingleSpc, 4, 8 ,true},
214 { ARM::VLD4LNq16Pseudo, ARM::VLD4LNq16, true, false, false, EvenDblSpc, 4, 4 ,true},
215 { ARM::VLD4LNq16Pseudo_UPD, ARM::VLD4LNq16_UPD, true, true, true, EvenDblSpc, 4, 4 ,true},
216 { ARM::VLD4LNq32Pseudo, ARM::VLD4LNq32, true, false, false, EvenDblSpc, 4, 2 ,true},
217 { ARM::VLD4LNq32Pseudo_UPD, ARM::VLD4LNq32_UPD, true, true, true, EvenDblSpc, 4, 2 ,true},
219 { ARM::VLD4d16Pseudo, ARM::VLD4d16, true, false, false, SingleSpc, 4, 4 ,true},
220 { ARM::VLD4d16Pseudo_UPD, ARM::VLD4d16_UPD, true, true, true, SingleSpc, 4, 4 ,true},
221 { ARM::VLD4d32Pseudo, ARM::VLD4d32, true, false, false, SingleSpc, 4, 2 ,true},
222 { ARM::VLD4d32Pseudo_UPD, ARM::VLD4d32_UPD, true, true, true, SingleSpc, 4, 2 ,true},
223 { ARM::VLD4d8Pseudo, ARM::VLD4d8, true, false, false, SingleSpc, 4, 8 ,true},
224 { ARM::VLD4d8Pseudo_UPD, ARM::VLD4d8_UPD, true, true, true, SingleSpc, 4, 8 ,true},
226 { ARM::VLD4q16Pseudo_UPD, ARM::VLD4q16_UPD, true, true, true, EvenDblSpc, 4, 4 ,true},
227 { ARM::VLD4q16oddPseudo, ARM::VLD4q16, true, false, false, OddDblSpc, 4, 4 ,true},
228 { ARM::VLD4q16oddPseudo_UPD, ARM::VLD4q16_UPD, true, true, true, OddDblSpc, 4, 4 ,true},
229 { ARM::VLD4q32Pseudo_UPD, ARM::VLD4q32_UPD, true, true, true, EvenDblSpc, 4, 2 ,true},
230 { ARM::VLD4q32oddPseudo, ARM::VLD4q32, true, false, false, OddDblSpc, 4, 2 ,true},
231 { ARM::VLD4q32oddPseudo_UPD, ARM::VLD4q32_UPD, true, true, true, OddDblSpc, 4, 2 ,true},
232 { ARM::VLD4q8Pseudo_UPD, ARM::VLD4q8_UPD, true, true, true, EvenDblSpc, 4, 8 ,true},
233 { ARM::VLD4q8oddPseudo, ARM::VLD4q8, true, false, false, OddDblSpc, 4, 8 ,true},
234 { ARM::VLD4q8oddPseudo_UPD, ARM::VLD4q8_UPD, true, true, true, OddDblSpc, 4, 8 ,true},
236 { ARM::VST1LNq16Pseudo, ARM::VST1LNd16, false, false, false, EvenDblSpc, 1, 4 ,true},
237 { ARM::VST1LNq16Pseudo_UPD, ARM::VST1LNd16_UPD, false, true, true, EvenDblSpc, 1, 4 ,true},
238 { ARM::VST1LNq32Pseudo, ARM::VST1LNd32, false, false, false, EvenDblSpc, 1, 2 ,true},
239 { ARM::VST1LNq32Pseudo_UPD, ARM::VST1LNd32_UPD, false, true, true, EvenDblSpc, 1, 2 ,true},
240 { ARM::VST1LNq8Pseudo, ARM::VST1LNd8, false, false, false, EvenDblSpc, 1, 8 ,true},
241 { ARM::VST1LNq8Pseudo_UPD, ARM::VST1LNd8_UPD, false, true, true, EvenDblSpc, 1, 8 ,true},
243 { ARM::VST1d64QPseudo, ARM::VST1d64Q, false, false, false, SingleSpc, 4, 1 ,false},
244 { ARM::VST1d64QPseudoWB_fixed, ARM::VST1d64Qwb_fixed, false, true, false, SingleSpc, 4, 1 ,false},
245 { ARM::VST1d64QPseudoWB_register, ARM::VST1d64Qwb_register, false, true, true, SingleSpc, 4, 1 ,false},
246 { ARM::VST1d64TPseudo, ARM::VST1d64T, false, false, false, SingleSpc, 3, 1 ,false},
247 { ARM::VST1d64TPseudoWB_fixed, ARM::VST1d64Twb_fixed, false, true, false, SingleSpc, 3, 1 ,false},
248 { ARM::VST1d64TPseudoWB_register, ARM::VST1d64Twb_register, false, true, true, SingleSpc, 3, 1 ,false},
250 { ARM::VST2LNd16Pseudo, ARM::VST2LNd16, false, false, false, SingleSpc, 2, 4 ,true},
251 { ARM::VST2LNd16Pseudo_UPD, ARM::VST2LNd16_UPD, false, true, true, SingleSpc, 2, 4 ,true},
252 { ARM::VST2LNd32Pseudo, ARM::VST2LNd32, false, false, false, SingleSpc, 2, 2 ,true},
253 { ARM::VST2LNd32Pseudo_UPD, ARM::VST2LNd32_UPD, false, true, true, SingleSpc, 2, 2 ,true},
254 { ARM::VST2LNd8Pseudo, ARM::VST2LNd8, false, false, false, SingleSpc, 2, 8 ,true},
255 { ARM::VST2LNd8Pseudo_UPD, ARM::VST2LNd8_UPD, false, true, true, SingleSpc, 2, 8 ,true},
256 { ARM::VST2LNq16Pseudo, ARM::VST2LNq16, false, false, false, EvenDblSpc, 2, 4,true},
257 { ARM::VST2LNq16Pseudo_UPD, ARM::VST2LNq16_UPD, false, true, true, EvenDblSpc, 2, 4,true},
258 { ARM::VST2LNq32Pseudo, ARM::VST2LNq32, false, false, false, EvenDblSpc, 2, 2,true},
259 { ARM::VST2LNq32Pseudo_UPD, ARM::VST2LNq32_UPD, false, true, true, EvenDblSpc, 2, 2,true},
261 { ARM::VST2q16Pseudo, ARM::VST2q16, false, false, false, SingleSpc, 4, 4 ,false},
262 { ARM::VST2q16PseudoWB_fixed, ARM::VST2q16wb_fixed, false, true, false, SingleSpc, 4, 4 ,false},
263 { ARM::VST2q16PseudoWB_register, ARM::VST2q16wb_register, false, true, true, SingleSpc, 4, 4 ,false},
264 { ARM::VST2q32Pseudo, ARM::VST2q32, false, false, false, SingleSpc, 4, 2 ,false},
265 { ARM::VST2q32PseudoWB_fixed, ARM::VST2q32wb_fixed, false, true, false, SingleSpc, 4, 2 ,false},
266 { ARM::VST2q32PseudoWB_register, ARM::VST2q32wb_register, false, true, true, SingleSpc, 4, 2 ,false},
267 { ARM::VST2q8Pseudo, ARM::VST2q8, false, false, false, SingleSpc, 4, 8 ,false},
268 { ARM::VST2q8PseudoWB_fixed, ARM::VST2q8wb_fixed, false, true, false, SingleSpc, 4, 8 ,false},
269 { ARM::VST2q8PseudoWB_register, ARM::VST2q8wb_register, false, true, true, SingleSpc, 4, 8 ,false},
271 { ARM::VST3LNd16Pseudo, ARM::VST3LNd16, false, false, false, SingleSpc, 3, 4 ,true},
272 { ARM::VST3LNd16Pseudo_UPD, ARM::VST3LNd16_UPD, false, true, true, SingleSpc, 3, 4 ,true},
273 { ARM::VST3LNd32Pseudo, ARM::VST3LNd32, false, false, false, SingleSpc, 3, 2 ,true},
274 { ARM::VST3LNd32Pseudo_UPD, ARM::VST3LNd32_UPD, false, true, true, SingleSpc, 3, 2 ,true},
275 { ARM::VST3LNd8Pseudo, ARM::VST3LNd8, false, false, false, SingleSpc, 3, 8 ,true},
276 { ARM::VST3LNd8Pseudo_UPD, ARM::VST3LNd8_UPD, false, true, true, SingleSpc, 3, 8 ,true},
277 { ARM::VST3LNq16Pseudo, ARM::VST3LNq16, false, false, false, EvenDblSpc, 3, 4,true},
278 { ARM::VST3LNq16Pseudo_UPD, ARM::VST3LNq16_UPD, false, true, true, EvenDblSpc, 3, 4,true},
279 { ARM::VST3LNq32Pseudo, ARM::VST3LNq32, false, false, false, EvenDblSpc, 3, 2,true},
280 { ARM::VST3LNq32Pseudo_UPD, ARM::VST3LNq32_UPD, false, true, true, EvenDblSpc, 3, 2,true},
282 { ARM::VST3d16Pseudo, ARM::VST3d16, false, false, false, SingleSpc, 3, 4 ,true},
283 { ARM::VST3d16Pseudo_UPD, ARM::VST3d16_UPD, false, true, true, SingleSpc, 3, 4 ,true},
284 { ARM::VST3d32Pseudo, ARM::VST3d32, false, false, false, SingleSpc, 3, 2 ,true},
285 { ARM::VST3d32Pseudo_UPD, ARM::VST3d32_UPD, false, true, true, SingleSpc, 3, 2 ,true},
286 { ARM::VST3d8Pseudo, ARM::VST3d8, false, false, false, SingleSpc, 3, 8 ,true},
287 { ARM::VST3d8Pseudo_UPD, ARM::VST3d8_UPD, false, true, true, SingleSpc, 3, 8 ,true},
289 { ARM::VST3q16Pseudo_UPD, ARM::VST3q16_UPD, false, true, true, EvenDblSpc, 3, 4 ,true},
290 { ARM::VST3q16oddPseudo, ARM::VST3q16, false, false, false, OddDblSpc, 3, 4 ,true},
291 { ARM::VST3q16oddPseudo_UPD, ARM::VST3q16_UPD, false, true, true, OddDblSpc, 3, 4 ,true},
292 { ARM::VST3q32Pseudo_UPD, ARM::VST3q32_UPD, false, true, true, EvenDblSpc, 3, 2 ,true},
293 { ARM::VST3q32oddPseudo, ARM::VST3q32, false, false, false, OddDblSpc, 3, 2 ,true},
294 { ARM::VST3q32oddPseudo_UPD, ARM::VST3q32_UPD, false, true, true, OddDblSpc, 3, 2 ,true},
295 { ARM::VST3q8Pseudo_UPD, ARM::VST3q8_UPD, false, true, true, EvenDblSpc, 3, 8 ,true},
296 { ARM::VST3q8oddPseudo, ARM::VST3q8, false, false, false, OddDblSpc, 3, 8 ,true},
297 { ARM::VST3q8oddPseudo_UPD, ARM::VST3q8_UPD, false, true, true, OddDblSpc, 3, 8 ,true},
299 { ARM::VST4LNd16Pseudo, ARM::VST4LNd16, false, false, false, SingleSpc, 4, 4 ,true},
300 { ARM::VST4LNd16Pseudo_UPD, ARM::VST4LNd16_UPD, false, true, true, SingleSpc, 4, 4 ,true},
301 { ARM::VST4LNd32Pseudo, ARM::VST4LNd32, false, false, false, SingleSpc, 4, 2 ,true},
302 { ARM::VST4LNd32Pseudo_UPD, ARM::VST4LNd32_UPD, false, true, true, SingleSpc, 4, 2 ,true},
303 { ARM::VST4LNd8Pseudo, ARM::VST4LNd8, false, false, false, SingleSpc, 4, 8 ,true},
304 { ARM::VST4LNd8Pseudo_UPD, ARM::VST4LNd8_UPD, false, true, true, SingleSpc, 4, 8 ,true},
305 { ARM::VST4LNq16Pseudo, ARM::VST4LNq16, false, false, false, EvenDblSpc, 4, 4,true},
306 { ARM::VST4LNq16Pseudo_UPD, ARM::VST4LNq16_UPD, false, true, true, EvenDblSpc, 4, 4,true},
307 { ARM::VST4LNq32Pseudo, ARM::VST4LNq32, false, false, false, EvenDblSpc, 4, 2,true},
308 { ARM::VST4LNq32Pseudo_UPD, ARM::VST4LNq32_UPD, false, true, true, EvenDblSpc, 4, 2,true},
310 { ARM::VST4d16Pseudo, ARM::VST4d16, false, false, false, SingleSpc, 4, 4 ,true},
311 { ARM::VST4d16Pseudo_UPD, ARM::VST4d16_UPD, false, true, true, SingleSpc, 4, 4 ,true},
312 { ARM::VST4d32Pseudo, ARM::VST4d32, false, false, false, SingleSpc, 4, 2 ,true},
313 { ARM::VST4d32Pseudo_UPD, ARM::VST4d32_UPD, false, true, true, SingleSpc, 4, 2 ,true},
314 { ARM::VST4d8Pseudo, ARM::VST4d8, false, false, false, SingleSpc, 4, 8 ,true},
315 { ARM::VST4d8Pseudo_UPD, ARM::VST4d8_UPD, false, true, true, SingleSpc, 4, 8 ,true},
317 { ARM::VST4q16Pseudo_UPD, ARM::VST4q16_UPD, false, true, true, EvenDblSpc, 4, 4 ,true},
318 { ARM::VST4q16oddPseudo, ARM::VST4q16, false, false, false, OddDblSpc, 4, 4 ,true},
319 { ARM::VST4q16oddPseudo_UPD, ARM::VST4q16_UPD, false, true, true, OddDblSpc, 4, 4 ,true},
320 { ARM::VST4q32Pseudo_UPD, ARM::VST4q32_UPD, false, true, true, EvenDblSpc, 4, 2 ,true},
321 { ARM::VST4q32oddPseudo, ARM::VST4q32, false, false, false, OddDblSpc, 4, 2 ,true},
322 { ARM::VST4q32oddPseudo_UPD, ARM::VST4q32_UPD, false, true, true, OddDblSpc, 4, 2 ,true},
323 { ARM::VST4q8Pseudo_UPD, ARM::VST4q8_UPD, false, true, true, EvenDblSpc, 4, 8 ,true},
324 { ARM::VST4q8oddPseudo, ARM::VST4q8, false, false, false, OddDblSpc, 4, 8 ,true},
325 { ARM::VST4q8oddPseudo_UPD, ARM::VST4q8_UPD, false, true, true, OddDblSpc, 4, 8 ,true}
328 /// LookupNEONLdSt - Search the NEONLdStTable for information about a NEON
329 /// load or store pseudo instruction.
330 static const NEONLdStTableEntry *LookupNEONLdSt(unsigned Opcode) {
331 const unsigned NumEntries = array_lengthof(NEONLdStTable);
334 // Make sure the table is sorted.
335 static bool TableChecked = false;
337 for (unsigned i = 0; i != NumEntries-1; ++i)
338 assert(NEONLdStTable[i] < NEONLdStTable[i+1] &&
339 "NEONLdStTable is not sorted!");
344 const NEONLdStTableEntry *I =
345 std::lower_bound(NEONLdStTable, NEONLdStTable + NumEntries, Opcode);
346 if (I != NEONLdStTable + NumEntries && I->PseudoOpc == Opcode)
351 /// GetDSubRegs - Get 4 D subregisters of a Q, QQ, or QQQQ register,
352 /// corresponding to the specified register spacing. Not all of the results
353 /// are necessarily valid, e.g., a Q register only has 2 D subregisters.
354 static void GetDSubRegs(unsigned Reg, NEONRegSpacing RegSpc,
355 const TargetRegisterInfo *TRI, unsigned &D0,
356 unsigned &D1, unsigned &D2, unsigned &D3) {
357 if (RegSpc == SingleSpc) {
358 D0 = TRI->getSubReg(Reg, ARM::dsub_0);
359 D1 = TRI->getSubReg(Reg, ARM::dsub_1);
360 D2 = TRI->getSubReg(Reg, ARM::dsub_2);
361 D3 = TRI->getSubReg(Reg, ARM::dsub_3);
362 } else if (RegSpc == EvenDblSpc) {
363 D0 = TRI->getSubReg(Reg, ARM::dsub_0);
364 D1 = TRI->getSubReg(Reg, ARM::dsub_2);
365 D2 = TRI->getSubReg(Reg, ARM::dsub_4);
366 D3 = TRI->getSubReg(Reg, ARM::dsub_6);
368 assert(RegSpc == OddDblSpc && "unknown register spacing");
369 D0 = TRI->getSubReg(Reg, ARM::dsub_1);
370 D1 = TRI->getSubReg(Reg, ARM::dsub_3);
371 D2 = TRI->getSubReg(Reg, ARM::dsub_5);
372 D3 = TRI->getSubReg(Reg, ARM::dsub_7);
376 /// ExpandVLD - Translate VLD pseudo instructions with Q, QQ or QQQQ register
377 /// operands to real VLD instructions with D register operands.
378 void ARMExpandPseudo::ExpandVLD(MachineBasicBlock::iterator &MBBI) {
379 MachineInstr &MI = *MBBI;
380 MachineBasicBlock &MBB = *MI.getParent();
382 const NEONLdStTableEntry *TableEntry = LookupNEONLdSt(MI.getOpcode());
383 assert(TableEntry && TableEntry->IsLoad && "NEONLdStTable lookup failed");
384 NEONRegSpacing RegSpc = (NEONRegSpacing)TableEntry->RegSpacing;
385 unsigned NumRegs = TableEntry->NumRegs;
387 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(),
388 TII->get(TableEntry->RealOpc));
391 bool DstIsDead = MI.getOperand(OpIdx).isDead();
392 unsigned DstReg = MI.getOperand(OpIdx++).getReg();
393 unsigned D0, D1, D2, D3;
394 GetDSubRegs(DstReg, RegSpc, TRI, D0, D1, D2, D3);
395 MIB.addReg(D0, RegState::Define | getDeadRegState(DstIsDead));
396 if (NumRegs > 1 && TableEntry->copyAllListRegs)
397 MIB.addReg(D1, RegState::Define | getDeadRegState(DstIsDead));
398 if (NumRegs > 2 && TableEntry->copyAllListRegs)
399 MIB.addReg(D2, RegState::Define | getDeadRegState(DstIsDead));
400 if (NumRegs > 3 && TableEntry->copyAllListRegs)
401 MIB.addReg(D3, RegState::Define | getDeadRegState(DstIsDead));
403 if (TableEntry->isUpdating)
404 MIB.addOperand(MI.getOperand(OpIdx++));
406 // Copy the addrmode6 operands.
407 MIB.addOperand(MI.getOperand(OpIdx++));
408 MIB.addOperand(MI.getOperand(OpIdx++));
409 // Copy the am6offset operand.
410 if (TableEntry->hasWritebackOperand)
411 MIB.addOperand(MI.getOperand(OpIdx++));
413 // For an instruction writing double-spaced subregs, the pseudo instruction
414 // has an extra operand that is a use of the super-register. Record the
415 // operand index and skip over it.
416 unsigned SrcOpIdx = 0;
417 if (RegSpc == EvenDblSpc || RegSpc == OddDblSpc)
420 // Copy the predicate operands.
421 MIB.addOperand(MI.getOperand(OpIdx++));
422 MIB.addOperand(MI.getOperand(OpIdx++));
424 // Copy the super-register source operand used for double-spaced subregs over
425 // to the new instruction as an implicit operand.
427 MachineOperand MO = MI.getOperand(SrcOpIdx);
428 MO.setImplicit(true);
431 // Add an implicit def for the super-register.
432 MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead));
433 TransferImpOps(MI, MIB, MIB);
435 // Transfer memoperands.
436 MIB->setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
438 MI.eraseFromParent();
441 /// ExpandVST - Translate VST pseudo instructions with Q, QQ or QQQQ register
442 /// operands to real VST instructions with D register operands.
443 void ARMExpandPseudo::ExpandVST(MachineBasicBlock::iterator &MBBI) {
444 MachineInstr &MI = *MBBI;
445 MachineBasicBlock &MBB = *MI.getParent();
447 const NEONLdStTableEntry *TableEntry = LookupNEONLdSt(MI.getOpcode());
448 assert(TableEntry && !TableEntry->IsLoad && "NEONLdStTable lookup failed");
449 NEONRegSpacing RegSpc = (NEONRegSpacing)TableEntry->RegSpacing;
450 unsigned NumRegs = TableEntry->NumRegs;
452 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(),
453 TII->get(TableEntry->RealOpc));
455 if (TableEntry->isUpdating)
456 MIB.addOperand(MI.getOperand(OpIdx++));
458 // Copy the addrmode6 operands.
459 MIB.addOperand(MI.getOperand(OpIdx++));
460 MIB.addOperand(MI.getOperand(OpIdx++));
461 // Copy the am6offset operand.
462 if (TableEntry->hasWritebackOperand)
463 MIB.addOperand(MI.getOperand(OpIdx++));
465 bool SrcIsKill = MI.getOperand(OpIdx).isKill();
466 bool SrcIsUndef = MI.getOperand(OpIdx).isUndef();
467 unsigned SrcReg = MI.getOperand(OpIdx++).getReg();
468 unsigned D0, D1, D2, D3;
469 GetDSubRegs(SrcReg, RegSpc, TRI, D0, D1, D2, D3);
470 MIB.addReg(D0, getUndefRegState(SrcIsUndef));
471 if (NumRegs > 1 && TableEntry->copyAllListRegs)
472 MIB.addReg(D1, getUndefRegState(SrcIsUndef));
473 if (NumRegs > 2 && TableEntry->copyAllListRegs)
474 MIB.addReg(D2, getUndefRegState(SrcIsUndef));
475 if (NumRegs > 3 && TableEntry->copyAllListRegs)
476 MIB.addReg(D3, getUndefRegState(SrcIsUndef));
478 // Copy the predicate operands.
479 MIB.addOperand(MI.getOperand(OpIdx++));
480 MIB.addOperand(MI.getOperand(OpIdx++));
482 if (SrcIsKill && !SrcIsUndef) // Add an implicit kill for the super-reg.
483 MIB->addRegisterKilled(SrcReg, TRI, true);
484 else if (!SrcIsUndef)
485 MIB.addReg(SrcReg, RegState::Implicit); // Add implicit uses for src reg.
486 TransferImpOps(MI, MIB, MIB);
488 // Transfer memoperands.
489 MIB->setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
491 MI.eraseFromParent();
494 /// ExpandLaneOp - Translate VLD*LN and VST*LN instructions with Q, QQ or QQQQ
495 /// register operands to real instructions with D register operands.
496 void ARMExpandPseudo::ExpandLaneOp(MachineBasicBlock::iterator &MBBI) {
497 MachineInstr &MI = *MBBI;
498 MachineBasicBlock &MBB = *MI.getParent();
500 const NEONLdStTableEntry *TableEntry = LookupNEONLdSt(MI.getOpcode());
501 assert(TableEntry && "NEONLdStTable lookup failed");
502 NEONRegSpacing RegSpc = (NEONRegSpacing)TableEntry->RegSpacing;
503 unsigned NumRegs = TableEntry->NumRegs;
504 unsigned RegElts = TableEntry->RegElts;
506 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(),
507 TII->get(TableEntry->RealOpc));
509 // The lane operand is always the 3rd from last operand, before the 2
510 // predicate operands.
511 unsigned Lane = MI.getOperand(MI.getDesc().getNumOperands() - 3).getImm();
513 // Adjust the lane and spacing as needed for Q registers.
514 assert(RegSpc != OddDblSpc && "unexpected register spacing for VLD/VST-lane");
515 if (RegSpc == EvenDblSpc && Lane >= RegElts) {
519 assert(Lane < RegElts && "out of range lane for VLD/VST-lane");
521 unsigned D0 = 0, D1 = 0, D2 = 0, D3 = 0;
523 bool DstIsDead = false;
524 if (TableEntry->IsLoad) {
525 DstIsDead = MI.getOperand(OpIdx).isDead();
526 DstReg = MI.getOperand(OpIdx++).getReg();
527 GetDSubRegs(DstReg, RegSpc, TRI, D0, D1, D2, D3);
528 MIB.addReg(D0, RegState::Define | getDeadRegState(DstIsDead));
530 MIB.addReg(D1, RegState::Define | getDeadRegState(DstIsDead));
532 MIB.addReg(D2, RegState::Define | getDeadRegState(DstIsDead));
534 MIB.addReg(D3, RegState::Define | getDeadRegState(DstIsDead));
537 if (TableEntry->isUpdating)
538 MIB.addOperand(MI.getOperand(OpIdx++));
540 // Copy the addrmode6 operands.
541 MIB.addOperand(MI.getOperand(OpIdx++));
542 MIB.addOperand(MI.getOperand(OpIdx++));
543 // Copy the am6offset operand.
544 if (TableEntry->hasWritebackOperand)
545 MIB.addOperand(MI.getOperand(OpIdx++));
547 // Grab the super-register source.
548 MachineOperand MO = MI.getOperand(OpIdx++);
549 if (!TableEntry->IsLoad)
550 GetDSubRegs(MO.getReg(), RegSpc, TRI, D0, D1, D2, D3);
552 // Add the subregs as sources of the new instruction.
553 unsigned SrcFlags = (getUndefRegState(MO.isUndef()) |
554 getKillRegState(MO.isKill()));
555 MIB.addReg(D0, SrcFlags);
557 MIB.addReg(D1, SrcFlags);
559 MIB.addReg(D2, SrcFlags);
561 MIB.addReg(D3, SrcFlags);
563 // Add the lane number operand.
567 // Copy the predicate operands.
568 MIB.addOperand(MI.getOperand(OpIdx++));
569 MIB.addOperand(MI.getOperand(OpIdx++));
571 // Copy the super-register source to be an implicit source.
572 MO.setImplicit(true);
574 if (TableEntry->IsLoad)
575 // Add an implicit def for the super-register.
576 MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead));
577 TransferImpOps(MI, MIB, MIB);
578 // Transfer memoperands.
579 MIB->setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
580 MI.eraseFromParent();
583 /// ExpandVTBL - Translate VTBL and VTBX pseudo instructions with Q or QQ
584 /// register operands to real instructions with D register operands.
585 void ARMExpandPseudo::ExpandVTBL(MachineBasicBlock::iterator &MBBI,
586 unsigned Opc, bool IsExt) {
587 MachineInstr &MI = *MBBI;
588 MachineBasicBlock &MBB = *MI.getParent();
590 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(Opc));
593 // Transfer the destination register operand.
594 MIB.addOperand(MI.getOperand(OpIdx++));
596 MIB.addOperand(MI.getOperand(OpIdx++));
598 bool SrcIsKill = MI.getOperand(OpIdx).isKill();
599 unsigned SrcReg = MI.getOperand(OpIdx++).getReg();
600 unsigned D0, D1, D2, D3;
601 GetDSubRegs(SrcReg, SingleSpc, TRI, D0, D1, D2, D3);
604 // Copy the other source register operand.
605 MIB.addOperand(MI.getOperand(OpIdx++));
607 // Copy the predicate operands.
608 MIB.addOperand(MI.getOperand(OpIdx++));
609 MIB.addOperand(MI.getOperand(OpIdx++));
611 // Add an implicit kill and use for the super-reg.
612 MIB.addReg(SrcReg, RegState::Implicit | getKillRegState(SrcIsKill));
613 TransferImpOps(MI, MIB, MIB);
614 MI.eraseFromParent();
617 void ARMExpandPseudo::ExpandMOV32BitImm(MachineBasicBlock &MBB,
618 MachineBasicBlock::iterator &MBBI) {
619 MachineInstr &MI = *MBBI;
620 unsigned Opcode = MI.getOpcode();
621 unsigned PredReg = 0;
622 ARMCC::CondCodes Pred = getInstrPredicate(&MI, PredReg);
623 unsigned DstReg = MI.getOperand(0).getReg();
624 bool DstIsDead = MI.getOperand(0).isDead();
625 bool isCC = Opcode == ARM::MOVCCi32imm || Opcode == ARM::t2MOVCCi32imm;
626 const MachineOperand &MO = MI.getOperand(isCC ? 2 : 1);
627 MachineInstrBuilder LO16, HI16;
629 if (!STI->hasV6T2Ops() &&
630 (Opcode == ARM::MOVi32imm || Opcode == ARM::MOVCCi32imm)) {
631 // Expand into a movi + orr.
632 LO16 = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::MOVi), DstReg);
633 HI16 = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::ORRri))
634 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
637 assert (MO.isImm() && "MOVi32imm w/ non-immediate source operand!");
638 unsigned ImmVal = (unsigned)MO.getImm();
639 unsigned SOImmValV1 = ARM_AM::getSOImmTwoPartFirst(ImmVal);
640 unsigned SOImmValV2 = ARM_AM::getSOImmTwoPartSecond(ImmVal);
641 LO16 = LO16.addImm(SOImmValV1);
642 HI16 = HI16.addImm(SOImmValV2);
643 LO16->setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
644 HI16->setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
645 LO16.addImm(Pred).addReg(PredReg).addReg(0);
646 HI16.addImm(Pred).addReg(PredReg).addReg(0);
647 TransferImpOps(MI, LO16, HI16);
648 MI.eraseFromParent();
652 unsigned LO16Opc = 0;
653 unsigned HI16Opc = 0;
654 if (Opcode == ARM::t2MOVi32imm || Opcode == ARM::t2MOVCCi32imm) {
655 LO16Opc = ARM::t2MOVi16;
656 HI16Opc = ARM::t2MOVTi16;
658 LO16Opc = ARM::MOVi16;
659 HI16Opc = ARM::MOVTi16;
662 LO16 = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(LO16Opc), DstReg);
663 HI16 = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(HI16Opc))
664 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
668 unsigned Imm = MO.getImm();
669 unsigned Lo16 = Imm & 0xffff;
670 unsigned Hi16 = (Imm >> 16) & 0xffff;
671 LO16 = LO16.addImm(Lo16);
672 HI16 = HI16.addImm(Hi16);
674 const GlobalValue *GV = MO.getGlobal();
675 unsigned TF = MO.getTargetFlags();
676 LO16 = LO16.addGlobalAddress(GV, MO.getOffset(), TF | ARMII::MO_LO16);
677 HI16 = HI16.addGlobalAddress(GV, MO.getOffset(), TF | ARMII::MO_HI16);
680 LO16->setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
681 HI16->setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
682 LO16.addImm(Pred).addReg(PredReg);
683 HI16.addImm(Pred).addReg(PredReg);
685 TransferImpOps(MI, LO16, HI16);
686 MI.eraseFromParent();
689 bool ARMExpandPseudo::ExpandMI(MachineBasicBlock &MBB,
690 MachineBasicBlock::iterator MBBI) {
691 MachineInstr &MI = *MBBI;
692 unsigned Opcode = MI.getOpcode();
698 unsigned newOpc = Opcode == ARM::VMOVScc ? ARM::VMOVS : ARM::VMOVD;
699 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(newOpc),
700 MI.getOperand(1).getReg())
701 .addOperand(MI.getOperand(2))
702 .addImm(MI.getOperand(3).getImm()) // 'pred'
703 .addOperand(MI.getOperand(4));
705 MI.eraseFromParent();
710 unsigned Opc = AFI->isThumbFunction() ? ARM::t2MOVr : ARM::MOVr;
711 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(Opc),
712 MI.getOperand(1).getReg())
713 .addOperand(MI.getOperand(2))
714 .addImm(MI.getOperand(3).getImm()) // 'pred'
715 .addOperand(MI.getOperand(4))
716 .addReg(0); // 's' bit
718 MI.eraseFromParent();
722 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::MOVsi),
723 (MI.getOperand(1).getReg()))
724 .addOperand(MI.getOperand(2))
725 .addImm(MI.getOperand(3).getImm())
726 .addImm(MI.getOperand(4).getImm()) // 'pred'
727 .addOperand(MI.getOperand(5))
728 .addReg(0); // 's' bit
730 MI.eraseFromParent();
734 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::MOVsr),
735 (MI.getOperand(1).getReg()))
736 .addOperand(MI.getOperand(2))
737 .addOperand(MI.getOperand(3))
738 .addImm(MI.getOperand(4).getImm())
739 .addImm(MI.getOperand(5).getImm()) // 'pred'
740 .addOperand(MI.getOperand(6))
741 .addReg(0); // 's' bit
743 MI.eraseFromParent();
746 case ARM::t2MOVCCi16:
747 case ARM::MOVCCi16: {
748 unsigned NewOpc = AFI->isThumbFunction() ? ARM::t2MOVi16 : ARM::MOVi16;
749 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(NewOpc),
750 MI.getOperand(1).getReg())
751 .addImm(MI.getOperand(2).getImm())
752 .addImm(MI.getOperand(3).getImm()) // 'pred'
753 .addOperand(MI.getOperand(4));
754 MI.eraseFromParent();
759 unsigned Opc = AFI->isThumbFunction() ? ARM::t2MOVi : ARM::MOVi;
760 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(Opc),
761 MI.getOperand(1).getReg())
762 .addImm(MI.getOperand(2).getImm())
763 .addImm(MI.getOperand(3).getImm()) // 'pred'
764 .addOperand(MI.getOperand(4))
765 .addReg(0); // 's' bit
767 MI.eraseFromParent();
772 unsigned Opc = AFI->isThumbFunction() ? ARM::t2MVNi : ARM::MVNi;
773 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(Opc),
774 MI.getOperand(1).getReg())
775 .addImm(MI.getOperand(2).getImm())
776 .addImm(MI.getOperand(3).getImm()) // 'pred'
777 .addOperand(MI.getOperand(4))
778 .addReg(0); // 's' bit
780 MI.eraseFromParent();
783 case ARM::t2MOVCClsl:
784 case ARM::t2MOVCClsr:
785 case ARM::t2MOVCCasr:
786 case ARM::t2MOVCCror: {
789 case ARM::t2MOVCClsl: NewOpc = ARM::t2LSLri; break;
790 case ARM::t2MOVCClsr: NewOpc = ARM::t2LSRri; break;
791 case ARM::t2MOVCCasr: NewOpc = ARM::t2ASRri; break;
792 case ARM::t2MOVCCror: NewOpc = ARM::t2RORri; break;
793 default: llvm_unreachable("unexpeced conditional move");
795 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(NewOpc),
796 MI.getOperand(1).getReg())
797 .addOperand(MI.getOperand(2))
798 .addImm(MI.getOperand(3).getImm())
799 .addImm(MI.getOperand(4).getImm()) // 'pred'
800 .addOperand(MI.getOperand(5))
801 .addReg(0); // 's' bit
802 MI.eraseFromParent();
805 case ARM::Int_eh_sjlj_dispatchsetup: {
806 MachineFunction &MF = *MI.getParent()->getParent();
807 const ARMBaseInstrInfo *AII =
808 static_cast<const ARMBaseInstrInfo*>(TII);
809 const ARMBaseRegisterInfo &RI = AII->getRegisterInfo();
810 // For functions using a base pointer, we rematerialize it (via the frame
811 // pointer) here since eh.sjlj.setjmp and eh.sjlj.longjmp don't do it
812 // for us. Otherwise, expand to nothing.
813 if (RI.hasBasePointer(MF)) {
814 int32_t NumBytes = AFI->getFramePtrSpillOffset();
815 unsigned FramePtr = RI.getFrameRegister(MF);
816 assert(MF.getTarget().getFrameLowering()->hasFP(MF) &&
817 "base pointer without frame pointer?");
819 if (AFI->isThumb2Function()) {
820 emitT2RegPlusImmediate(MBB, MBBI, MI.getDebugLoc(), ARM::R6,
821 FramePtr, -NumBytes, ARMCC::AL, 0, *TII);
822 } else if (AFI->isThumbFunction()) {
823 emitThumbRegPlusImmediate(MBB, MBBI, MI.getDebugLoc(), ARM::R6,
824 FramePtr, -NumBytes, *TII, RI);
826 emitARMRegPlusImmediate(MBB, MBBI, MI.getDebugLoc(), ARM::R6,
827 FramePtr, -NumBytes, ARMCC::AL, 0,
830 // If there's dynamic realignment, adjust for it.
831 if (RI.needsStackRealignment(MF)) {
832 MachineFrameInfo *MFI = MF.getFrameInfo();
833 unsigned MaxAlign = MFI->getMaxAlignment();
834 assert (!AFI->isThumb1OnlyFunction());
835 // Emit bic r6, r6, MaxAlign
836 unsigned bicOpc = AFI->isThumbFunction() ?
837 ARM::t2BICri : ARM::BICri;
838 AddDefaultCC(AddDefaultPred(BuildMI(MBB, MBBI, MI.getDebugLoc(),
839 TII->get(bicOpc), ARM::R6)
840 .addReg(ARM::R6, RegState::Kill)
841 .addImm(MaxAlign-1)));
845 MI.eraseFromParent();
849 case ARM::MOVsrl_flag:
850 case ARM::MOVsra_flag: {
851 // These are just fancy MOVs instructions.
852 AddDefaultPred(BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::MOVsi),
853 MI.getOperand(0).getReg())
854 .addOperand(MI.getOperand(1))
855 .addImm(ARM_AM::getSORegOpc((Opcode == ARM::MOVsrl_flag ?
856 ARM_AM::lsr : ARM_AM::asr),
858 .addReg(ARM::CPSR, RegState::Define);
859 MI.eraseFromParent();
863 // This encodes as "MOVs Rd, Rm, rrx
864 MachineInstrBuilder MIB =
865 AddDefaultPred(BuildMI(MBB, MBBI, MI.getDebugLoc(),TII->get(ARM::MOVsi),
866 MI.getOperand(0).getReg())
867 .addOperand(MI.getOperand(1))
868 .addImm(ARM_AM::getSORegOpc(ARM_AM::rrx, 0)))
870 TransferImpOps(MI, MIB, MIB);
871 MI.eraseFromParent();
876 MachineInstrBuilder MIB =
877 BuildMI(MBB, MBBI, MI.getDebugLoc(),
878 TII->get(Opcode == ARM::tTPsoft ? ARM::tBL : ARM::BL))
879 .addExternalSymbol("__aeabi_read_tp", 0);
881 MIB->setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
882 TransferImpOps(MI, MIB, MIB);
883 MI.eraseFromParent();
886 case ARM::tLDRpci_pic:
887 case ARM::t2LDRpci_pic: {
888 unsigned NewLdOpc = (Opcode == ARM::tLDRpci_pic)
889 ? ARM::tLDRpci : ARM::t2LDRpci;
890 unsigned DstReg = MI.getOperand(0).getReg();
891 bool DstIsDead = MI.getOperand(0).isDead();
892 MachineInstrBuilder MIB1 =
893 AddDefaultPred(BuildMI(MBB, MBBI, MI.getDebugLoc(),
894 TII->get(NewLdOpc), DstReg)
895 .addOperand(MI.getOperand(1)));
896 MIB1->setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
897 MachineInstrBuilder MIB2 = BuildMI(MBB, MBBI, MI.getDebugLoc(),
898 TII->get(ARM::tPICADD))
899 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
901 .addOperand(MI.getOperand(2));
902 TransferImpOps(MI, MIB1, MIB2);
903 MI.eraseFromParent();
907 case ARM::LDRLIT_ga_abs:
908 case ARM::LDRLIT_ga_pcrel:
909 case ARM::LDRLIT_ga_pcrel_ldr:
910 case ARM::tLDRLIT_ga_abs:
911 case ARM::tLDRLIT_ga_pcrel: {
912 unsigned DstReg = MI.getOperand(0).getReg();
913 bool DstIsDead = MI.getOperand(0).isDead();
914 const MachineOperand &MO1 = MI.getOperand(1);
915 const GlobalValue *GV = MO1.getGlobal();
917 Opcode != ARM::tLDRLIT_ga_pcrel && Opcode != ARM::tLDRLIT_ga_abs;
919 Opcode != ARM::LDRLIT_ga_abs && Opcode != ARM::tLDRLIT_ga_abs;
920 unsigned LDRLITOpc = IsARM ? ARM::LDRi12 : ARM::tLDRpci;
923 ? (Opcode == ARM::LDRLIT_ga_pcrel_ldr ? ARM::PICADD : ARM::PICLDR)
926 // We need a new const-pool entry to load from.
927 MachineConstantPool *MCP = MBB.getParent()->getConstantPool();
928 unsigned ARMPCLabelIndex = 0;
929 MachineConstantPoolValue *CPV;
932 unsigned PCAdj = IsARM ? 8 : 4;
933 ARMPCLabelIndex = AFI->createPICLabelUId();
934 CPV = ARMConstantPoolConstant::Create(GV, ARMPCLabelIndex,
935 ARMCP::CPValue, PCAdj);
937 CPV = ARMConstantPoolConstant::Create(GV, ARMCP::no_modifier);
939 MachineInstrBuilder MIB =
940 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(LDRLITOpc), DstReg)
941 .addConstantPoolIndex(MCP->getConstantPoolIndex(CPV, 4));
947 MachineInstrBuilder MIB =
948 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(PICAddOpc))
949 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
951 .addImm(ARMPCLabelIndex);
957 MI.eraseFromParent();
960 case ARM::MOV_ga_pcrel:
961 case ARM::MOV_ga_pcrel_ldr:
962 case ARM::t2MOV_ga_pcrel: {
963 // Expand into movw + movw. Also "add pc" / ldr [pc] in PIC mode.
964 unsigned LabelId = AFI->createPICLabelUId();
965 unsigned DstReg = MI.getOperand(0).getReg();
966 bool DstIsDead = MI.getOperand(0).isDead();
967 const MachineOperand &MO1 = MI.getOperand(1);
968 const GlobalValue *GV = MO1.getGlobal();
969 unsigned TF = MO1.getTargetFlags();
970 bool isARM = Opcode != ARM::t2MOV_ga_pcrel;
971 unsigned LO16Opc = isARM ? ARM::MOVi16_ga_pcrel : ARM::t2MOVi16_ga_pcrel;
972 unsigned HI16Opc = isARM ? ARM::MOVTi16_ga_pcrel :ARM::t2MOVTi16_ga_pcrel;
973 unsigned LO16TF = TF | ARMII::MO_LO16;
974 unsigned HI16TF = TF | ARMII::MO_HI16;
975 unsigned PICAddOpc = isARM
976 ? (Opcode == ARM::MOV_ga_pcrel_ldr ? ARM::PICLDR : ARM::PICADD)
978 MachineInstrBuilder MIB1 = BuildMI(MBB, MBBI, MI.getDebugLoc(),
979 TII->get(LO16Opc), DstReg)
980 .addGlobalAddress(GV, MO1.getOffset(), TF | LO16TF)
983 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(HI16Opc), DstReg)
985 .addGlobalAddress(GV, MO1.getOffset(), TF | HI16TF)
988 MachineInstrBuilder MIB3 = BuildMI(MBB, MBBI, MI.getDebugLoc(),
990 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
991 .addReg(DstReg).addImm(LabelId);
993 AddDefaultPred(MIB3);
994 if (Opcode == ARM::MOV_ga_pcrel_ldr)
995 MIB3->setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
997 TransferImpOps(MI, MIB1, MIB3);
998 MI.eraseFromParent();
1002 case ARM::MOVi32imm:
1003 case ARM::MOVCCi32imm:
1004 case ARM::t2MOVi32imm:
1005 case ARM::t2MOVCCi32imm:
1006 ExpandMOV32BitImm(MBB, MBBI);
1009 case ARM::SUBS_PC_LR: {
1010 MachineInstrBuilder MIB =
1011 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::SUBri), ARM::PC)
1013 .addOperand(MI.getOperand(0))
1014 .addOperand(MI.getOperand(1))
1015 .addOperand(MI.getOperand(2))
1016 .addReg(ARM::CPSR, RegState::Undef);
1017 TransferImpOps(MI, MIB, MIB);
1018 MI.eraseFromParent();
1021 case ARM::VLDMQIA: {
1022 unsigned NewOpc = ARM::VLDMDIA;
1023 MachineInstrBuilder MIB =
1024 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(NewOpc));
1027 // Grab the Q register destination.
1028 bool DstIsDead = MI.getOperand(OpIdx).isDead();
1029 unsigned DstReg = MI.getOperand(OpIdx++).getReg();
1031 // Copy the source register.
1032 MIB.addOperand(MI.getOperand(OpIdx++));
1034 // Copy the predicate operands.
1035 MIB.addOperand(MI.getOperand(OpIdx++));
1036 MIB.addOperand(MI.getOperand(OpIdx++));
1038 // Add the destination operands (D subregs).
1039 unsigned D0 = TRI->getSubReg(DstReg, ARM::dsub_0);
1040 unsigned D1 = TRI->getSubReg(DstReg, ARM::dsub_1);
1041 MIB.addReg(D0, RegState::Define | getDeadRegState(DstIsDead))
1042 .addReg(D1, RegState::Define | getDeadRegState(DstIsDead));
1044 // Add an implicit def for the super-register.
1045 MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead));
1046 TransferImpOps(MI, MIB, MIB);
1047 MIB.setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
1048 MI.eraseFromParent();
1052 case ARM::VSTMQIA: {
1053 unsigned NewOpc = ARM::VSTMDIA;
1054 MachineInstrBuilder MIB =
1055 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(NewOpc));
1058 // Grab the Q register source.
1059 bool SrcIsKill = MI.getOperand(OpIdx).isKill();
1060 unsigned SrcReg = MI.getOperand(OpIdx++).getReg();
1062 // Copy the destination register.
1063 MIB.addOperand(MI.getOperand(OpIdx++));
1065 // Copy the predicate operands.
1066 MIB.addOperand(MI.getOperand(OpIdx++));
1067 MIB.addOperand(MI.getOperand(OpIdx++));
1069 // Add the source operands (D subregs).
1070 unsigned D0 = TRI->getSubReg(SrcReg, ARM::dsub_0);
1071 unsigned D1 = TRI->getSubReg(SrcReg, ARM::dsub_1);
1072 MIB.addReg(D0).addReg(D1);
1074 if (SrcIsKill) // Add an implicit kill for the Q register.
1075 MIB->addRegisterKilled(SrcReg, TRI, true);
1077 TransferImpOps(MI, MIB, MIB);
1078 MIB.setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
1079 MI.eraseFromParent();
1083 case ARM::VLD2q8Pseudo:
1084 case ARM::VLD2q16Pseudo:
1085 case ARM::VLD2q32Pseudo:
1086 case ARM::VLD2q8PseudoWB_fixed:
1087 case ARM::VLD2q16PseudoWB_fixed:
1088 case ARM::VLD2q32PseudoWB_fixed:
1089 case ARM::VLD2q8PseudoWB_register:
1090 case ARM::VLD2q16PseudoWB_register:
1091 case ARM::VLD2q32PseudoWB_register:
1092 case ARM::VLD3d8Pseudo:
1093 case ARM::VLD3d16Pseudo:
1094 case ARM::VLD3d32Pseudo:
1095 case ARM::VLD1d64TPseudo:
1096 case ARM::VLD1d64TPseudoWB_fixed:
1097 case ARM::VLD3d8Pseudo_UPD:
1098 case ARM::VLD3d16Pseudo_UPD:
1099 case ARM::VLD3d32Pseudo_UPD:
1100 case ARM::VLD3q8Pseudo_UPD:
1101 case ARM::VLD3q16Pseudo_UPD:
1102 case ARM::VLD3q32Pseudo_UPD:
1103 case ARM::VLD3q8oddPseudo:
1104 case ARM::VLD3q16oddPseudo:
1105 case ARM::VLD3q32oddPseudo:
1106 case ARM::VLD3q8oddPseudo_UPD:
1107 case ARM::VLD3q16oddPseudo_UPD:
1108 case ARM::VLD3q32oddPseudo_UPD:
1109 case ARM::VLD4d8Pseudo:
1110 case ARM::VLD4d16Pseudo:
1111 case ARM::VLD4d32Pseudo:
1112 case ARM::VLD1d64QPseudo:
1113 case ARM::VLD1d64QPseudoWB_fixed:
1114 case ARM::VLD4d8Pseudo_UPD:
1115 case ARM::VLD4d16Pseudo_UPD:
1116 case ARM::VLD4d32Pseudo_UPD:
1117 case ARM::VLD4q8Pseudo_UPD:
1118 case ARM::VLD4q16Pseudo_UPD:
1119 case ARM::VLD4q32Pseudo_UPD:
1120 case ARM::VLD4q8oddPseudo:
1121 case ARM::VLD4q16oddPseudo:
1122 case ARM::VLD4q32oddPseudo:
1123 case ARM::VLD4q8oddPseudo_UPD:
1124 case ARM::VLD4q16oddPseudo_UPD:
1125 case ARM::VLD4q32oddPseudo_UPD:
1126 case ARM::VLD3DUPd8Pseudo:
1127 case ARM::VLD3DUPd16Pseudo:
1128 case ARM::VLD3DUPd32Pseudo:
1129 case ARM::VLD3DUPd8Pseudo_UPD:
1130 case ARM::VLD3DUPd16Pseudo_UPD:
1131 case ARM::VLD3DUPd32Pseudo_UPD:
1132 case ARM::VLD4DUPd8Pseudo:
1133 case ARM::VLD4DUPd16Pseudo:
1134 case ARM::VLD4DUPd32Pseudo:
1135 case ARM::VLD4DUPd8Pseudo_UPD:
1136 case ARM::VLD4DUPd16Pseudo_UPD:
1137 case ARM::VLD4DUPd32Pseudo_UPD:
1141 case ARM::VST2q8Pseudo:
1142 case ARM::VST2q16Pseudo:
1143 case ARM::VST2q32Pseudo:
1144 case ARM::VST2q8PseudoWB_fixed:
1145 case ARM::VST2q16PseudoWB_fixed:
1146 case ARM::VST2q32PseudoWB_fixed:
1147 case ARM::VST2q8PseudoWB_register:
1148 case ARM::VST2q16PseudoWB_register:
1149 case ARM::VST2q32PseudoWB_register:
1150 case ARM::VST3d8Pseudo:
1151 case ARM::VST3d16Pseudo:
1152 case ARM::VST3d32Pseudo:
1153 case ARM::VST1d64TPseudo:
1154 case ARM::VST3d8Pseudo_UPD:
1155 case ARM::VST3d16Pseudo_UPD:
1156 case ARM::VST3d32Pseudo_UPD:
1157 case ARM::VST1d64TPseudoWB_fixed:
1158 case ARM::VST1d64TPseudoWB_register:
1159 case ARM::VST3q8Pseudo_UPD:
1160 case ARM::VST3q16Pseudo_UPD:
1161 case ARM::VST3q32Pseudo_UPD:
1162 case ARM::VST3q8oddPseudo:
1163 case ARM::VST3q16oddPseudo:
1164 case ARM::VST3q32oddPseudo:
1165 case ARM::VST3q8oddPseudo_UPD:
1166 case ARM::VST3q16oddPseudo_UPD:
1167 case ARM::VST3q32oddPseudo_UPD:
1168 case ARM::VST4d8Pseudo:
1169 case ARM::VST4d16Pseudo:
1170 case ARM::VST4d32Pseudo:
1171 case ARM::VST1d64QPseudo:
1172 case ARM::VST4d8Pseudo_UPD:
1173 case ARM::VST4d16Pseudo_UPD:
1174 case ARM::VST4d32Pseudo_UPD:
1175 case ARM::VST1d64QPseudoWB_fixed:
1176 case ARM::VST1d64QPseudoWB_register:
1177 case ARM::VST4q8Pseudo_UPD:
1178 case ARM::VST4q16Pseudo_UPD:
1179 case ARM::VST4q32Pseudo_UPD:
1180 case ARM::VST4q8oddPseudo:
1181 case ARM::VST4q16oddPseudo:
1182 case ARM::VST4q32oddPseudo:
1183 case ARM::VST4q8oddPseudo_UPD:
1184 case ARM::VST4q16oddPseudo_UPD:
1185 case ARM::VST4q32oddPseudo_UPD:
1189 case ARM::VLD1LNq8Pseudo:
1190 case ARM::VLD1LNq16Pseudo:
1191 case ARM::VLD1LNq32Pseudo:
1192 case ARM::VLD1LNq8Pseudo_UPD:
1193 case ARM::VLD1LNq16Pseudo_UPD:
1194 case ARM::VLD1LNq32Pseudo_UPD:
1195 case ARM::VLD2LNd8Pseudo:
1196 case ARM::VLD2LNd16Pseudo:
1197 case ARM::VLD2LNd32Pseudo:
1198 case ARM::VLD2LNq16Pseudo:
1199 case ARM::VLD2LNq32Pseudo:
1200 case ARM::VLD2LNd8Pseudo_UPD:
1201 case ARM::VLD2LNd16Pseudo_UPD:
1202 case ARM::VLD2LNd32Pseudo_UPD:
1203 case ARM::VLD2LNq16Pseudo_UPD:
1204 case ARM::VLD2LNq32Pseudo_UPD:
1205 case ARM::VLD3LNd8Pseudo:
1206 case ARM::VLD3LNd16Pseudo:
1207 case ARM::VLD3LNd32Pseudo:
1208 case ARM::VLD3LNq16Pseudo:
1209 case ARM::VLD3LNq32Pseudo:
1210 case ARM::VLD3LNd8Pseudo_UPD:
1211 case ARM::VLD3LNd16Pseudo_UPD:
1212 case ARM::VLD3LNd32Pseudo_UPD:
1213 case ARM::VLD3LNq16Pseudo_UPD:
1214 case ARM::VLD3LNq32Pseudo_UPD:
1215 case ARM::VLD4LNd8Pseudo:
1216 case ARM::VLD4LNd16Pseudo:
1217 case ARM::VLD4LNd32Pseudo:
1218 case ARM::VLD4LNq16Pseudo:
1219 case ARM::VLD4LNq32Pseudo:
1220 case ARM::VLD4LNd8Pseudo_UPD:
1221 case ARM::VLD4LNd16Pseudo_UPD:
1222 case ARM::VLD4LNd32Pseudo_UPD:
1223 case ARM::VLD4LNq16Pseudo_UPD:
1224 case ARM::VLD4LNq32Pseudo_UPD:
1225 case ARM::VST1LNq8Pseudo:
1226 case ARM::VST1LNq16Pseudo:
1227 case ARM::VST1LNq32Pseudo:
1228 case ARM::VST1LNq8Pseudo_UPD:
1229 case ARM::VST1LNq16Pseudo_UPD:
1230 case ARM::VST1LNq32Pseudo_UPD:
1231 case ARM::VST2LNd8Pseudo:
1232 case ARM::VST2LNd16Pseudo:
1233 case ARM::VST2LNd32Pseudo:
1234 case ARM::VST2LNq16Pseudo:
1235 case ARM::VST2LNq32Pseudo:
1236 case ARM::VST2LNd8Pseudo_UPD:
1237 case ARM::VST2LNd16Pseudo_UPD:
1238 case ARM::VST2LNd32Pseudo_UPD:
1239 case ARM::VST2LNq16Pseudo_UPD:
1240 case ARM::VST2LNq32Pseudo_UPD:
1241 case ARM::VST3LNd8Pseudo:
1242 case ARM::VST3LNd16Pseudo:
1243 case ARM::VST3LNd32Pseudo:
1244 case ARM::VST3LNq16Pseudo:
1245 case ARM::VST3LNq32Pseudo:
1246 case ARM::VST3LNd8Pseudo_UPD:
1247 case ARM::VST3LNd16Pseudo_UPD:
1248 case ARM::VST3LNd32Pseudo_UPD:
1249 case ARM::VST3LNq16Pseudo_UPD:
1250 case ARM::VST3LNq32Pseudo_UPD:
1251 case ARM::VST4LNd8Pseudo:
1252 case ARM::VST4LNd16Pseudo:
1253 case ARM::VST4LNd32Pseudo:
1254 case ARM::VST4LNq16Pseudo:
1255 case ARM::VST4LNq32Pseudo:
1256 case ARM::VST4LNd8Pseudo_UPD:
1257 case ARM::VST4LNd16Pseudo_UPD:
1258 case ARM::VST4LNd32Pseudo_UPD:
1259 case ARM::VST4LNq16Pseudo_UPD:
1260 case ARM::VST4LNq32Pseudo_UPD:
1264 case ARM::VTBL3Pseudo: ExpandVTBL(MBBI, ARM::VTBL3, false); return true;
1265 case ARM::VTBL4Pseudo: ExpandVTBL(MBBI, ARM::VTBL4, false); return true;
1266 case ARM::VTBX3Pseudo: ExpandVTBL(MBBI, ARM::VTBX3, true); return true;
1267 case ARM::VTBX4Pseudo: ExpandVTBL(MBBI, ARM::VTBX4, true); return true;
1271 bool ARMExpandPseudo::ExpandMBB(MachineBasicBlock &MBB) {
1272 bool Modified = false;
1274 MachineBasicBlock::iterator MBBI = MBB.begin(), E = MBB.end();
1276 MachineBasicBlock::iterator NMBBI = llvm::next(MBBI);
1277 Modified |= ExpandMI(MBB, MBBI);
1284 bool ARMExpandPseudo::runOnMachineFunction(MachineFunction &MF) {
1285 const TargetMachine &TM = MF.getTarget();
1286 TII = static_cast<const ARMBaseInstrInfo*>(TM.getInstrInfo());
1287 TRI = TM.getRegisterInfo();
1288 STI = &TM.getSubtarget<ARMSubtarget>();
1289 AFI = MF.getInfo<ARMFunctionInfo>();
1291 bool Modified = false;
1292 for (MachineFunction::iterator MFI = MF.begin(), E = MF.end(); MFI != E;
1294 Modified |= ExpandMBB(*MFI);
1295 if (VerifyARMPseudo)
1296 MF.verify(this, "After expanding ARM pseudo instructions.");
1300 /// createARMExpandPseudoPass - returns an instance of the pseudo instruction
1302 FunctionPass *llvm::createARMExpandPseudoPass() {
1303 return new ARMExpandPseudo();