1 //===-- ARM/ARMCodeEmitter.cpp - Convert ARM code to machine code ---------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the pass that transforms the ARM machine instructions into
11 // relocatable machine code.
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "jit"
17 #include "ARMAddressingModes.h"
18 #include "ARMConstantPoolValue.h"
19 #include "ARMInstrInfo.h"
20 #include "ARMRelocations.h"
21 #include "ARMSubtarget.h"
22 #include "ARMTargetMachine.h"
23 #include "llvm/Constants.h"
24 #include "llvm/DerivedTypes.h"
25 #include "llvm/Function.h"
26 #include "llvm/PassManager.h"
27 #include "llvm/CodeGen/JITCodeEmitter.h"
28 #include "llvm/CodeGen/MachineConstantPool.h"
29 #include "llvm/CodeGen/MachineFunctionPass.h"
30 #include "llvm/CodeGen/MachineInstr.h"
31 #include "llvm/CodeGen/MachineJumpTableInfo.h"
32 #include "llvm/CodeGen/MachineModuleInfo.h"
33 #include "llvm/CodeGen/Passes.h"
34 #include "llvm/ADT/Statistic.h"
35 #include "llvm/Support/Debug.h"
36 #include "llvm/Support/ErrorHandling.h"
37 #include "llvm/Support/raw_ostream.h"
43 STATISTIC(NumEmitted, "Number of machine instructions emitted");
47 class ARMCodeEmitter : public MachineFunctionPass {
49 const ARMInstrInfo *II;
51 const ARMSubtarget *Subtarget;
54 MachineModuleInfo *MMI;
55 const std::vector<MachineConstantPoolEntry> *MCPEs;
56 const std::vector<MachineJumpTableEntry> *MJTEs;
60 void getAnalysisUsage(AnalysisUsage &AU) const {
61 AU.addRequired<MachineModuleInfo>();
62 MachineFunctionPass::getAnalysisUsage(AU);
67 ARMCodeEmitter(TargetMachine &tm, JITCodeEmitter &mce)
68 : MachineFunctionPass(ID), JTI(0),
69 II((const ARMInstrInfo *)tm.getInstrInfo()),
70 TD(tm.getTargetData()), TM(tm),
71 MCE(mce), MCPEs(0), MJTEs(0),
72 IsPIC(TM.getRelocationModel() == Reloc::PIC_), IsThumb(false) {}
74 /// getBinaryCodeForInstr - This function, generated by the
75 /// CodeEmitterGenerator using TableGen, produces the binary encoding for
76 /// machine instructions.
77 unsigned getBinaryCodeForInstr(const MachineInstr &MI) const;
79 bool runOnMachineFunction(MachineFunction &MF);
81 virtual const char *getPassName() const {
82 return "ARM Machine Code Emitter";
85 void emitInstruction(const MachineInstr &MI);
89 void emitWordLE(unsigned Binary);
90 void emitDWordLE(uint64_t Binary);
91 void emitConstPoolInstruction(const MachineInstr &MI);
92 void emitMOVi32immInstruction(const MachineInstr &MI);
93 void emitMOVi2piecesInstruction(const MachineInstr &MI);
94 void emitLEApcrelJTInstruction(const MachineInstr &MI);
95 void emitPseudoMoveInstruction(const MachineInstr &MI);
96 void addPCLabel(unsigned LabelID);
97 void emitPseudoInstruction(const MachineInstr &MI);
98 unsigned getMachineSoRegOpValue(const MachineInstr &MI,
99 const TargetInstrDesc &TID,
100 const MachineOperand &MO,
103 unsigned getMachineSoImmOpValue(unsigned SoImm);
104 unsigned getAddrModeSBit(const MachineInstr &MI,
105 const TargetInstrDesc &TID) const;
107 void emitDataProcessingInstruction(const MachineInstr &MI,
108 unsigned ImplicitRd = 0,
109 unsigned ImplicitRn = 0);
111 void emitLoadStoreInstruction(const MachineInstr &MI,
112 unsigned ImplicitRd = 0,
113 unsigned ImplicitRn = 0);
115 void emitMiscLoadStoreInstruction(const MachineInstr &MI,
116 unsigned ImplicitRn = 0);
118 void emitLoadStoreMultipleInstruction(const MachineInstr &MI);
120 void emitMulFrmInstruction(const MachineInstr &MI);
122 void emitExtendInstruction(const MachineInstr &MI);
124 void emitMiscArithInstruction(const MachineInstr &MI);
126 void emitSaturateInstruction(const MachineInstr &MI);
128 void emitBranchInstruction(const MachineInstr &MI);
130 void emitInlineJumpTable(unsigned JTIndex);
132 void emitMiscBranchInstruction(const MachineInstr &MI);
134 void emitVFPArithInstruction(const MachineInstr &MI);
136 void emitVFPConversionInstruction(const MachineInstr &MI);
138 void emitVFPLoadStoreInstruction(const MachineInstr &MI);
140 void emitVFPLoadStoreMultipleInstruction(const MachineInstr &MI);
142 void emitNEONLaneInstruction(const MachineInstr &MI);
143 void emitNEONDupInstruction(const MachineInstr &MI);
144 void emitNEON1RegModImmInstruction(const MachineInstr &MI);
145 void emitNEON2RegInstruction(const MachineInstr &MI);
146 void emitNEON3RegInstruction(const MachineInstr &MI);
148 /// getMachineOpValue - Return binary encoding of operand. If the machine
149 /// operand requires relocation, record the relocation and return zero.
150 unsigned getMachineOpValue(const MachineInstr &MI,
151 const MachineOperand &MO) const;
152 unsigned getMachineOpValue(const MachineInstr &MI, unsigned OpIdx) const {
153 return getMachineOpValue(MI, MI.getOperand(OpIdx));
156 // FIXME: The legacy JIT ARMCodeEmitter doesn't rely on the the
157 // TableGen'erated getBinaryCodeForInstr() function to encode any
158 // operand values, instead querying getMachineOpValue() directly for
159 // each operand it needs to encode. Thus, any of the new encoder
160 // helper functions can simply return 0 as the values the return
161 // are already handled elsewhere. They are placeholders to allow this
162 // encoder to continue to function until the MC encoder is sufficiently
163 // far along that this one can be eliminated entirely.
164 unsigned NEONThumb2DataIPostEncoder(const MachineInstr &MI, unsigned Val)
166 unsigned NEONThumb2LoadStorePostEncoder(const MachineInstr &MI,unsigned Val)
168 unsigned NEONThumb2DupPostEncoder(const MachineInstr &MI,unsigned Val)
170 unsigned getBranchTargetOpValue(const MachineInstr &MI, unsigned Op)
172 unsigned getCCOutOpValue(const MachineInstr &MI, unsigned Op)
174 unsigned getSOImmOpValue(const MachineInstr &MI, unsigned Op)
176 unsigned getT2SOImmOpValue(const MachineInstr &MI, unsigned Op)
178 unsigned getSORegOpValue(const MachineInstr &MI, unsigned Op)
180 unsigned getT2SORegOpValue(const MachineInstr &MI, unsigned Op)
182 unsigned getRotImmOpValue(const MachineInstr &MI, unsigned Op)
184 unsigned getImmMinusOneOpValue(const MachineInstr &MI, unsigned Op)
186 unsigned getAddrMode6AddressOpValue(const MachineInstr &MI, unsigned Op)
188 unsigned getAddrMode6OffsetOpValue(const MachineInstr &MI, unsigned Op)
190 unsigned getBitfieldInvertedMaskOpValue(const MachineInstr &MI,
191 unsigned Op) const { return 0; }
192 uint32_t getLdStmModeOpValue(const MachineInstr &MI, unsigned OpIdx)
194 uint32_t getLdStSORegOpValue(const MachineInstr &MI, unsigned OpIdx)
197 unsigned getAddrModeImm12OpValue(const MachineInstr &MI, unsigned Op)
200 // {12} = (U)nsigned (add == '1', sub == '0')
202 const MachineOperand &MO = MI.getOperand(Op);
203 const MachineOperand &MO1 = MI.getOperand(Op + 1);
205 emitConstPoolAddress(MO.getIndex(), ARM::reloc_arm_cp_entry);
208 unsigned Reg = getARMRegisterNumbering(MO.getReg());
209 int32_t Imm12 = MO1.getImm();
211 Binary = Imm12 & 0xfff;
214 Binary |= (Reg << 13);
218 unsigned getMovtImmOpValue(const MachineInstr &MI, unsigned Op) const {
222 uint32_t getAddrMode2OpValue(const MachineInstr &MI, unsigned OpIdx)
224 uint32_t getAddrMode2OffsetOpValue(const MachineInstr &MI, unsigned OpIdx)
226 uint32_t getAddrMode3OffsetOpValue(const MachineInstr &MI, unsigned OpIdx)
228 uint32_t getAddrMode3OpValue(const MachineInstr &MI, unsigned Op) const
230 uint32_t getAddrMode5OpValue(const MachineInstr &MI, unsigned Op) const {
232 // {8} = (U)nsigned (add == '1', sub == '0')
234 const MachineOperand &MO = MI.getOperand(Op);
235 const MachineOperand &MO1 = MI.getOperand(Op + 1);
237 emitConstPoolAddress(MO.getIndex(), ARM::reloc_arm_cp_entry);
240 unsigned Reg = getARMRegisterNumbering(MO.getReg());
241 int32_t Imm8 = MO1.getImm();
243 Binary = Imm8 & 0xff;
246 Binary |= (Reg << 9);
249 unsigned getNEONVcvtImm32OpValue(const MachineInstr &MI, unsigned Op)
252 unsigned getRegisterListOpValue(const MachineInstr &MI, unsigned Op)
255 /// getMovi32Value - Return binary encoding of operand for movw/movt. If the
256 /// machine operand requires relocation, record the relocation and return
258 unsigned getMovi32Value(const MachineInstr &MI,const MachineOperand &MO,
261 /// getShiftOp - Return the shift opcode (bit[6:5]) of the immediate value.
263 unsigned getShiftOp(unsigned Imm) const ;
265 /// Routines that handle operands which add machine relocations which are
266 /// fixed up by the relocation stage.
267 void emitGlobalAddress(const GlobalValue *GV, unsigned Reloc,
268 bool MayNeedFarStub, bool Indirect,
269 intptr_t ACPV = 0) const;
270 void emitExternalSymbolAddress(const char *ES, unsigned Reloc) const;
271 void emitConstPoolAddress(unsigned CPI, unsigned Reloc) const;
272 void emitJumpTableAddress(unsigned JTIndex, unsigned Reloc) const;
273 void emitMachineBasicBlock(MachineBasicBlock *BB, unsigned Reloc,
274 intptr_t JTBase = 0) const;
278 char ARMCodeEmitter::ID = 0;
280 /// createARMJITCodeEmitterPass - Return a pass that emits the collected ARM
281 /// code to the specified MCE object.
282 FunctionPass *llvm::createARMJITCodeEmitterPass(ARMBaseTargetMachine &TM,
283 JITCodeEmitter &JCE) {
284 return new ARMCodeEmitter(TM, JCE);
287 bool ARMCodeEmitter::runOnMachineFunction(MachineFunction &MF) {
288 assert((MF.getTarget().getRelocationModel() != Reloc::Default ||
289 MF.getTarget().getRelocationModel() != Reloc::Static) &&
290 "JIT relocation model must be set to static or default!");
291 JTI = ((ARMTargetMachine &)MF.getTarget()).getJITInfo();
292 II = ((const ARMTargetMachine &)MF.getTarget()).getInstrInfo();
293 TD = ((const ARMTargetMachine &)MF.getTarget()).getTargetData();
294 Subtarget = &TM.getSubtarget<ARMSubtarget>();
295 MCPEs = &MF.getConstantPool()->getConstants();
297 if (MF.getJumpTableInfo()) MJTEs = &MF.getJumpTableInfo()->getJumpTables();
298 IsPIC = TM.getRelocationModel() == Reloc::PIC_;
299 IsThumb = MF.getInfo<ARMFunctionInfo>()->isThumbFunction();
300 JTI->Initialize(MF, IsPIC);
301 MMI = &getAnalysis<MachineModuleInfo>();
302 MCE.setModuleInfo(MMI);
305 DEBUG(errs() << "JITTing function '"
306 << MF.getFunction()->getName() << "'\n");
307 MCE.startFunction(MF);
308 for (MachineFunction::iterator MBB = MF.begin(), E = MF.end();
310 MCE.StartMachineBasicBlock(MBB);
311 for (MachineBasicBlock::const_iterator I = MBB->begin(), E = MBB->end();
315 } while (MCE.finishFunction(MF));
320 /// getShiftOp - Return the shift opcode (bit[6:5]) of the immediate value.
322 unsigned ARMCodeEmitter::getShiftOp(unsigned Imm) const {
323 switch (ARM_AM::getAM2ShiftOpc(Imm)) {
324 default: llvm_unreachable("Unknown shift opc!");
325 case ARM_AM::asr: return 2;
326 case ARM_AM::lsl: return 0;
327 case ARM_AM::lsr: return 1;
329 case ARM_AM::rrx: return 3;
334 /// getMovi32Value - Return binary encoding of operand for movw/movt. If the
335 /// machine operand requires relocation, record the relocation and return zero.
336 unsigned ARMCodeEmitter::getMovi32Value(const MachineInstr &MI,
337 const MachineOperand &MO,
339 assert(((Reloc == ARM::reloc_arm_movt) || (Reloc == ARM::reloc_arm_movw))
340 && "Relocation to this function should be for movt or movw");
343 return static_cast<unsigned>(MO.getImm());
344 else if (MO.isGlobal())
345 emitGlobalAddress(MO.getGlobal(), Reloc, true, false);
346 else if (MO.isSymbol())
347 emitExternalSymbolAddress(MO.getSymbolName(), Reloc);
349 emitMachineBasicBlock(MO.getMBB(), Reloc);
354 llvm_unreachable("Unsupported operand type for movw/movt");
359 /// getMachineOpValue - Return binary encoding of operand. If the machine
360 /// operand requires relocation, record the relocation and return zero.
361 unsigned ARMCodeEmitter::getMachineOpValue(const MachineInstr &MI,
362 const MachineOperand &MO) const {
364 return getARMRegisterNumbering(MO.getReg());
366 return static_cast<unsigned>(MO.getImm());
367 else if (MO.isGlobal())
368 emitGlobalAddress(MO.getGlobal(), ARM::reloc_arm_branch, true, false);
369 else if (MO.isSymbol())
370 emitExternalSymbolAddress(MO.getSymbolName(), ARM::reloc_arm_branch);
371 else if (MO.isCPI()) {
372 const TargetInstrDesc &TID = MI.getDesc();
373 // For VFP load, the immediate offset is multiplied by 4.
374 unsigned Reloc = ((TID.TSFlags & ARMII::FormMask) == ARMII::VFPLdStFrm)
375 ? ARM::reloc_arm_vfp_cp_entry : ARM::reloc_arm_cp_entry;
376 emitConstPoolAddress(MO.getIndex(), Reloc);
377 } else if (MO.isJTI())
378 emitJumpTableAddress(MO.getIndex(), ARM::reloc_arm_relative);
380 emitMachineBasicBlock(MO.getMBB(), ARM::reloc_arm_branch);
382 llvm_unreachable("Unable to encode MachineOperand!");
386 /// emitGlobalAddress - Emit the specified address to the code stream.
388 void ARMCodeEmitter::emitGlobalAddress(const GlobalValue *GV, unsigned Reloc,
389 bool MayNeedFarStub, bool Indirect,
390 intptr_t ACPV) const {
391 MachineRelocation MR = Indirect
392 ? MachineRelocation::getIndirectSymbol(MCE.getCurrentPCOffset(), Reloc,
393 const_cast<GlobalValue *>(GV),
394 ACPV, MayNeedFarStub)
395 : MachineRelocation::getGV(MCE.getCurrentPCOffset(), Reloc,
396 const_cast<GlobalValue *>(GV), ACPV,
398 MCE.addRelocation(MR);
401 /// emitExternalSymbolAddress - Arrange for the address of an external symbol to
402 /// be emitted to the current location in the function, and allow it to be PC
404 void ARMCodeEmitter::
405 emitExternalSymbolAddress(const char *ES, unsigned Reloc) const {
406 MCE.addRelocation(MachineRelocation::getExtSym(MCE.getCurrentPCOffset(),
410 /// emitConstPoolAddress - Arrange for the address of an constant pool
411 /// to be emitted to the current location in the function, and allow it to be PC
413 void ARMCodeEmitter::emitConstPoolAddress(unsigned CPI, unsigned Reloc) const {
414 // Tell JIT emitter we'll resolve the address.
415 MCE.addRelocation(MachineRelocation::getConstPool(MCE.getCurrentPCOffset(),
416 Reloc, CPI, 0, true));
419 /// emitJumpTableAddress - Arrange for the address of a jump table to
420 /// be emitted to the current location in the function, and allow it to be PC
422 void ARMCodeEmitter::
423 emitJumpTableAddress(unsigned JTIndex, unsigned Reloc) const {
424 MCE.addRelocation(MachineRelocation::getJumpTable(MCE.getCurrentPCOffset(),
425 Reloc, JTIndex, 0, true));
428 /// emitMachineBasicBlock - Emit the specified address basic block.
429 void ARMCodeEmitter::emitMachineBasicBlock(MachineBasicBlock *BB,
431 intptr_t JTBase) const {
432 MCE.addRelocation(MachineRelocation::getBB(MCE.getCurrentPCOffset(),
436 void ARMCodeEmitter::emitWordLE(unsigned Binary) {
437 DEBUG(errs() << " 0x";
438 errs().write_hex(Binary) << "\n");
439 MCE.emitWordLE(Binary);
442 void ARMCodeEmitter::emitDWordLE(uint64_t Binary) {
443 DEBUG(errs() << " 0x";
444 errs().write_hex(Binary) << "\n");
445 MCE.emitDWordLE(Binary);
448 void ARMCodeEmitter::emitInstruction(const MachineInstr &MI) {
449 DEBUG(errs() << "JIT: " << (void*)MCE.getCurrentPCValue() << ":\t" << MI);
451 MCE.processDebugLoc(MI.getDebugLoc(), true);
453 ++NumEmitted; // Keep track of the # of mi's emitted
454 switch (MI.getDesc().TSFlags & ARMII::FormMask) {
456 llvm_unreachable("Unhandled instruction encoding format!");
460 if (MI.getOpcode() == ARM::LEApcrelJT) {
461 // Materialize jumptable address.
462 emitLEApcrelJTInstruction(MI);
465 llvm_unreachable("Unhandled instruction encoding!");
468 emitPseudoInstruction(MI);
471 case ARMII::DPSoRegFrm:
472 emitDataProcessingInstruction(MI);
476 emitLoadStoreInstruction(MI);
478 case ARMII::LdMiscFrm:
479 case ARMII::StMiscFrm:
480 emitMiscLoadStoreInstruction(MI);
482 case ARMII::LdStMulFrm:
483 emitLoadStoreMultipleInstruction(MI);
486 emitMulFrmInstruction(MI);
489 emitExtendInstruction(MI);
491 case ARMII::ArithMiscFrm:
492 emitMiscArithInstruction(MI);
495 emitSaturateInstruction(MI);
498 emitBranchInstruction(MI);
500 case ARMII::BrMiscFrm:
501 emitMiscBranchInstruction(MI);
504 case ARMII::VFPUnaryFrm:
505 case ARMII::VFPBinaryFrm:
506 emitVFPArithInstruction(MI);
508 case ARMII::VFPConv1Frm:
509 case ARMII::VFPConv2Frm:
510 case ARMII::VFPConv3Frm:
511 case ARMII::VFPConv4Frm:
512 case ARMII::VFPConv5Frm:
513 emitVFPConversionInstruction(MI);
515 case ARMII::VFPLdStFrm:
516 emitVFPLoadStoreInstruction(MI);
518 case ARMII::VFPLdStMulFrm:
519 emitVFPLoadStoreMultipleInstruction(MI);
522 // NEON instructions.
523 case ARMII::NGetLnFrm:
524 case ARMII::NSetLnFrm:
525 emitNEONLaneInstruction(MI);
528 emitNEONDupInstruction(MI);
530 case ARMII::N1RegModImmFrm:
531 emitNEON1RegModImmInstruction(MI);
533 case ARMII::N2RegFrm:
534 emitNEON2RegInstruction(MI);
536 case ARMII::N3RegFrm:
537 emitNEON3RegInstruction(MI);
540 MCE.processDebugLoc(MI.getDebugLoc(), false);
543 void ARMCodeEmitter::emitConstPoolInstruction(const MachineInstr &MI) {
544 unsigned CPI = MI.getOperand(0).getImm(); // CP instruction index.
545 unsigned CPIndex = MI.getOperand(1).getIndex(); // Actual cp entry index.
546 const MachineConstantPoolEntry &MCPE = (*MCPEs)[CPIndex];
548 // Remember the CONSTPOOL_ENTRY address for later relocation.
549 JTI->addConstantPoolEntryAddr(CPI, MCE.getCurrentPCValue());
551 // Emit constpool island entry. In most cases, the actual values will be
552 // resolved and relocated after code emission.
553 if (MCPE.isMachineConstantPoolEntry()) {
554 ARMConstantPoolValue *ACPV =
555 static_cast<ARMConstantPoolValue*>(MCPE.Val.MachineCPVal);
557 DEBUG(errs() << " ** ARM constant pool #" << CPI << " @ "
558 << (void*)MCE.getCurrentPCValue() << " " << *ACPV << '\n');
560 assert(ACPV->isGlobalValue() && "unsupported constant pool value");
561 const GlobalValue *GV = ACPV->getGV();
563 Reloc::Model RelocM = TM.getRelocationModel();
564 emitGlobalAddress(GV, ARM::reloc_arm_machine_cp_entry,
566 Subtarget->GVIsIndirectSymbol(GV, RelocM),
569 emitExternalSymbolAddress(ACPV->getSymbol(), ARM::reloc_arm_absolute);
573 const Constant *CV = MCPE.Val.ConstVal;
576 errs() << " ** Constant pool #" << CPI << " @ "
577 << (void*)MCE.getCurrentPCValue() << " ";
578 if (const Function *F = dyn_cast<Function>(CV))
579 errs() << F->getName();
585 if (const GlobalValue *GV = dyn_cast<GlobalValue>(CV)) {
586 emitGlobalAddress(GV, ARM::reloc_arm_absolute, isa<Function>(GV), false);
588 } else if (const ConstantInt *CI = dyn_cast<ConstantInt>(CV)) {
589 uint32_t Val = uint32_t(*CI->getValue().getRawData());
591 } else if (const ConstantFP *CFP = dyn_cast<ConstantFP>(CV)) {
592 if (CFP->getType()->isFloatTy())
593 emitWordLE(CFP->getValueAPF().bitcastToAPInt().getZExtValue());
594 else if (CFP->getType()->isDoubleTy())
595 emitDWordLE(CFP->getValueAPF().bitcastToAPInt().getZExtValue());
597 llvm_unreachable("Unable to handle this constantpool entry!");
600 llvm_unreachable("Unable to handle this constantpool entry!");
605 void ARMCodeEmitter::emitMOVi32immInstruction(const MachineInstr &MI) {
606 const MachineOperand &MO0 = MI.getOperand(0);
607 const MachineOperand &MO1 = MI.getOperand(1);
609 // Emit the 'movw' instruction.
610 unsigned Binary = 0x30 << 20; // mov: Insts{27-20} = 0b00110000
612 unsigned Lo16 = getMovi32Value(MI, MO1, ARM::reloc_arm_movw) & 0xFFFF;
614 // Set the conditional execution predicate.
615 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
618 Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRdShift;
620 // Encode imm16 as imm4:imm12
621 Binary |= Lo16 & 0xFFF; // Insts{11-0} = imm12
622 Binary |= ((Lo16 >> 12) & 0xF) << 16; // Insts{19-16} = imm4
625 unsigned Hi16 = getMovi32Value(MI, MO1, ARM::reloc_arm_movt) >> 16;
626 // Emit the 'movt' instruction.
627 Binary = 0x34 << 20; // movt: Insts{27-20} = 0b00110100
629 // Set the conditional execution predicate.
630 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
633 Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRdShift;
635 // Encode imm16 as imm4:imm1, same as movw above.
636 Binary |= Hi16 & 0xFFF;
637 Binary |= ((Hi16 >> 12) & 0xF) << 16;
641 void ARMCodeEmitter::emitMOVi2piecesInstruction(const MachineInstr &MI) {
642 const MachineOperand &MO0 = MI.getOperand(0);
643 const MachineOperand &MO1 = MI.getOperand(1);
644 assert(MO1.isImm() && ARM_AM::isSOImmTwoPartVal(MO1.getImm()) &&
645 "Not a valid so_imm value!");
646 unsigned V1 = ARM_AM::getSOImmTwoPartFirst(MO1.getImm());
647 unsigned V2 = ARM_AM::getSOImmTwoPartSecond(MO1.getImm());
649 // Emit the 'mov' instruction.
650 unsigned Binary = 0xd << 21; // mov: Insts{24-21} = 0b1101
652 // Set the conditional execution predicate.
653 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
656 Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRdShift;
659 // Set bit I(25) to identify this is the immediate form of <shifter_op>
660 Binary |= 1 << ARMII::I_BitShift;
661 Binary |= getMachineSoImmOpValue(V1);
664 // Now the 'orr' instruction.
665 Binary = 0xc << 21; // orr: Insts{24-21} = 0b1100
667 // Set the conditional execution predicate.
668 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
671 Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRdShift;
674 Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRnShift;
677 // Set bit I(25) to identify this is the immediate form of <shifter_op>
678 Binary |= 1 << ARMII::I_BitShift;
679 Binary |= getMachineSoImmOpValue(V2);
683 void ARMCodeEmitter::emitLEApcrelJTInstruction(const MachineInstr &MI) {
684 // It's basically add r, pc, (LJTI - $+8)
686 const TargetInstrDesc &TID = MI.getDesc();
688 // Emit the 'add' instruction.
689 unsigned Binary = 0x4 << 21; // add: Insts{24-21} = 0b0100
691 // Set the conditional execution predicate
692 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
694 // Encode S bit if MI modifies CPSR.
695 Binary |= getAddrModeSBit(MI, TID);
698 Binary |= getMachineOpValue(MI, 0) << ARMII::RegRdShift;
700 // Encode Rn which is PC.
701 Binary |= getARMRegisterNumbering(ARM::PC) << ARMII::RegRnShift;
703 // Encode the displacement.
704 Binary |= 1 << ARMII::I_BitShift;
705 emitJumpTableAddress(MI.getOperand(1).getIndex(), ARM::reloc_arm_jt_base);
710 void ARMCodeEmitter::emitPseudoMoveInstruction(const MachineInstr &MI) {
711 unsigned Opcode = MI.getDesc().Opcode;
713 // Part of binary is determined by TableGn.
714 unsigned Binary = getBinaryCodeForInstr(MI);
716 // Set the conditional execution predicate
717 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
719 // Encode S bit if MI modifies CPSR.
720 if (Opcode == ARM::MOVsrl_flag || Opcode == ARM::MOVsra_flag)
721 Binary |= 1 << ARMII::S_BitShift;
723 // Encode register def if there is one.
724 Binary |= getMachineOpValue(MI, 0) << ARMII::RegRdShift;
726 // Encode the shift operation.
733 case ARM::MOVsrl_flag:
735 Binary |= (0x2 << 4) | (1 << 7);
737 case ARM::MOVsra_flag:
739 Binary |= (0x4 << 4) | (1 << 7);
743 // Encode register Rm.
744 Binary |= getMachineOpValue(MI, 1);
749 void ARMCodeEmitter::addPCLabel(unsigned LabelID) {
750 DEBUG(errs() << " ** LPC" << LabelID << " @ "
751 << (void*)MCE.getCurrentPCValue() << '\n');
752 JTI->addPCLabelAddr(LabelID, MCE.getCurrentPCValue());
755 void ARMCodeEmitter::emitPseudoInstruction(const MachineInstr &MI) {
756 unsigned Opcode = MI.getDesc().Opcode;
759 llvm_unreachable("ARMCodeEmitter::emitPseudoInstruction");
763 case ARM::BMOVPCRXr9: {
764 // First emit mov lr, pc
765 unsigned Binary = 0x01a0e00f;
766 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
769 // and then emit the branch.
770 emitMiscBranchInstruction(MI);
773 case TargetOpcode::INLINEASM: {
774 // We allow inline assembler nodes with empty bodies - they can
775 // implicitly define registers, which is ok for JIT.
776 if (MI.getOperand(0).getSymbolName()[0]) {
777 report_fatal_error("JIT does not support inline asm!");
781 case TargetOpcode::PROLOG_LABEL:
782 case TargetOpcode::EH_LABEL:
783 MCE.emitLabel(MI.getOperand(0).getMCSymbol());
785 case TargetOpcode::IMPLICIT_DEF:
786 case TargetOpcode::KILL:
789 case ARM::CONSTPOOL_ENTRY:
790 emitConstPoolInstruction(MI);
793 // Remember of the address of the PC label for relocation later.
794 addPCLabel(MI.getOperand(2).getImm());
795 // PICADD is just an add instruction that implicitly read pc.
796 emitDataProcessingInstruction(MI, 0, ARM::PC);
803 // Remember of the address of the PC label for relocation later.
804 addPCLabel(MI.getOperand(2).getImm());
805 // These are just load / store instructions that implicitly read pc.
806 emitLoadStoreInstruction(MI, 0, ARM::PC);
813 // Remember of the address of the PC label for relocation later.
814 addPCLabel(MI.getOperand(2).getImm());
815 // These are just load / store instructions that implicitly read pc.
816 emitMiscLoadStoreInstruction(MI, ARM::PC);
821 // Two instructions to materialize a constant.
822 if (Subtarget->hasV6T2Ops())
823 emitMOVi32immInstruction(MI);
825 emitMOVi2piecesInstruction(MI);
828 case ARM::LEApcrelJT:
829 // Materialize jumptable address.
830 emitLEApcrelJTInstruction(MI);
833 case ARM::MOVsrl_flag:
834 case ARM::MOVsra_flag:
835 emitPseudoMoveInstruction(MI);
840 unsigned ARMCodeEmitter::getMachineSoRegOpValue(const MachineInstr &MI,
841 const TargetInstrDesc &TID,
842 const MachineOperand &MO,
844 unsigned Binary = getMachineOpValue(MI, MO);
846 const MachineOperand &MO1 = MI.getOperand(OpIdx + 1);
847 const MachineOperand &MO2 = MI.getOperand(OpIdx + 2);
848 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO2.getImm());
850 // Encode the shift opcode.
852 unsigned Rs = MO1.getReg();
854 // Set shift operand (bit[7:4]).
859 // RRX - 0110 and bit[11:8] clear.
861 default: llvm_unreachable("Unknown shift opc!");
862 case ARM_AM::lsl: SBits = 0x1; break;
863 case ARM_AM::lsr: SBits = 0x3; break;
864 case ARM_AM::asr: SBits = 0x5; break;
865 case ARM_AM::ror: SBits = 0x7; break;
866 case ARM_AM::rrx: SBits = 0x6; break;
869 // Set shift operand (bit[6:4]).
875 default: llvm_unreachable("Unknown shift opc!");
876 case ARM_AM::lsl: SBits = 0x0; break;
877 case ARM_AM::lsr: SBits = 0x2; break;
878 case ARM_AM::asr: SBits = 0x4; break;
879 case ARM_AM::ror: SBits = 0x6; break;
882 Binary |= SBits << 4;
883 if (SOpc == ARM_AM::rrx)
886 // Encode the shift operation Rs or shift_imm (except rrx).
888 // Encode Rs bit[11:8].
889 assert(ARM_AM::getSORegOffset(MO2.getImm()) == 0);
890 return Binary | (getARMRegisterNumbering(Rs) << ARMII::RegRsShift);
893 // Encode shift_imm bit[11:7].
894 return Binary | ARM_AM::getSORegOffset(MO2.getImm()) << 7;
897 unsigned ARMCodeEmitter::getMachineSoImmOpValue(unsigned SoImm) {
898 int SoImmVal = ARM_AM::getSOImmVal(SoImm);
899 assert(SoImmVal != -1 && "Not a valid so_imm value!");
901 // Encode rotate_imm.
902 unsigned Binary = (ARM_AM::getSOImmValRot((unsigned)SoImmVal) >> 1)
903 << ARMII::SoRotImmShift;
906 Binary |= ARM_AM::getSOImmValImm((unsigned)SoImmVal);
910 unsigned ARMCodeEmitter::getAddrModeSBit(const MachineInstr &MI,
911 const TargetInstrDesc &TID) const {
912 for (unsigned i = MI.getNumOperands(), e = TID.getNumOperands(); i != e; --i){
913 const MachineOperand &MO = MI.getOperand(i-1);
914 if (MO.isReg() && MO.isDef() && MO.getReg() == ARM::CPSR)
915 return 1 << ARMII::S_BitShift;
920 void ARMCodeEmitter::emitDataProcessingInstruction(const MachineInstr &MI,
922 unsigned ImplicitRn) {
923 const TargetInstrDesc &TID = MI.getDesc();
925 // Part of binary is determined by TableGn.
926 unsigned Binary = getBinaryCodeForInstr(MI);
928 // Set the conditional execution predicate
929 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
931 // Encode S bit if MI modifies CPSR.
932 Binary |= getAddrModeSBit(MI, TID);
934 // Encode register def if there is one.
935 unsigned NumDefs = TID.getNumDefs();
938 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
940 // Special handling for implicit use (e.g. PC).
941 Binary |= (getARMRegisterNumbering(ImplicitRd) << ARMII::RegRdShift);
943 if (TID.Opcode == ARM::MOVi16) {
944 // Get immediate from MI.
945 unsigned Lo16 = getMovi32Value(MI, MI.getOperand(OpIdx),
946 ARM::reloc_arm_movw);
947 // Encode imm which is the same as in emitMOVi32immInstruction().
948 Binary |= Lo16 & 0xFFF;
949 Binary |= ((Lo16 >> 12) & 0xF) << 16;
952 } else if(TID.Opcode == ARM::MOVTi16) {
953 unsigned Hi16 = (getMovi32Value(MI, MI.getOperand(OpIdx),
954 ARM::reloc_arm_movt) >> 16);
955 Binary |= Hi16 & 0xFFF;
956 Binary |= ((Hi16 >> 12) & 0xF) << 16;
959 } else if ((TID.Opcode == ARM::BFC) || (TID.Opcode == ARM::BFI)) {
960 uint32_t v = ~MI.getOperand(2).getImm();
961 int32_t lsb = CountTrailingZeros_32(v);
962 int32_t msb = (32 - CountLeadingZeros_32(v)) - 1;
963 // Instr{20-16} = msb, Instr{11-7} = lsb
964 Binary |= (msb & 0x1F) << 16;
965 Binary |= (lsb & 0x1F) << 7;
968 } else if ((TID.Opcode == ARM::UBFX) || (TID.Opcode == ARM::SBFX)) {
969 // Encode Rn in Instr{0-3}
970 Binary |= getMachineOpValue(MI, OpIdx++);
972 uint32_t lsb = MI.getOperand(OpIdx++).getImm();
973 uint32_t widthm1 = MI.getOperand(OpIdx++).getImm() - 1;
975 // Instr{20-16} = widthm1, Instr{11-7} = lsb
976 Binary |= (widthm1 & 0x1F) << 16;
977 Binary |= (lsb & 0x1F) << 7;
982 // If this is a two-address operand, skip it. e.g. MOVCCr operand 1.
983 if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
986 // Encode first non-shifter register operand if there is one.
987 bool isUnary = TID.TSFlags & ARMII::UnaryDP;
990 // Special handling for implicit use (e.g. PC).
991 Binary |= (getARMRegisterNumbering(ImplicitRn) << ARMII::RegRnShift);
993 Binary |= getMachineOpValue(MI, OpIdx) << ARMII::RegRnShift;
998 // Encode shifter operand.
999 const MachineOperand &MO = MI.getOperand(OpIdx);
1000 if ((TID.TSFlags & ARMII::FormMask) == ARMII::DPSoRegFrm) {
1002 emitWordLE(Binary | getMachineSoRegOpValue(MI, TID, MO, OpIdx));
1007 // Encode register Rm.
1008 emitWordLE(Binary | getARMRegisterNumbering(MO.getReg()));
1013 Binary |= getMachineSoImmOpValue((unsigned)MO.getImm());
1018 void ARMCodeEmitter::emitLoadStoreInstruction(const MachineInstr &MI,
1019 unsigned ImplicitRd,
1020 unsigned ImplicitRn) {
1021 const TargetInstrDesc &TID = MI.getDesc();
1022 unsigned Form = TID.TSFlags & ARMII::FormMask;
1023 bool IsPrePost = (TID.TSFlags & ARMII::IndexModeMask) != 0;
1025 // Part of binary is determined by TableGn.
1026 unsigned Binary = getBinaryCodeForInstr(MI);
1028 // If this is an LDRi12, STRi12 or LDRcp, nothing more needs be done.
1029 if (MI.getOpcode() == ARM::LDRi12 || MI.getOpcode() == ARM::LDRcp ||
1030 MI.getOpcode() == ARM::STRi12) {
1035 // Set the conditional execution predicate
1036 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1040 // Operand 0 of a pre- and post-indexed store is the address base
1041 // writeback. Skip it.
1042 bool Skipped = false;
1043 if (IsPrePost && Form == ARMII::StFrm) {
1048 // Set first operand
1050 // Special handling for implicit use (e.g. PC).
1051 Binary |= (getARMRegisterNumbering(ImplicitRd) << ARMII::RegRdShift);
1053 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
1055 // Set second operand
1057 // Special handling for implicit use (e.g. PC).
1058 Binary |= (getARMRegisterNumbering(ImplicitRn) << ARMII::RegRnShift);
1060 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift;
1062 // If this is a two-address operand, skip it. e.g. LDR_PRE.
1063 if (!Skipped && TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
1066 const MachineOperand &MO2 = MI.getOperand(OpIdx);
1067 unsigned AM2Opc = (ImplicitRn == ARM::PC)
1068 ? 0 : MI.getOperand(OpIdx+1).getImm();
1070 // Set bit U(23) according to sign of immed value (positive or negative).
1071 Binary |= ((ARM_AM::getAM2Op(AM2Opc) == ARM_AM::add ? 1 : 0) <<
1073 if (!MO2.getReg()) { // is immediate
1074 if (ARM_AM::getAM2Offset(AM2Opc))
1075 // Set the value of offset_12 field
1076 Binary |= ARM_AM::getAM2Offset(AM2Opc);
1081 // Set bit I(25), because this is not in immediate encoding.
1082 Binary |= 1 << ARMII::I_BitShift;
1083 assert(TargetRegisterInfo::isPhysicalRegister(MO2.getReg()));
1084 // Set bit[3:0] to the corresponding Rm register
1085 Binary |= getARMRegisterNumbering(MO2.getReg());
1087 // If this instr is in scaled register offset/index instruction, set
1088 // shift_immed(bit[11:7]) and shift(bit[6:5]) fields.
1089 if (unsigned ShImm = ARM_AM::getAM2Offset(AM2Opc)) {
1090 Binary |= getShiftOp(AM2Opc) << ARMII::ShiftImmShift; // shift
1091 Binary |= ShImm << ARMII::ShiftShift; // shift_immed
1097 void ARMCodeEmitter::emitMiscLoadStoreInstruction(const MachineInstr &MI,
1098 unsigned ImplicitRn) {
1099 const TargetInstrDesc &TID = MI.getDesc();
1100 unsigned Form = TID.TSFlags & ARMII::FormMask;
1101 bool IsPrePost = (TID.TSFlags & ARMII::IndexModeMask) != 0;
1103 // Part of binary is determined by TableGn.
1104 unsigned Binary = getBinaryCodeForInstr(MI);
1106 // Set the conditional execution predicate
1107 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1111 // Operand 0 of a pre- and post-indexed store is the address base
1112 // writeback. Skip it.
1113 bool Skipped = false;
1114 if (IsPrePost && Form == ARMII::StMiscFrm) {
1119 // Set first operand
1120 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
1122 // Skip LDRD and STRD's second operand.
1123 if (TID.Opcode == ARM::LDRD || TID.Opcode == ARM::STRD)
1126 // Set second operand
1128 // Special handling for implicit use (e.g. PC).
1129 Binary |= (getARMRegisterNumbering(ImplicitRn) << ARMII::RegRnShift);
1131 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift;
1133 // If this is a two-address operand, skip it. e.g. LDRH_POST.
1134 if (!Skipped && TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
1137 const MachineOperand &MO2 = MI.getOperand(OpIdx);
1138 unsigned AM3Opc = (ImplicitRn == ARM::PC)
1139 ? 0 : MI.getOperand(OpIdx+1).getImm();
1141 // Set bit U(23) according to sign of immed value (positive or negative)
1142 Binary |= ((ARM_AM::getAM3Op(AM3Opc) == ARM_AM::add ? 1 : 0) <<
1145 // If this instr is in register offset/index encoding, set bit[3:0]
1146 // to the corresponding Rm register.
1148 Binary |= getARMRegisterNumbering(MO2.getReg());
1153 // This instr is in immediate offset/index encoding, set bit 22 to 1.
1154 Binary |= 1 << ARMII::AM3_I_BitShift;
1155 if (unsigned ImmOffs = ARM_AM::getAM3Offset(AM3Opc)) {
1157 Binary |= (ImmOffs >> 4) << ARMII::ImmHiShift; // immedH
1158 Binary |= (ImmOffs & 0xF); // immedL
1164 static unsigned getAddrModeUPBits(unsigned Mode) {
1165 unsigned Binary = 0;
1167 // Set addressing mode by modifying bits U(23) and P(24)
1168 // IA - Increment after - bit U = 1 and bit P = 0
1169 // IB - Increment before - bit U = 1 and bit P = 1
1170 // DA - Decrement after - bit U = 0 and bit P = 0
1171 // DB - Decrement before - bit U = 0 and bit P = 1
1173 default: llvm_unreachable("Unknown addressing sub-mode!");
1174 case ARM_AM::da: break;
1175 case ARM_AM::db: Binary |= 0x1 << ARMII::P_BitShift; break;
1176 case ARM_AM::ia: Binary |= 0x1 << ARMII::U_BitShift; break;
1177 case ARM_AM::ib: Binary |= 0x3 << ARMII::U_BitShift; break;
1183 void ARMCodeEmitter::emitLoadStoreMultipleInstruction(const MachineInstr &MI) {
1184 const TargetInstrDesc &TID = MI.getDesc();
1185 bool IsUpdating = (TID.TSFlags & ARMII::IndexModeMask) != 0;
1187 // Part of binary is determined by TableGn.
1188 unsigned Binary = getBinaryCodeForInstr(MI);
1190 // Set the conditional execution predicate
1191 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1193 // Skip operand 0 of an instruction with base register update.
1198 // Set base address operand
1199 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift;
1201 // Set addressing mode by modifying bits U(23) and P(24)
1202 ARM_AM::AMSubMode Mode = ARM_AM::getLoadStoreMultipleSubMode(MI.getOpcode());
1203 Binary |= getAddrModeUPBits(ARM_AM::getAM4SubMode(Mode));
1207 Binary |= 0x1 << ARMII::W_BitShift;
1210 for (unsigned i = OpIdx+2, e = MI.getNumOperands(); i != e; ++i) {
1211 const MachineOperand &MO = MI.getOperand(i);
1212 if (!MO.isReg() || MO.isImplicit())
1214 unsigned RegNum = getARMRegisterNumbering(MO.getReg());
1215 assert(TargetRegisterInfo::isPhysicalRegister(MO.getReg()) &&
1217 Binary |= 0x1 << RegNum;
1223 void ARMCodeEmitter::emitMulFrmInstruction(const MachineInstr &MI) {
1224 const TargetInstrDesc &TID = MI.getDesc();
1226 // Part of binary is determined by TableGn.
1227 unsigned Binary = getBinaryCodeForInstr(MI);
1229 // Set the conditional execution predicate
1230 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1232 // Encode S bit if MI modifies CPSR.
1233 Binary |= getAddrModeSBit(MI, TID);
1235 // 32x32->64bit operations have two destination registers. The number
1236 // of register definitions will tell us if that's what we're dealing with.
1238 if (TID.getNumDefs() == 2)
1239 Binary |= getMachineOpValue (MI, OpIdx++) << ARMII::RegRdLoShift;
1242 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdHiShift;
1245 Binary |= getMachineOpValue(MI, OpIdx++);
1248 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRsShift;
1250 // Many multiple instructions (e.g. MLA) have three src operands. Encode
1251 // it as Rn (for multiply, that's in the same offset as RdLo.
1252 if (TID.getNumOperands() > OpIdx &&
1253 !TID.OpInfo[OpIdx].isPredicate() &&
1254 !TID.OpInfo[OpIdx].isOptionalDef())
1255 Binary |= getMachineOpValue(MI, OpIdx) << ARMII::RegRdLoShift;
1260 void ARMCodeEmitter::emitExtendInstruction(const MachineInstr &MI) {
1261 const TargetInstrDesc &TID = MI.getDesc();
1263 // Part of binary is determined by TableGn.
1264 unsigned Binary = getBinaryCodeForInstr(MI);
1266 // Set the conditional execution predicate
1267 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1272 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
1274 const MachineOperand &MO1 = MI.getOperand(OpIdx++);
1275 const MachineOperand &MO2 = MI.getOperand(OpIdx);
1277 // Two register operand form.
1279 Binary |= getMachineOpValue(MI, MO1) << ARMII::RegRnShift;
1282 Binary |= getMachineOpValue(MI, MO2);
1285 Binary |= getMachineOpValue(MI, MO1);
1288 // Encode rot imm (0, 8, 16, or 24) if it has a rotate immediate operand.
1289 if (MI.getOperand(OpIdx).isImm() &&
1290 !TID.OpInfo[OpIdx].isPredicate() &&
1291 !TID.OpInfo[OpIdx].isOptionalDef())
1292 Binary |= (getMachineOpValue(MI, OpIdx) / 8) << ARMII::ExtRotImmShift;
1297 void ARMCodeEmitter::emitMiscArithInstruction(const MachineInstr &MI) {
1298 const TargetInstrDesc &TID = MI.getDesc();
1300 // Part of binary is determined by TableGn.
1301 unsigned Binary = getBinaryCodeForInstr(MI);
1303 // Set the conditional execution predicate
1304 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1309 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
1311 const MachineOperand &MO = MI.getOperand(OpIdx++);
1312 if (OpIdx == TID.getNumOperands() ||
1313 TID.OpInfo[OpIdx].isPredicate() ||
1314 TID.OpInfo[OpIdx].isOptionalDef()) {
1315 // Encode Rm and it's done.
1316 Binary |= getMachineOpValue(MI, MO);
1322 Binary |= getMachineOpValue(MI, MO) << ARMII::RegRnShift;
1325 Binary |= getMachineOpValue(MI, OpIdx++);
1327 // Encode shift_imm.
1328 unsigned ShiftAmt = MI.getOperand(OpIdx).getImm();
1329 if (TID.Opcode == ARM::PKHTB) {
1330 assert(ShiftAmt != 0 && "PKHTB shift_imm is 0!");
1334 assert(ShiftAmt < 32 && "shift_imm range is 0 to 31!");
1335 Binary |= ShiftAmt << ARMII::ShiftShift;
1340 void ARMCodeEmitter::emitSaturateInstruction(const MachineInstr &MI) {
1341 const TargetInstrDesc &TID = MI.getDesc();
1343 // Part of binary is determined by TableGen.
1344 unsigned Binary = getBinaryCodeForInstr(MI);
1346 // Set the conditional execution predicate
1347 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1350 Binary |= getMachineOpValue(MI, 0) << ARMII::RegRdShift;
1352 // Encode saturate bit position.
1353 unsigned Pos = MI.getOperand(1).getImm();
1354 if (TID.Opcode == ARM::SSAT || TID.Opcode == ARM::SSAT16)
1356 assert((Pos < 16 || (Pos < 32 &&
1357 TID.Opcode != ARM::SSAT16 &&
1358 TID.Opcode != ARM::USAT16)) &&
1359 "saturate bit position out of range");
1360 Binary |= Pos << 16;
1363 Binary |= getMachineOpValue(MI, 2);
1365 // Encode shift_imm.
1366 if (TID.getNumOperands() == 4) {
1367 unsigned ShiftOp = MI.getOperand(3).getImm();
1368 ARM_AM::ShiftOpc Opc = ARM_AM::getSORegShOp(ShiftOp);
1369 if (Opc == ARM_AM::asr)
1371 unsigned ShiftAmt = MI.getOperand(3).getImm();
1372 if (ShiftAmt == 32 && Opc == ARM_AM::asr)
1374 assert(ShiftAmt < 32 && "shift_imm range is 0 to 31!");
1375 Binary |= ShiftAmt << ARMII::ShiftShift;
1381 void ARMCodeEmitter::emitBranchInstruction(const MachineInstr &MI) {
1382 const TargetInstrDesc &TID = MI.getDesc();
1384 if (TID.Opcode == ARM::TPsoft) {
1385 llvm_unreachable("ARM::TPsoft FIXME"); // FIXME
1388 // Part of binary is determined by TableGn.
1389 unsigned Binary = getBinaryCodeForInstr(MI);
1391 // Set the conditional execution predicate
1392 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1394 // Set signed_immed_24 field
1395 Binary |= getMachineOpValue(MI, 0);
1400 void ARMCodeEmitter::emitInlineJumpTable(unsigned JTIndex) {
1401 // Remember the base address of the inline jump table.
1402 uintptr_t JTBase = MCE.getCurrentPCValue();
1403 JTI->addJumpTableBaseAddr(JTIndex, JTBase);
1404 DEBUG(errs() << " ** Jump Table #" << JTIndex << " @ " << (void*)JTBase
1407 // Now emit the jump table entries.
1408 const std::vector<MachineBasicBlock*> &MBBs = (*MJTEs)[JTIndex].MBBs;
1409 for (unsigned i = 0, e = MBBs.size(); i != e; ++i) {
1411 // DestBB address - JT base.
1412 emitMachineBasicBlock(MBBs[i], ARM::reloc_arm_pic_jt, JTBase);
1414 // Absolute DestBB address.
1415 emitMachineBasicBlock(MBBs[i], ARM::reloc_arm_absolute);
1420 void ARMCodeEmitter::emitMiscBranchInstruction(const MachineInstr &MI) {
1421 const TargetInstrDesc &TID = MI.getDesc();
1423 // Handle jump tables.
1424 if (TID.Opcode == ARM::BR_JTr || TID.Opcode == ARM::BR_JTadd) {
1425 // First emit a ldr pc, [] instruction.
1426 emitDataProcessingInstruction(MI, ARM::PC);
1428 // Then emit the inline jump table.
1430 (TID.Opcode == ARM::BR_JTr)
1431 ? MI.getOperand(1).getIndex() : MI.getOperand(2).getIndex();
1432 emitInlineJumpTable(JTIndex);
1434 } else if (TID.Opcode == ARM::BR_JTm) {
1435 // First emit a ldr pc, [] instruction.
1436 emitLoadStoreInstruction(MI, ARM::PC);
1438 // Then emit the inline jump table.
1439 emitInlineJumpTable(MI.getOperand(3).getIndex());
1443 // Part of binary is determined by TableGn.
1444 unsigned Binary = getBinaryCodeForInstr(MI);
1446 // Set the conditional execution predicate
1447 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1449 if (TID.Opcode == ARM::BX_RET || TID.Opcode == ARM::MOVPCLR)
1450 // The return register is LR.
1451 Binary |= getARMRegisterNumbering(ARM::LR);
1453 // otherwise, set the return register
1454 Binary |= getMachineOpValue(MI, 0);
1459 static unsigned encodeVFPRd(const MachineInstr &MI, unsigned OpIdx) {
1460 unsigned RegD = MI.getOperand(OpIdx).getReg();
1461 unsigned Binary = 0;
1462 bool isSPVFP = ARM::SPRRegisterClass->contains(RegD);
1463 RegD = getARMRegisterNumbering(RegD);
1465 Binary |= RegD << ARMII::RegRdShift;
1467 Binary |= ((RegD & 0x1E) >> 1) << ARMII::RegRdShift;
1468 Binary |= (RegD & 0x01) << ARMII::D_BitShift;
1473 static unsigned encodeVFPRn(const MachineInstr &MI, unsigned OpIdx) {
1474 unsigned RegN = MI.getOperand(OpIdx).getReg();
1475 unsigned Binary = 0;
1476 bool isSPVFP = ARM::SPRRegisterClass->contains(RegN);
1477 RegN = getARMRegisterNumbering(RegN);
1479 Binary |= RegN << ARMII::RegRnShift;
1481 Binary |= ((RegN & 0x1E) >> 1) << ARMII::RegRnShift;
1482 Binary |= (RegN & 0x01) << ARMII::N_BitShift;
1487 static unsigned encodeVFPRm(const MachineInstr &MI, unsigned OpIdx) {
1488 unsigned RegM = MI.getOperand(OpIdx).getReg();
1489 unsigned Binary = 0;
1490 bool isSPVFP = ARM::SPRRegisterClass->contains(RegM);
1491 RegM = getARMRegisterNumbering(RegM);
1495 Binary |= ((RegM & 0x1E) >> 1);
1496 Binary |= (RegM & 0x01) << ARMII::M_BitShift;
1501 void ARMCodeEmitter::emitVFPArithInstruction(const MachineInstr &MI) {
1502 const TargetInstrDesc &TID = MI.getDesc();
1504 // Part of binary is determined by TableGn.
1505 unsigned Binary = getBinaryCodeForInstr(MI);
1507 // Set the conditional execution predicate
1508 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1511 assert((Binary & ARMII::D_BitShift) == 0 &&
1512 (Binary & ARMII::N_BitShift) == 0 &&
1513 (Binary & ARMII::M_BitShift) == 0 && "VFP encoding bug!");
1516 Binary |= encodeVFPRd(MI, OpIdx++);
1518 // If this is a two-address operand, skip it, e.g. FMACD.
1519 if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
1523 if ((TID.TSFlags & ARMII::FormMask) == ARMII::VFPBinaryFrm)
1524 Binary |= encodeVFPRn(MI, OpIdx++);
1526 if (OpIdx == TID.getNumOperands() ||
1527 TID.OpInfo[OpIdx].isPredicate() ||
1528 TID.OpInfo[OpIdx].isOptionalDef()) {
1529 // FCMPEZD etc. has only one operand.
1535 Binary |= encodeVFPRm(MI, OpIdx);
1540 void ARMCodeEmitter::emitVFPConversionInstruction(const MachineInstr &MI) {
1541 const TargetInstrDesc &TID = MI.getDesc();
1542 unsigned Form = TID.TSFlags & ARMII::FormMask;
1544 // Part of binary is determined by TableGn.
1545 unsigned Binary = getBinaryCodeForInstr(MI);
1547 // Set the conditional execution predicate
1548 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1552 case ARMII::VFPConv1Frm:
1553 case ARMII::VFPConv2Frm:
1554 case ARMII::VFPConv3Frm:
1556 Binary |= encodeVFPRd(MI, 0);
1558 case ARMII::VFPConv4Frm:
1560 Binary |= encodeVFPRn(MI, 0);
1562 case ARMII::VFPConv5Frm:
1564 Binary |= encodeVFPRm(MI, 0);
1570 case ARMII::VFPConv1Frm:
1572 Binary |= encodeVFPRm(MI, 1);
1574 case ARMII::VFPConv2Frm:
1575 case ARMII::VFPConv3Frm:
1577 Binary |= encodeVFPRn(MI, 1);
1579 case ARMII::VFPConv4Frm:
1580 case ARMII::VFPConv5Frm:
1582 Binary |= encodeVFPRd(MI, 1);
1586 if (Form == ARMII::VFPConv5Frm)
1588 Binary |= encodeVFPRn(MI, 2);
1589 else if (Form == ARMII::VFPConv3Frm)
1591 Binary |= encodeVFPRm(MI, 2);
1596 void ARMCodeEmitter::emitVFPLoadStoreInstruction(const MachineInstr &MI) {
1597 // Part of binary is determined by TableGn.
1598 unsigned Binary = getBinaryCodeForInstr(MI);
1600 // Set the conditional execution predicate
1601 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1606 Binary |= encodeVFPRd(MI, OpIdx++);
1608 // Encode address base.
1609 const MachineOperand &Base = MI.getOperand(OpIdx++);
1610 Binary |= getMachineOpValue(MI, Base) << ARMII::RegRnShift;
1612 // If there is a non-zero immediate offset, encode it.
1614 const MachineOperand &Offset = MI.getOperand(OpIdx);
1615 if (unsigned ImmOffs = ARM_AM::getAM5Offset(Offset.getImm())) {
1616 if (ARM_AM::getAM5Op(Offset.getImm()) == ARM_AM::add)
1617 Binary |= 1 << ARMII::U_BitShift;
1624 // If immediate offset is omitted, default to +0.
1625 Binary |= 1 << ARMII::U_BitShift;
1631 ARMCodeEmitter::emitVFPLoadStoreMultipleInstruction(const MachineInstr &MI) {
1632 const TargetInstrDesc &TID = MI.getDesc();
1633 bool IsUpdating = (TID.TSFlags & ARMII::IndexModeMask) != 0;
1635 // Part of binary is determined by TableGn.
1636 unsigned Binary = getBinaryCodeForInstr(MI);
1638 // Set the conditional execution predicate
1639 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1641 // Skip operand 0 of an instruction with base register update.
1646 // Set base address operand
1647 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift;
1649 // Set addressing mode by modifying bits U(23) and P(24)
1650 ARM_AM::AMSubMode Mode = ARM_AM::getLoadStoreMultipleSubMode(MI.getOpcode());
1651 Binary |= getAddrModeUPBits(ARM_AM::getAM4SubMode(Mode));
1655 Binary |= 0x1 << ARMII::W_BitShift;
1657 // First register is encoded in Dd.
1658 Binary |= encodeVFPRd(MI, OpIdx+2);
1660 // Count the number of registers.
1661 unsigned NumRegs = 1;
1662 for (unsigned i = OpIdx+3, e = MI.getNumOperands(); i != e; ++i) {
1663 const MachineOperand &MO = MI.getOperand(i);
1664 if (!MO.isReg() || MO.isImplicit())
1668 // Bit 8 will be set if <list> is consecutive 64-bit registers (e.g., D0)
1669 // Otherwise, it will be 0, in the case of 32-bit registers.
1671 Binary |= NumRegs * 2;
1678 static unsigned encodeNEONRd(const MachineInstr &MI, unsigned OpIdx) {
1679 unsigned RegD = MI.getOperand(OpIdx).getReg();
1680 unsigned Binary = 0;
1681 RegD = getARMRegisterNumbering(RegD);
1682 Binary |= (RegD & 0xf) << ARMII::RegRdShift;
1683 Binary |= ((RegD >> 4) & 1) << ARMII::D_BitShift;
1687 static unsigned encodeNEONRn(const MachineInstr &MI, unsigned OpIdx) {
1688 unsigned RegN = MI.getOperand(OpIdx).getReg();
1689 unsigned Binary = 0;
1690 RegN = getARMRegisterNumbering(RegN);
1691 Binary |= (RegN & 0xf) << ARMII::RegRnShift;
1692 Binary |= ((RegN >> 4) & 1) << ARMII::N_BitShift;
1696 static unsigned encodeNEONRm(const MachineInstr &MI, unsigned OpIdx) {
1697 unsigned RegM = MI.getOperand(OpIdx).getReg();
1698 unsigned Binary = 0;
1699 RegM = getARMRegisterNumbering(RegM);
1700 Binary |= (RegM & 0xf);
1701 Binary |= ((RegM >> 4) & 1) << ARMII::M_BitShift;
1705 /// convertNEONDataProcToThumb - Convert the ARM mode encoding for a NEON
1706 /// data-processing instruction to the corresponding Thumb encoding.
1707 static unsigned convertNEONDataProcToThumb(unsigned Binary) {
1708 assert((Binary & 0xfe000000) == 0xf2000000 &&
1709 "not an ARM NEON data-processing instruction");
1710 unsigned UBit = (Binary >> 24) & 1;
1711 return 0xef000000 | (UBit << 28) | (Binary & 0xffffff);
1714 void ARMCodeEmitter::emitNEONLaneInstruction(const MachineInstr &MI) {
1715 unsigned Binary = getBinaryCodeForInstr(MI);
1717 unsigned RegTOpIdx, RegNOpIdx, LnOpIdx;
1718 const TargetInstrDesc &TID = MI.getDesc();
1719 if ((TID.TSFlags & ARMII::FormMask) == ARMII::NGetLnFrm) {
1723 } else { // ARMII::NSetLnFrm
1729 // Set the conditional execution predicate
1730 Binary |= (IsThumb ? ARMCC::AL : II->getPredicate(&MI)) << ARMII::CondShift;
1732 unsigned RegT = MI.getOperand(RegTOpIdx).getReg();
1733 RegT = getARMRegisterNumbering(RegT);
1734 Binary |= (RegT << ARMII::RegRdShift);
1735 Binary |= encodeNEONRn(MI, RegNOpIdx);
1738 if ((Binary & (1 << 22)) != 0)
1739 LaneShift = 0; // 8-bit elements
1740 else if ((Binary & (1 << 5)) != 0)
1741 LaneShift = 1; // 16-bit elements
1743 LaneShift = 2; // 32-bit elements
1745 unsigned Lane = MI.getOperand(LnOpIdx).getImm() << LaneShift;
1746 unsigned Opc1 = Lane >> 2;
1747 unsigned Opc2 = Lane & 3;
1748 assert((Opc1 & 3) == 0 && "out-of-range lane number operand");
1749 Binary |= (Opc1 << 21);
1750 Binary |= (Opc2 << 5);
1755 void ARMCodeEmitter::emitNEONDupInstruction(const MachineInstr &MI) {
1756 unsigned Binary = getBinaryCodeForInstr(MI);
1758 // Set the conditional execution predicate
1759 Binary |= (IsThumb ? ARMCC::AL : II->getPredicate(&MI)) << ARMII::CondShift;
1761 unsigned RegT = MI.getOperand(1).getReg();
1762 RegT = getARMRegisterNumbering(RegT);
1763 Binary |= (RegT << ARMII::RegRdShift);
1764 Binary |= encodeNEONRn(MI, 0);
1768 void ARMCodeEmitter::emitNEON1RegModImmInstruction(const MachineInstr &MI) {
1769 unsigned Binary = getBinaryCodeForInstr(MI);
1770 // Destination register is encoded in Dd.
1771 Binary |= encodeNEONRd(MI, 0);
1772 // Immediate fields: Op, Cmode, I, Imm3, Imm4
1773 unsigned Imm = MI.getOperand(1).getImm();
1774 unsigned Op = (Imm >> 12) & 1;
1775 unsigned Cmode = (Imm >> 8) & 0xf;
1776 unsigned I = (Imm >> 7) & 1;
1777 unsigned Imm3 = (Imm >> 4) & 0x7;
1778 unsigned Imm4 = Imm & 0xf;
1779 Binary |= (I << 24) | (Imm3 << 16) | (Cmode << 8) | (Op << 5) | Imm4;
1781 Binary = convertNEONDataProcToThumb(Binary);
1785 void ARMCodeEmitter::emitNEON2RegInstruction(const MachineInstr &MI) {
1786 const TargetInstrDesc &TID = MI.getDesc();
1787 unsigned Binary = getBinaryCodeForInstr(MI);
1788 // Destination register is encoded in Dd; source register in Dm.
1790 Binary |= encodeNEONRd(MI, OpIdx++);
1791 if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
1793 Binary |= encodeNEONRm(MI, OpIdx);
1795 Binary = convertNEONDataProcToThumb(Binary);
1796 // FIXME: This does not handle VDUPfdf or VDUPfqf.
1800 void ARMCodeEmitter::emitNEON3RegInstruction(const MachineInstr &MI) {
1801 const TargetInstrDesc &TID = MI.getDesc();
1802 unsigned Binary = getBinaryCodeForInstr(MI);
1803 // Destination register is encoded in Dd; source registers in Dn and Dm.
1805 Binary |= encodeNEONRd(MI, OpIdx++);
1806 if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
1808 Binary |= encodeNEONRn(MI, OpIdx++);
1809 if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
1811 Binary |= encodeNEONRm(MI, OpIdx);
1813 Binary = convertNEONDataProcToThumb(Binary);
1814 // FIXME: This does not handle VMOVDneon or VMOVQ.
1818 #include "ARMGenCodeEmitter.inc"