1 //===-- ARM/ARMCodeEmitter.cpp - Convert ARM code to machine code ---------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the pass that transforms the ARM machine instructions into
11 // relocatable machine code.
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "jit"
17 #include "ARMAddressingModes.h"
18 #include "ARMConstantPoolValue.h"
19 #include "ARMInstrInfo.h"
20 #include "ARMRelocations.h"
21 #include "ARMSubtarget.h"
22 #include "ARMTargetMachine.h"
23 #include "llvm/Constants.h"
24 #include "llvm/DerivedTypes.h"
25 #include "llvm/Function.h"
26 #include "llvm/PassManager.h"
27 #include "llvm/CodeGen/MachineCodeEmitter.h"
28 #include "llvm/CodeGen/MachineConstantPool.h"
29 #include "llvm/CodeGen/MachineFunctionPass.h"
30 #include "llvm/CodeGen/MachineInstr.h"
31 #include "llvm/CodeGen/MachineJumpTableInfo.h"
32 #include "llvm/CodeGen/Passes.h"
33 #include "llvm/ADT/Statistic.h"
34 #include "llvm/Support/Compiler.h"
35 #include "llvm/Support/Debug.h"
41 STATISTIC(NumEmitted, "Number of machine instructions emitted");
44 class VISIBILITY_HIDDEN ARMCodeEmitter : public MachineFunctionPass {
46 const ARMInstrInfo *II;
49 MachineCodeEmitter &MCE;
50 const std::vector<MachineConstantPoolEntry> *MCPEs;
51 const std::vector<MachineJumpTableEntry> *MJTEs;
56 explicit ARMCodeEmitter(TargetMachine &tm, MachineCodeEmitter &mce)
57 : MachineFunctionPass(&ID), JTI(0), II(0), TD(0), TM(tm),
58 MCE(mce), MCPEs(0), MJTEs(0),
59 IsPIC(TM.getRelocationModel() == Reloc::PIC_) {}
60 ARMCodeEmitter(TargetMachine &tm, MachineCodeEmitter &mce,
61 const ARMInstrInfo &ii, const TargetData &td)
62 : MachineFunctionPass(&ID), JTI(0), II(&ii), TD(&td), TM(tm),
63 MCE(mce), MCPEs(0), MJTEs(0),
64 IsPIC(TM.getRelocationModel() == Reloc::PIC_) {}
66 bool runOnMachineFunction(MachineFunction &MF);
68 virtual const char *getPassName() const {
69 return "ARM Machine Code Emitter";
72 void emitInstruction(const MachineInstr &MI);
76 void emitWordLE(unsigned Binary);
78 void emitDWordLE(uint64_t Binary);
80 void emitConstPoolInstruction(const MachineInstr &MI);
82 void emitMOVi2piecesInstruction(const MachineInstr &MI);
84 void emitLEApcrelJTInstruction(const MachineInstr &MI);
86 void addPCLabel(unsigned LabelID);
88 void emitPseudoInstruction(const MachineInstr &MI);
90 unsigned getMachineSoRegOpValue(const MachineInstr &MI,
91 const TargetInstrDesc &TID,
92 const MachineOperand &MO,
95 unsigned getMachineSoImmOpValue(unsigned SoImm);
97 unsigned getAddrModeSBit(const MachineInstr &MI,
98 const TargetInstrDesc &TID) const;
100 void emitDataProcessingInstruction(const MachineInstr &MI,
101 unsigned ImplicitRd = 0,
102 unsigned ImplicitRn = 0);
104 void emitLoadStoreInstruction(const MachineInstr &MI,
105 unsigned ImplicitRd = 0,
106 unsigned ImplicitRn = 0);
108 void emitMiscLoadStoreInstruction(const MachineInstr &MI,
109 unsigned ImplicitRn = 0);
111 void emitLoadStoreMultipleInstruction(const MachineInstr &MI);
113 void emitMulFrmInstruction(const MachineInstr &MI);
115 void emitExtendInstruction(const MachineInstr &MI);
117 void emitMiscArithInstruction(const MachineInstr &MI);
119 void emitBranchInstruction(const MachineInstr &MI);
121 void emitInlineJumpTable(unsigned JTIndex);
123 void emitMiscBranchInstruction(const MachineInstr &MI);
125 void emitVFPArithInstruction(const MachineInstr &MI);
127 void emitVFPConversionInstruction(const MachineInstr &MI);
129 void emitVFPLoadStoreInstruction(const MachineInstr &MI);
131 void emitVFPLoadStoreMultipleInstruction(const MachineInstr &MI);
133 void emitMiscInstruction(const MachineInstr &MI);
135 /// getBinaryCodeForInstr - This function, generated by the
136 /// CodeEmitterGenerator using TableGen, produces the binary encoding for
137 /// machine instructions.
139 unsigned getBinaryCodeForInstr(const MachineInstr &MI);
141 /// getMachineOpValue - Return binary encoding of operand. If the machine
142 /// operand requires relocation, record the relocation and return zero.
143 unsigned getMachineOpValue(const MachineInstr &MI,const MachineOperand &MO);
144 unsigned getMachineOpValue(const MachineInstr &MI, unsigned OpIdx) {
145 return getMachineOpValue(MI, MI.getOperand(OpIdx));
148 /// getShiftOp - Return the shift opcode (bit[6:5]) of the immediate value.
150 unsigned getShiftOp(unsigned Imm) const ;
152 /// Routines that handle operands which add machine relocations which are
153 /// fixed up by the relocation stage.
154 void emitGlobalAddress(GlobalValue *GV, unsigned Reloc,
155 bool NeedStub, intptr_t ACPV = 0);
156 void emitExternalSymbolAddress(const char *ES, unsigned Reloc);
157 void emitConstPoolAddress(unsigned CPI, unsigned Reloc);
158 void emitJumpTableAddress(unsigned JTIndex, unsigned Reloc);
159 void emitMachineBasicBlock(MachineBasicBlock *BB, unsigned Reloc,
160 intptr_t JTBase = 0);
162 char ARMCodeEmitter::ID = 0;
165 /// createARMCodeEmitterPass - Return a pass that emits the collected ARM code
166 /// to the specified MCE object.
167 FunctionPass *llvm::createARMCodeEmitterPass(ARMTargetMachine &TM,
168 MachineCodeEmitter &MCE) {
169 return new ARMCodeEmitter(TM, MCE);
172 bool ARMCodeEmitter::runOnMachineFunction(MachineFunction &MF) {
173 assert((MF.getTarget().getRelocationModel() != Reloc::Default ||
174 MF.getTarget().getRelocationModel() != Reloc::Static) &&
175 "JIT relocation model must be set to static or default!");
176 II = ((ARMTargetMachine&)MF.getTarget()).getInstrInfo();
177 TD = ((ARMTargetMachine&)MF.getTarget()).getTargetData();
178 JTI = ((ARMTargetMachine&)MF.getTarget()).getJITInfo();
179 MCPEs = &MF.getConstantPool()->getConstants();
180 MJTEs = &MF.getJumpTableInfo()->getJumpTables();
181 IsPIC = TM.getRelocationModel() == Reloc::PIC_;
182 JTI->Initialize(MF, IsPIC);
185 DOUT << "JITTing function '" << MF.getFunction()->getName() << "'\n";
186 MCE.startFunction(MF);
187 for (MachineFunction::iterator MBB = MF.begin(), E = MF.end();
189 MCE.StartMachineBasicBlock(MBB);
190 for (MachineBasicBlock::const_iterator I = MBB->begin(), E = MBB->end();
194 } while (MCE.finishFunction(MF));
199 /// getShiftOp - Return the shift opcode (bit[6:5]) of the immediate value.
201 unsigned ARMCodeEmitter::getShiftOp(unsigned Imm) const {
202 switch (ARM_AM::getAM2ShiftOpc(Imm)) {
203 default: assert(0 && "Unknown shift opc!");
204 case ARM_AM::asr: return 2;
205 case ARM_AM::lsl: return 0;
206 case ARM_AM::lsr: return 1;
208 case ARM_AM::rrx: return 3;
213 /// getMachineOpValue - Return binary encoding of operand. If the machine
214 /// operand requires relocation, record the relocation and return zero.
215 unsigned ARMCodeEmitter::getMachineOpValue(const MachineInstr &MI,
216 const MachineOperand &MO) {
218 return ARMRegisterInfo::getRegisterNumbering(MO.getReg());
220 return static_cast<unsigned>(MO.getImm());
221 else if (MO.isGlobal())
222 emitGlobalAddress(MO.getGlobal(), ARM::reloc_arm_branch, true);
223 else if (MO.isSymbol())
224 emitExternalSymbolAddress(MO.getSymbolName(), ARM::reloc_arm_branch);
226 emitConstPoolAddress(MO.getIndex(), ARM::reloc_arm_cp_entry);
228 emitJumpTableAddress(MO.getIndex(), ARM::reloc_arm_relative);
230 emitMachineBasicBlock(MO.getMBB(), ARM::reloc_arm_branch);
232 cerr << "ERROR: Unknown type of MachineOperand: " << MO << "\n";
238 /// emitGlobalAddress - Emit the specified address to the code stream.
240 void ARMCodeEmitter::emitGlobalAddress(GlobalValue *GV, unsigned Reloc,
241 bool NeedStub, intptr_t ACPV) {
242 MCE.addRelocation(MachineRelocation::getGV(MCE.getCurrentPCOffset(),
243 Reloc, GV, ACPV, NeedStub));
246 /// emitExternalSymbolAddress - Arrange for the address of an external symbol to
247 /// be emitted to the current location in the function, and allow it to be PC
249 void ARMCodeEmitter::emitExternalSymbolAddress(const char *ES, unsigned Reloc) {
250 MCE.addRelocation(MachineRelocation::getExtSym(MCE.getCurrentPCOffset(),
254 /// emitConstPoolAddress - Arrange for the address of an constant pool
255 /// to be emitted to the current location in the function, and allow it to be PC
257 void ARMCodeEmitter::emitConstPoolAddress(unsigned CPI, unsigned Reloc) {
258 // Tell JIT emitter we'll resolve the address.
259 MCE.addRelocation(MachineRelocation::getConstPool(MCE.getCurrentPCOffset(),
260 Reloc, CPI, 0, true));
263 /// emitJumpTableAddress - Arrange for the address of a jump table to
264 /// be emitted to the current location in the function, and allow it to be PC
266 void ARMCodeEmitter::emitJumpTableAddress(unsigned JTIndex, unsigned Reloc) {
267 MCE.addRelocation(MachineRelocation::getJumpTable(MCE.getCurrentPCOffset(),
268 Reloc, JTIndex, 0, true));
271 /// emitMachineBasicBlock - Emit the specified address basic block.
272 void ARMCodeEmitter::emitMachineBasicBlock(MachineBasicBlock *BB,
273 unsigned Reloc, intptr_t JTBase) {
274 MCE.addRelocation(MachineRelocation::getBB(MCE.getCurrentPCOffset(),
278 void ARMCodeEmitter::emitWordLE(unsigned Binary) {
280 DOUT << " 0x" << std::hex << std::setw(8) << std::setfill('0')
281 << Binary << std::dec << "\n";
283 MCE.emitWordLE(Binary);
286 void ARMCodeEmitter::emitDWordLE(uint64_t Binary) {
288 DOUT << " 0x" << std::hex << std::setw(8) << std::setfill('0')
289 << (unsigned)Binary << std::dec << "\n";
290 DOUT << " 0x" << std::hex << std::setw(8) << std::setfill('0')
291 << (unsigned)(Binary >> 32) << std::dec << "\n";
293 MCE.emitDWordLE(Binary);
296 void ARMCodeEmitter::emitInstruction(const MachineInstr &MI) {
297 DOUT << "JIT: " << (void*)MCE.getCurrentPCValue() << ":\t" << MI;
299 NumEmitted++; // Keep track of the # of mi's emitted
300 switch (MI.getDesc().TSFlags & ARMII::FormMask) {
302 assert(0 && "Unhandled instruction encoding format!");
305 emitPseudoInstruction(MI);
308 case ARMII::DPSoRegFrm:
309 emitDataProcessingInstruction(MI);
313 emitLoadStoreInstruction(MI);
315 case ARMII::LdMiscFrm:
316 case ARMII::StMiscFrm:
317 emitMiscLoadStoreInstruction(MI);
319 case ARMII::LdMulFrm:
320 case ARMII::StMulFrm:
321 emitLoadStoreMultipleInstruction(MI);
324 emitMulFrmInstruction(MI);
327 emitExtendInstruction(MI);
329 case ARMII::ArithMiscFrm:
330 emitMiscArithInstruction(MI);
333 emitBranchInstruction(MI);
335 case ARMII::BrMiscFrm:
336 emitMiscBranchInstruction(MI);
339 case ARMII::VFPUnaryFrm:
340 case ARMII::VFPBinaryFrm:
341 emitVFPArithInstruction(MI);
343 case ARMII::VFPConv1Frm:
344 case ARMII::VFPConv2Frm:
345 case ARMII::VFPConv3Frm:
346 emitVFPConversionInstruction(MI);
348 case ARMII::VFPLdStFrm:
349 emitVFPLoadStoreInstruction(MI);
351 case ARMII::VFPLdStMulFrm:
352 emitVFPLoadStoreMultipleInstruction(MI);
354 case ARMII::VFPMiscFrm:
355 emitMiscInstruction(MI);
360 void ARMCodeEmitter::emitConstPoolInstruction(const MachineInstr &MI) {
361 unsigned CPI = MI.getOperand(0).getImm(); // CP instruction index.
362 unsigned CPIndex = MI.getOperand(1).getIndex(); // Actual cp entry index.
363 const MachineConstantPoolEntry &MCPE = (*MCPEs)[CPIndex];
365 // Remember the CONSTPOOL_ENTRY address for later relocation.
366 JTI->addConstantPoolEntryAddr(CPI, MCE.getCurrentPCValue());
368 // Emit constpool island entry. In most cases, the actual values will be
369 // resolved and relocated after code emission.
370 if (MCPE.isMachineConstantPoolEntry()) {
371 ARMConstantPoolValue *ACPV =
372 static_cast<ARMConstantPoolValue*>(MCPE.Val.MachineCPVal);
374 DOUT << " ** ARM constant pool #" << CPI << " @ "
375 << (void*)MCE.getCurrentPCValue() << " " << *ACPV << '\n';
377 GlobalValue *GV = ACPV->getGV();
379 assert(!ACPV->isStub() && "Don't know how to deal this yet!");
380 if (ACPV->isNonLazyPointer())
381 MCE.addRelocation(MachineRelocation::getIndirectSymbol(
382 MCE.getCurrentPCOffset(), ARM::reloc_arm_machine_cp_entry, GV,
383 (intptr_t)ACPV, false));
385 emitGlobalAddress(GV, ARM::reloc_arm_machine_cp_entry,
386 ACPV->isStub(), (intptr_t)ACPV);
388 assert(!ACPV->isNonLazyPointer() && "Don't know how to deal this yet!");
389 emitExternalSymbolAddress(ACPV->getSymbol(), ARM::reloc_arm_absolute);
393 Constant *CV = MCPE.Val.ConstVal;
395 DOUT << " ** Constant pool #" << CPI << " @ "
396 << (void*)MCE.getCurrentPCValue() << " " << *CV << '\n';
398 if (GlobalValue *GV = dyn_cast<GlobalValue>(CV)) {
399 emitGlobalAddress(GV, ARM::reloc_arm_absolute, false);
401 } else if (const ConstantInt *CI = dyn_cast<ConstantInt>(CV)) {
402 uint32_t Val = *(uint32_t*)CI->getValue().getRawData();
404 } else if (const ConstantFP *CFP = dyn_cast<ConstantFP>(CV)) {
405 if (CFP->getType() == Type::FloatTy)
406 emitWordLE(CFP->getValueAPF().bitcastToAPInt().getZExtValue());
407 else if (CFP->getType() == Type::DoubleTy)
408 emitDWordLE(CFP->getValueAPF().bitcastToAPInt().getZExtValue());
410 assert(0 && "Unable to handle this constantpool entry!");
414 assert(0 && "Unable to handle this constantpool entry!");
420 void ARMCodeEmitter::emitMOVi2piecesInstruction(const MachineInstr &MI) {
421 const MachineOperand &MO0 = MI.getOperand(0);
422 const MachineOperand &MO1 = MI.getOperand(1);
423 assert(MO1.isImm() && "Not a valid so_imm value!");
424 unsigned V1 = ARM_AM::getSOImmTwoPartFirst(MO1.getImm());
425 unsigned V2 = ARM_AM::getSOImmTwoPartSecond(MO1.getImm());
427 // Emit the 'mov' instruction.
428 unsigned Binary = 0xd << 21; // mov: Insts{24-21} = 0b1101
430 // Set the conditional execution predicate.
431 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
434 Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRdShift;
437 // Set bit I(25) to identify this is the immediate form of <shifter_op>
438 Binary |= 1 << ARMII::I_BitShift;
439 Binary |= getMachineSoImmOpValue(ARM_AM::getSOImmVal(V1));
442 // Now the 'orr' instruction.
443 Binary = 0xc << 21; // orr: Insts{24-21} = 0b1100
445 // Set the conditional execution predicate.
446 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
449 Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRdShift;
452 Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRnShift;
455 // Set bit I(25) to identify this is the immediate form of <shifter_op>
456 Binary |= 1 << ARMII::I_BitShift;
457 Binary |= getMachineSoImmOpValue(ARM_AM::getSOImmVal(V2));
461 void ARMCodeEmitter::emitLEApcrelJTInstruction(const MachineInstr &MI) {
462 // It's basically add r, pc, (LJTI - $+8)
464 const TargetInstrDesc &TID = MI.getDesc();
466 // Emit the 'add' instruction.
467 unsigned Binary = 0x4 << 21; // add: Insts{24-31} = 0b0100
469 // Set the conditional execution predicate
470 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
472 // Encode S bit if MI modifies CPSR.
473 Binary |= getAddrModeSBit(MI, TID);
476 Binary |= getMachineOpValue(MI, 0) << ARMII::RegRdShift;
478 // Encode Rn which is PC.
479 Binary |= ARMRegisterInfo::getRegisterNumbering(ARM::PC) << ARMII::RegRnShift;
481 // Encode the displacement.
482 // Set bit I(25) to identify this is the immediate form of <shifter_op>.
483 Binary |= 1 << ARMII::I_BitShift;
484 emitJumpTableAddress(MI.getOperand(1).getIndex(), ARM::reloc_arm_jt_base);
489 void ARMCodeEmitter::addPCLabel(unsigned LabelID) {
490 DOUT << " ** LPC" << LabelID << " @ "
491 << (void*)MCE.getCurrentPCValue() << '\n';
492 JTI->addPCLabelAddr(LabelID, MCE.getCurrentPCValue());
495 void ARMCodeEmitter::emitPseudoInstruction(const MachineInstr &MI) {
496 unsigned Opcode = MI.getDesc().Opcode;
500 case ARM::CONSTPOOL_ENTRY:
501 emitConstPoolInstruction(MI);
504 // Remember of the address of the PC label for relocation later.
505 addPCLabel(MI.getOperand(2).getImm());
506 // PICADD is just an add instruction that implicitly read pc.
507 emitDataProcessingInstruction(MI, 0, ARM::PC);
514 // Remember of the address of the PC label for relocation later.
515 addPCLabel(MI.getOperand(2).getImm());
516 // These are just load / store instructions that implicitly read pc.
517 emitLoadStoreInstruction(MI, 0, ARM::PC);
524 // Remember of the address of the PC label for relocation later.
525 addPCLabel(MI.getOperand(2).getImm());
526 // These are just load / store instructions that implicitly read pc.
527 emitMiscLoadStoreInstruction(MI, ARM::PC);
530 case ARM::MOVi2pieces:
531 // Two instructions to materialize a constant.
532 emitMOVi2piecesInstruction(MI);
534 case ARM::LEApcrelJT:
535 // Materialize jumptable address.
536 emitLEApcrelJTInstruction(MI);
542 unsigned ARMCodeEmitter::getMachineSoRegOpValue(const MachineInstr &MI,
543 const TargetInstrDesc &TID,
544 const MachineOperand &MO,
546 unsigned Binary = getMachineOpValue(MI, MO);
548 const MachineOperand &MO1 = MI.getOperand(OpIdx + 1);
549 const MachineOperand &MO2 = MI.getOperand(OpIdx + 2);
550 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO2.getImm());
552 // Encode the shift opcode.
554 unsigned Rs = MO1.getReg();
556 // Set shift operand (bit[7:4]).
561 // RRX - 0110 and bit[11:8] clear.
563 default: assert(0 && "Unknown shift opc!");
564 case ARM_AM::lsl: SBits = 0x1; break;
565 case ARM_AM::lsr: SBits = 0x3; break;
566 case ARM_AM::asr: SBits = 0x5; break;
567 case ARM_AM::ror: SBits = 0x7; break;
568 case ARM_AM::rrx: SBits = 0x6; break;
571 // Set shift operand (bit[6:4]).
577 default: assert(0 && "Unknown shift opc!");
578 case ARM_AM::lsl: SBits = 0x0; break;
579 case ARM_AM::lsr: SBits = 0x2; break;
580 case ARM_AM::asr: SBits = 0x4; break;
581 case ARM_AM::ror: SBits = 0x6; break;
584 Binary |= SBits << 4;
585 if (SOpc == ARM_AM::rrx)
588 // Encode the shift operation Rs or shift_imm (except rrx).
590 // Encode Rs bit[11:8].
591 assert(ARM_AM::getSORegOffset(MO2.getImm()) == 0);
593 (ARMRegisterInfo::getRegisterNumbering(Rs) << ARMII::RegRsShift);
596 // Encode shift_imm bit[11:7].
597 return Binary | ARM_AM::getSORegOffset(MO2.getImm()) << 7;
600 unsigned ARMCodeEmitter::getMachineSoImmOpValue(unsigned SoImm) {
601 // Encode rotate_imm.
602 unsigned Binary = (ARM_AM::getSOImmValRot(SoImm) >> 1)
603 << ARMII::SoRotImmShift;
606 Binary |= ARM_AM::getSOImmValImm(SoImm);
610 unsigned ARMCodeEmitter::getAddrModeSBit(const MachineInstr &MI,
611 const TargetInstrDesc &TID) const {
612 for (unsigned i = MI.getNumOperands(), e = TID.getNumOperands(); i != e; --i){
613 const MachineOperand &MO = MI.getOperand(i-1);
614 if (MO.isReg() && MO.isDef() && MO.getReg() == ARM::CPSR)
615 return 1 << ARMII::S_BitShift;
620 void ARMCodeEmitter::emitDataProcessingInstruction(const MachineInstr &MI,
622 unsigned ImplicitRn) {
623 const TargetInstrDesc &TID = MI.getDesc();
625 // Part of binary is determined by TableGn.
626 unsigned Binary = getBinaryCodeForInstr(MI);
628 // Set the conditional execution predicate
629 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
631 // Encode S bit if MI modifies CPSR.
632 Binary |= getAddrModeSBit(MI, TID);
634 // Encode register def if there is one.
635 unsigned NumDefs = TID.getNumDefs();
638 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
640 // Special handling for implicit use (e.g. PC).
641 Binary |= (ARMRegisterInfo::getRegisterNumbering(ImplicitRd)
642 << ARMII::RegRdShift);
644 // If this is a two-address operand, skip it. e.g. MOVCCr operand 1.
645 if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
648 // Encode first non-shifter register operand if there is one.
649 bool isUnary = TID.TSFlags & ARMII::UnaryDP;
652 // Special handling for implicit use (e.g. PC).
653 Binary |= (ARMRegisterInfo::getRegisterNumbering(ImplicitRn)
654 << ARMII::RegRnShift);
656 Binary |= getMachineOpValue(MI, OpIdx) << ARMII::RegRnShift;
661 // Encode shifter operand.
662 const MachineOperand &MO = MI.getOperand(OpIdx);
663 if ((TID.TSFlags & ARMII::FormMask) == ARMII::DPSoRegFrm) {
665 emitWordLE(Binary | getMachineSoRegOpValue(MI, TID, MO, OpIdx));
670 // Encode register Rm.
671 emitWordLE(Binary | ARMRegisterInfo::getRegisterNumbering(MO.getReg()));
676 // Set bit I(25) to identify this is the immediate form of <shifter_op>.
677 Binary |= 1 << ARMII::I_BitShift;
678 Binary |= getMachineSoImmOpValue(MO.getImm());
683 void ARMCodeEmitter::emitLoadStoreInstruction(const MachineInstr &MI,
685 unsigned ImplicitRn) {
686 const TargetInstrDesc &TID = MI.getDesc();
688 // Part of binary is determined by TableGn.
689 unsigned Binary = getBinaryCodeForInstr(MI);
691 // Set the conditional execution predicate
692 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
697 // Special handling for implicit use (e.g. PC).
698 Binary |= (ARMRegisterInfo::getRegisterNumbering(ImplicitRd)
699 << ARMII::RegRdShift);
701 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
703 // Set second operand
705 // Special handling for implicit use (e.g. PC).
706 Binary |= (ARMRegisterInfo::getRegisterNumbering(ImplicitRn)
707 << ARMII::RegRnShift);
709 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift;
711 // If this is a two-address operand, skip it. e.g. LDR_PRE.
712 if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
715 const MachineOperand &MO2 = MI.getOperand(OpIdx);
716 unsigned AM2Opc = (ImplicitRn == ARM::PC)
717 ? 0 : MI.getOperand(OpIdx+1).getImm();
719 // Set bit U(23) according to sign of immed value (positive or negative).
720 Binary |= ((ARM_AM::getAM2Op(AM2Opc) == ARM_AM::add ? 1 : 0) <<
722 if (!MO2.getReg()) { // is immediate
723 if (ARM_AM::getAM2Offset(AM2Opc))
724 // Set the value of offset_12 field
725 Binary |= ARM_AM::getAM2Offset(AM2Opc);
730 // Set bit I(25), because this is not in immediate enconding.
731 Binary |= 1 << ARMII::I_BitShift;
732 assert(TargetRegisterInfo::isPhysicalRegister(MO2.getReg()));
733 // Set bit[3:0] to the corresponding Rm register
734 Binary |= ARMRegisterInfo::getRegisterNumbering(MO2.getReg());
736 // if this instr is in scaled register offset/index instruction, set
737 // shift_immed(bit[11:7]) and shift(bit[6:5]) fields.
738 if (unsigned ShImm = ARM_AM::getAM2Offset(AM2Opc)) {
739 Binary |= getShiftOp(AM2Opc) << 5; // shift
740 Binary |= ShImm << 7; // shift_immed
746 void ARMCodeEmitter::emitMiscLoadStoreInstruction(const MachineInstr &MI,
747 unsigned ImplicitRn) {
748 const TargetInstrDesc &TID = MI.getDesc();
750 // Part of binary is determined by TableGn.
751 unsigned Binary = getBinaryCodeForInstr(MI);
753 // Set the conditional execution predicate
754 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
757 Binary |= getMachineOpValue(MI, 0) << ARMII::RegRdShift;
759 // Set second operand
762 // Special handling for implicit use (e.g. PC).
763 Binary |= (ARMRegisterInfo::getRegisterNumbering(ImplicitRn)
764 << ARMII::RegRnShift);
766 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift;
768 // If this is a two-address operand, skip it. e.g. LDRH_POST.
769 if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
772 const MachineOperand &MO2 = MI.getOperand(OpIdx);
773 unsigned AM3Opc = (ImplicitRn == ARM::PC)
774 ? 0 : MI.getOperand(OpIdx+1).getImm();
776 // Set bit U(23) according to sign of immed value (positive or negative)
777 Binary |= ((ARM_AM::getAM3Op(AM3Opc) == ARM_AM::add ? 1 : 0) <<
780 // If this instr is in register offset/index encoding, set bit[3:0]
781 // to the corresponding Rm register.
783 Binary |= ARMRegisterInfo::getRegisterNumbering(MO2.getReg());
788 // This instr is in immediate offset/index encoding, set bit 22 to 1.
789 Binary |= 1 << ARMII::AM3_I_BitShift;
790 if (unsigned ImmOffs = ARM_AM::getAM3Offset(AM3Opc)) {
792 Binary |= (ImmOffs >> 4) << 8; // immedH
793 Binary |= (ImmOffs & ~0xF); // immedL
799 static unsigned getAddrModeUPBits(unsigned Mode) {
802 // Set addressing mode by modifying bits U(23) and P(24)
803 // IA - Increment after - bit U = 1 and bit P = 0
804 // IB - Increment before - bit U = 1 and bit P = 1
805 // DA - Decrement after - bit U = 0 and bit P = 0
806 // DB - Decrement before - bit U = 0 and bit P = 1
808 default: assert(0 && "Unknown addressing sub-mode!");
809 case ARM_AM::da: break;
810 case ARM_AM::db: Binary |= 0x1 << ARMII::P_BitShift; break;
811 case ARM_AM::ia: Binary |= 0x1 << ARMII::U_BitShift; break;
812 case ARM_AM::ib: Binary |= 0x3 << ARMII::U_BitShift; break;
818 void ARMCodeEmitter::emitLoadStoreMultipleInstruction(const MachineInstr &MI) {
819 // Part of binary is determined by TableGn.
820 unsigned Binary = getBinaryCodeForInstr(MI);
822 // Set the conditional execution predicate
823 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
825 // Set base address operand
826 Binary |= getMachineOpValue(MI, 0) << ARMII::RegRnShift;
828 // Set addressing mode by modifying bits U(23) and P(24)
829 const MachineOperand &MO = MI.getOperand(1);
830 Binary |= getAddrModeUPBits(ARM_AM::getAM4SubMode(MO.getImm()));
833 if (ARM_AM::getAM4WBFlag(MO.getImm()))
834 Binary |= 0x1 << ARMII::W_BitShift;
837 for (unsigned i = 4, e = MI.getNumOperands(); i != e; ++i) {
838 const MachineOperand &MO = MI.getOperand(i);
839 if (!MO.isReg() || MO.isImplicit())
841 unsigned RegNum = ARMRegisterInfo::getRegisterNumbering(MO.getReg());
842 assert(TargetRegisterInfo::isPhysicalRegister(MO.getReg()) &&
844 Binary |= 0x1 << RegNum;
850 void ARMCodeEmitter::emitMulFrmInstruction(const MachineInstr &MI) {
851 const TargetInstrDesc &TID = MI.getDesc();
853 // Part of binary is determined by TableGn.
854 unsigned Binary = getBinaryCodeForInstr(MI);
856 // Set the conditional execution predicate
857 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
859 // Encode S bit if MI modifies CPSR.
860 Binary |= getAddrModeSBit(MI, TID);
862 // 32x32->64bit operations have two destination registers. The number
863 // of register definitions will tell us if that's what we're dealing with.
865 if (TID.getNumDefs() == 2)
866 Binary |= getMachineOpValue (MI, OpIdx++) << ARMII::RegRdLoShift;
869 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdHiShift;
872 Binary |= getMachineOpValue(MI, OpIdx++);
875 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRsShift;
877 // Many multiple instructions (e.g. MLA) have three src operands. Encode
878 // it as Rn (for multiply, that's in the same offset as RdLo.
879 if (TID.getNumOperands() > OpIdx &&
880 !TID.OpInfo[OpIdx].isPredicate() &&
881 !TID.OpInfo[OpIdx].isOptionalDef())
882 Binary |= getMachineOpValue(MI, OpIdx) << ARMII::RegRdLoShift;
887 void ARMCodeEmitter::emitExtendInstruction(const MachineInstr &MI) {
888 const TargetInstrDesc &TID = MI.getDesc();
890 // Part of binary is determined by TableGn.
891 unsigned Binary = getBinaryCodeForInstr(MI);
893 // Set the conditional execution predicate
894 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
899 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
901 const MachineOperand &MO1 = MI.getOperand(OpIdx++);
902 const MachineOperand &MO2 = MI.getOperand(OpIdx);
904 // Two register operand form.
906 Binary |= getMachineOpValue(MI, MO1) << ARMII::RegRnShift;
909 Binary |= getMachineOpValue(MI, MO2);
912 Binary |= getMachineOpValue(MI, MO1);
915 // Encode rot imm (0, 8, 16, or 24) if it has a rotate immediate operand.
916 if (MI.getOperand(OpIdx).isImm() &&
917 !TID.OpInfo[OpIdx].isPredicate() &&
918 !TID.OpInfo[OpIdx].isOptionalDef())
919 Binary |= (getMachineOpValue(MI, OpIdx) / 8) << ARMII::ExtRotImmShift;
924 void ARMCodeEmitter::emitMiscArithInstruction(const MachineInstr &MI) {
925 const TargetInstrDesc &TID = MI.getDesc();
927 // Part of binary is determined by TableGn.
928 unsigned Binary = getBinaryCodeForInstr(MI);
930 // Set the conditional execution predicate
931 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
936 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
938 const MachineOperand &MO = MI.getOperand(OpIdx++);
939 if (OpIdx == TID.getNumOperands() ||
940 TID.OpInfo[OpIdx].isPredicate() ||
941 TID.OpInfo[OpIdx].isOptionalDef()) {
942 // Encode Rm and it's done.
943 Binary |= getMachineOpValue(MI, MO);
949 Binary |= getMachineOpValue(MI, MO) << ARMII::RegRnShift;
952 Binary |= getMachineOpValue(MI, OpIdx++);
955 unsigned ShiftAmt = MI.getOperand(OpIdx).getImm();
956 assert(ShiftAmt < 32 && "shift_imm range is 0 to 31!");
957 Binary |= ShiftAmt << ARMII::ShiftShift;
962 void ARMCodeEmitter::emitBranchInstruction(const MachineInstr &MI) {
963 const TargetInstrDesc &TID = MI.getDesc();
965 if (TID.Opcode == ARM::TPsoft)
968 // Part of binary is determined by TableGn.
969 unsigned Binary = getBinaryCodeForInstr(MI);
971 // Set the conditional execution predicate
972 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
974 // Set signed_immed_24 field
975 Binary |= getMachineOpValue(MI, 0);
980 void ARMCodeEmitter::emitInlineJumpTable(unsigned JTIndex) {
981 // Remember the base address of the inline jump table.
982 intptr_t JTBase = MCE.getCurrentPCValue();
983 JTI->addJumpTableBaseAddr(JTIndex, JTBase);
984 DOUT << " ** Jump Table #" << JTIndex << " @ " << (void*)JTBase << '\n';
986 // Now emit the jump table entries.
987 const std::vector<MachineBasicBlock*> &MBBs = (*MJTEs)[JTIndex].MBBs;
988 for (unsigned i = 0, e = MBBs.size(); i != e; ++i) {
990 // DestBB address - JT base.
991 emitMachineBasicBlock(MBBs[i], ARM::reloc_arm_pic_jt, JTBase);
993 // Absolute DestBB address.
994 emitMachineBasicBlock(MBBs[i], ARM::reloc_arm_absolute);
999 void ARMCodeEmitter::emitMiscBranchInstruction(const MachineInstr &MI) {
1000 const TargetInstrDesc &TID = MI.getDesc();
1002 // Handle jump tables.
1003 if (TID.Opcode == ARM::BR_JTr || TID.Opcode == ARM::BR_JTadd) {
1004 // First emit a ldr pc, [] instruction.
1005 emitDataProcessingInstruction(MI, ARM::PC);
1007 // Then emit the inline jump table.
1008 unsigned JTIndex = (TID.Opcode == ARM::BR_JTr)
1009 ? MI.getOperand(1).getIndex() : MI.getOperand(2).getIndex();
1010 emitInlineJumpTable(JTIndex);
1012 } else if (TID.Opcode == ARM::BR_JTm) {
1013 // First emit a ldr pc, [] instruction.
1014 emitLoadStoreInstruction(MI, ARM::PC);
1016 // Then emit the inline jump table.
1017 emitInlineJumpTable(MI.getOperand(3).getIndex());
1021 // Part of binary is determined by TableGn.
1022 unsigned Binary = getBinaryCodeForInstr(MI);
1024 // Set the conditional execution predicate
1025 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1027 if (TID.Opcode == ARM::BX_RET)
1028 // The return register is LR.
1029 Binary |= ARMRegisterInfo::getRegisterNumbering(ARM::LR);
1031 // otherwise, set the return register
1032 Binary |= getMachineOpValue(MI, 0);
1037 void ARMCodeEmitter::emitVFPArithInstruction(const MachineInstr &MI) {
1038 const TargetInstrDesc &TID = MI.getDesc();
1040 // Part of binary is determined by TableGn.
1041 unsigned Binary = getBinaryCodeForInstr(MI);
1043 // Set the conditional execution predicate
1044 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1047 assert((Binary & ARMII::D_BitShift) == 0 &&
1048 (Binary & ARMII::N_BitShift) == 0 &&
1049 (Binary & ARMII::M_BitShift) == 0 && "VFP encoding bug!");
1052 unsigned RegD = getMachineOpValue(MI, OpIdx++);
1053 Binary |= (RegD & 0x0f) << ARMII::RegRdShift;
1054 Binary |= (RegD & 0x10) << ARMII::D_BitShift;
1056 // If this is a two-address operand, skip it, e.g. FMACD.
1057 if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
1061 if ((TID.TSFlags & ARMII::FormMask) == ARMII::VFPBinaryFrm) {
1062 unsigned RegN = getMachineOpValue(MI, OpIdx++);
1063 Binary |= (RegN & 0x0f) << ARMII::RegRnShift;
1064 Binary |= (RegN & 0x10) << ARMII::N_BitShift;
1068 unsigned RegM = getMachineOpValue(MI, OpIdx++);
1069 Binary |= (RegM & 0x0f);
1070 Binary |= (RegM & 0x10) << ARMII::M_BitShift;
1075 void ARMCodeEmitter::emitVFPConversionInstruction(const MachineInstr &MI) {
1076 const TargetInstrDesc &TID = MI.getDesc();
1078 // Part of binary is determined by TableGn.
1079 unsigned Binary = getBinaryCodeForInstr(MI);
1081 // Set the conditional execution predicate
1082 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1084 // FMDRR encodes registers in reverse order.
1085 unsigned Form = TID.TSFlags & ARMII::FormMask;
1086 unsigned OpIdx = (Form == ARMII::VFPConv2Frm) ? 2 : 0;
1089 unsigned RegD = getMachineOpValue(MI, OpIdx);
1090 Binary |= (RegD & 0x0f) << ARMII::RegRdShift;
1091 Binary |= (RegD & 0x10) << ARMII::D_BitShift;
1092 if (Form == ARMII::VFPConv2Frm)
1098 if (Form == ARMII::VFPConv1Frm || Form == ARMII::VFPConv2Frm) {
1099 unsigned RegN = getMachineOpValue(MI, OpIdx);
1100 Binary |= (RegN & 0x0f) << ARMII::RegRnShift;
1101 Binary |= (RegN & 0x10) << ARMII::N_BitShift;
1102 if (Form == ARMII::VFPConv2Frm)
1107 // FMRS / FMSR do not have Rm.
1108 if (TID.getNumOperands() > OpIdx && MI.getOperand(OpIdx).isReg()) {
1109 unsigned RegM = getMachineOpValue(MI, OpIdx);
1110 Binary |= (RegM & 0x0f);
1111 Binary |= (RegM & 0x10) << ARMII::M_BitShift;
1112 } else if (Form == ARMII::VFPConv2Frm) {
1113 // FMDRR encodes definition register in Dm field.
1114 Binary |= getMachineOpValue(MI, 0);
1117 assert(Form == ARMII::VFPConv3Frm && "Unsupported format!");
1118 unsigned RegM = getMachineOpValue(MI, OpIdx);
1119 Binary |= (RegM & 0x0f);
1120 Binary |= (RegM & 0x10) << ARMII::M_BitShift;
1126 void ARMCodeEmitter::emitVFPLoadStoreInstruction(const MachineInstr &MI) {
1127 // Part of binary is determined by TableGn.
1128 unsigned Binary = getBinaryCodeForInstr(MI);
1130 // Set the conditional execution predicate
1131 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1136 unsigned RegD = getMachineOpValue(MI, OpIdx++);
1137 Binary |= (RegD & 0x0f) << ARMII::RegRdShift;
1138 Binary |= (RegD & 0x10) << ARMII::D_BitShift;
1140 // Encode address base.
1141 const MachineOperand &Base = MI.getOperand(OpIdx++);
1142 Binary |= getMachineOpValue(MI, Base) << ARMII::RegRnShift;
1144 // If there is a non-zero immediate offset, encode it.
1146 const MachineOperand &Offset = MI.getOperand(OpIdx);
1147 if (unsigned ImmOffs = ARM_AM::getAM5Offset(Offset.getImm())) {
1148 if (ARM_AM::getAM5Op(Offset.getImm()) == ARM_AM::add)
1149 Binary |= 1 << ARMII::U_BitShift;
1150 // Immediate offset is multiplied by 4.
1151 Binary |= ImmOffs >> 2;
1157 // If immediate offset is omitted, default to +0.
1158 Binary |= 1 << ARMII::U_BitShift;
1164 ARMCodeEmitter::emitVFPLoadStoreMultipleInstruction(const MachineInstr &MI) {
1165 // Part of binary is determined by TableGn.
1166 unsigned Binary = getBinaryCodeForInstr(MI);
1168 // Set the conditional execution predicate
1169 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1171 // Set base address operand
1172 Binary |= getMachineOpValue(MI, 0) << ARMII::RegRnShift;
1174 // Set addressing mode by modifying bits U(23) and P(24)
1175 const MachineOperand &MO = MI.getOperand(1);
1176 Binary |= getAddrModeUPBits(ARM_AM::getAM5SubMode(MO.getImm()));
1179 if (ARM_AM::getAM5WBFlag(MO.getImm()))
1180 Binary |= 0x1 << ARMII::W_BitShift;
1182 // First register is encoded in Dd.
1183 unsigned FirstReg = MI.getOperand(4).getReg();
1184 Binary |= ARMRegisterInfo::getRegisterNumbering(FirstReg)<< ARMII::RegRdShift;
1186 // Number of registers are encoded in offset field.
1187 unsigned NumRegs = 1;
1188 for (unsigned i = 5, e = MI.getNumOperands(); i != e; ++i) {
1189 const MachineOperand &MO = MI.getOperand(i);
1190 if (!MO.isReg() || MO.isImplicit())
1194 Binary |= NumRegs * 2;
1199 void ARMCodeEmitter::emitMiscInstruction(const MachineInstr &MI) {
1200 // Part of binary is determined by TableGn.
1201 unsigned Binary = getBinaryCodeForInstr(MI);
1203 // Set the conditional execution predicate
1204 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1209 #include "ARMGenCodeEmitter.inc"