1 //===-- ARM/ARMCodeEmitter.cpp - Convert ARM code to machine code ---------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the pass that transforms the ARM machine instructions into
11 // relocatable machine code.
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "jit"
17 #include "ARMAddressingModes.h"
18 #include "ARMConstantPoolValue.h"
19 #include "ARMInstrInfo.h"
20 #include "ARMRelocations.h"
21 #include "ARMSubtarget.h"
22 #include "ARMTargetMachine.h"
23 #include "llvm/Constants.h"
24 #include "llvm/DerivedTypes.h"
25 #include "llvm/Function.h"
26 #include "llvm/PassManager.h"
27 #include "llvm/CodeGen/JITCodeEmitter.h"
28 #include "llvm/CodeGen/MachineConstantPool.h"
29 #include "llvm/CodeGen/MachineFunctionPass.h"
30 #include "llvm/CodeGen/MachineInstr.h"
31 #include "llvm/CodeGen/MachineJumpTableInfo.h"
32 #include "llvm/CodeGen/MachineModuleInfo.h"
33 #include "llvm/CodeGen/Passes.h"
34 #include "llvm/ADT/Statistic.h"
35 #include "llvm/Support/Debug.h"
36 #include "llvm/Support/ErrorHandling.h"
37 #include "llvm/Support/raw_ostream.h"
43 STATISTIC(NumEmitted, "Number of machine instructions emitted");
47 class ARMCodeEmitter : public MachineFunctionPass {
49 const ARMInstrInfo *II;
51 const ARMSubtarget *Subtarget;
54 MachineModuleInfo *MMI;
55 const std::vector<MachineConstantPoolEntry> *MCPEs;
56 const std::vector<MachineJumpTableEntry> *MJTEs;
60 void getAnalysisUsage(AnalysisUsage &AU) const {
61 AU.addRequired<MachineModuleInfo>();
62 MachineFunctionPass::getAnalysisUsage(AU);
67 ARMCodeEmitter(TargetMachine &tm, JITCodeEmitter &mce)
68 : MachineFunctionPass(ID), JTI(0),
69 II((const ARMInstrInfo *)tm.getInstrInfo()),
70 TD(tm.getTargetData()), TM(tm),
71 MCE(mce), MCPEs(0), MJTEs(0),
72 IsPIC(TM.getRelocationModel() == Reloc::PIC_), IsThumb(false) {}
74 /// getBinaryCodeForInstr - This function, generated by the
75 /// CodeEmitterGenerator using TableGen, produces the binary encoding for
76 /// machine instructions.
77 unsigned getBinaryCodeForInstr(const MachineInstr &MI) const;
79 bool runOnMachineFunction(MachineFunction &MF);
81 virtual const char *getPassName() const {
82 return "ARM Machine Code Emitter";
85 void emitInstruction(const MachineInstr &MI);
89 void emitWordLE(unsigned Binary);
90 void emitDWordLE(uint64_t Binary);
91 void emitConstPoolInstruction(const MachineInstr &MI);
92 void emitMOVi32immInstruction(const MachineInstr &MI);
93 void emitMOVi2piecesInstruction(const MachineInstr &MI);
94 void emitLEApcrelJTInstruction(const MachineInstr &MI);
95 void emitPseudoMoveInstruction(const MachineInstr &MI);
96 void addPCLabel(unsigned LabelID);
97 void emitPseudoInstruction(const MachineInstr &MI);
98 unsigned getMachineSoRegOpValue(const MachineInstr &MI,
99 const TargetInstrDesc &TID,
100 const MachineOperand &MO,
103 unsigned getMachineSoImmOpValue(unsigned SoImm);
104 unsigned getAddrModeSBit(const MachineInstr &MI,
105 const TargetInstrDesc &TID) const;
107 void emitDataProcessingInstruction(const MachineInstr &MI,
108 unsigned ImplicitRd = 0,
109 unsigned ImplicitRn = 0);
111 void emitLoadStoreInstruction(const MachineInstr &MI,
112 unsigned ImplicitRd = 0,
113 unsigned ImplicitRn = 0);
115 void emitMiscLoadStoreInstruction(const MachineInstr &MI,
116 unsigned ImplicitRn = 0);
118 void emitLoadStoreMultipleInstruction(const MachineInstr &MI);
120 void emitMulFrmInstruction(const MachineInstr &MI);
122 void emitExtendInstruction(const MachineInstr &MI);
124 void emitMiscArithInstruction(const MachineInstr &MI);
126 void emitSaturateInstruction(const MachineInstr &MI);
128 void emitBranchInstruction(const MachineInstr &MI);
130 void emitInlineJumpTable(unsigned JTIndex);
132 void emitMiscBranchInstruction(const MachineInstr &MI);
134 void emitVFPArithInstruction(const MachineInstr &MI);
136 void emitVFPConversionInstruction(const MachineInstr &MI);
138 void emitVFPLoadStoreInstruction(const MachineInstr &MI);
140 void emitVFPLoadStoreMultipleInstruction(const MachineInstr &MI);
142 void emitNEONLaneInstruction(const MachineInstr &MI);
143 void emitNEONDupInstruction(const MachineInstr &MI);
144 void emitNEON1RegModImmInstruction(const MachineInstr &MI);
145 void emitNEON2RegInstruction(const MachineInstr &MI);
146 void emitNEON3RegInstruction(const MachineInstr &MI);
148 /// getMachineOpValue - Return binary encoding of operand. If the machine
149 /// operand requires relocation, record the relocation and return zero.
150 unsigned getMachineOpValue(const MachineInstr &MI,
151 const MachineOperand &MO) const;
152 unsigned getMachineOpValue(const MachineInstr &MI, unsigned OpIdx) const {
153 return getMachineOpValue(MI, MI.getOperand(OpIdx));
156 // FIXME: The legacy JIT ARMCodeEmitter doesn't rely on the the
157 // TableGen'erated getBinaryCodeForInstr() function to encode any
158 // operand values, instead querying getMachineOpValue() directly for
159 // each operand it needs to encode. Thus, any of the new encoder
160 // helper functions can simply return 0 as the values the return
161 // are already handled elsewhere. They are placeholders to allow this
162 // encoder to continue to function until the MC encoder is sufficiently
163 // far along that this one can be eliminated entirely.
164 unsigned NEONThumb2DataIPostEncoder(const MachineInstr &MI, unsigned Val)
166 unsigned NEONThumb2LoadStorePostEncoder(const MachineInstr &MI,unsigned Val)
168 unsigned NEONThumb2DupPostEncoder(const MachineInstr &MI,unsigned Val)
170 unsigned VFPThumb2PostEncoder(const MachineInstr&MI, unsigned Val)
172 unsigned getAdrLabelOpValue(const MachineInstr &MI, unsigned Op)
174 unsigned getThumbAdrLabelOpValue(const MachineInstr &MI, unsigned Op)
176 unsigned getThumbBLTargetOpValue(const MachineInstr &MI, unsigned Op)
178 unsigned getThumbBLXTargetOpValue(const MachineInstr &MI, unsigned Op)
180 unsigned getThumbBRTargetOpValue(const MachineInstr &MI, unsigned Op)
182 unsigned getThumbBCCTargetOpValue(const MachineInstr &MI, unsigned Op)
184 unsigned getThumbCBTargetOpValue(const MachineInstr &MI, unsigned Op)
186 unsigned getBranchTargetOpValue(const MachineInstr &MI, unsigned Op)
188 unsigned getUnconditionalBranchTargetOpValue(const MachineInstr &MI,
189 unsigned Op) const { return 0; }
190 unsigned getARMBranchTargetOpValue(const MachineInstr &MI, unsigned Op)
192 unsigned getCCOutOpValue(const MachineInstr &MI, unsigned Op)
194 unsigned getSOImmOpValue(const MachineInstr &MI, unsigned Op)
196 unsigned getT2SOImmOpValue(const MachineInstr &MI, unsigned Op)
198 unsigned getSORegOpValue(const MachineInstr &MI, unsigned Op)
200 unsigned getThumbAddrModeRegRegOpValue(const MachineInstr &MI, unsigned Op)
202 unsigned getT2AddrModeImm12OpValue(const MachineInstr &MI, unsigned Op)
204 unsigned getT2AddrModeImm8OpValue(const MachineInstr &MI, unsigned Op)
206 unsigned getT2AddrModeImm8s4OpValue(const MachineInstr &MI, unsigned Op)
208 unsigned getT2AddrModeImm8OffsetOpValue(const MachineInstr &MI, unsigned Op)
210 unsigned getT2AddrModeImm12OffsetOpValue(const MachineInstr &MI,unsigned Op)
212 unsigned getT2AddrModeSORegOpValue(const MachineInstr &MI, unsigned Op)
214 unsigned getT2SORegOpValue(const MachineInstr &MI, unsigned Op)
216 unsigned getRotImmOpValue(const MachineInstr &MI, unsigned Op)
218 unsigned getImmMinusOneOpValue(const MachineInstr &MI, unsigned Op)
220 unsigned getT2AdrLabelOpValue(const MachineInstr &MI, unsigned Op)
222 unsigned getAddrMode6AddressOpValue(const MachineInstr &MI, unsigned Op)
224 unsigned getAddrMode6DupAddressOpValue(const MachineInstr &MI, unsigned Op)
226 unsigned getAddrMode6OffsetOpValue(const MachineInstr &MI, unsigned Op)
228 unsigned getBitfieldInvertedMaskOpValue(const MachineInstr &MI,
229 unsigned Op) const { return 0; }
230 unsigned getMsbOpValue(const MachineInstr &MI,
231 unsigned Op) const { return 0; }
232 uint32_t getLdStmModeOpValue(const MachineInstr &MI, unsigned OpIdx)
234 uint32_t getLdStSORegOpValue(const MachineInstr &MI, unsigned OpIdx)
237 unsigned getAddrModeImm12OpValue(const MachineInstr &MI, unsigned Op)
240 // {12} = (U)nsigned (add == '1', sub == '0')
242 const MachineOperand &MO = MI.getOperand(Op);
243 const MachineOperand &MO1 = MI.getOperand(Op + 1);
245 emitConstPoolAddress(MO.getIndex(), ARM::reloc_arm_cp_entry);
248 unsigned Reg = getARMRegisterNumbering(MO.getReg());
249 int32_t Imm12 = MO1.getImm();
251 Binary = Imm12 & 0xfff;
254 Binary |= (Reg << 13);
258 unsigned getHiLo16ImmOpValue(const MachineInstr &MI, unsigned Op) const {
262 uint32_t getAddrMode2OpValue(const MachineInstr &MI, unsigned OpIdx)
264 uint32_t getAddrMode2OffsetOpValue(const MachineInstr &MI, unsigned OpIdx)
266 uint32_t getAddrMode3OffsetOpValue(const MachineInstr &MI, unsigned OpIdx)
268 uint32_t getAddrMode3OpValue(const MachineInstr &MI, unsigned Op)
270 uint32_t getAddrModeThumbSPOpValue(const MachineInstr &MI, unsigned Op)
272 uint32_t getAddrModeSOpValue(const MachineInstr &MI, unsigned Op)
274 uint32_t getAddrModeISOpValue(const MachineInstr &MI, unsigned Op)
276 uint32_t getAddrModePCOpValue(const MachineInstr &MI, unsigned Op)
278 uint32_t getAddrMode5OpValue(const MachineInstr &MI, unsigned Op) const {
280 // {12} = (U)nsigned (add == '1', sub == '0')
282 const MachineOperand &MO = MI.getOperand(Op);
283 const MachineOperand &MO1 = MI.getOperand(Op + 1);
285 emitConstPoolAddress(MO.getIndex(), ARM::reloc_arm_cp_entry);
288 unsigned Reg = getARMRegisterNumbering(MO.getReg());
289 int32_t Imm12 = MO1.getImm();
291 // Special value for #-0
292 if (Imm12 == INT32_MIN)
295 // Immediate is always encoded as positive. The 'U' bit controls add vs
303 uint32_t Binary = Imm12 & 0xfff;
306 Binary |= (Reg << 13);
309 unsigned getNEONVcvtImm32OpValue(const MachineInstr &MI, unsigned Op)
312 unsigned getRegisterListOpValue(const MachineInstr &MI, unsigned Op)
315 unsigned getNarrowShiftRight16Imm(const MachineInstr &MI, unsigned Op)
317 unsigned getNarrowShiftRight32Imm(const MachineInstr &MI, unsigned Op)
319 unsigned getNarrowShiftRight64Imm(const MachineInstr &MI, unsigned Op)
322 /// getMovi32Value - Return binary encoding of operand for movw/movt. If the
323 /// machine operand requires relocation, record the relocation and return
325 unsigned getMovi32Value(const MachineInstr &MI,const MachineOperand &MO,
328 /// getShiftOp - Return the shift opcode (bit[6:5]) of the immediate value.
330 unsigned getShiftOp(unsigned Imm) const ;
332 /// Routines that handle operands which add machine relocations which are
333 /// fixed up by the relocation stage.
334 void emitGlobalAddress(const GlobalValue *GV, unsigned Reloc,
335 bool MayNeedFarStub, bool Indirect,
336 intptr_t ACPV = 0) const;
337 void emitExternalSymbolAddress(const char *ES, unsigned Reloc) const;
338 void emitConstPoolAddress(unsigned CPI, unsigned Reloc) const;
339 void emitJumpTableAddress(unsigned JTIndex, unsigned Reloc) const;
340 void emitMachineBasicBlock(MachineBasicBlock *BB, unsigned Reloc,
341 intptr_t JTBase = 0) const;
345 char ARMCodeEmitter::ID = 0;
347 /// createARMJITCodeEmitterPass - Return a pass that emits the collected ARM
348 /// code to the specified MCE object.
349 FunctionPass *llvm::createARMJITCodeEmitterPass(ARMBaseTargetMachine &TM,
350 JITCodeEmitter &JCE) {
351 return new ARMCodeEmitter(TM, JCE);
354 bool ARMCodeEmitter::runOnMachineFunction(MachineFunction &MF) {
355 assert((MF.getTarget().getRelocationModel() != Reloc::Default ||
356 MF.getTarget().getRelocationModel() != Reloc::Static) &&
357 "JIT relocation model must be set to static or default!");
358 JTI = ((ARMTargetMachine &)MF.getTarget()).getJITInfo();
359 II = ((const ARMTargetMachine &)MF.getTarget()).getInstrInfo();
360 TD = ((const ARMTargetMachine &)MF.getTarget()).getTargetData();
361 Subtarget = &TM.getSubtarget<ARMSubtarget>();
362 MCPEs = &MF.getConstantPool()->getConstants();
364 if (MF.getJumpTableInfo()) MJTEs = &MF.getJumpTableInfo()->getJumpTables();
365 IsPIC = TM.getRelocationModel() == Reloc::PIC_;
366 IsThumb = MF.getInfo<ARMFunctionInfo>()->isThumbFunction();
367 JTI->Initialize(MF, IsPIC);
368 MMI = &getAnalysis<MachineModuleInfo>();
369 MCE.setModuleInfo(MMI);
372 DEBUG(errs() << "JITTing function '"
373 << MF.getFunction()->getName() << "'\n");
374 MCE.startFunction(MF);
375 for (MachineFunction::iterator MBB = MF.begin(), E = MF.end();
377 MCE.StartMachineBasicBlock(MBB);
378 for (MachineBasicBlock::const_iterator I = MBB->begin(), E = MBB->end();
382 } while (MCE.finishFunction(MF));
387 /// getShiftOp - Return the shift opcode (bit[6:5]) of the immediate value.
389 unsigned ARMCodeEmitter::getShiftOp(unsigned Imm) const {
390 switch (ARM_AM::getAM2ShiftOpc(Imm)) {
391 default: llvm_unreachable("Unknown shift opc!");
392 case ARM_AM::asr: return 2;
393 case ARM_AM::lsl: return 0;
394 case ARM_AM::lsr: return 1;
396 case ARM_AM::rrx: return 3;
401 /// getMovi32Value - Return binary encoding of operand for movw/movt. If the
402 /// machine operand requires relocation, record the relocation and return zero.
403 unsigned ARMCodeEmitter::getMovi32Value(const MachineInstr &MI,
404 const MachineOperand &MO,
406 assert(((Reloc == ARM::reloc_arm_movt) || (Reloc == ARM::reloc_arm_movw))
407 && "Relocation to this function should be for movt or movw");
410 return static_cast<unsigned>(MO.getImm());
411 else if (MO.isGlobal())
412 emitGlobalAddress(MO.getGlobal(), Reloc, true, false);
413 else if (MO.isSymbol())
414 emitExternalSymbolAddress(MO.getSymbolName(), Reloc);
416 emitMachineBasicBlock(MO.getMBB(), Reloc);
421 llvm_unreachable("Unsupported operand type for movw/movt");
426 /// getMachineOpValue - Return binary encoding of operand. If the machine
427 /// operand requires relocation, record the relocation and return zero.
428 unsigned ARMCodeEmitter::getMachineOpValue(const MachineInstr &MI,
429 const MachineOperand &MO) const {
431 return getARMRegisterNumbering(MO.getReg());
433 return static_cast<unsigned>(MO.getImm());
434 else if (MO.isGlobal())
435 emitGlobalAddress(MO.getGlobal(), ARM::reloc_arm_branch, true, false);
436 else if (MO.isSymbol())
437 emitExternalSymbolAddress(MO.getSymbolName(), ARM::reloc_arm_branch);
438 else if (MO.isCPI()) {
439 const TargetInstrDesc &TID = MI.getDesc();
440 // For VFP load, the immediate offset is multiplied by 4.
441 unsigned Reloc = ((TID.TSFlags & ARMII::FormMask) == ARMII::VFPLdStFrm)
442 ? ARM::reloc_arm_vfp_cp_entry : ARM::reloc_arm_cp_entry;
443 emitConstPoolAddress(MO.getIndex(), Reloc);
444 } else if (MO.isJTI())
445 emitJumpTableAddress(MO.getIndex(), ARM::reloc_arm_relative);
447 emitMachineBasicBlock(MO.getMBB(), ARM::reloc_arm_branch);
449 llvm_unreachable("Unable to encode MachineOperand!");
453 /// emitGlobalAddress - Emit the specified address to the code stream.
455 void ARMCodeEmitter::emitGlobalAddress(const GlobalValue *GV, unsigned Reloc,
456 bool MayNeedFarStub, bool Indirect,
457 intptr_t ACPV) const {
458 MachineRelocation MR = Indirect
459 ? MachineRelocation::getIndirectSymbol(MCE.getCurrentPCOffset(), Reloc,
460 const_cast<GlobalValue *>(GV),
461 ACPV, MayNeedFarStub)
462 : MachineRelocation::getGV(MCE.getCurrentPCOffset(), Reloc,
463 const_cast<GlobalValue *>(GV), ACPV,
465 MCE.addRelocation(MR);
468 /// emitExternalSymbolAddress - Arrange for the address of an external symbol to
469 /// be emitted to the current location in the function, and allow it to be PC
471 void ARMCodeEmitter::
472 emitExternalSymbolAddress(const char *ES, unsigned Reloc) const {
473 MCE.addRelocation(MachineRelocation::getExtSym(MCE.getCurrentPCOffset(),
477 /// emitConstPoolAddress - Arrange for the address of an constant pool
478 /// to be emitted to the current location in the function, and allow it to be PC
480 void ARMCodeEmitter::emitConstPoolAddress(unsigned CPI, unsigned Reloc) const {
481 // Tell JIT emitter we'll resolve the address.
482 MCE.addRelocation(MachineRelocation::getConstPool(MCE.getCurrentPCOffset(),
483 Reloc, CPI, 0, true));
486 /// emitJumpTableAddress - Arrange for the address of a jump table to
487 /// be emitted to the current location in the function, and allow it to be PC
489 void ARMCodeEmitter::
490 emitJumpTableAddress(unsigned JTIndex, unsigned Reloc) const {
491 MCE.addRelocation(MachineRelocation::getJumpTable(MCE.getCurrentPCOffset(),
492 Reloc, JTIndex, 0, true));
495 /// emitMachineBasicBlock - Emit the specified address basic block.
496 void ARMCodeEmitter::emitMachineBasicBlock(MachineBasicBlock *BB,
498 intptr_t JTBase) const {
499 MCE.addRelocation(MachineRelocation::getBB(MCE.getCurrentPCOffset(),
503 void ARMCodeEmitter::emitWordLE(unsigned Binary) {
504 DEBUG(errs() << " 0x";
505 errs().write_hex(Binary) << "\n");
506 MCE.emitWordLE(Binary);
509 void ARMCodeEmitter::emitDWordLE(uint64_t Binary) {
510 DEBUG(errs() << " 0x";
511 errs().write_hex(Binary) << "\n");
512 MCE.emitDWordLE(Binary);
515 void ARMCodeEmitter::emitInstruction(const MachineInstr &MI) {
516 DEBUG(errs() << "JIT: " << (void*)MCE.getCurrentPCValue() << ":\t" << MI);
518 MCE.processDebugLoc(MI.getDebugLoc(), true);
520 ++NumEmitted; // Keep track of the # of mi's emitted
521 switch (MI.getDesc().TSFlags & ARMII::FormMask) {
523 llvm_unreachable("Unhandled instruction encoding format!");
527 if (MI.getOpcode() == ARM::LEApcrelJT) {
528 // Materialize jumptable address.
529 emitLEApcrelJTInstruction(MI);
532 llvm_unreachable("Unhandled instruction encoding!");
535 emitPseudoInstruction(MI);
538 case ARMII::DPSoRegFrm:
539 emitDataProcessingInstruction(MI);
543 emitLoadStoreInstruction(MI);
545 case ARMII::LdMiscFrm:
546 case ARMII::StMiscFrm:
547 emitMiscLoadStoreInstruction(MI);
549 case ARMII::LdStMulFrm:
550 emitLoadStoreMultipleInstruction(MI);
553 emitMulFrmInstruction(MI);
556 emitExtendInstruction(MI);
558 case ARMII::ArithMiscFrm:
559 emitMiscArithInstruction(MI);
562 emitSaturateInstruction(MI);
565 emitBranchInstruction(MI);
567 case ARMII::BrMiscFrm:
568 emitMiscBranchInstruction(MI);
571 case ARMII::VFPUnaryFrm:
572 case ARMII::VFPBinaryFrm:
573 emitVFPArithInstruction(MI);
575 case ARMII::VFPConv1Frm:
576 case ARMII::VFPConv2Frm:
577 case ARMII::VFPConv3Frm:
578 case ARMII::VFPConv4Frm:
579 case ARMII::VFPConv5Frm:
580 emitVFPConversionInstruction(MI);
582 case ARMII::VFPLdStFrm:
583 emitVFPLoadStoreInstruction(MI);
585 case ARMII::VFPLdStMulFrm:
586 emitVFPLoadStoreMultipleInstruction(MI);
589 // NEON instructions.
590 case ARMII::NGetLnFrm:
591 case ARMII::NSetLnFrm:
592 emitNEONLaneInstruction(MI);
595 emitNEONDupInstruction(MI);
597 case ARMII::N1RegModImmFrm:
598 emitNEON1RegModImmInstruction(MI);
600 case ARMII::N2RegFrm:
601 emitNEON2RegInstruction(MI);
603 case ARMII::N3RegFrm:
604 emitNEON3RegInstruction(MI);
607 MCE.processDebugLoc(MI.getDebugLoc(), false);
610 void ARMCodeEmitter::emitConstPoolInstruction(const MachineInstr &MI) {
611 unsigned CPI = MI.getOperand(0).getImm(); // CP instruction index.
612 unsigned CPIndex = MI.getOperand(1).getIndex(); // Actual cp entry index.
613 const MachineConstantPoolEntry &MCPE = (*MCPEs)[CPIndex];
615 // Remember the CONSTPOOL_ENTRY address for later relocation.
616 JTI->addConstantPoolEntryAddr(CPI, MCE.getCurrentPCValue());
618 // Emit constpool island entry. In most cases, the actual values will be
619 // resolved and relocated after code emission.
620 if (MCPE.isMachineConstantPoolEntry()) {
621 ARMConstantPoolValue *ACPV =
622 static_cast<ARMConstantPoolValue*>(MCPE.Val.MachineCPVal);
624 DEBUG(errs() << " ** ARM constant pool #" << CPI << " @ "
625 << (void*)MCE.getCurrentPCValue() << " " << *ACPV << '\n');
627 assert(ACPV->isGlobalValue() && "unsupported constant pool value");
628 const GlobalValue *GV = ACPV->getGV();
630 Reloc::Model RelocM = TM.getRelocationModel();
631 emitGlobalAddress(GV, ARM::reloc_arm_machine_cp_entry,
633 Subtarget->GVIsIndirectSymbol(GV, RelocM),
636 emitExternalSymbolAddress(ACPV->getSymbol(), ARM::reloc_arm_absolute);
640 const Constant *CV = MCPE.Val.ConstVal;
643 errs() << " ** Constant pool #" << CPI << " @ "
644 << (void*)MCE.getCurrentPCValue() << " ";
645 if (const Function *F = dyn_cast<Function>(CV))
646 errs() << F->getName();
652 if (const GlobalValue *GV = dyn_cast<GlobalValue>(CV)) {
653 emitGlobalAddress(GV, ARM::reloc_arm_absolute, isa<Function>(GV), false);
655 } else if (const ConstantInt *CI = dyn_cast<ConstantInt>(CV)) {
656 uint32_t Val = uint32_t(*CI->getValue().getRawData());
658 } else if (const ConstantFP *CFP = dyn_cast<ConstantFP>(CV)) {
659 if (CFP->getType()->isFloatTy())
660 emitWordLE(CFP->getValueAPF().bitcastToAPInt().getZExtValue());
661 else if (CFP->getType()->isDoubleTy())
662 emitDWordLE(CFP->getValueAPF().bitcastToAPInt().getZExtValue());
664 llvm_unreachable("Unable to handle this constantpool entry!");
667 llvm_unreachable("Unable to handle this constantpool entry!");
672 void ARMCodeEmitter::emitMOVi32immInstruction(const MachineInstr &MI) {
673 const MachineOperand &MO0 = MI.getOperand(0);
674 const MachineOperand &MO1 = MI.getOperand(1);
676 // Emit the 'movw' instruction.
677 unsigned Binary = 0x30 << 20; // mov: Insts{27-20} = 0b00110000
679 unsigned Lo16 = getMovi32Value(MI, MO1, ARM::reloc_arm_movw) & 0xFFFF;
681 // Set the conditional execution predicate.
682 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
685 Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRdShift;
687 // Encode imm16 as imm4:imm12
688 Binary |= Lo16 & 0xFFF; // Insts{11-0} = imm12
689 Binary |= ((Lo16 >> 12) & 0xF) << 16; // Insts{19-16} = imm4
692 unsigned Hi16 = getMovi32Value(MI, MO1, ARM::reloc_arm_movt) >> 16;
693 // Emit the 'movt' instruction.
694 Binary = 0x34 << 20; // movt: Insts{27-20} = 0b00110100
696 // Set the conditional execution predicate.
697 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
700 Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRdShift;
702 // Encode imm16 as imm4:imm1, same as movw above.
703 Binary |= Hi16 & 0xFFF;
704 Binary |= ((Hi16 >> 12) & 0xF) << 16;
708 void ARMCodeEmitter::emitMOVi2piecesInstruction(const MachineInstr &MI) {
709 const MachineOperand &MO0 = MI.getOperand(0);
710 const MachineOperand &MO1 = MI.getOperand(1);
711 assert(MO1.isImm() && ARM_AM::isSOImmTwoPartVal(MO1.getImm()) &&
712 "Not a valid so_imm value!");
713 unsigned V1 = ARM_AM::getSOImmTwoPartFirst(MO1.getImm());
714 unsigned V2 = ARM_AM::getSOImmTwoPartSecond(MO1.getImm());
716 // Emit the 'mov' instruction.
717 unsigned Binary = 0xd << 21; // mov: Insts{24-21} = 0b1101
719 // Set the conditional execution predicate.
720 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
723 Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRdShift;
726 // Set bit I(25) to identify this is the immediate form of <shifter_op>
727 Binary |= 1 << ARMII::I_BitShift;
728 Binary |= getMachineSoImmOpValue(V1);
731 // Now the 'orr' instruction.
732 Binary = 0xc << 21; // orr: Insts{24-21} = 0b1100
734 // Set the conditional execution predicate.
735 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
738 Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRdShift;
741 Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRnShift;
744 // Set bit I(25) to identify this is the immediate form of <shifter_op>
745 Binary |= 1 << ARMII::I_BitShift;
746 Binary |= getMachineSoImmOpValue(V2);
750 void ARMCodeEmitter::emitLEApcrelJTInstruction(const MachineInstr &MI) {
751 // It's basically add r, pc, (LJTI - $+8)
753 const TargetInstrDesc &TID = MI.getDesc();
755 // Emit the 'add' instruction.
756 unsigned Binary = 0x4 << 21; // add: Insts{24-21} = 0b0100
758 // Set the conditional execution predicate
759 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
761 // Encode S bit if MI modifies CPSR.
762 Binary |= getAddrModeSBit(MI, TID);
765 Binary |= getMachineOpValue(MI, 0) << ARMII::RegRdShift;
767 // Encode Rn which is PC.
768 Binary |= getARMRegisterNumbering(ARM::PC) << ARMII::RegRnShift;
770 // Encode the displacement.
771 Binary |= 1 << ARMII::I_BitShift;
772 emitJumpTableAddress(MI.getOperand(1).getIndex(), ARM::reloc_arm_jt_base);
777 void ARMCodeEmitter::emitPseudoMoveInstruction(const MachineInstr &MI) {
778 unsigned Opcode = MI.getDesc().Opcode;
780 // Part of binary is determined by TableGn.
781 unsigned Binary = getBinaryCodeForInstr(MI);
783 // Set the conditional execution predicate
784 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
786 // Encode S bit if MI modifies CPSR.
787 if (Opcode == ARM::MOVsrl_flag || Opcode == ARM::MOVsra_flag)
788 Binary |= 1 << ARMII::S_BitShift;
790 // Encode register def if there is one.
791 Binary |= getMachineOpValue(MI, 0) << ARMII::RegRdShift;
793 // Encode the shift operation.
800 case ARM::MOVsrl_flag:
802 Binary |= (0x2 << 4) | (1 << 7);
804 case ARM::MOVsra_flag:
806 Binary |= (0x4 << 4) | (1 << 7);
810 // Encode register Rm.
811 Binary |= getMachineOpValue(MI, 1);
816 void ARMCodeEmitter::addPCLabel(unsigned LabelID) {
817 DEBUG(errs() << " ** LPC" << LabelID << " @ "
818 << (void*)MCE.getCurrentPCValue() << '\n');
819 JTI->addPCLabelAddr(LabelID, MCE.getCurrentPCValue());
822 void ARMCodeEmitter::emitPseudoInstruction(const MachineInstr &MI) {
823 unsigned Opcode = MI.getDesc().Opcode;
826 llvm_unreachable("ARMCodeEmitter::emitPseudoInstruction");
828 case ARM::BMOVPCRX_CALL:
830 case ARM::BMOVPCRXr9_CALL: {
831 // First emit mov lr, pc
832 unsigned Binary = 0x01a0e00f;
833 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
836 // and then emit the branch.
837 emitMiscBranchInstruction(MI);
840 case TargetOpcode::INLINEASM: {
841 // We allow inline assembler nodes with empty bodies - they can
842 // implicitly define registers, which is ok for JIT.
843 if (MI.getOperand(0).getSymbolName()[0]) {
844 report_fatal_error("JIT does not support inline asm!");
848 case TargetOpcode::PROLOG_LABEL:
849 case TargetOpcode::EH_LABEL:
850 MCE.emitLabel(MI.getOperand(0).getMCSymbol());
852 case TargetOpcode::IMPLICIT_DEF:
853 case TargetOpcode::KILL:
856 case ARM::CONSTPOOL_ENTRY:
857 emitConstPoolInstruction(MI);
860 // Remember of the address of the PC label for relocation later.
861 addPCLabel(MI.getOperand(2).getImm());
862 // PICADD is just an add instruction that implicitly read pc.
863 emitDataProcessingInstruction(MI, 0, ARM::PC);
870 // Remember of the address of the PC label for relocation later.
871 addPCLabel(MI.getOperand(2).getImm());
872 // These are just load / store instructions that implicitly read pc.
873 emitLoadStoreInstruction(MI, 0, ARM::PC);
880 // Remember of the address of the PC label for relocation later.
881 addPCLabel(MI.getOperand(2).getImm());
882 // These are just load / store instructions that implicitly read pc.
883 emitMiscLoadStoreInstruction(MI, ARM::PC);
888 // Two instructions to materialize a constant.
889 if (Subtarget->hasV6T2Ops())
890 emitMOVi32immInstruction(MI);
892 emitMOVi2piecesInstruction(MI);
895 case ARM::LEApcrelJT:
896 // Materialize jumptable address.
897 emitLEApcrelJTInstruction(MI);
900 case ARM::MOVsrl_flag:
901 case ARM::MOVsra_flag:
902 emitPseudoMoveInstruction(MI);
907 unsigned ARMCodeEmitter::getMachineSoRegOpValue(const MachineInstr &MI,
908 const TargetInstrDesc &TID,
909 const MachineOperand &MO,
911 unsigned Binary = getMachineOpValue(MI, MO);
913 const MachineOperand &MO1 = MI.getOperand(OpIdx + 1);
914 const MachineOperand &MO2 = MI.getOperand(OpIdx + 2);
915 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO2.getImm());
917 // Encode the shift opcode.
919 unsigned Rs = MO1.getReg();
921 // Set shift operand (bit[7:4]).
926 // RRX - 0110 and bit[11:8] clear.
928 default: llvm_unreachable("Unknown shift opc!");
929 case ARM_AM::lsl: SBits = 0x1; break;
930 case ARM_AM::lsr: SBits = 0x3; break;
931 case ARM_AM::asr: SBits = 0x5; break;
932 case ARM_AM::ror: SBits = 0x7; break;
933 case ARM_AM::rrx: SBits = 0x6; break;
936 // Set shift operand (bit[6:4]).
942 default: llvm_unreachable("Unknown shift opc!");
943 case ARM_AM::lsl: SBits = 0x0; break;
944 case ARM_AM::lsr: SBits = 0x2; break;
945 case ARM_AM::asr: SBits = 0x4; break;
946 case ARM_AM::ror: SBits = 0x6; break;
949 Binary |= SBits << 4;
950 if (SOpc == ARM_AM::rrx)
953 // Encode the shift operation Rs or shift_imm (except rrx).
955 // Encode Rs bit[11:8].
956 assert(ARM_AM::getSORegOffset(MO2.getImm()) == 0);
957 return Binary | (getARMRegisterNumbering(Rs) << ARMII::RegRsShift);
960 // Encode shift_imm bit[11:7].
961 return Binary | ARM_AM::getSORegOffset(MO2.getImm()) << 7;
964 unsigned ARMCodeEmitter::getMachineSoImmOpValue(unsigned SoImm) {
965 int SoImmVal = ARM_AM::getSOImmVal(SoImm);
966 assert(SoImmVal != -1 && "Not a valid so_imm value!");
968 // Encode rotate_imm.
969 unsigned Binary = (ARM_AM::getSOImmValRot((unsigned)SoImmVal) >> 1)
970 << ARMII::SoRotImmShift;
973 Binary |= ARM_AM::getSOImmValImm((unsigned)SoImmVal);
977 unsigned ARMCodeEmitter::getAddrModeSBit(const MachineInstr &MI,
978 const TargetInstrDesc &TID) const {
979 for (unsigned i = MI.getNumOperands(), e = TID.getNumOperands(); i != e; --i){
980 const MachineOperand &MO = MI.getOperand(i-1);
981 if (MO.isReg() && MO.isDef() && MO.getReg() == ARM::CPSR)
982 return 1 << ARMII::S_BitShift;
987 void ARMCodeEmitter::emitDataProcessingInstruction(const MachineInstr &MI,
989 unsigned ImplicitRn) {
990 const TargetInstrDesc &TID = MI.getDesc();
992 // Part of binary is determined by TableGn.
993 unsigned Binary = getBinaryCodeForInstr(MI);
995 // Set the conditional execution predicate
996 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
998 // Encode S bit if MI modifies CPSR.
999 Binary |= getAddrModeSBit(MI, TID);
1001 // Encode register def if there is one.
1002 unsigned NumDefs = TID.getNumDefs();
1005 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
1006 else if (ImplicitRd)
1007 // Special handling for implicit use (e.g. PC).
1008 Binary |= (getARMRegisterNumbering(ImplicitRd) << ARMII::RegRdShift);
1010 if (TID.Opcode == ARM::MOVi16) {
1011 // Get immediate from MI.
1012 unsigned Lo16 = getMovi32Value(MI, MI.getOperand(OpIdx),
1013 ARM::reloc_arm_movw);
1014 // Encode imm which is the same as in emitMOVi32immInstruction().
1015 Binary |= Lo16 & 0xFFF;
1016 Binary |= ((Lo16 >> 12) & 0xF) << 16;
1019 } else if(TID.Opcode == ARM::MOVTi16) {
1020 unsigned Hi16 = (getMovi32Value(MI, MI.getOperand(OpIdx),
1021 ARM::reloc_arm_movt) >> 16);
1022 Binary |= Hi16 & 0xFFF;
1023 Binary |= ((Hi16 >> 12) & 0xF) << 16;
1026 } else if ((TID.Opcode == ARM::BFC) || (TID.Opcode == ARM::BFI)) {
1027 uint32_t v = ~MI.getOperand(2).getImm();
1028 int32_t lsb = CountTrailingZeros_32(v);
1029 int32_t msb = (32 - CountLeadingZeros_32(v)) - 1;
1030 // Instr{20-16} = msb, Instr{11-7} = lsb
1031 Binary |= (msb & 0x1F) << 16;
1032 Binary |= (lsb & 0x1F) << 7;
1035 } else if ((TID.Opcode == ARM::UBFX) || (TID.Opcode == ARM::SBFX)) {
1036 // Encode Rn in Instr{0-3}
1037 Binary |= getMachineOpValue(MI, OpIdx++);
1039 uint32_t lsb = MI.getOperand(OpIdx++).getImm();
1040 uint32_t widthm1 = MI.getOperand(OpIdx++).getImm() - 1;
1042 // Instr{20-16} = widthm1, Instr{11-7} = lsb
1043 Binary |= (widthm1 & 0x1F) << 16;
1044 Binary |= (lsb & 0x1F) << 7;
1049 // If this is a two-address operand, skip it. e.g. MOVCCr operand 1.
1050 if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
1053 // Encode first non-shifter register operand if there is one.
1054 bool isUnary = TID.TSFlags & ARMII::UnaryDP;
1057 // Special handling for implicit use (e.g. PC).
1058 Binary |= (getARMRegisterNumbering(ImplicitRn) << ARMII::RegRnShift);
1060 Binary |= getMachineOpValue(MI, OpIdx) << ARMII::RegRnShift;
1065 // Encode shifter operand.
1066 const MachineOperand &MO = MI.getOperand(OpIdx);
1067 if ((TID.TSFlags & ARMII::FormMask) == ARMII::DPSoRegFrm) {
1069 emitWordLE(Binary | getMachineSoRegOpValue(MI, TID, MO, OpIdx));
1074 // Encode register Rm.
1075 emitWordLE(Binary | getARMRegisterNumbering(MO.getReg()));
1080 Binary |= getMachineSoImmOpValue((unsigned)MO.getImm());
1085 void ARMCodeEmitter::emitLoadStoreInstruction(const MachineInstr &MI,
1086 unsigned ImplicitRd,
1087 unsigned ImplicitRn) {
1088 const TargetInstrDesc &TID = MI.getDesc();
1089 unsigned Form = TID.TSFlags & ARMII::FormMask;
1090 bool IsPrePost = (TID.TSFlags & ARMII::IndexModeMask) != 0;
1092 // Part of binary is determined by TableGn.
1093 unsigned Binary = getBinaryCodeForInstr(MI);
1095 // If this is an LDRi12, STRi12 or LDRcp, nothing more needs be done.
1096 if (MI.getOpcode() == ARM::LDRi12 || MI.getOpcode() == ARM::LDRcp ||
1097 MI.getOpcode() == ARM::STRi12) {
1102 // Set the conditional execution predicate
1103 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1107 // Operand 0 of a pre- and post-indexed store is the address base
1108 // writeback. Skip it.
1109 bool Skipped = false;
1110 if (IsPrePost && Form == ARMII::StFrm) {
1115 // Set first operand
1117 // Special handling for implicit use (e.g. PC).
1118 Binary |= (getARMRegisterNumbering(ImplicitRd) << ARMII::RegRdShift);
1120 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
1122 // Set second operand
1124 // Special handling for implicit use (e.g. PC).
1125 Binary |= (getARMRegisterNumbering(ImplicitRn) << ARMII::RegRnShift);
1127 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift;
1129 // If this is a two-address operand, skip it. e.g. LDR_PRE.
1130 if (!Skipped && TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
1133 const MachineOperand &MO2 = MI.getOperand(OpIdx);
1134 unsigned AM2Opc = (ImplicitRn == ARM::PC)
1135 ? 0 : MI.getOperand(OpIdx+1).getImm();
1137 // Set bit U(23) according to sign of immed value (positive or negative).
1138 Binary |= ((ARM_AM::getAM2Op(AM2Opc) == ARM_AM::add ? 1 : 0) <<
1140 if (!MO2.getReg()) { // is immediate
1141 if (ARM_AM::getAM2Offset(AM2Opc))
1142 // Set the value of offset_12 field
1143 Binary |= ARM_AM::getAM2Offset(AM2Opc);
1148 // Set bit I(25), because this is not in immediate encoding.
1149 Binary |= 1 << ARMII::I_BitShift;
1150 assert(TargetRegisterInfo::isPhysicalRegister(MO2.getReg()));
1151 // Set bit[3:0] to the corresponding Rm register
1152 Binary |= getARMRegisterNumbering(MO2.getReg());
1154 // If this instr is in scaled register offset/index instruction, set
1155 // shift_immed(bit[11:7]) and shift(bit[6:5]) fields.
1156 if (unsigned ShImm = ARM_AM::getAM2Offset(AM2Opc)) {
1157 Binary |= getShiftOp(AM2Opc) << ARMII::ShiftImmShift; // shift
1158 Binary |= ShImm << ARMII::ShiftShift; // shift_immed
1164 void ARMCodeEmitter::emitMiscLoadStoreInstruction(const MachineInstr &MI,
1165 unsigned ImplicitRn) {
1166 const TargetInstrDesc &TID = MI.getDesc();
1167 unsigned Form = TID.TSFlags & ARMII::FormMask;
1168 bool IsPrePost = (TID.TSFlags & ARMII::IndexModeMask) != 0;
1170 // Part of binary is determined by TableGn.
1171 unsigned Binary = getBinaryCodeForInstr(MI);
1173 // Set the conditional execution predicate
1174 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1178 // Operand 0 of a pre- and post-indexed store is the address base
1179 // writeback. Skip it.
1180 bool Skipped = false;
1181 if (IsPrePost && Form == ARMII::StMiscFrm) {
1186 // Set first operand
1187 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
1189 // Skip LDRD and STRD's second operand.
1190 if (TID.Opcode == ARM::LDRD || TID.Opcode == ARM::STRD)
1193 // Set second operand
1195 // Special handling for implicit use (e.g. PC).
1196 Binary |= (getARMRegisterNumbering(ImplicitRn) << ARMII::RegRnShift);
1198 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift;
1200 // If this is a two-address operand, skip it. e.g. LDRH_POST.
1201 if (!Skipped && TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
1204 const MachineOperand &MO2 = MI.getOperand(OpIdx);
1205 unsigned AM3Opc = (ImplicitRn == ARM::PC)
1206 ? 0 : MI.getOperand(OpIdx+1).getImm();
1208 // Set bit U(23) according to sign of immed value (positive or negative)
1209 Binary |= ((ARM_AM::getAM3Op(AM3Opc) == ARM_AM::add ? 1 : 0) <<
1212 // If this instr is in register offset/index encoding, set bit[3:0]
1213 // to the corresponding Rm register.
1215 Binary |= getARMRegisterNumbering(MO2.getReg());
1220 // This instr is in immediate offset/index encoding, set bit 22 to 1.
1221 Binary |= 1 << ARMII::AM3_I_BitShift;
1222 if (unsigned ImmOffs = ARM_AM::getAM3Offset(AM3Opc)) {
1224 Binary |= (ImmOffs >> 4) << ARMII::ImmHiShift; // immedH
1225 Binary |= (ImmOffs & 0xF); // immedL
1231 static unsigned getAddrModeUPBits(unsigned Mode) {
1232 unsigned Binary = 0;
1234 // Set addressing mode by modifying bits U(23) and P(24)
1235 // IA - Increment after - bit U = 1 and bit P = 0
1236 // IB - Increment before - bit U = 1 and bit P = 1
1237 // DA - Decrement after - bit U = 0 and bit P = 0
1238 // DB - Decrement before - bit U = 0 and bit P = 1
1240 default: llvm_unreachable("Unknown addressing sub-mode!");
1241 case ARM_AM::da: break;
1242 case ARM_AM::db: Binary |= 0x1 << ARMII::P_BitShift; break;
1243 case ARM_AM::ia: Binary |= 0x1 << ARMII::U_BitShift; break;
1244 case ARM_AM::ib: Binary |= 0x3 << ARMII::U_BitShift; break;
1250 void ARMCodeEmitter::emitLoadStoreMultipleInstruction(const MachineInstr &MI) {
1251 const TargetInstrDesc &TID = MI.getDesc();
1252 bool IsUpdating = (TID.TSFlags & ARMII::IndexModeMask) != 0;
1254 // Part of binary is determined by TableGn.
1255 unsigned Binary = getBinaryCodeForInstr(MI);
1257 // Set the conditional execution predicate
1258 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1260 // Skip operand 0 of an instruction with base register update.
1265 // Set base address operand
1266 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift;
1268 // Set addressing mode by modifying bits U(23) and P(24)
1269 ARM_AM::AMSubMode Mode = ARM_AM::getLoadStoreMultipleSubMode(MI.getOpcode());
1270 Binary |= getAddrModeUPBits(ARM_AM::getAM4SubMode(Mode));
1274 Binary |= 0x1 << ARMII::W_BitShift;
1277 for (unsigned i = OpIdx+2, e = MI.getNumOperands(); i != e; ++i) {
1278 const MachineOperand &MO = MI.getOperand(i);
1279 if (!MO.isReg() || MO.isImplicit())
1281 unsigned RegNum = getARMRegisterNumbering(MO.getReg());
1282 assert(TargetRegisterInfo::isPhysicalRegister(MO.getReg()) &&
1284 Binary |= 0x1 << RegNum;
1290 void ARMCodeEmitter::emitMulFrmInstruction(const MachineInstr &MI) {
1291 const TargetInstrDesc &TID = MI.getDesc();
1293 // Part of binary is determined by TableGn.
1294 unsigned Binary = getBinaryCodeForInstr(MI);
1296 // Set the conditional execution predicate
1297 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1299 // Encode S bit if MI modifies CPSR.
1300 Binary |= getAddrModeSBit(MI, TID);
1302 // 32x32->64bit operations have two destination registers. The number
1303 // of register definitions will tell us if that's what we're dealing with.
1305 if (TID.getNumDefs() == 2)
1306 Binary |= getMachineOpValue (MI, OpIdx++) << ARMII::RegRdLoShift;
1309 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdHiShift;
1312 Binary |= getMachineOpValue(MI, OpIdx++);
1315 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRsShift;
1317 // Many multiple instructions (e.g. MLA) have three src operands. Encode
1318 // it as Rn (for multiply, that's in the same offset as RdLo.
1319 if (TID.getNumOperands() > OpIdx &&
1320 !TID.OpInfo[OpIdx].isPredicate() &&
1321 !TID.OpInfo[OpIdx].isOptionalDef())
1322 Binary |= getMachineOpValue(MI, OpIdx) << ARMII::RegRdLoShift;
1327 void ARMCodeEmitter::emitExtendInstruction(const MachineInstr &MI) {
1328 const TargetInstrDesc &TID = MI.getDesc();
1330 // Part of binary is determined by TableGn.
1331 unsigned Binary = getBinaryCodeForInstr(MI);
1333 // Set the conditional execution predicate
1334 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1339 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
1341 const MachineOperand &MO1 = MI.getOperand(OpIdx++);
1342 const MachineOperand &MO2 = MI.getOperand(OpIdx);
1344 // Two register operand form.
1346 Binary |= getMachineOpValue(MI, MO1) << ARMII::RegRnShift;
1349 Binary |= getMachineOpValue(MI, MO2);
1352 Binary |= getMachineOpValue(MI, MO1);
1355 // Encode rot imm (0, 8, 16, or 24) if it has a rotate immediate operand.
1356 if (MI.getOperand(OpIdx).isImm() &&
1357 !TID.OpInfo[OpIdx].isPredicate() &&
1358 !TID.OpInfo[OpIdx].isOptionalDef())
1359 Binary |= (getMachineOpValue(MI, OpIdx) / 8) << ARMII::ExtRotImmShift;
1364 void ARMCodeEmitter::emitMiscArithInstruction(const MachineInstr &MI) {
1365 const TargetInstrDesc &TID = MI.getDesc();
1367 // Part of binary is determined by TableGn.
1368 unsigned Binary = getBinaryCodeForInstr(MI);
1370 // Set the conditional execution predicate
1371 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1376 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
1378 const MachineOperand &MO = MI.getOperand(OpIdx++);
1379 if (OpIdx == TID.getNumOperands() ||
1380 TID.OpInfo[OpIdx].isPredicate() ||
1381 TID.OpInfo[OpIdx].isOptionalDef()) {
1382 // Encode Rm and it's done.
1383 Binary |= getMachineOpValue(MI, MO);
1389 Binary |= getMachineOpValue(MI, MO) << ARMII::RegRnShift;
1392 Binary |= getMachineOpValue(MI, OpIdx++);
1394 // Encode shift_imm.
1395 unsigned ShiftAmt = MI.getOperand(OpIdx).getImm();
1396 if (TID.Opcode == ARM::PKHTB) {
1397 assert(ShiftAmt != 0 && "PKHTB shift_imm is 0!");
1401 assert(ShiftAmt < 32 && "shift_imm range is 0 to 31!");
1402 Binary |= ShiftAmt << ARMII::ShiftShift;
1407 void ARMCodeEmitter::emitSaturateInstruction(const MachineInstr &MI) {
1408 const TargetInstrDesc &TID = MI.getDesc();
1410 // Part of binary is determined by TableGen.
1411 unsigned Binary = getBinaryCodeForInstr(MI);
1413 // Set the conditional execution predicate
1414 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1417 Binary |= getMachineOpValue(MI, 0) << ARMII::RegRdShift;
1419 // Encode saturate bit position.
1420 unsigned Pos = MI.getOperand(1).getImm();
1421 if (TID.Opcode == ARM::SSAT || TID.Opcode == ARM::SSAT16)
1423 assert((Pos < 16 || (Pos < 32 &&
1424 TID.Opcode != ARM::SSAT16 &&
1425 TID.Opcode != ARM::USAT16)) &&
1426 "saturate bit position out of range");
1427 Binary |= Pos << 16;
1430 Binary |= getMachineOpValue(MI, 2);
1432 // Encode shift_imm.
1433 if (TID.getNumOperands() == 4) {
1434 unsigned ShiftOp = MI.getOperand(3).getImm();
1435 ARM_AM::ShiftOpc Opc = ARM_AM::getSORegShOp(ShiftOp);
1436 if (Opc == ARM_AM::asr)
1438 unsigned ShiftAmt = MI.getOperand(3).getImm();
1439 if (ShiftAmt == 32 && Opc == ARM_AM::asr)
1441 assert(ShiftAmt < 32 && "shift_imm range is 0 to 31!");
1442 Binary |= ShiftAmt << ARMII::ShiftShift;
1448 void ARMCodeEmitter::emitBranchInstruction(const MachineInstr &MI) {
1449 const TargetInstrDesc &TID = MI.getDesc();
1451 if (TID.Opcode == ARM::TPsoft) {
1452 llvm_unreachable("ARM::TPsoft FIXME"); // FIXME
1455 // Part of binary is determined by TableGn.
1456 unsigned Binary = getBinaryCodeForInstr(MI);
1458 // Set the conditional execution predicate
1459 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1461 // Set signed_immed_24 field
1462 Binary |= getMachineOpValue(MI, 0);
1467 void ARMCodeEmitter::emitInlineJumpTable(unsigned JTIndex) {
1468 // Remember the base address of the inline jump table.
1469 uintptr_t JTBase = MCE.getCurrentPCValue();
1470 JTI->addJumpTableBaseAddr(JTIndex, JTBase);
1471 DEBUG(errs() << " ** Jump Table #" << JTIndex << " @ " << (void*)JTBase
1474 // Now emit the jump table entries.
1475 const std::vector<MachineBasicBlock*> &MBBs = (*MJTEs)[JTIndex].MBBs;
1476 for (unsigned i = 0, e = MBBs.size(); i != e; ++i) {
1478 // DestBB address - JT base.
1479 emitMachineBasicBlock(MBBs[i], ARM::reloc_arm_pic_jt, JTBase);
1481 // Absolute DestBB address.
1482 emitMachineBasicBlock(MBBs[i], ARM::reloc_arm_absolute);
1487 void ARMCodeEmitter::emitMiscBranchInstruction(const MachineInstr &MI) {
1488 const TargetInstrDesc &TID = MI.getDesc();
1490 // Handle jump tables.
1491 if (TID.Opcode == ARM::BR_JTr || TID.Opcode == ARM::BR_JTadd) {
1492 // First emit a ldr pc, [] instruction.
1493 emitDataProcessingInstruction(MI, ARM::PC);
1495 // Then emit the inline jump table.
1497 (TID.Opcode == ARM::BR_JTr)
1498 ? MI.getOperand(1).getIndex() : MI.getOperand(2).getIndex();
1499 emitInlineJumpTable(JTIndex);
1501 } else if (TID.Opcode == ARM::BR_JTm) {
1502 // First emit a ldr pc, [] instruction.
1503 emitLoadStoreInstruction(MI, ARM::PC);
1505 // Then emit the inline jump table.
1506 emitInlineJumpTable(MI.getOperand(3).getIndex());
1510 // Part of binary is determined by TableGn.
1511 unsigned Binary = getBinaryCodeForInstr(MI);
1513 // Set the conditional execution predicate
1514 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1516 if (TID.Opcode == ARM::BX_RET || TID.Opcode == ARM::MOVPCLR)
1517 // The return register is LR.
1518 Binary |= getARMRegisterNumbering(ARM::LR);
1520 // otherwise, set the return register
1521 Binary |= getMachineOpValue(MI, 0);
1526 static unsigned encodeVFPRd(const MachineInstr &MI, unsigned OpIdx) {
1527 unsigned RegD = MI.getOperand(OpIdx).getReg();
1528 unsigned Binary = 0;
1529 bool isSPVFP = ARM::SPRRegisterClass->contains(RegD);
1530 RegD = getARMRegisterNumbering(RegD);
1532 Binary |= RegD << ARMII::RegRdShift;
1534 Binary |= ((RegD & 0x1E) >> 1) << ARMII::RegRdShift;
1535 Binary |= (RegD & 0x01) << ARMII::D_BitShift;
1540 static unsigned encodeVFPRn(const MachineInstr &MI, unsigned OpIdx) {
1541 unsigned RegN = MI.getOperand(OpIdx).getReg();
1542 unsigned Binary = 0;
1543 bool isSPVFP = ARM::SPRRegisterClass->contains(RegN);
1544 RegN = getARMRegisterNumbering(RegN);
1546 Binary |= RegN << ARMII::RegRnShift;
1548 Binary |= ((RegN & 0x1E) >> 1) << ARMII::RegRnShift;
1549 Binary |= (RegN & 0x01) << ARMII::N_BitShift;
1554 static unsigned encodeVFPRm(const MachineInstr &MI, unsigned OpIdx) {
1555 unsigned RegM = MI.getOperand(OpIdx).getReg();
1556 unsigned Binary = 0;
1557 bool isSPVFP = ARM::SPRRegisterClass->contains(RegM);
1558 RegM = getARMRegisterNumbering(RegM);
1562 Binary |= ((RegM & 0x1E) >> 1);
1563 Binary |= (RegM & 0x01) << ARMII::M_BitShift;
1568 void ARMCodeEmitter::emitVFPArithInstruction(const MachineInstr &MI) {
1569 const TargetInstrDesc &TID = MI.getDesc();
1571 // Part of binary is determined by TableGn.
1572 unsigned Binary = getBinaryCodeForInstr(MI);
1574 // Set the conditional execution predicate
1575 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1578 assert((Binary & ARMII::D_BitShift) == 0 &&
1579 (Binary & ARMII::N_BitShift) == 0 &&
1580 (Binary & ARMII::M_BitShift) == 0 && "VFP encoding bug!");
1583 Binary |= encodeVFPRd(MI, OpIdx++);
1585 // If this is a two-address operand, skip it, e.g. FMACD.
1586 if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
1590 if ((TID.TSFlags & ARMII::FormMask) == ARMII::VFPBinaryFrm)
1591 Binary |= encodeVFPRn(MI, OpIdx++);
1593 if (OpIdx == TID.getNumOperands() ||
1594 TID.OpInfo[OpIdx].isPredicate() ||
1595 TID.OpInfo[OpIdx].isOptionalDef()) {
1596 // FCMPEZD etc. has only one operand.
1602 Binary |= encodeVFPRm(MI, OpIdx);
1607 void ARMCodeEmitter::emitVFPConversionInstruction(const MachineInstr &MI) {
1608 const TargetInstrDesc &TID = MI.getDesc();
1609 unsigned Form = TID.TSFlags & ARMII::FormMask;
1611 // Part of binary is determined by TableGn.
1612 unsigned Binary = getBinaryCodeForInstr(MI);
1614 // Set the conditional execution predicate
1615 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1619 case ARMII::VFPConv1Frm:
1620 case ARMII::VFPConv2Frm:
1621 case ARMII::VFPConv3Frm:
1623 Binary |= encodeVFPRd(MI, 0);
1625 case ARMII::VFPConv4Frm:
1627 Binary |= encodeVFPRn(MI, 0);
1629 case ARMII::VFPConv5Frm:
1631 Binary |= encodeVFPRm(MI, 0);
1637 case ARMII::VFPConv1Frm:
1639 Binary |= encodeVFPRm(MI, 1);
1641 case ARMII::VFPConv2Frm:
1642 case ARMII::VFPConv3Frm:
1644 Binary |= encodeVFPRn(MI, 1);
1646 case ARMII::VFPConv4Frm:
1647 case ARMII::VFPConv5Frm:
1649 Binary |= encodeVFPRd(MI, 1);
1653 if (Form == ARMII::VFPConv5Frm)
1655 Binary |= encodeVFPRn(MI, 2);
1656 else if (Form == ARMII::VFPConv3Frm)
1658 Binary |= encodeVFPRm(MI, 2);
1663 void ARMCodeEmitter::emitVFPLoadStoreInstruction(const MachineInstr &MI) {
1664 // Part of binary is determined by TableGn.
1665 unsigned Binary = getBinaryCodeForInstr(MI);
1667 // Set the conditional execution predicate
1668 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1673 Binary |= encodeVFPRd(MI, OpIdx++);
1675 // Encode address base.
1676 const MachineOperand &Base = MI.getOperand(OpIdx++);
1677 Binary |= getMachineOpValue(MI, Base) << ARMII::RegRnShift;
1679 // If there is a non-zero immediate offset, encode it.
1681 const MachineOperand &Offset = MI.getOperand(OpIdx);
1682 if (unsigned ImmOffs = ARM_AM::getAM5Offset(Offset.getImm())) {
1683 if (ARM_AM::getAM5Op(Offset.getImm()) == ARM_AM::add)
1684 Binary |= 1 << ARMII::U_BitShift;
1691 // If immediate offset is omitted, default to +0.
1692 Binary |= 1 << ARMII::U_BitShift;
1698 ARMCodeEmitter::emitVFPLoadStoreMultipleInstruction(const MachineInstr &MI) {
1699 const TargetInstrDesc &TID = MI.getDesc();
1700 bool IsUpdating = (TID.TSFlags & ARMII::IndexModeMask) != 0;
1702 // Part of binary is determined by TableGn.
1703 unsigned Binary = getBinaryCodeForInstr(MI);
1705 // Set the conditional execution predicate
1706 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1708 // Skip operand 0 of an instruction with base register update.
1713 // Set base address operand
1714 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift;
1716 // Set addressing mode by modifying bits U(23) and P(24)
1717 ARM_AM::AMSubMode Mode = ARM_AM::getLoadStoreMultipleSubMode(MI.getOpcode());
1718 Binary |= getAddrModeUPBits(ARM_AM::getAM4SubMode(Mode));
1722 Binary |= 0x1 << ARMII::W_BitShift;
1724 // First register is encoded in Dd.
1725 Binary |= encodeVFPRd(MI, OpIdx+2);
1727 // Count the number of registers.
1728 unsigned NumRegs = 1;
1729 for (unsigned i = OpIdx+3, e = MI.getNumOperands(); i != e; ++i) {
1730 const MachineOperand &MO = MI.getOperand(i);
1731 if (!MO.isReg() || MO.isImplicit())
1735 // Bit 8 will be set if <list> is consecutive 64-bit registers (e.g., D0)
1736 // Otherwise, it will be 0, in the case of 32-bit registers.
1738 Binary |= NumRegs * 2;
1745 static unsigned encodeNEONRd(const MachineInstr &MI, unsigned OpIdx) {
1746 unsigned RegD = MI.getOperand(OpIdx).getReg();
1747 unsigned Binary = 0;
1748 RegD = getARMRegisterNumbering(RegD);
1749 Binary |= (RegD & 0xf) << ARMII::RegRdShift;
1750 Binary |= ((RegD >> 4) & 1) << ARMII::D_BitShift;
1754 static unsigned encodeNEONRn(const MachineInstr &MI, unsigned OpIdx) {
1755 unsigned RegN = MI.getOperand(OpIdx).getReg();
1756 unsigned Binary = 0;
1757 RegN = getARMRegisterNumbering(RegN);
1758 Binary |= (RegN & 0xf) << ARMII::RegRnShift;
1759 Binary |= ((RegN >> 4) & 1) << ARMII::N_BitShift;
1763 static unsigned encodeNEONRm(const MachineInstr &MI, unsigned OpIdx) {
1764 unsigned RegM = MI.getOperand(OpIdx).getReg();
1765 unsigned Binary = 0;
1766 RegM = getARMRegisterNumbering(RegM);
1767 Binary |= (RegM & 0xf);
1768 Binary |= ((RegM >> 4) & 1) << ARMII::M_BitShift;
1772 /// convertNEONDataProcToThumb - Convert the ARM mode encoding for a NEON
1773 /// data-processing instruction to the corresponding Thumb encoding.
1774 static unsigned convertNEONDataProcToThumb(unsigned Binary) {
1775 assert((Binary & 0xfe000000) == 0xf2000000 &&
1776 "not an ARM NEON data-processing instruction");
1777 unsigned UBit = (Binary >> 24) & 1;
1778 return 0xef000000 | (UBit << 28) | (Binary & 0xffffff);
1781 void ARMCodeEmitter::emitNEONLaneInstruction(const MachineInstr &MI) {
1782 unsigned Binary = getBinaryCodeForInstr(MI);
1784 unsigned RegTOpIdx, RegNOpIdx, LnOpIdx;
1785 const TargetInstrDesc &TID = MI.getDesc();
1786 if ((TID.TSFlags & ARMII::FormMask) == ARMII::NGetLnFrm) {
1790 } else { // ARMII::NSetLnFrm
1796 // Set the conditional execution predicate
1797 Binary |= (IsThumb ? ARMCC::AL : II->getPredicate(&MI)) << ARMII::CondShift;
1799 unsigned RegT = MI.getOperand(RegTOpIdx).getReg();
1800 RegT = getARMRegisterNumbering(RegT);
1801 Binary |= (RegT << ARMII::RegRdShift);
1802 Binary |= encodeNEONRn(MI, RegNOpIdx);
1805 if ((Binary & (1 << 22)) != 0)
1806 LaneShift = 0; // 8-bit elements
1807 else if ((Binary & (1 << 5)) != 0)
1808 LaneShift = 1; // 16-bit elements
1810 LaneShift = 2; // 32-bit elements
1812 unsigned Lane = MI.getOperand(LnOpIdx).getImm() << LaneShift;
1813 unsigned Opc1 = Lane >> 2;
1814 unsigned Opc2 = Lane & 3;
1815 assert((Opc1 & 3) == 0 && "out-of-range lane number operand");
1816 Binary |= (Opc1 << 21);
1817 Binary |= (Opc2 << 5);
1822 void ARMCodeEmitter::emitNEONDupInstruction(const MachineInstr &MI) {
1823 unsigned Binary = getBinaryCodeForInstr(MI);
1825 // Set the conditional execution predicate
1826 Binary |= (IsThumb ? ARMCC::AL : II->getPredicate(&MI)) << ARMII::CondShift;
1828 unsigned RegT = MI.getOperand(1).getReg();
1829 RegT = getARMRegisterNumbering(RegT);
1830 Binary |= (RegT << ARMII::RegRdShift);
1831 Binary |= encodeNEONRn(MI, 0);
1835 void ARMCodeEmitter::emitNEON1RegModImmInstruction(const MachineInstr &MI) {
1836 unsigned Binary = getBinaryCodeForInstr(MI);
1837 // Destination register is encoded in Dd.
1838 Binary |= encodeNEONRd(MI, 0);
1839 // Immediate fields: Op, Cmode, I, Imm3, Imm4
1840 unsigned Imm = MI.getOperand(1).getImm();
1841 unsigned Op = (Imm >> 12) & 1;
1842 unsigned Cmode = (Imm >> 8) & 0xf;
1843 unsigned I = (Imm >> 7) & 1;
1844 unsigned Imm3 = (Imm >> 4) & 0x7;
1845 unsigned Imm4 = Imm & 0xf;
1846 Binary |= (I << 24) | (Imm3 << 16) | (Cmode << 8) | (Op << 5) | Imm4;
1848 Binary = convertNEONDataProcToThumb(Binary);
1852 void ARMCodeEmitter::emitNEON2RegInstruction(const MachineInstr &MI) {
1853 const TargetInstrDesc &TID = MI.getDesc();
1854 unsigned Binary = getBinaryCodeForInstr(MI);
1855 // Destination register is encoded in Dd; source register in Dm.
1857 Binary |= encodeNEONRd(MI, OpIdx++);
1858 if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
1860 Binary |= encodeNEONRm(MI, OpIdx);
1862 Binary = convertNEONDataProcToThumb(Binary);
1863 // FIXME: This does not handle VDUPfdf or VDUPfqf.
1867 void ARMCodeEmitter::emitNEON3RegInstruction(const MachineInstr &MI) {
1868 const TargetInstrDesc &TID = MI.getDesc();
1869 unsigned Binary = getBinaryCodeForInstr(MI);
1870 // Destination register is encoded in Dd; source registers in Dn and Dm.
1872 Binary |= encodeNEONRd(MI, OpIdx++);
1873 if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
1875 Binary |= encodeNEONRn(MI, OpIdx++);
1876 if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
1878 Binary |= encodeNEONRm(MI, OpIdx);
1880 Binary = convertNEONDataProcToThumb(Binary);
1881 // FIXME: This does not handle VMOVDneon or VMOVQ.
1885 #include "ARMGenCodeEmitter.inc"