1 //===-- ARM/ARMCodeEmitter.cpp - Convert ARM code to machine code ---------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the pass that transforms the ARM machine instructions into
11 // relocatable machine code.
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "jit"
17 #include "ARMAddressingModes.h"
18 #include "ARMConstantPoolValue.h"
19 #include "ARMInstrInfo.h"
20 #include "ARMRelocations.h"
21 #include "ARMSubtarget.h"
22 #include "ARMTargetMachine.h"
23 #include "llvm/Constants.h"
24 #include "llvm/DerivedTypes.h"
25 #include "llvm/Function.h"
26 #include "llvm/PassManager.h"
27 #include "llvm/CodeGen/MachineCodeEmitter.h"
28 #include "llvm/CodeGen/MachineConstantPool.h"
29 #include "llvm/CodeGen/MachineFunctionPass.h"
30 #include "llvm/CodeGen/MachineInstr.h"
31 #include "llvm/CodeGen/MachineJumpTableInfo.h"
32 #include "llvm/CodeGen/Passes.h"
33 #include "llvm/ADT/Statistic.h"
34 #include "llvm/Support/Compiler.h"
35 #include "llvm/Support/Debug.h"
41 STATISTIC(NumEmitted, "Number of machine instructions emitted");
44 class VISIBILITY_HIDDEN ARMCodeEmitter : public MachineFunctionPass {
46 const ARMInstrInfo *II;
49 MachineCodeEmitter &MCE;
50 const std::vector<MachineConstantPoolEntry> *MCPEs;
51 const std::vector<MachineJumpTableEntry> *MJTEs;
56 explicit ARMCodeEmitter(TargetMachine &tm, MachineCodeEmitter &mce)
57 : MachineFunctionPass(&ID), JTI(0), II(0), TD(0), TM(tm),
58 MCE(mce), MCPEs(0), MJTEs(0),
59 IsPIC(TM.getRelocationModel() == Reloc::PIC_) {}
60 ARMCodeEmitter(TargetMachine &tm, MachineCodeEmitter &mce,
61 const ARMInstrInfo &ii, const TargetData &td)
62 : MachineFunctionPass(&ID), JTI(0), II(&ii), TD(&td), TM(tm),
63 MCE(mce), MCPEs(0), MJTEs(0),
64 IsPIC(TM.getRelocationModel() == Reloc::PIC_) {}
66 bool runOnMachineFunction(MachineFunction &MF);
68 virtual const char *getPassName() const {
69 return "ARM Machine Code Emitter";
72 void emitInstruction(const MachineInstr &MI);
76 void emitWordLE(unsigned Binary);
78 void emitConstPoolInstruction(const MachineInstr &MI);
80 void emitMOVi2piecesInstruction(const MachineInstr &MI);
82 void emitLEApcrelJTInstruction(const MachineInstr &MI);
84 void addPCLabel(unsigned LabelID);
86 void emitPseudoInstruction(const MachineInstr &MI);
88 unsigned getMachineSoRegOpValue(const MachineInstr &MI,
89 const TargetInstrDesc &TID,
90 const MachineOperand &MO,
93 unsigned getMachineSoImmOpValue(unsigned SoImm);
95 unsigned getAddrModeSBit(const MachineInstr &MI,
96 const TargetInstrDesc &TID) const;
98 void emitDataProcessingInstruction(const MachineInstr &MI,
99 unsigned ImplicitRd = 0,
100 unsigned ImplicitRn = 0);
102 void emitLoadStoreInstruction(const MachineInstr &MI,
103 unsigned ImplicitRd = 0,
104 unsigned ImplicitRn = 0);
106 void emitMiscLoadStoreInstruction(const MachineInstr &MI,
107 unsigned ImplicitRn = 0);
109 void emitLoadStoreMultipleInstruction(const MachineInstr &MI);
111 void emitMulFrmInstruction(const MachineInstr &MI);
113 void emitExtendInstruction(const MachineInstr &MI);
115 void emitMiscArithInstruction(const MachineInstr &MI);
117 void emitBranchInstruction(const MachineInstr &MI);
119 void emitInlineJumpTable(unsigned JTIndex);
121 void emitMiscBranchInstruction(const MachineInstr &MI);
123 void emitVFPArithInstruction(const MachineInstr &MI);
125 void emitVFPConversionInstruction(const MachineInstr &MI);
127 /// getBinaryCodeForInstr - This function, generated by the
128 /// CodeEmitterGenerator using TableGen, produces the binary encoding for
129 /// machine instructions.
131 unsigned getBinaryCodeForInstr(const MachineInstr &MI);
133 /// getMachineOpValue - Return binary encoding of operand. If the machine
134 /// operand requires relocation, record the relocation and return zero.
135 unsigned getMachineOpValue(const MachineInstr &MI,const MachineOperand &MO);
136 unsigned getMachineOpValue(const MachineInstr &MI, unsigned OpIdx) {
137 return getMachineOpValue(MI, MI.getOperand(OpIdx));
140 /// getShiftOp - Return the shift opcode (bit[6:5]) of the immediate value.
142 unsigned getShiftOp(unsigned Imm) const ;
144 /// Routines that handle operands which add machine relocations which are
145 /// fixed up by the relocation stage.
146 void emitGlobalAddress(GlobalValue *GV, unsigned Reloc,
147 bool NeedStub, intptr_t ACPV = 0);
148 void emitExternalSymbolAddress(const char *ES, unsigned Reloc);
149 void emitConstPoolAddress(unsigned CPI, unsigned Reloc);
150 void emitJumpTableAddress(unsigned JTIndex, unsigned Reloc);
151 void emitMachineBasicBlock(MachineBasicBlock *BB, unsigned Reloc,
152 intptr_t JTBase = 0);
154 char ARMCodeEmitter::ID = 0;
157 /// createARMCodeEmitterPass - Return a pass that emits the collected ARM code
158 /// to the specified MCE object.
159 FunctionPass *llvm::createARMCodeEmitterPass(ARMTargetMachine &TM,
160 MachineCodeEmitter &MCE) {
161 return new ARMCodeEmitter(TM, MCE);
164 bool ARMCodeEmitter::runOnMachineFunction(MachineFunction &MF) {
165 assert((MF.getTarget().getRelocationModel() != Reloc::Default ||
166 MF.getTarget().getRelocationModel() != Reloc::Static) &&
167 "JIT relocation model must be set to static or default!");
168 II = ((ARMTargetMachine&)MF.getTarget()).getInstrInfo();
169 TD = ((ARMTargetMachine&)MF.getTarget()).getTargetData();
170 JTI = ((ARMTargetMachine&)MF.getTarget()).getJITInfo();
171 MCPEs = &MF.getConstantPool()->getConstants();
172 MJTEs = &MF.getJumpTableInfo()->getJumpTables();
173 IsPIC = TM.getRelocationModel() == Reloc::PIC_;
174 JTI->Initialize(MF, IsPIC);
177 DOUT << "JITTing function '" << MF.getFunction()->getName() << "'\n";
178 MCE.startFunction(MF);
179 for (MachineFunction::iterator MBB = MF.begin(), E = MF.end();
181 MCE.StartMachineBasicBlock(MBB);
182 for (MachineBasicBlock::const_iterator I = MBB->begin(), E = MBB->end();
186 } while (MCE.finishFunction(MF));
191 /// getShiftOp - Return the shift opcode (bit[6:5]) of the immediate value.
193 unsigned ARMCodeEmitter::getShiftOp(unsigned Imm) const {
194 switch (ARM_AM::getAM2ShiftOpc(Imm)) {
195 default: assert(0 && "Unknown shift opc!");
196 case ARM_AM::asr: return 2;
197 case ARM_AM::lsl: return 0;
198 case ARM_AM::lsr: return 1;
200 case ARM_AM::rrx: return 3;
205 /// getMachineOpValue - Return binary encoding of operand. If the machine
206 /// operand requires relocation, record the relocation and return zero.
207 unsigned ARMCodeEmitter::getMachineOpValue(const MachineInstr &MI,
208 const MachineOperand &MO) {
210 return ARMRegisterInfo::getRegisterNumbering(MO.getReg());
212 return static_cast<unsigned>(MO.getImm());
213 else if (MO.isGlobal())
214 emitGlobalAddress(MO.getGlobal(), ARM::reloc_arm_branch, true);
215 else if (MO.isSymbol())
216 emitExternalSymbolAddress(MO.getSymbolName(), ARM::reloc_arm_branch);
218 emitConstPoolAddress(MO.getIndex(), ARM::reloc_arm_cp_entry);
220 emitJumpTableAddress(MO.getIndex(), ARM::reloc_arm_relative);
222 emitMachineBasicBlock(MO.getMBB(), ARM::reloc_arm_branch);
224 cerr << "ERROR: Unknown type of MachineOperand: " << MO << "\n";
230 /// emitGlobalAddress - Emit the specified address to the code stream.
232 void ARMCodeEmitter::emitGlobalAddress(GlobalValue *GV, unsigned Reloc,
233 bool NeedStub, intptr_t ACPV) {
234 MCE.addRelocation(MachineRelocation::getGV(MCE.getCurrentPCOffset(),
235 Reloc, GV, ACPV, NeedStub));
238 /// emitExternalSymbolAddress - Arrange for the address of an external symbol to
239 /// be emitted to the current location in the function, and allow it to be PC
241 void ARMCodeEmitter::emitExternalSymbolAddress(const char *ES, unsigned Reloc) {
242 MCE.addRelocation(MachineRelocation::getExtSym(MCE.getCurrentPCOffset(),
246 /// emitConstPoolAddress - Arrange for the address of an constant pool
247 /// to be emitted to the current location in the function, and allow it to be PC
249 void ARMCodeEmitter::emitConstPoolAddress(unsigned CPI, unsigned Reloc) {
250 // Tell JIT emitter we'll resolve the address.
251 MCE.addRelocation(MachineRelocation::getConstPool(MCE.getCurrentPCOffset(),
252 Reloc, CPI, 0, true));
255 /// emitJumpTableAddress - Arrange for the address of a jump table to
256 /// be emitted to the current location in the function, and allow it to be PC
258 void ARMCodeEmitter::emitJumpTableAddress(unsigned JTIndex, unsigned Reloc) {
259 MCE.addRelocation(MachineRelocation::getJumpTable(MCE.getCurrentPCOffset(),
260 Reloc, JTIndex, 0, true));
263 /// emitMachineBasicBlock - Emit the specified address basic block.
264 void ARMCodeEmitter::emitMachineBasicBlock(MachineBasicBlock *BB,
265 unsigned Reloc, intptr_t JTBase) {
266 MCE.addRelocation(MachineRelocation::getBB(MCE.getCurrentPCOffset(),
270 void ARMCodeEmitter::emitWordLE(unsigned Binary) {
272 DOUT << " 0x" << std::hex << std::setw(8) << std::setfill('0')
273 << Binary << std::dec << "\n";
275 MCE.emitWordLE(Binary);
278 void ARMCodeEmitter::emitInstruction(const MachineInstr &MI) {
279 DOUT << "JIT: " << (void*)MCE.getCurrentPCValue() << ":\t" << MI;
281 NumEmitted++; // Keep track of the # of mi's emitted
282 switch (MI.getDesc().TSFlags & ARMII::FormMask) {
284 assert(0 && "Unhandled instruction encoding format!");
287 emitPseudoInstruction(MI);
290 case ARMII::DPSoRegFrm:
291 emitDataProcessingInstruction(MI);
295 emitLoadStoreInstruction(MI);
297 case ARMII::LdMiscFrm:
298 case ARMII::StMiscFrm:
299 emitMiscLoadStoreInstruction(MI);
301 case ARMII::LdMulFrm:
302 case ARMII::StMulFrm:
303 emitLoadStoreMultipleInstruction(MI);
306 emitMulFrmInstruction(MI);
309 emitExtendInstruction(MI);
311 case ARMII::ArithMiscFrm:
312 emitMiscArithInstruction(MI);
315 emitBranchInstruction(MI);
317 case ARMII::BrMiscFrm:
318 emitMiscBranchInstruction(MI);
321 case ARMII::VFPUnaryFrm:
322 case ARMII::VFPBinaryFrm:
323 emitVFPArithInstruction(MI);
325 case ARMII::VFPConv1Frm:
326 case ARMII::VFPConv2Frm:
327 emitVFPConversionInstruction(MI);
332 void ARMCodeEmitter::emitConstPoolInstruction(const MachineInstr &MI) {
333 unsigned CPI = MI.getOperand(0).getImm(); // CP instruction index.
334 unsigned CPIndex = MI.getOperand(1).getIndex(); // Actual cp entry index.
335 const MachineConstantPoolEntry &MCPE = (*MCPEs)[CPIndex];
337 // Remember the CONSTPOOL_ENTRY address for later relocation.
338 JTI->addConstantPoolEntryAddr(CPI, MCE.getCurrentPCValue());
340 // Emit constpool island entry. In most cases, the actual values will be
341 // resolved and relocated after code emission.
342 if (MCPE.isMachineConstantPoolEntry()) {
343 ARMConstantPoolValue *ACPV =
344 static_cast<ARMConstantPoolValue*>(MCPE.Val.MachineCPVal);
346 DOUT << " ** ARM constant pool #" << CPI << " @ "
347 << (void*)MCE.getCurrentPCValue() << " " << *ACPV << '\n';
349 GlobalValue *GV = ACPV->getGV();
351 assert(!ACPV->isStub() && "Don't know how to deal this yet!");
352 if (ACPV->isNonLazyPointer())
353 MCE.addRelocation(MachineRelocation::getIndirectSymbol(
354 MCE.getCurrentPCOffset(), ARM::reloc_arm_machine_cp_entry, GV,
355 (intptr_t)ACPV, false));
357 emitGlobalAddress(GV, ARM::reloc_arm_machine_cp_entry,
358 ACPV->isStub(), (intptr_t)ACPV);
360 assert(!ACPV->isNonLazyPointer() && "Don't know how to deal this yet!");
361 emitExternalSymbolAddress(ACPV->getSymbol(), ARM::reloc_arm_absolute);
365 Constant *CV = MCPE.Val.ConstVal;
367 DOUT << " ** Constant pool #" << CPI << " @ "
368 << (void*)MCE.getCurrentPCValue() << " " << *CV << '\n';
370 if (GlobalValue *GV = dyn_cast<GlobalValue>(CV)) {
371 emitGlobalAddress(GV, ARM::reloc_arm_absolute, false);
374 assert(CV->getType()->isInteger() &&
375 "Not expecting non-integer constpool entries yet!");
376 const ConstantInt *CI = dyn_cast<ConstantInt>(CV);
377 uint32_t Val = *(uint32_t*)CI->getValue().getRawData();
383 void ARMCodeEmitter::emitMOVi2piecesInstruction(const MachineInstr &MI) {
384 const MachineOperand &MO0 = MI.getOperand(0);
385 const MachineOperand &MO1 = MI.getOperand(1);
386 assert(MO1.isImm() && "Not a valid so_imm value!");
387 unsigned V1 = ARM_AM::getSOImmTwoPartFirst(MO1.getImm());
388 unsigned V2 = ARM_AM::getSOImmTwoPartSecond(MO1.getImm());
390 // Emit the 'mov' instruction.
391 unsigned Binary = 0xd << 21; // mov: Insts{24-21} = 0b1101
393 // Set the conditional execution predicate.
394 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
397 Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRdShift;
400 // Set bit I(25) to identify this is the immediate form of <shifter_op>
401 Binary |= 1 << ARMII::I_BitShift;
402 Binary |= getMachineSoImmOpValue(ARM_AM::getSOImmVal(V1));
405 // Now the 'orr' instruction.
406 Binary = 0xc << 21; // orr: Insts{24-21} = 0b1100
408 // Set the conditional execution predicate.
409 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
412 Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRdShift;
415 Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRnShift;
418 // Set bit I(25) to identify this is the immediate form of <shifter_op>
419 Binary |= 1 << ARMII::I_BitShift;
420 Binary |= getMachineSoImmOpValue(ARM_AM::getSOImmVal(V2));
424 void ARMCodeEmitter::emitLEApcrelJTInstruction(const MachineInstr &MI) {
425 // It's basically add r, pc, (LJTI - $+8)
427 const TargetInstrDesc &TID = MI.getDesc();
429 // Emit the 'add' instruction.
430 unsigned Binary = 0x4 << 21; // add: Insts{24-31} = 0b0100
432 // Set the conditional execution predicate
433 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
435 // Encode S bit if MI modifies CPSR.
436 Binary |= getAddrModeSBit(MI, TID);
439 Binary |= getMachineOpValue(MI, 0) << ARMII::RegRdShift;
441 // Encode Rn which is PC.
442 Binary |= ARMRegisterInfo::getRegisterNumbering(ARM::PC) << ARMII::RegRnShift;
444 // Encode the displacement.
445 // Set bit I(25) to identify this is the immediate form of <shifter_op>.
446 Binary |= 1 << ARMII::I_BitShift;
447 emitJumpTableAddress(MI.getOperand(1).getIndex(), ARM::reloc_arm_jt_base);
452 void ARMCodeEmitter::addPCLabel(unsigned LabelID) {
453 DOUT << " ** LPC" << LabelID << " @ "
454 << (void*)MCE.getCurrentPCValue() << '\n';
455 JTI->addPCLabelAddr(LabelID, MCE.getCurrentPCValue());
458 void ARMCodeEmitter::emitPseudoInstruction(const MachineInstr &MI) {
459 unsigned Opcode = MI.getDesc().Opcode;
463 case ARM::CONSTPOOL_ENTRY:
464 emitConstPoolInstruction(MI);
467 // Remember of the address of the PC label for relocation later.
468 addPCLabel(MI.getOperand(2).getImm());
469 // PICADD is just an add instruction that implicitly read pc.
470 emitDataProcessingInstruction(MI, 0, ARM::PC);
477 // Remember of the address of the PC label for relocation later.
478 addPCLabel(MI.getOperand(2).getImm());
479 // These are just load / store instructions that implicitly read pc.
480 emitLoadStoreInstruction(MI, 0, ARM::PC);
487 // Remember of the address of the PC label for relocation later.
488 addPCLabel(MI.getOperand(2).getImm());
489 // These are just load / store instructions that implicitly read pc.
490 emitMiscLoadStoreInstruction(MI, ARM::PC);
493 case ARM::MOVi2pieces:
494 // Two instructions to materialize a constant.
495 emitMOVi2piecesInstruction(MI);
497 case ARM::LEApcrelJT:
498 // Materialize jumptable address.
499 emitLEApcrelJTInstruction(MI);
505 unsigned ARMCodeEmitter::getMachineSoRegOpValue(const MachineInstr &MI,
506 const TargetInstrDesc &TID,
507 const MachineOperand &MO,
509 unsigned Binary = getMachineOpValue(MI, MO);
511 const MachineOperand &MO1 = MI.getOperand(OpIdx + 1);
512 const MachineOperand &MO2 = MI.getOperand(OpIdx + 2);
513 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO2.getImm());
515 // Encode the shift opcode.
517 unsigned Rs = MO1.getReg();
519 // Set shift operand (bit[7:4]).
524 // RRX - 0110 and bit[11:8] clear.
526 default: assert(0 && "Unknown shift opc!");
527 case ARM_AM::lsl: SBits = 0x1; break;
528 case ARM_AM::lsr: SBits = 0x3; break;
529 case ARM_AM::asr: SBits = 0x5; break;
530 case ARM_AM::ror: SBits = 0x7; break;
531 case ARM_AM::rrx: SBits = 0x6; break;
534 // Set shift operand (bit[6:4]).
540 default: assert(0 && "Unknown shift opc!");
541 case ARM_AM::lsl: SBits = 0x0; break;
542 case ARM_AM::lsr: SBits = 0x2; break;
543 case ARM_AM::asr: SBits = 0x4; break;
544 case ARM_AM::ror: SBits = 0x6; break;
547 Binary |= SBits << 4;
548 if (SOpc == ARM_AM::rrx)
551 // Encode the shift operation Rs or shift_imm (except rrx).
553 // Encode Rs bit[11:8].
554 assert(ARM_AM::getSORegOffset(MO2.getImm()) == 0);
556 (ARMRegisterInfo::getRegisterNumbering(Rs) << ARMII::RegRsShift);
559 // Encode shift_imm bit[11:7].
560 return Binary | ARM_AM::getSORegOffset(MO2.getImm()) << 7;
563 unsigned ARMCodeEmitter::getMachineSoImmOpValue(unsigned SoImm) {
564 // Encode rotate_imm.
565 unsigned Binary = (ARM_AM::getSOImmValRot(SoImm) >> 1)
566 << ARMII::SoRotImmShift;
569 Binary |= ARM_AM::getSOImmValImm(SoImm);
573 unsigned ARMCodeEmitter::getAddrModeSBit(const MachineInstr &MI,
574 const TargetInstrDesc &TID) const {
575 for (unsigned i = MI.getNumOperands(), e = TID.getNumOperands(); i != e; --i){
576 const MachineOperand &MO = MI.getOperand(i-1);
577 if (MO.isReg() && MO.isDef() && MO.getReg() == ARM::CPSR)
578 return 1 << ARMII::S_BitShift;
583 void ARMCodeEmitter::emitDataProcessingInstruction(const MachineInstr &MI,
585 unsigned ImplicitRn) {
586 const TargetInstrDesc &TID = MI.getDesc();
588 // Part of binary is determined by TableGn.
589 unsigned Binary = getBinaryCodeForInstr(MI);
591 // Set the conditional execution predicate
592 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
594 // Encode S bit if MI modifies CPSR.
595 Binary |= getAddrModeSBit(MI, TID);
597 // Encode register def if there is one.
598 unsigned NumDefs = TID.getNumDefs();
601 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
603 // Special handling for implicit use (e.g. PC).
604 Binary |= (ARMRegisterInfo::getRegisterNumbering(ImplicitRd)
605 << ARMII::RegRdShift);
607 // If this is a two-address operand, skip it. e.g. MOVCCr operand 1.
608 if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
611 // Encode first non-shifter register operand if there is one.
612 bool isUnary = TID.TSFlags & ARMII::UnaryDP;
615 // Special handling for implicit use (e.g. PC).
616 Binary |= (ARMRegisterInfo::getRegisterNumbering(ImplicitRn)
617 << ARMII::RegRnShift);
619 Binary |= getMachineOpValue(MI, OpIdx) << ARMII::RegRnShift;
624 // Encode shifter operand.
625 const MachineOperand &MO = MI.getOperand(OpIdx);
626 if ((TID.TSFlags & ARMII::FormMask) == ARMII::DPSoRegFrm) {
628 emitWordLE(Binary | getMachineSoRegOpValue(MI, TID, MO, OpIdx));
633 // Encode register Rm.
634 emitWordLE(Binary | ARMRegisterInfo::getRegisterNumbering(MO.getReg()));
639 // Set bit I(25) to identify this is the immediate form of <shifter_op>.
640 Binary |= 1 << ARMII::I_BitShift;
641 Binary |= getMachineSoImmOpValue(MO.getImm());
646 void ARMCodeEmitter::emitLoadStoreInstruction(const MachineInstr &MI,
648 unsigned ImplicitRn) {
649 const TargetInstrDesc &TID = MI.getDesc();
651 // Part of binary is determined by TableGn.
652 unsigned Binary = getBinaryCodeForInstr(MI);
654 // Set the conditional execution predicate
655 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
660 // Special handling for implicit use (e.g. PC).
661 Binary |= (ARMRegisterInfo::getRegisterNumbering(ImplicitRd)
662 << ARMII::RegRdShift);
664 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
666 // Set second operand
668 // Special handling for implicit use (e.g. PC).
669 Binary |= (ARMRegisterInfo::getRegisterNumbering(ImplicitRn)
670 << ARMII::RegRnShift);
672 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift;
674 // If this is a two-address operand, skip it. e.g. LDR_PRE.
675 if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
678 const MachineOperand &MO2 = MI.getOperand(OpIdx);
679 unsigned AM2Opc = (ImplicitRn == ARM::PC)
680 ? 0 : MI.getOperand(OpIdx+1).getImm();
682 // Set bit U(23) according to sign of immed value (positive or negative).
683 Binary |= ((ARM_AM::getAM2Op(AM2Opc) == ARM_AM::add ? 1 : 0) <<
685 if (!MO2.getReg()) { // is immediate
686 if (ARM_AM::getAM2Offset(AM2Opc))
687 // Set the value of offset_12 field
688 Binary |= ARM_AM::getAM2Offset(AM2Opc);
693 // Set bit I(25), because this is not in immediate enconding.
694 Binary |= 1 << ARMII::I_BitShift;
695 assert(TargetRegisterInfo::isPhysicalRegister(MO2.getReg()));
696 // Set bit[3:0] to the corresponding Rm register
697 Binary |= ARMRegisterInfo::getRegisterNumbering(MO2.getReg());
699 // if this instr is in scaled register offset/index instruction, set
700 // shift_immed(bit[11:7]) and shift(bit[6:5]) fields.
701 if (unsigned ShImm = ARM_AM::getAM2Offset(AM2Opc)) {
702 Binary |= getShiftOp(AM2Opc) << 5; // shift
703 Binary |= ShImm << 7; // shift_immed
709 void ARMCodeEmitter::emitMiscLoadStoreInstruction(const MachineInstr &MI,
710 unsigned ImplicitRn) {
711 const TargetInstrDesc &TID = MI.getDesc();
713 // Part of binary is determined by TableGn.
714 unsigned Binary = getBinaryCodeForInstr(MI);
716 // Set the conditional execution predicate
717 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
720 Binary |= getMachineOpValue(MI, 0) << ARMII::RegRdShift;
722 // Set second operand
725 // Special handling for implicit use (e.g. PC).
726 Binary |= (ARMRegisterInfo::getRegisterNumbering(ImplicitRn)
727 << ARMII::RegRnShift);
729 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift;
731 // If this is a two-address operand, skip it. e.g. LDRH_POST.
732 if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
735 const MachineOperand &MO2 = MI.getOperand(OpIdx);
736 unsigned AM3Opc = (ImplicitRn == ARM::PC)
737 ? 0 : MI.getOperand(OpIdx+1).getImm();
739 // Set bit U(23) according to sign of immed value (positive or negative)
740 Binary |= ((ARM_AM::getAM3Op(AM3Opc) == ARM_AM::add ? 1 : 0) <<
743 // If this instr is in register offset/index encoding, set bit[3:0]
744 // to the corresponding Rm register.
746 Binary |= ARMRegisterInfo::getRegisterNumbering(MO2.getReg());
751 // This instr is in immediate offset/index encoding, set bit 22 to 1.
752 Binary |= 1 << ARMII::AM3_I_BitShift;
753 if (unsigned ImmOffs = ARM_AM::getAM3Offset(AM3Opc)) {
755 Binary |= (ImmOffs >> 4) << 8; // immedH
756 Binary |= (ImmOffs & ~0xF); // immedL
762 void ARMCodeEmitter::emitLoadStoreMultipleInstruction(const MachineInstr &MI) {
763 // Part of binary is determined by TableGn.
764 unsigned Binary = getBinaryCodeForInstr(MI);
766 // Set the conditional execution predicate
767 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
770 Binary |= getMachineOpValue(MI, 0) << ARMII::RegRnShift;
772 // Set addressing mode by modifying bits U(23) and P(24)
773 // IA - Increment after - bit U = 1 and bit P = 0
774 // IB - Increment before - bit U = 1 and bit P = 1
775 // DA - Decrement after - bit U = 0 and bit P = 0
776 // DB - Decrement before - bit U = 0 and bit P = 1
777 const MachineOperand &MO = MI.getOperand(1);
778 ARM_AM::AMSubMode Mode = ARM_AM::getAM4SubMode(MO.getImm());
780 default: assert(0 && "Unknown addressing sub-mode!");
781 case ARM_AM::da: break;
782 case ARM_AM::db: Binary |= 0x1 << ARMII::P_BitShift; break;
783 case ARM_AM::ia: Binary |= 0x1 << ARMII::U_BitShift; break;
784 case ARM_AM::ib: Binary |= 0x3 << ARMII::U_BitShift; break;
788 if (ARM_AM::getAM4WBFlag(MO.getImm()))
789 Binary |= 0x1 << ARMII::W_BitShift;
792 for (unsigned i = 4, e = MI.getNumOperands(); i != e; ++i) {
793 const MachineOperand &MO = MI.getOperand(i);
794 if (MO.isReg() && MO.isImplicit())
796 unsigned RegNum = ARMRegisterInfo::getRegisterNumbering(MO.getReg());
797 assert(TargetRegisterInfo::isPhysicalRegister(MO.getReg()) &&
799 Binary |= 0x1 << RegNum;
805 void ARMCodeEmitter::emitMulFrmInstruction(const MachineInstr &MI) {
806 const TargetInstrDesc &TID = MI.getDesc();
808 // Part of binary is determined by TableGn.
809 unsigned Binary = getBinaryCodeForInstr(MI);
811 // Set the conditional execution predicate
812 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
814 // Encode S bit if MI modifies CPSR.
815 Binary |= getAddrModeSBit(MI, TID);
817 // 32x32->64bit operations have two destination registers. The number
818 // of register definitions will tell us if that's what we're dealing with.
820 if (TID.getNumDefs() == 2)
821 Binary |= getMachineOpValue (MI, OpIdx++) << ARMII::RegRdLoShift;
824 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdHiShift;
827 Binary |= getMachineOpValue(MI, OpIdx++);
830 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRsShift;
832 // Many multiple instructions (e.g. MLA) have three src operands. Encode
833 // it as Rn (for multiply, that's in the same offset as RdLo.
834 if (TID.getNumOperands() > OpIdx &&
835 !TID.OpInfo[OpIdx].isPredicate() &&
836 !TID.OpInfo[OpIdx].isOptionalDef())
837 Binary |= getMachineOpValue(MI, OpIdx) << ARMII::RegRdLoShift;
842 void ARMCodeEmitter::emitExtendInstruction(const MachineInstr &MI) {
843 const TargetInstrDesc &TID = MI.getDesc();
845 // Part of binary is determined by TableGn.
846 unsigned Binary = getBinaryCodeForInstr(MI);
848 // Set the conditional execution predicate
849 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
854 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
856 const MachineOperand &MO1 = MI.getOperand(OpIdx++);
857 const MachineOperand &MO2 = MI.getOperand(OpIdx);
859 // Two register operand form.
861 Binary |= getMachineOpValue(MI, MO1) << ARMII::RegRnShift;
864 Binary |= getMachineOpValue(MI, MO2);
867 Binary |= getMachineOpValue(MI, MO1);
870 // Encode rot imm (0, 8, 16, or 24) if it has a rotate immediate operand.
871 if (MI.getOperand(OpIdx).isImm() &&
872 !TID.OpInfo[OpIdx].isPredicate() &&
873 !TID.OpInfo[OpIdx].isOptionalDef())
874 Binary |= (getMachineOpValue(MI, OpIdx) / 8) << ARMII::ExtRotImmShift;
879 void ARMCodeEmitter::emitMiscArithInstruction(const MachineInstr &MI) {
880 const TargetInstrDesc &TID = MI.getDesc();
882 // Part of binary is determined by TableGn.
883 unsigned Binary = getBinaryCodeForInstr(MI);
885 // Set the conditional execution predicate
886 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
891 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
893 const MachineOperand &MO = MI.getOperand(OpIdx++);
894 if (OpIdx == TID.getNumOperands() ||
895 TID.OpInfo[OpIdx].isPredicate() ||
896 TID.OpInfo[OpIdx].isOptionalDef()) {
897 // Encode Rm and it's done.
898 Binary |= getMachineOpValue(MI, MO);
904 Binary |= getMachineOpValue(MI, MO) << ARMII::RegRnShift;
907 Binary |= getMachineOpValue(MI, OpIdx++);
910 unsigned ShiftAmt = MI.getOperand(OpIdx).getImm();
911 assert(ShiftAmt < 32 && "shift_imm range is 0 to 31!");
912 Binary |= ShiftAmt << ARMII::ShiftShift;
917 void ARMCodeEmitter::emitBranchInstruction(const MachineInstr &MI) {
918 const TargetInstrDesc &TID = MI.getDesc();
920 if (TID.Opcode == ARM::TPsoft)
923 // Part of binary is determined by TableGn.
924 unsigned Binary = getBinaryCodeForInstr(MI);
926 // Set the conditional execution predicate
927 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
929 // Set signed_immed_24 field
930 Binary |= getMachineOpValue(MI, 0);
935 void ARMCodeEmitter::emitInlineJumpTable(unsigned JTIndex) {
936 // Remember the base address of the inline jump table.
937 intptr_t JTBase = MCE.getCurrentPCValue();
938 JTI->addJumpTableBaseAddr(JTIndex, JTBase);
939 DOUT << " ** Jump Table #" << JTIndex << " @ " << (void*)JTBase << '\n';
941 // Now emit the jump table entries.
942 const std::vector<MachineBasicBlock*> &MBBs = (*MJTEs)[JTIndex].MBBs;
943 for (unsigned i = 0, e = MBBs.size(); i != e; ++i) {
945 // DestBB address - JT base.
946 emitMachineBasicBlock(MBBs[i], ARM::reloc_arm_pic_jt, JTBase);
948 // Absolute DestBB address.
949 emitMachineBasicBlock(MBBs[i], ARM::reloc_arm_absolute);
954 void ARMCodeEmitter::emitMiscBranchInstruction(const MachineInstr &MI) {
955 const TargetInstrDesc &TID = MI.getDesc();
957 // Handle jump tables.
958 if (TID.Opcode == ARM::BR_JTr || TID.Opcode == ARM::BR_JTadd) {
959 // First emit a ldr pc, [] instruction.
960 emitDataProcessingInstruction(MI, ARM::PC);
962 // Then emit the inline jump table.
963 unsigned JTIndex = (TID.Opcode == ARM::BR_JTr)
964 ? MI.getOperand(1).getIndex() : MI.getOperand(2).getIndex();
965 emitInlineJumpTable(JTIndex);
967 } else if (TID.Opcode == ARM::BR_JTm) {
968 // First emit a ldr pc, [] instruction.
969 emitLoadStoreInstruction(MI, ARM::PC);
971 // Then emit the inline jump table.
972 emitInlineJumpTable(MI.getOperand(3).getIndex());
976 // Part of binary is determined by TableGn.
977 unsigned Binary = getBinaryCodeForInstr(MI);
979 // Set the conditional execution predicate
980 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
982 if (TID.Opcode == ARM::BX_RET)
983 // The return register is LR.
984 Binary |= ARMRegisterInfo::getRegisterNumbering(ARM::LR);
986 // otherwise, set the return register
987 Binary |= getMachineOpValue(MI, 0);
992 void ARMCodeEmitter::emitVFPArithInstruction(const MachineInstr &MI) {
993 const TargetInstrDesc &TID = MI.getDesc();
995 // Part of binary is determined by TableGn.
996 unsigned Binary = getBinaryCodeForInstr(MI);
998 // Set the conditional execution predicate
999 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1002 assert((Binary & ARMII::D_BitShift) == 0 &&
1003 (Binary & ARMII::N_BitShift) == 0 &&
1004 (Binary & ARMII::M_BitShift) == 0 && "VFP encoding bug!");
1007 unsigned RegD = getMachineOpValue(MI, OpIdx++);
1008 Binary |= (RegD & 0x0f) << ARMII::RegRdShift;
1009 Binary |= (RegD & 0x10) << ARMII::D_BitShift;
1011 // If this is a two-address operand, skip it, e.g. FMACD.
1012 if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
1016 if ((TID.TSFlags & ARMII::FormMask) == ARMII::VFPBinaryFrm) {
1017 unsigned RegN = getMachineOpValue(MI, OpIdx++);
1018 Binary |= (RegN & 0x0f) << ARMII::RegRnShift;
1019 Binary |= (RegN & 0x10) << ARMII::N_BitShift;
1023 unsigned RegM = getMachineOpValue(MI, OpIdx++);
1024 Binary |= (RegM & 0x0f);
1025 Binary |= (RegM & 0x10) << ARMII::M_BitShift;
1030 void ARMCodeEmitter::emitVFPConversionInstruction(const MachineInstr &MI) {
1031 const TargetInstrDesc &TID = MI.getDesc();
1033 // Part of binary is determined by TableGn.
1034 unsigned Binary = getBinaryCodeForInstr(MI);
1036 // Set the conditional execution predicate
1037 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1042 unsigned RegD = getMachineOpValue(MI, OpIdx++);
1043 Binary |= (RegD & 0x0f) << ARMII::RegRdShift;
1044 Binary |= (RegD & 0x10) << ARMII::D_BitShift;
1047 if ((TID.TSFlags & ARMII::FormMask) == ARMII::VFPConv1Frm) {
1048 unsigned RegN = getMachineOpValue(MI, OpIdx++);
1049 Binary |= (RegN & 0x0f) << ARMII::RegRnShift;
1050 Binary |= (RegN & 0x10) << ARMII::N_BitShift;
1052 // FMRS / FMSR do not have Rm.
1053 if (!TID.OpInfo[2].isPredicate()) {
1054 unsigned RegM = getMachineOpValue(MI, OpIdx++);
1055 Binary |= (RegM & 0x0f);
1056 Binary |= (RegM & 0x10) << ARMII::M_BitShift;
1059 unsigned RegM = getMachineOpValue(MI, OpIdx++);
1060 Binary |= (RegM & 0x0f);
1061 Binary |= (RegM & 0x10) << ARMII::M_BitShift;
1067 #include "ARMGenCodeEmitter.inc"