1 //===- ARMCallingConv.td - Calling Conventions for ARM ----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
9 // This describes the calling conventions for ARM architecture.
10 //===----------------------------------------------------------------------===//
12 /// CCIfSubtarget - Match if the current subtarget has a feature F.
13 class CCIfSubtarget<string F, CCAction A>:
14 CCIf<!strconcat("State.getTarget().getSubtarget<ARMSubtarget>().", F), A>;
16 /// CCIfAlign - Match of the original alignment of the arg
17 class CCIfAlign<string Align, CCAction A>:
18 CCIf<!strconcat("ArgFlags.getOrigAlign() == ", Align), A>;
20 //===----------------------------------------------------------------------===//
21 // ARM APCS Calling Convention
22 //===----------------------------------------------------------------------===//
23 def CC_ARM_APCS : CallingConv<[
25 CCIfType<[i8, i16], CCPromoteToType<i32>>,
27 // f64 is passed in pairs of GPRs, possibly split onto the stack
28 CCIfType<[f64], CCCustom<"CC_ARM_APCS_Custom_f64">>,
30 CCIfType<[f32], CCBitConvertToType<i32>>,
31 CCIfType<[i32], CCAssignToReg<[R0, R1, R2, R3]>>,
33 CCIfType<[i32], CCAssignToStack<4, 4>>,
34 CCIfType<[f64], CCAssignToStack<8, 4>>
37 def RetCC_ARM_APCS : CallingConv<[
38 CCIfType<[f32], CCBitConvertToType<i32>>,
39 CCIfType<[f64], CCCustom<"RetCC_ARM_APCS_Custom_f64">>,
41 CCIfType<[i32], CCAssignToReg<[R0, R1, R2, R3]>>,
42 CCIfType<[i64], CCAssignToRegWithShadow<[R0, R2], [R1, R3]>>
45 //===----------------------------------------------------------------------===//
46 // ARM AAPCS (EABI) Calling Convention
47 //===----------------------------------------------------------------------===//
48 def CC_ARM_AAPCS : CallingConv<[
50 CCIfType<[i8, i16], CCPromoteToType<i32>>,
52 // i64/f64 is passed in even pairs of GPRs
53 // i64 is 8-aligned i32 here, so we may need to eat R1 as a pad register
54 // (and the same is true for f64 if VFP is not enabled)
55 CCIfType<[i32], CCIfAlign<"8", CCAssignToRegWithShadow<[R0, R2], [R0, R1]>>>,
56 CCIfType<[f64], CCCustom<"CC_ARM_AAPCS_Custom_f64">>,
58 CCIfType<[f32], CCBitConvertToType<i32>>,
59 CCIfType<[i32], CCIf<"State.getNextStackOffset() == 0 &&"
60 "ArgFlags.getOrigAlign() != 8",
61 CCAssignToReg<[R0, R1, R2, R3]>>>,
63 CCIfType<[i32], CCAssignToStack<4, 4>>,
64 CCIfType<[f64], CCAssignToStack<8, 8>>
67 def RetCC_ARM_AAPCS : CallingConv<[
68 CCIfType<[f32], CCBitConvertToType<i32>>,
69 CCIfType<[f64], CCCustom<"RetCC_ARM_AAPCS_Custom_f64">>,
71 CCIfType<[i32], CCAssignToReg<[R0, R1, R2, R3]>>,
72 CCIfType<[i64], CCAssignToRegWithShadow<[R0, R2], [R1, R3]>>
75 //===----------------------------------------------------------------------===//
76 // ARM Calling Convention Dispatch
77 //===----------------------------------------------------------------------===//
79 def CC_ARM : CallingConv<[
80 CCIfSubtarget<"isAAPCS_ABI()", CCDelegateTo<CC_ARM_AAPCS>>,
81 CCDelegateTo<CC_ARM_APCS>
84 def RetCC_ARM : CallingConv<[
85 CCIfSubtarget<"isAAPCS_ABI()", CCDelegateTo<RetCC_ARM_AAPCS>>,
86 CCDelegateTo<RetCC_ARM_APCS>