1 //===- ARMBaseRegisterInfo.h - ARM Register Information Impl ----*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the base ARM implementation of TargetRegisterInfo class.
12 //===----------------------------------------------------------------------===//
14 #ifndef ARMBASEREGISTERINFO_H
15 #define ARMBASEREGISTERINFO_H
18 #include "llvm/Target/TargetRegisterInfo.h"
19 #include "ARMGenRegisterInfo.h.inc"
23 class ARMBaseInstrInfo;
26 /// Register allocation hints.
34 /// isARMLowRegister - Returns true if the register is low register r0-r7.
36 static inline bool isARMLowRegister(unsigned Reg) {
39 case R0: case R1: case R2: case R3:
40 case R4: case R5: case R6: case R7:
47 class ARMBaseRegisterInfo : public ARMGenRegisterInfo {
49 const ARMBaseInstrInfo &TII;
50 const ARMSubtarget &STI;
52 /// FramePtr - ARM physical register used as frame ptr.
55 /// BasePtr - ARM physical register used as a base ptr in complex stack
56 /// frames. I.e., when we need a 3rd base, not just SP and FP, due to
57 /// variable size stack objects.
60 // Can be only subclassed.
61 explicit ARMBaseRegisterInfo(const ARMBaseInstrInfo &tii,
62 const ARMSubtarget &STI);
64 // Return the opcode that implements 'Op', or 0 if no opcode
65 unsigned getOpcode(int Op) const;
68 /// getRegisterNumbering - Given the enum value for some register, e.g.
69 /// ARM::LR, return the number that it corresponds to (e.g. 14). It
70 /// also returns true in isSPVFP if the register is a single precision
72 static unsigned getRegisterNumbering(unsigned RegEnum, bool *isSPVFP = 0);
74 /// Code Generation virtual methods...
75 const unsigned *getCalleeSavedRegs(const MachineFunction *MF = 0) const;
77 BitVector getReservedRegs(const MachineFunction &MF) const;
79 /// getMatchingSuperRegClass - Return a subclass of the specified register
80 /// class A so that each register in it has a sub-register of the
81 /// specified sub-register index which is in the specified register class B.
82 virtual const TargetRegisterClass *
83 getMatchingSuperRegClass(const TargetRegisterClass *A,
84 const TargetRegisterClass *B, unsigned Idx) const;
86 /// canCombineSubRegIndices - Given a register class and a list of
87 /// subregister indices, return true if it's possible to combine the
88 /// subregister indices into one that corresponds to a larger
89 /// subregister. Return the new subregister index by reference. Note the
90 /// new index may be zero if the given subregisters can be combined to
91 /// form the whole register.
92 virtual bool canCombineSubRegIndices(const TargetRegisterClass *RC,
93 SmallVectorImpl<unsigned> &SubIndices,
94 unsigned &NewSubIdx) const;
96 const TargetRegisterClass *getPointerRegClass(unsigned Kind = 0) const;
98 std::pair<TargetRegisterClass::iterator,TargetRegisterClass::iterator>
99 getAllocationOrder(const TargetRegisterClass *RC,
100 unsigned HintType, unsigned HintReg,
101 const MachineFunction &MF) const;
103 unsigned ResolveRegAllocHint(unsigned Type, unsigned Reg,
104 const MachineFunction &MF) const;
106 void UpdateRegAllocHint(unsigned Reg, unsigned NewReg,
107 MachineFunction &MF) const;
109 bool hasFP(const MachineFunction &MF) const;
110 bool hasBasePointer(const MachineFunction &MF) const;
112 bool canRealignStack(const MachineFunction &MF) const;
113 bool needsStackRealignment(const MachineFunction &MF) const;
114 int64_t getFrameIndexInstrOffset(const MachineInstr *MI, int Idx) const;
115 bool needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const;
116 void materializeFrameBaseRegister(MachineBasicBlock::iterator I,
117 unsigned BaseReg, int FrameIdx,
118 int64_t Offset) const;
119 void resolveFrameIndex(MachineBasicBlock::iterator I,
120 unsigned BaseReg, int64_t Offset) const;
121 bool isFrameOffsetLegal(const MachineInstr *MI, int64_t Offset) const;
123 bool cannotEliminateFrame(const MachineFunction &MF) const;
125 void processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
126 RegScavenger *RS = NULL) const;
128 // Debug information queries.
129 unsigned getRARegister() const;
130 unsigned getFrameRegister(const MachineFunction &MF) const;
131 int getFrameIndexReference(const MachineFunction &MF, int FI,
132 unsigned &FrameReg) const;
133 int ResolveFrameIndexReference(const MachineFunction &MF, int FI,
134 unsigned &FrameReg, int SPAdj) const;
135 int getFrameIndexOffset(const MachineFunction &MF, int FI) const;
137 // Exception handling queries.
138 unsigned getEHExceptionRegister() const;
139 unsigned getEHHandlerRegister() const;
141 int getDwarfRegNum(unsigned RegNum, bool isEH) const;
143 bool isLowRegister(unsigned Reg) const;
146 /// emitLoadConstPool - Emits a load from constpool to materialize the
147 /// specified immediate.
148 virtual void emitLoadConstPool(MachineBasicBlock &MBB,
149 MachineBasicBlock::iterator &MBBI,
151 unsigned DestReg, unsigned SubIdx,
153 ARMCC::CondCodes Pred = ARMCC::AL,
154 unsigned PredReg = 0) const;
156 /// Code Generation virtual methods...
157 virtual bool isReservedReg(const MachineFunction &MF, unsigned Reg) const;
159 virtual bool requiresRegisterScavenging(const MachineFunction &MF) const;
161 virtual bool requiresFrameIndexScavenging(const MachineFunction &MF) const;
163 virtual bool requiresVirtualBaseRegisters(const MachineFunction &MF) const;
165 virtual bool hasReservedCallFrame(const MachineFunction &MF) const;
166 virtual bool canSimplifyCallFramePseudos(const MachineFunction &MF) const;
168 virtual void eliminateCallFramePseudoInstr(MachineFunction &MF,
169 MachineBasicBlock &MBB,
170 MachineBasicBlock::iterator I) const;
172 virtual void eliminateFrameIndex(MachineBasicBlock::iterator II,
173 int SPAdj, RegScavenger *RS = NULL) const;
175 virtual void emitPrologue(MachineFunction &MF) const;
176 virtual void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const;
179 unsigned estimateRSStackSizeLimit(MachineFunction &MF) const;
181 unsigned getRegisterPairEven(unsigned Reg, const MachineFunction &MF) const;
183 unsigned getRegisterPairOdd(unsigned Reg, const MachineFunction &MF) const;
186 } // end namespace llvm