1 //===- ARMBaseRegisterInfo.h - ARM Register Information Impl ----*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the base ARM implementation of TargetRegisterInfo class.
12 //===----------------------------------------------------------------------===//
14 #ifndef ARMBASEREGISTERINFO_H
15 #define ARMBASEREGISTERINFO_H
18 #include "llvm/Target/TargetRegisterInfo.h"
19 #include "ARMGenRegisterInfo.h.inc"
23 class ARMBaseInstrInfo;
26 /// Register allocation hints.
34 /// isARMLowRegister - Returns true if the register is low register r0-r7.
36 static inline bool isARMLowRegister(unsigned Reg) {
39 case R0: case R1: case R2: case R3:
40 case R4: case R5: case R6: case R7:
47 struct ARMBaseRegisterInfo : public ARMGenRegisterInfo {
49 const ARMBaseInstrInfo &TII;
50 const ARMSubtarget &STI;
52 /// FramePtr - ARM physical register used as frame ptr.
55 // Can be only subclassed.
56 explicit ARMBaseRegisterInfo(const ARMBaseInstrInfo &tii,
57 const ARMSubtarget &STI);
59 // Return the opcode that implements 'Op', or 0 if no opcode
60 unsigned getOpcode(int Op) const;
63 /// getRegisterNumbering - Given the enum value for some register, e.g.
64 /// ARM::LR, return the number that it corresponds to (e.g. 14). It
65 /// also returns true in isSPVFP if the register is a single precision
67 static unsigned getRegisterNumbering(unsigned RegEnum, bool *isSPVFP = 0);
69 /// Code Generation virtual methods...
70 const unsigned *getCalleeSavedRegs(const MachineFunction *MF = 0) const;
72 BitVector getReservedRegs(const MachineFunction &MF) const;
74 /// getMatchingSuperRegClass - Return a subclass of the specified register
75 /// class A so that each register in it has a sub-register of the
76 /// specified sub-register index which is in the specified register class B.
77 virtual const TargetRegisterClass *
78 getMatchingSuperRegClass(const TargetRegisterClass *A,
79 const TargetRegisterClass *B, unsigned Idx) const;
81 /// canCombineSubRegIndices - Given a register class and a list of
82 /// subregister indices, return true if it's possible to combine the
83 /// subregister indices into one that corresponds to a larger
84 /// subregister. Return the new subregister index by reference. Note the
85 /// new index may be zero if the given subregisters can be combined to
86 /// form the whole register.
87 virtual bool canCombineSubRegIndices(const TargetRegisterClass *RC,
88 SmallVectorImpl<unsigned> &SubIndices,
89 unsigned &NewSubIdx) const;
91 const TargetRegisterClass *getPointerRegClass(unsigned Kind = 0) const;
93 std::pair<TargetRegisterClass::iterator,TargetRegisterClass::iterator>
94 getAllocationOrder(const TargetRegisterClass *RC,
95 unsigned HintType, unsigned HintReg,
96 const MachineFunction &MF) const;
98 unsigned ResolveRegAllocHint(unsigned Type, unsigned Reg,
99 const MachineFunction &MF) const;
101 void UpdateRegAllocHint(unsigned Reg, unsigned NewReg,
102 MachineFunction &MF) const;
104 bool hasFP(const MachineFunction &MF) const;
106 bool canRealignStack(const MachineFunction &MF) const;
107 bool needsStackRealignment(const MachineFunction &MF) const;
109 bool cannotEliminateFrame(const MachineFunction &MF) const;
111 void processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
112 RegScavenger *RS = NULL) const;
114 // Debug information queries.
115 unsigned getRARegister() const;
116 unsigned getFrameRegister(const MachineFunction &MF) const;
117 int getFrameIndexReference(const MachineFunction &MF, int FI,
118 unsigned &FrameReg) const;
119 int getFrameIndexOffset(const MachineFunction &MF, int FI) const;
121 // Exception handling queries.
122 unsigned getEHExceptionRegister() const;
123 unsigned getEHHandlerRegister() const;
125 int getDwarfRegNum(unsigned RegNum, bool isEH) const;
127 bool isLowRegister(unsigned Reg) const;
130 /// emitLoadConstPool - Emits a load from constpool to materialize the
131 /// specified immediate.
132 virtual void emitLoadConstPool(MachineBasicBlock &MBB,
133 MachineBasicBlock::iterator &MBBI,
135 unsigned DestReg, unsigned SubIdx,
137 ARMCC::CondCodes Pred = ARMCC::AL,
138 unsigned PredReg = 0) const;
140 /// Code Generation virtual methods...
141 virtual bool isReservedReg(const MachineFunction &MF, unsigned Reg) const;
143 virtual bool requiresRegisterScavenging(const MachineFunction &MF) const;
145 virtual bool requiresFrameIndexScavenging(const MachineFunction &MF) const;
147 virtual bool hasReservedCallFrame(MachineFunction &MF) const;
148 virtual bool canSimplifyCallFramePseudos(MachineFunction &MF) const;
150 virtual void eliminateCallFramePseudoInstr(MachineFunction &MF,
151 MachineBasicBlock &MBB,
152 MachineBasicBlock::iterator I) const;
154 virtual unsigned eliminateFrameIndex(MachineBasicBlock::iterator II,
155 int SPAdj, FrameIndexValue *Value = NULL,
156 RegScavenger *RS = NULL) const;
158 virtual void emitPrologue(MachineFunction &MF) const;
159 virtual void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const;
162 unsigned estimateRSStackSizeLimit(MachineFunction &MF) const;
164 unsigned getRegisterPairEven(unsigned Reg, const MachineFunction &MF) const;
166 unsigned getRegisterPairOdd(unsigned Reg, const MachineFunction &MF) const;
169 } // end namespace llvm