1 //===- ARMBaseRegisterInfo.h - ARM Register Information Impl --------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the base ARM implementation of TargetRegisterInfo class.
12 //===----------------------------------------------------------------------===//
14 #ifndef ARMBASEREGISTERINFO_H
15 #define ARMBASEREGISTERINFO_H
18 #include "llvm/Target/TargetRegisterInfo.h"
19 #include "ARMGenRegisterInfo.h.inc"
23 class ARMBaseInstrInfo;
26 /// Register allocation hints.
34 /// isARMLowRegister - Returns true if the register is low register r0-r7.
36 static inline bool isARMLowRegister(unsigned Reg) {
39 case R0: case R1: case R2: case R3:
40 case R4: case R5: case R6: case R7:
47 struct ARMBaseRegisterInfo : public ARMGenRegisterInfo {
49 const ARMBaseInstrInfo &TII;
50 const ARMSubtarget &STI;
52 /// FramePtr - ARM physical register used as frame ptr.
55 // Can be only subclassed.
56 explicit ARMBaseRegisterInfo(const ARMBaseInstrInfo &tii,
57 const ARMSubtarget &STI);
59 // Return the opcode that implements 'Op', or 0 if no opcode
60 unsigned getOpcode(int Op) const;
62 // If 'opcode' is an instruction with an unsigned offset that also
63 // has a version with a signed offset, return the opcode for the
64 // version with the signed offset. In 'NumBits' return the number of
65 // bits for the signed offset.
66 unsigned unsignedOffsetOpcodeToSigned(unsigned opcode,
67 unsigned *NumBits) const;
70 /// getRegisterNumbering - Given the enum value for some register, e.g.
71 /// ARM::LR, return the number that it corresponds to (e.g. 14). It
72 /// also returns true in isSPVFP if the register is a single precision
74 static unsigned getRegisterNumbering(unsigned RegEnum, bool *isSPVFP = 0);
76 /// Code Generation virtual methods...
77 const unsigned *getCalleeSavedRegs(const MachineFunction *MF = 0) const;
79 const TargetRegisterClass* const*
80 getCalleeSavedRegClasses(const MachineFunction *MF = 0) const;
82 BitVector getReservedRegs(const MachineFunction &MF) const;
84 const TargetRegisterClass *getPointerRegClass() const;
86 std::pair<TargetRegisterClass::iterator,TargetRegisterClass::iterator>
87 getAllocationOrder(const TargetRegisterClass *RC,
88 unsigned HintType, unsigned HintReg,
89 const MachineFunction &MF) const;
91 unsigned ResolveRegAllocHint(unsigned Type, unsigned Reg,
92 const MachineFunction &MF) const;
94 void UpdateRegAllocHint(unsigned Reg, unsigned NewReg,
95 MachineFunction &MF) const;
97 bool hasFP(const MachineFunction &MF) const;
99 void processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
100 RegScavenger *RS = NULL) const;
102 // Debug information queries.
103 unsigned getRARegister() const;
104 unsigned getFrameRegister(MachineFunction &MF) const;
106 // Exception handling queries.
107 unsigned getEHExceptionRegister() const;
108 unsigned getEHHandlerRegister() const;
110 int getDwarfRegNum(unsigned RegNum, bool isEH) const;
112 bool isLowRegister(unsigned Reg) const;
115 /// emitLoadConstPool - Emits a load from constpool to materialize the
116 /// specified immediate.
117 virtual void emitLoadConstPool(MachineBasicBlock &MBB,
118 MachineBasicBlock::iterator &MBBI,
120 unsigned DestReg, unsigned SubIdx,
122 ARMCC::CondCodes Pred = ARMCC::AL,
123 unsigned PredReg = 0) const;
125 /// Code Generation virtual methods...
126 virtual bool isReservedReg(const MachineFunction &MF, unsigned Reg) const;
128 virtual bool requiresRegisterScavenging(const MachineFunction &MF) const;
130 virtual bool hasReservedCallFrame(MachineFunction &MF) const;
132 virtual void eliminateCallFramePseudoInstr(MachineFunction &MF,
133 MachineBasicBlock &MBB,
134 MachineBasicBlock::iterator I) const;
136 virtual void eliminateFrameIndex(MachineBasicBlock::iterator II,
137 int SPAdj, RegScavenger *RS = NULL) const;
139 virtual void emitPrologue(MachineFunction &MF) const;
140 virtual void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const;
143 unsigned getRegisterPairEven(unsigned Reg, const MachineFunction &MF) const;
145 unsigned getRegisterPairOdd(unsigned Reg, const MachineFunction &MF) const;
148 } // end namespace llvm