1 //===-- ARMBaseRegisterInfo.h - ARM Register Information Impl ---*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the base ARM implementation of TargetRegisterInfo class.
12 //===----------------------------------------------------------------------===//
14 #ifndef ARMBASEREGISTERINFO_H
15 #define ARMBASEREGISTERINFO_H
18 #include "llvm/Target/TargetRegisterInfo.h"
20 #define GET_REGINFO_HEADER
21 #include "ARMGenRegisterInfo.inc"
25 class ARMBaseInstrInfo;
28 /// Register allocation hints.
36 /// isARMArea1Register - Returns true if the register is a low register (r0-r7)
37 /// or a stack/pc register that we should push/pop.
38 static inline bool isARMArea1Register(unsigned Reg, bool isIOS) {
41 case R0: case R1: case R2: case R3:
42 case R4: case R5: case R6: case R7:
43 case LR: case SP: case PC:
45 case R8: case R9: case R10: case R11:
46 // For iOS we want r7 and lr to be next to each other.
53 static inline bool isARMArea2Register(unsigned Reg, bool isIOS) {
56 case R8: case R9: case R10: case R11:
57 // iOS has this second area.
64 static inline bool isARMArea3Register(unsigned Reg, bool isIOS) {
67 case D15: case D14: case D13: case D12:
68 case D11: case D10: case D9: case D8:
75 class ARMBaseRegisterInfo : public ARMGenRegisterInfo {
77 const ARMSubtarget &STI;
79 /// FramePtr - ARM physical register used as frame ptr.
82 /// BasePtr - ARM physical register used as a base ptr in complex stack
83 /// frames. I.e., when we need a 3rd base, not just SP and FP, due to
84 /// variable size stack objects.
87 // Can be only subclassed.
88 explicit ARMBaseRegisterInfo(const ARMSubtarget &STI);
90 // Return the opcode that implements 'Op', or 0 if no opcode
91 unsigned getOpcode(int Op) const;
94 /// Code Generation virtual methods...
95 const uint16_t *getCalleeSavedRegs(const MachineFunction *MF = 0) const;
96 const uint32_t *getCallPreservedMask(CallingConv::ID) const;
97 const uint32_t *getThisReturnPreservedMask(CallingConv::ID) const;
98 const uint32_t *getNoPreservedMask() const;
100 BitVector getReservedRegs(const MachineFunction &MF) const;
102 const TargetRegisterClass*
103 getPointerRegClass(const MachineFunction &MF, unsigned Kind = 0) const;
104 const TargetRegisterClass*
105 getCrossCopyRegClass(const TargetRegisterClass *RC) const;
107 const TargetRegisterClass*
108 getLargestLegalSuperClass(const TargetRegisterClass *RC) const;
110 unsigned getRegPressureLimit(const TargetRegisterClass *RC,
111 MachineFunction &MF) const;
113 void getRegAllocationHints(unsigned VirtReg,
114 ArrayRef<MCPhysReg> Order,
115 SmallVectorImpl<MCPhysReg> &Hints,
116 const MachineFunction &MF,
117 const VirtRegMap *VRM) const;
119 void UpdateRegAllocHint(unsigned Reg, unsigned NewReg,
120 MachineFunction &MF) const;
122 virtual bool avoidWriteAfterWrite(const TargetRegisterClass *RC) const;
124 bool hasBasePointer(const MachineFunction &MF) const;
126 bool canRealignStack(const MachineFunction &MF) const;
127 bool needsStackRealignment(const MachineFunction &MF) const;
128 int64_t getFrameIndexInstrOffset(const MachineInstr *MI, int Idx) const;
129 bool needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const;
130 void materializeFrameBaseRegister(MachineBasicBlock *MBB,
131 unsigned BaseReg, int FrameIdx,
132 int64_t Offset) const;
133 void resolveFrameIndex(MachineBasicBlock::iterator I,
134 unsigned BaseReg, int64_t Offset) const;
135 bool isFrameOffsetLegal(const MachineInstr *MI, int64_t Offset) const;
137 bool cannotEliminateFrame(const MachineFunction &MF) const;
139 // Debug information queries.
140 unsigned getFrameRegister(const MachineFunction &MF) const;
141 unsigned getBaseRegister() const { return BasePtr; }
143 // Exception handling queries.
144 unsigned getEHExceptionRegister() const;
145 unsigned getEHHandlerRegister() const;
147 bool isLowRegister(unsigned Reg) const;
150 /// emitLoadConstPool - Emits a load from constpool to materialize the
151 /// specified immediate.
152 virtual void emitLoadConstPool(MachineBasicBlock &MBB,
153 MachineBasicBlock::iterator &MBBI,
155 unsigned DestReg, unsigned SubIdx,
157 ARMCC::CondCodes Pred = ARMCC::AL,
158 unsigned PredReg = 0,
159 unsigned MIFlags = MachineInstr::NoFlags)const;
161 /// Code Generation virtual methods...
162 virtual bool requiresRegisterScavenging(const MachineFunction &MF) const;
164 virtual bool trackLivenessAfterRegAlloc(const MachineFunction &MF) const;
166 virtual bool requiresFrameIndexScavenging(const MachineFunction &MF) const;
168 virtual bool requiresVirtualBaseRegisters(const MachineFunction &MF) const;
170 virtual void eliminateFrameIndex(MachineBasicBlock::iterator II,
171 int SPAdj, unsigned FIOperandNum,
172 RegScavenger *RS = NULL) const;
175 } // end namespace llvm