1 //===- ARMBaseRegisterInfo.cpp - ARM Register Information -------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the base ARM implementation of TargetRegisterInfo class.
12 //===----------------------------------------------------------------------===//
15 #include "ARMAddressingModes.h"
16 #include "ARMBaseInstrInfo.h"
17 #include "ARMBaseRegisterInfo.h"
18 #include "ARMInstrInfo.h"
19 #include "ARMMachineFunctionInfo.h"
20 #include "ARMSubtarget.h"
21 #include "llvm/Constants.h"
22 #include "llvm/DerivedTypes.h"
23 #include "llvm/Function.h"
24 #include "llvm/LLVMContext.h"
25 #include "llvm/CodeGen/MachineConstantPool.h"
26 #include "llvm/CodeGen/MachineFrameInfo.h"
27 #include "llvm/CodeGen/MachineFunction.h"
28 #include "llvm/CodeGen/MachineInstrBuilder.h"
29 #include "llvm/CodeGen/MachineLocation.h"
30 #include "llvm/CodeGen/MachineRegisterInfo.h"
31 #include "llvm/CodeGen/RegisterScavenging.h"
32 #include "llvm/Support/Debug.h"
33 #include "llvm/Support/ErrorHandling.h"
34 #include "llvm/Support/raw_ostream.h"
35 #include "llvm/Target/TargetFrameInfo.h"
36 #include "llvm/Target/TargetMachine.h"
37 #include "llvm/Target/TargetOptions.h"
38 #include "llvm/ADT/BitVector.h"
39 #include "llvm/ADT/SmallVector.h"
40 #include "llvm/Support/CommandLine.h"
44 ReuseFrameIndexVals("arm-reuse-frame-index-vals", cl::Hidden, cl::init(true),
45 cl::desc("Reuse repeated frame index values"));
47 ForceAllBaseRegAlloc("arm-force-base-reg-alloc", cl::Hidden, cl::init(true),
48 cl::desc("Force use of virtual base registers for stack load/store"));
53 unsigned ARMBaseRegisterInfo::getRegisterNumbering(unsigned RegEnum,
61 llvm_unreachable("Unknown ARM register!");
62 case R0: case D0: case Q0: return 0;
63 case R1: case D1: case Q1: return 1;
64 case R2: case D2: case Q2: return 2;
65 case R3: case D3: case Q3: return 3;
66 case R4: case D4: case Q4: return 4;
67 case R5: case D5: case Q5: return 5;
68 case R6: case D6: case Q6: return 6;
69 case R7: case D7: case Q7: return 7;
70 case R8: case D8: case Q8: return 8;
71 case R9: case D9: case Q9: return 9;
72 case R10: case D10: case Q10: return 10;
73 case R11: case D11: case Q11: return 11;
74 case R12: case D12: case Q12: return 12;
75 case SP: case D13: case Q13: return 13;
76 case LR: case D14: case Q14: return 14;
77 case PC: case D15: case Q15: return 15;
96 case S0: case S1: case S2: case S3:
97 case S4: case S5: case S6: case S7:
98 case S8: case S9: case S10: case S11:
99 case S12: case S13: case S14: case S15:
100 case S16: case S17: case S18: case S19:
101 case S20: case S21: case S22: case S23:
102 case S24: case S25: case S26: case S27:
103 case S28: case S29: case S30: case S31: {
107 default: return 0; // Avoid compile time warning.
145 ARMBaseRegisterInfo::ARMBaseRegisterInfo(const ARMBaseInstrInfo &tii,
146 const ARMSubtarget &sti)
147 : ARMGenRegisterInfo(ARM::ADJCALLSTACKDOWN, ARM::ADJCALLSTACKUP),
149 FramePtr((STI.isTargetDarwin() || STI.isThumb()) ? ARM::R7 : ARM::R11) {
153 ARMBaseRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
154 static const unsigned CalleeSavedRegs[] = {
155 ARM::LR, ARM::R11, ARM::R10, ARM::R9, ARM::R8,
156 ARM::R7, ARM::R6, ARM::R5, ARM::R4,
158 ARM::D15, ARM::D14, ARM::D13, ARM::D12,
159 ARM::D11, ARM::D10, ARM::D9, ARM::D8,
163 static const unsigned DarwinCalleeSavedRegs[] = {
164 // Darwin ABI deviates from ARM standard ABI. R9 is not a callee-saved
166 ARM::LR, ARM::R7, ARM::R6, ARM::R5, ARM::R4,
167 ARM::R11, ARM::R10, ARM::R8,
169 ARM::D15, ARM::D14, ARM::D13, ARM::D12,
170 ARM::D11, ARM::D10, ARM::D9, ARM::D8,
173 return STI.isTargetDarwin() ? DarwinCalleeSavedRegs : CalleeSavedRegs;
176 BitVector ARMBaseRegisterInfo::
177 getReservedRegs(const MachineFunction &MF) const {
178 // FIXME: avoid re-calculating this everytime.
179 BitVector Reserved(getNumRegs());
180 Reserved.set(ARM::SP);
181 Reserved.set(ARM::PC);
182 Reserved.set(ARM::FPSCR);
184 Reserved.set(FramePtr);
185 // Some targets reserve R9.
186 if (STI.isR9Reserved())
187 Reserved.set(ARM::R9);
191 bool ARMBaseRegisterInfo::isReservedReg(const MachineFunction &MF,
192 unsigned Reg) const {
200 if (FramePtr == Reg && hasFP(MF))
204 return STI.isR9Reserved();
210 const TargetRegisterClass *
211 ARMBaseRegisterInfo::getMatchingSuperRegClass(const TargetRegisterClass *A,
212 const TargetRegisterClass *B,
213 unsigned SubIdx) const {
221 if (A->getSize() == 8) {
222 if (B == &ARM::SPR_8RegClass)
223 return &ARM::DPR_8RegClass;
224 assert(B == &ARM::SPRRegClass && "Expecting SPR register class!");
225 if (A == &ARM::DPR_8RegClass)
227 return &ARM::DPR_VFP2RegClass;
230 if (A->getSize() == 16) {
231 if (B == &ARM::SPR_8RegClass)
232 return &ARM::QPR_8RegClass;
233 return &ARM::QPR_VFP2RegClass;
236 if (A->getSize() == 32) {
237 if (B == &ARM::SPR_8RegClass)
238 return 0; // Do not allow coalescing!
239 return &ARM::QQPR_VFP2RegClass;
242 assert(A->getSize() == 64 && "Expecting a QQQQ register class!");
243 return 0; // Do not allow coalescing!
250 if (A->getSize() == 16) {
251 if (B == &ARM::DPR_VFP2RegClass)
252 return &ARM::QPR_VFP2RegClass;
253 if (B == &ARM::DPR_8RegClass)
254 return 0; // Do not allow coalescing!
258 if (A->getSize() == 32) {
259 if (B == &ARM::DPR_VFP2RegClass)
260 return &ARM::QQPR_VFP2RegClass;
261 if (B == &ARM::DPR_8RegClass)
262 return 0; // Do not allow coalescing!
266 assert(A->getSize() == 64 && "Expecting a QQQQ register class!");
267 if (B != &ARM::DPRRegClass)
268 return 0; // Do not allow coalescing!
275 // D sub-registers of QQQQ registers.
276 if (A->getSize() == 64 && B == &ARM::DPRRegClass)
278 return 0; // Do not allow coalescing!
284 if (A->getSize() == 32) {
285 if (B == &ARM::QPR_VFP2RegClass)
286 return &ARM::QQPR_VFP2RegClass;
287 if (B == &ARM::QPR_8RegClass)
288 return 0; // Do not allow coalescing!
292 assert(A->getSize() == 64 && "Expecting a QQQQ register class!");
293 if (B == &ARM::QPRRegClass)
295 return 0; // Do not allow coalescing!
299 // Q sub-registers of QQQQ registers.
300 if (A->getSize() == 64 && B == &ARM::QPRRegClass)
302 return 0; // Do not allow coalescing!
309 ARMBaseRegisterInfo::canCombineSubRegIndices(const TargetRegisterClass *RC,
310 SmallVectorImpl<unsigned> &SubIndices,
311 unsigned &NewSubIdx) const {
313 unsigned Size = RC->getSize() * 8;
317 NewSubIdx = 0; // Whole register.
318 unsigned NumRegs = SubIndices.size();
320 // 8 D registers -> 1 QQQQ register.
321 return (Size == 512 &&
322 SubIndices[0] == ARM::dsub_0 &&
323 SubIndices[1] == ARM::dsub_1 &&
324 SubIndices[2] == ARM::dsub_2 &&
325 SubIndices[3] == ARM::dsub_3 &&
326 SubIndices[4] == ARM::dsub_4 &&
327 SubIndices[5] == ARM::dsub_5 &&
328 SubIndices[6] == ARM::dsub_6 &&
329 SubIndices[7] == ARM::dsub_7);
330 } else if (NumRegs == 4) {
331 if (SubIndices[0] == ARM::qsub_0) {
332 // 4 Q registers -> 1 QQQQ register.
333 return (Size == 512 &&
334 SubIndices[1] == ARM::qsub_1 &&
335 SubIndices[2] == ARM::qsub_2 &&
336 SubIndices[3] == ARM::qsub_3);
337 } else if (SubIndices[0] == ARM::dsub_0) {
338 // 4 D registers -> 1 QQ register.
340 SubIndices[1] == ARM::dsub_1 &&
341 SubIndices[2] == ARM::dsub_2 &&
342 SubIndices[3] == ARM::dsub_3) {
344 NewSubIdx = ARM::qqsub_0;
347 } else if (SubIndices[0] == ARM::dsub_4) {
348 // 4 D registers -> 1 QQ register (2nd).
350 SubIndices[1] == ARM::dsub_5 &&
351 SubIndices[2] == ARM::dsub_6 &&
352 SubIndices[3] == ARM::dsub_7) {
353 NewSubIdx = ARM::qqsub_1;
356 } else if (SubIndices[0] == ARM::ssub_0) {
357 // 4 S registers -> 1 Q register.
359 SubIndices[1] == ARM::ssub_1 &&
360 SubIndices[2] == ARM::ssub_2 &&
361 SubIndices[3] == ARM::ssub_3) {
363 NewSubIdx = ARM::qsub_0;
367 } else if (NumRegs == 2) {
368 if (SubIndices[0] == ARM::qsub_0) {
369 // 2 Q registers -> 1 QQ register.
370 if (Size >= 256 && SubIndices[1] == ARM::qsub_1) {
372 NewSubIdx = ARM::qqsub_0;
375 } else if (SubIndices[0] == ARM::qsub_2) {
376 // 2 Q registers -> 1 QQ register (2nd).
377 if (Size == 512 && SubIndices[1] == ARM::qsub_3) {
378 NewSubIdx = ARM::qqsub_1;
381 } else if (SubIndices[0] == ARM::dsub_0) {
382 // 2 D registers -> 1 Q register.
383 if (Size >= 128 && SubIndices[1] == ARM::dsub_1) {
385 NewSubIdx = ARM::qsub_0;
388 } else if (SubIndices[0] == ARM::dsub_2) {
389 // 2 D registers -> 1 Q register (2nd).
390 if (Size >= 256 && SubIndices[1] == ARM::dsub_3) {
391 NewSubIdx = ARM::qsub_1;
394 } else if (SubIndices[0] == ARM::dsub_4) {
395 // 2 D registers -> 1 Q register (3rd).
396 if (Size == 512 && SubIndices[1] == ARM::dsub_5) {
397 NewSubIdx = ARM::qsub_2;
400 } else if (SubIndices[0] == ARM::dsub_6) {
401 // 2 D registers -> 1 Q register (3rd).
402 if (Size == 512 && SubIndices[1] == ARM::dsub_7) {
403 NewSubIdx = ARM::qsub_3;
406 } else if (SubIndices[0] == ARM::ssub_0) {
407 // 2 S registers -> 1 D register.
408 if (SubIndices[1] == ARM::ssub_1) {
410 NewSubIdx = ARM::dsub_0;
413 } else if (SubIndices[0] == ARM::ssub_2) {
414 // 2 S registers -> 1 D register (2nd).
415 if (Size >= 128 && SubIndices[1] == ARM::ssub_3) {
416 NewSubIdx = ARM::dsub_1;
425 const TargetRegisterClass *
426 ARMBaseRegisterInfo::getPointerRegClass(unsigned Kind) const {
427 return ARM::GPRRegisterClass;
430 /// getAllocationOrder - Returns the register allocation order for a specified
431 /// register class in the form of a pair of TargetRegisterClass iterators.
432 std::pair<TargetRegisterClass::iterator,TargetRegisterClass::iterator>
433 ARMBaseRegisterInfo::getAllocationOrder(const TargetRegisterClass *RC,
434 unsigned HintType, unsigned HintReg,
435 const MachineFunction &MF) const {
436 // Alternative register allocation orders when favoring even / odd registers
437 // of register pairs.
439 // No FP, R9 is available.
440 static const unsigned GPREven1[] = {
441 ARM::R0, ARM::R2, ARM::R4, ARM::R6, ARM::R8, ARM::R10,
442 ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R7,
445 static const unsigned GPROdd1[] = {
446 ARM::R1, ARM::R3, ARM::R5, ARM::R7, ARM::R9, ARM::R11,
447 ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6,
451 // FP is R7, R9 is available.
452 static const unsigned GPREven2[] = {
453 ARM::R0, ARM::R2, ARM::R4, ARM::R8, ARM::R10,
454 ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R6,
457 static const unsigned GPROdd2[] = {
458 ARM::R1, ARM::R3, ARM::R5, ARM::R9, ARM::R11,
459 ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6,
463 // FP is R11, R9 is available.
464 static const unsigned GPREven3[] = {
465 ARM::R0, ARM::R2, ARM::R4, ARM::R6, ARM::R8,
466 ARM::R1, ARM::R3, ARM::R10,ARM::R12,ARM::LR, ARM::R5, ARM::R7,
469 static const unsigned GPROdd3[] = {
470 ARM::R1, ARM::R3, ARM::R5, ARM::R6, ARM::R9,
471 ARM::R0, ARM::R2, ARM::R10,ARM::R12,ARM::LR, ARM::R4, ARM::R7,
475 // No FP, R9 is not available.
476 static const unsigned GPREven4[] = {
477 ARM::R0, ARM::R2, ARM::R4, ARM::R6, ARM::R10,
478 ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R7, ARM::R8,
481 static const unsigned GPROdd4[] = {
482 ARM::R1, ARM::R3, ARM::R5, ARM::R7, ARM::R11,
483 ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6, ARM::R8,
487 // FP is R7, R9 is not available.
488 static const unsigned GPREven5[] = {
489 ARM::R0, ARM::R2, ARM::R4, ARM::R10,
490 ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R6, ARM::R8,
493 static const unsigned GPROdd5[] = {
494 ARM::R1, ARM::R3, ARM::R5, ARM::R11,
495 ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6, ARM::R8,
499 // FP is R11, R9 is not available.
500 static const unsigned GPREven6[] = {
501 ARM::R0, ARM::R2, ARM::R4, ARM::R6,
502 ARM::R1, ARM::R3, ARM::R10,ARM::R12,ARM::LR, ARM::R5, ARM::R7, ARM::R8
504 static const unsigned GPROdd6[] = {
505 ARM::R1, ARM::R3, ARM::R5, ARM::R7,
506 ARM::R0, ARM::R2, ARM::R10,ARM::R12,ARM::LR, ARM::R4, ARM::R6, ARM::R8
510 if (HintType == ARMRI::RegPairEven) {
511 if (isPhysicalRegister(HintReg) && getRegisterPairEven(HintReg, MF) == 0)
512 // It's no longer possible to fulfill this hint. Return the default
514 return std::make_pair(RC->allocation_order_begin(MF),
515 RC->allocation_order_end(MF));
518 if (!STI.isR9Reserved())
519 return std::make_pair(GPREven1,
520 GPREven1 + (sizeof(GPREven1)/sizeof(unsigned)));
522 return std::make_pair(GPREven4,
523 GPREven4 + (sizeof(GPREven4)/sizeof(unsigned)));
524 } else if (FramePtr == ARM::R7) {
525 if (!STI.isR9Reserved())
526 return std::make_pair(GPREven2,
527 GPREven2 + (sizeof(GPREven2)/sizeof(unsigned)));
529 return std::make_pair(GPREven5,
530 GPREven5 + (sizeof(GPREven5)/sizeof(unsigned)));
531 } else { // FramePtr == ARM::R11
532 if (!STI.isR9Reserved())
533 return std::make_pair(GPREven3,
534 GPREven3 + (sizeof(GPREven3)/sizeof(unsigned)));
536 return std::make_pair(GPREven6,
537 GPREven6 + (sizeof(GPREven6)/sizeof(unsigned)));
539 } else if (HintType == ARMRI::RegPairOdd) {
540 if (isPhysicalRegister(HintReg) && getRegisterPairOdd(HintReg, MF) == 0)
541 // It's no longer possible to fulfill this hint. Return the default
543 return std::make_pair(RC->allocation_order_begin(MF),
544 RC->allocation_order_end(MF));
547 if (!STI.isR9Reserved())
548 return std::make_pair(GPROdd1,
549 GPROdd1 + (sizeof(GPROdd1)/sizeof(unsigned)));
551 return std::make_pair(GPROdd4,
552 GPROdd4 + (sizeof(GPROdd4)/sizeof(unsigned)));
553 } else if (FramePtr == ARM::R7) {
554 if (!STI.isR9Reserved())
555 return std::make_pair(GPROdd2,
556 GPROdd2 + (sizeof(GPROdd2)/sizeof(unsigned)));
558 return std::make_pair(GPROdd5,
559 GPROdd5 + (sizeof(GPROdd5)/sizeof(unsigned)));
560 } else { // FramePtr == ARM::R11
561 if (!STI.isR9Reserved())
562 return std::make_pair(GPROdd3,
563 GPROdd3 + (sizeof(GPROdd3)/sizeof(unsigned)));
565 return std::make_pair(GPROdd6,
566 GPROdd6 + (sizeof(GPROdd6)/sizeof(unsigned)));
569 return std::make_pair(RC->allocation_order_begin(MF),
570 RC->allocation_order_end(MF));
573 /// ResolveRegAllocHint - Resolves the specified register allocation hint
574 /// to a physical register. Returns the physical register if it is successful.
576 ARMBaseRegisterInfo::ResolveRegAllocHint(unsigned Type, unsigned Reg,
577 const MachineFunction &MF) const {
578 if (Reg == 0 || !isPhysicalRegister(Reg))
582 else if (Type == (unsigned)ARMRI::RegPairOdd)
584 return getRegisterPairOdd(Reg, MF);
585 else if (Type == (unsigned)ARMRI::RegPairEven)
587 return getRegisterPairEven(Reg, MF);
592 ARMBaseRegisterInfo::UpdateRegAllocHint(unsigned Reg, unsigned NewReg,
593 MachineFunction &MF) const {
594 MachineRegisterInfo *MRI = &MF.getRegInfo();
595 std::pair<unsigned, unsigned> Hint = MRI->getRegAllocationHint(Reg);
596 if ((Hint.first == (unsigned)ARMRI::RegPairOdd ||
597 Hint.first == (unsigned)ARMRI::RegPairEven) &&
598 Hint.second && TargetRegisterInfo::isVirtualRegister(Hint.second)) {
599 // If 'Reg' is one of the even / odd register pair and it's now changed
600 // (e.g. coalesced) into a different register. The other register of the
601 // pair allocation hint must be updated to reflect the relationship
603 unsigned OtherReg = Hint.second;
604 Hint = MRI->getRegAllocationHint(OtherReg);
605 if (Hint.second == Reg)
606 // Make sure the pair has not already divorced.
607 MRI->setRegAllocationHint(OtherReg, Hint.first, NewReg);
611 /// hasFP - Return true if the specified function should have a dedicated frame
612 /// pointer register. This is true if the function has variable sized allocas
613 /// or if frame pointer elimination is disabled.
615 bool ARMBaseRegisterInfo::hasFP(const MachineFunction &MF) const {
616 // Mac OS X requires FP not to be clobbered for backtracing purpose.
617 if (STI.isTargetDarwin())
620 const MachineFrameInfo *MFI = MF.getFrameInfo();
621 // Always eliminate non-leaf frame pointers.
622 return ((DisableFramePointerElim(MF) && MFI->hasCalls()) ||
623 needsStackRealignment(MF) ||
624 MFI->hasVarSizedObjects() ||
625 MFI->isFrameAddressTaken());
628 bool ARMBaseRegisterInfo::canRealignStack(const MachineFunction &MF) const {
629 const MachineFrameInfo *MFI = MF.getFrameInfo();
630 const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
631 return (RealignStack &&
632 !AFI->isThumb1OnlyFunction() &&
633 !MFI->hasVarSizedObjects());
636 bool ARMBaseRegisterInfo::
637 needsStackRealignment(const MachineFunction &MF) const {
638 const MachineFrameInfo *MFI = MF.getFrameInfo();
639 const Function *F = MF.getFunction();
640 const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
641 unsigned StackAlign = MF.getTarget().getFrameInfo()->getStackAlignment();
642 bool requiresRealignment = ((MFI->getMaxAlignment() > StackAlign) ||
643 F->hasFnAttr(Attribute::StackAlignment));
645 // FIXME: Currently we don't support stack realignment for functions with
646 // variable-sized allocas.
647 // FIXME: It's more complicated than this...
648 if (0 && requiresRealignment && MFI->hasVarSizedObjects())
650 "Stack realignment in presense of dynamic allocas is not supported");
652 // FIXME: This probably isn't the right place for this.
653 if (0 && requiresRealignment && AFI->isThumb1OnlyFunction())
655 "Stack realignment in thumb1 functions is not supported");
657 return requiresRealignment && canRealignStack(MF);
660 bool ARMBaseRegisterInfo::
661 cannotEliminateFrame(const MachineFunction &MF) const {
662 const MachineFrameInfo *MFI = MF.getFrameInfo();
663 if (DisableFramePointerElim(MF) && MFI->adjustsStack())
665 return MFI->hasVarSizedObjects() || MFI->isFrameAddressTaken()
666 || needsStackRealignment(MF);
669 /// estimateStackSize - Estimate and return the size of the frame.
670 static unsigned estimateStackSize(MachineFunction &MF) {
671 const MachineFrameInfo *FFI = MF.getFrameInfo();
673 for (int i = FFI->getObjectIndexBegin(); i != 0; ++i) {
674 int FixedOff = -FFI->getObjectOffset(i);
675 if (FixedOff > Offset) Offset = FixedOff;
677 for (unsigned i = 0, e = FFI->getObjectIndexEnd(); i != e; ++i) {
678 if (FFI->isDeadObjectIndex(i))
680 Offset += FFI->getObjectSize(i);
681 unsigned Align = FFI->getObjectAlignment(i);
682 // Adjust to alignment boundary
683 Offset = (Offset+Align-1)/Align*Align;
685 return (unsigned)Offset;
688 /// estimateRSStackSizeLimit - Look at each instruction that references stack
689 /// frames and return the stack size limit beyond which some of these
690 /// instructions will require a scratch register during their expansion later.
692 ARMBaseRegisterInfo::estimateRSStackSizeLimit(MachineFunction &MF) const {
693 const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
694 unsigned Limit = (1 << 12) - 1;
695 for (MachineFunction::iterator BB = MF.begin(),E = MF.end(); BB != E; ++BB) {
696 for (MachineBasicBlock::iterator I = BB->begin(), E = BB->end();
698 for (unsigned i = 0, e = I->getNumOperands(); i != e; ++i) {
699 if (!I->getOperand(i).isFI()) continue;
701 // When using ADDri to get the address of a stack object, 255 is the
702 // largest offset guaranteed to fit in the immediate offset.
703 if (I->getOpcode() == ARM::ADDri) {
704 Limit = std::min(Limit, (1U << 8) - 1);
708 // Otherwise check the addressing mode.
709 switch (I->getDesc().TSFlags & ARMII::AddrModeMask) {
710 case ARMII::AddrMode3:
711 case ARMII::AddrModeT2_i8:
712 Limit = std::min(Limit, (1U << 8) - 1);
714 case ARMII::AddrMode5:
715 case ARMII::AddrModeT2_i8s4:
716 Limit = std::min(Limit, ((1U << 8) - 1) * 4);
718 case ARMII::AddrModeT2_i12:
719 // i12 supports only positive offset so these will be converted to
720 // i8 opcodes. See llvm::rewriteT2FrameIndex.
721 if (hasFP(MF) && AFI->hasStackFrame())
722 Limit = std::min(Limit, (1U << 8) - 1);
724 case ARMII::AddrMode6:
725 // Addressing mode 6 (load/store) instructions can't encode an
726 // immediate offset for stack references.
731 break; // At most one FI per instruction
739 static unsigned GetFunctionSizeInBytes(const MachineFunction &MF,
740 const ARMBaseInstrInfo &TII) {
742 for (MachineFunction::const_iterator MBBI = MF.begin(), E = MF.end();
744 const MachineBasicBlock &MBB = *MBBI;
745 for (MachineBasicBlock::const_iterator I = MBB.begin(),E = MBB.end();
747 FnSize += TII.GetInstSizeInBytes(I);
753 ARMBaseRegisterInfo::processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
754 RegScavenger *RS) const {
755 // This tells PEI to spill the FP as if it is any other callee-save register
756 // to take advantage the eliminateFrameIndex machinery. This also ensures it
757 // is spilled in the order specified by getCalleeSavedRegs() to make it easier
758 // to combine multiple loads / stores.
759 bool CanEliminateFrame = true;
760 bool CS1Spilled = false;
761 bool LRSpilled = false;
762 unsigned NumGPRSpills = 0;
763 SmallVector<unsigned, 4> UnspilledCS1GPRs;
764 SmallVector<unsigned, 4> UnspilledCS2GPRs;
765 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
766 MachineFrameInfo *MFI = MF.getFrameInfo();
768 // Spill R4 if Thumb2 function requires stack realignment - it will be used as
770 // FIXME: It will be better just to find spare register here.
771 if (needsStackRealignment(MF) &&
772 AFI->isThumb2Function())
773 MF.getRegInfo().setPhysRegUsed(ARM::R4);
775 // Spill LR if Thumb1 function uses variable length argument lists.
776 if (AFI->isThumb1OnlyFunction() && AFI->getVarArgsRegSaveSize() > 0)
777 MF.getRegInfo().setPhysRegUsed(ARM::LR);
779 // Don't spill FP if the frame can be eliminated. This is determined
780 // by scanning the callee-save registers to see if any is used.
781 const unsigned *CSRegs = getCalleeSavedRegs();
782 for (unsigned i = 0; CSRegs[i]; ++i) {
783 unsigned Reg = CSRegs[i];
784 bool Spilled = false;
785 if (MF.getRegInfo().isPhysRegUsed(Reg)) {
786 AFI->setCSRegisterIsSpilled(Reg);
788 CanEliminateFrame = false;
790 // Check alias registers too.
791 for (const unsigned *Aliases = getAliasSet(Reg); *Aliases; ++Aliases) {
792 if (MF.getRegInfo().isPhysRegUsed(*Aliases)) {
794 CanEliminateFrame = false;
799 if (!ARM::GPRRegisterClass->contains(Reg))
805 if (!STI.isTargetDarwin()) {
812 // Keep track if LR and any of R4, R5, R6, and R7 is spilled.
827 if (!STI.isTargetDarwin()) {
828 UnspilledCS1GPRs.push_back(Reg);
838 UnspilledCS1GPRs.push_back(Reg);
841 UnspilledCS2GPRs.push_back(Reg);
847 bool ForceLRSpill = false;
848 if (!LRSpilled && AFI->isThumb1OnlyFunction()) {
849 unsigned FnSize = GetFunctionSizeInBytes(MF, TII);
850 // Force LR to be spilled if the Thumb function size is > 2048. This enables
851 // use of BL to implement far jump. If it turns out that it's not needed
852 // then the branch fix up path will undo it.
853 if (FnSize >= (1 << 11)) {
854 CanEliminateFrame = false;
859 // If any of the stack slot references may be out of range of an immediate
860 // offset, make sure a register (or a spill slot) is available for the
861 // register scavenger. Note that if we're indexing off the frame pointer, the
862 // effective stack size is 4 bytes larger since the FP points to the stack
863 // slot of the previous FP. Also, if we have variable sized objects in the
864 // function, stack slot references will often be negative, and some of
865 // our instructions are positive-offset only, so conservatively consider
866 // that case to want a spill slot (or register) as well. Similarly, if
867 // the function adjusts the stack pointer during execution and the
868 // adjustments aren't already part of our stack size estimate, our offset
869 // calculations may be off, so be conservative.
870 // FIXME: We could add logic to be more precise about negative offsets
871 // and which instructions will need a scratch register for them. Is it
872 // worth the effort and added fragility?
875 (estimateStackSize(MF) + ((hasFP(MF) && AFI->hasStackFrame()) ? 4:0) >=
876 estimateRSStackSizeLimit(MF)))
877 || MFI->hasVarSizedObjects()
878 || (MFI->adjustsStack() && !canSimplifyCallFramePseudos(MF));
880 bool ExtraCSSpill = false;
881 if (BigStack || !CanEliminateFrame || cannotEliminateFrame(MF)) {
882 AFI->setHasStackFrame(true);
884 // If LR is not spilled, but at least one of R4, R5, R6, and R7 is spilled.
885 // Spill LR as well so we can fold BX_RET to the registers restore (LDM).
886 if (!LRSpilled && CS1Spilled) {
887 MF.getRegInfo().setPhysRegUsed(ARM::LR);
888 AFI->setCSRegisterIsSpilled(ARM::LR);
890 UnspilledCS1GPRs.erase(std::find(UnspilledCS1GPRs.begin(),
891 UnspilledCS1GPRs.end(), (unsigned)ARM::LR));
892 ForceLRSpill = false;
897 MF.getRegInfo().setPhysRegUsed(FramePtr);
901 // If stack and double are 8-byte aligned and we are spilling an odd number
902 // of GPRs. Spill one extra callee save GPR so we won't have to pad between
903 // the integer and double callee save areas.
904 unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment();
905 if (TargetAlign == 8 && (NumGPRSpills & 1)) {
906 if (CS1Spilled && !UnspilledCS1GPRs.empty()) {
907 for (unsigned i = 0, e = UnspilledCS1GPRs.size(); i != e; ++i) {
908 unsigned Reg = UnspilledCS1GPRs[i];
909 // Don't spill high register if the function is thumb1
910 if (!AFI->isThumb1OnlyFunction() ||
911 isARMLowRegister(Reg) || Reg == ARM::LR) {
912 MF.getRegInfo().setPhysRegUsed(Reg);
913 AFI->setCSRegisterIsSpilled(Reg);
914 if (!isReservedReg(MF, Reg))
919 } else if (!UnspilledCS2GPRs.empty() &&
920 !AFI->isThumb1OnlyFunction()) {
921 unsigned Reg = UnspilledCS2GPRs.front();
922 MF.getRegInfo().setPhysRegUsed(Reg);
923 AFI->setCSRegisterIsSpilled(Reg);
924 if (!isReservedReg(MF, Reg))
929 // Estimate if we might need to scavenge a register at some point in order
930 // to materialize a stack offset. If so, either spill one additional
931 // callee-saved register or reserve a special spill slot to facilitate
932 // register scavenging. Thumb1 needs a spill slot for stack pointer
933 // adjustments also, even when the frame itself is small.
934 if (BigStack && !ExtraCSSpill) {
935 // If any non-reserved CS register isn't spilled, just spill one or two
936 // extra. That should take care of it!
937 unsigned NumExtras = TargetAlign / 4;
938 SmallVector<unsigned, 2> Extras;
939 while (NumExtras && !UnspilledCS1GPRs.empty()) {
940 unsigned Reg = UnspilledCS1GPRs.back();
941 UnspilledCS1GPRs.pop_back();
942 if (!isReservedReg(MF, Reg) &&
943 (!AFI->isThumb1OnlyFunction() || isARMLowRegister(Reg) ||
945 Extras.push_back(Reg);
949 // For non-Thumb1 functions, also check for hi-reg CS registers
950 if (!AFI->isThumb1OnlyFunction()) {
951 while (NumExtras && !UnspilledCS2GPRs.empty()) {
952 unsigned Reg = UnspilledCS2GPRs.back();
953 UnspilledCS2GPRs.pop_back();
954 if (!isReservedReg(MF, Reg)) {
955 Extras.push_back(Reg);
960 if (Extras.size() && NumExtras == 0) {
961 for (unsigned i = 0, e = Extras.size(); i != e; ++i) {
962 MF.getRegInfo().setPhysRegUsed(Extras[i]);
963 AFI->setCSRegisterIsSpilled(Extras[i]);
965 } else if (!AFI->isThumb1OnlyFunction()) {
966 // note: Thumb1 functions spill to R12, not the stack. Reserve a slot
967 // closest to SP or frame pointer.
968 const TargetRegisterClass *RC = ARM::GPRRegisterClass;
969 RS->setScavengingFrameIndex(MFI->CreateStackObject(RC->getSize(),
977 MF.getRegInfo().setPhysRegUsed(ARM::LR);
978 AFI->setCSRegisterIsSpilled(ARM::LR);
979 AFI->setLRIsSpilledForFarJump(true);
983 unsigned ARMBaseRegisterInfo::getRARegister() const {
988 ARMBaseRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
994 // Provide a base+offset reference to an FI slot for debug info. It's the
995 // same as what we use for resolving the code-gen references for now.
996 // FIXME: This can go wrong when references are SP-relative and simple call
997 // frames aren't used.
999 ARMBaseRegisterInfo::getFrameIndexReference(const MachineFunction &MF, int FI,
1000 unsigned &FrameReg) const {
1001 return ResolveFrameIndexReference(MF, FI, FrameReg, 0);
1005 ARMBaseRegisterInfo::ResolveFrameIndexReference(const MachineFunction &MF,
1009 const MachineFrameInfo *MFI = MF.getFrameInfo();
1010 const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1011 int Offset = MFI->getObjectOffset(FI) + MFI->getStackSize();
1012 int FPOffset = Offset - AFI->getFramePtrSpillOffset();
1013 bool isFixed = MFI->isFixedObjectIndex(FI);
1017 if (AFI->isGPRCalleeSavedArea1Frame(FI))
1018 return Offset - AFI->getGPRCalleeSavedArea1Offset();
1019 else if (AFI->isGPRCalleeSavedArea2Frame(FI))
1020 return Offset - AFI->getGPRCalleeSavedArea2Offset();
1021 else if (AFI->isDPRCalleeSavedAreaFrame(FI))
1022 return Offset - AFI->getDPRCalleeSavedAreaOffset();
1024 // When dynamically realigning the stack, use the frame pointer for
1025 // parameters, and the stack pointer for locals.
1026 if (needsStackRealignment(MF)) {
1027 assert (hasFP(MF) && "dynamic stack realignment without a FP!");
1029 FrameReg = getFrameRegister(MF);
1035 // If there is a frame pointer, use it when we can.
1036 if (hasFP(MF) && AFI->hasStackFrame()) {
1037 // Use frame pointer to reference fixed objects. Use it for locals if
1038 // there are VLAs (and thus the SP isn't reliable as a base).
1039 if (isFixed || MFI->hasVarSizedObjects()) {
1040 FrameReg = getFrameRegister(MF);
1042 } else if (AFI->isThumb2Function()) {
1043 // In Thumb2 mode, the negative offset is very limited. Try to avoid
1044 // out of range references.
1045 if (FPOffset >= -255 && FPOffset < 0) {
1046 FrameReg = getFrameRegister(MF);
1049 } else if (Offset > (FPOffset < 0 ? -FPOffset : FPOffset)) {
1050 // Otherwise, use SP or FP, whichever is closer to the stack slot.
1051 FrameReg = getFrameRegister(MF);
1059 ARMBaseRegisterInfo::getFrameIndexOffset(const MachineFunction &MF,
1062 return getFrameIndexReference(MF, FI, FrameReg);
1065 unsigned ARMBaseRegisterInfo::getEHExceptionRegister() const {
1066 llvm_unreachable("What is the exception register");
1070 unsigned ARMBaseRegisterInfo::getEHHandlerRegister() const {
1071 llvm_unreachable("What is the exception handler register");
1075 int ARMBaseRegisterInfo::getDwarfRegNum(unsigned RegNum, bool isEH) const {
1076 return ARMGenRegisterInfo::getDwarfRegNumFull(RegNum, 0);
1079 unsigned ARMBaseRegisterInfo::getRegisterPairEven(unsigned Reg,
1080 const MachineFunction &MF) const {
1083 // Return 0 if either register of the pair is a special register.
1092 return isReservedReg(MF, ARM::R7) ? 0 : ARM::R6;
1094 return isReservedReg(MF, ARM::R9) ? 0 :ARM::R8;
1096 return isReservedReg(MF, ARM::R11) ? 0 : ARM::R10;
1168 unsigned ARMBaseRegisterInfo::getRegisterPairOdd(unsigned Reg,
1169 const MachineFunction &MF) const {
1172 // Return 0 if either register of the pair is a special register.
1181 return isReservedReg(MF, ARM::R7) ? 0 : ARM::R7;
1183 return isReservedReg(MF, ARM::R9) ? 0 :ARM::R9;
1185 return isReservedReg(MF, ARM::R11) ? 0 : ARM::R11;
1257 /// emitLoadConstPool - Emits a load from constpool to materialize the
1258 /// specified immediate.
1259 void ARMBaseRegisterInfo::
1260 emitLoadConstPool(MachineBasicBlock &MBB,
1261 MachineBasicBlock::iterator &MBBI,
1263 unsigned DestReg, unsigned SubIdx, int Val,
1264 ARMCC::CondCodes Pred,
1265 unsigned PredReg) const {
1266 MachineFunction &MF = *MBB.getParent();
1267 MachineConstantPool *ConstantPool = MF.getConstantPool();
1269 ConstantInt::get(Type::getInt32Ty(MF.getFunction()->getContext()), Val);
1270 unsigned Idx = ConstantPool->getConstantPoolIndex(C, 4);
1272 BuildMI(MBB, MBBI, dl, TII.get(ARM::LDRcp))
1273 .addReg(DestReg, getDefRegState(true), SubIdx)
1274 .addConstantPoolIndex(Idx)
1275 .addReg(0).addImm(0).addImm(Pred).addReg(PredReg);
1278 bool ARMBaseRegisterInfo::
1279 requiresRegisterScavenging(const MachineFunction &MF) const {
1283 bool ARMBaseRegisterInfo::
1284 requiresFrameIndexScavenging(const MachineFunction &MF) const {
1288 // hasReservedCallFrame - Under normal circumstances, when a frame pointer is
1289 // not required, we reserve argument space for call sites in the function
1290 // immediately on entry to the current function. This eliminates the need for
1291 // add/sub sp brackets around call sites. Returns true if the call frame is
1292 // included as part of the stack frame.
1293 bool ARMBaseRegisterInfo::
1294 hasReservedCallFrame(const MachineFunction &MF) const {
1295 const MachineFrameInfo *FFI = MF.getFrameInfo();
1296 unsigned CFSize = FFI->getMaxCallFrameSize();
1297 // It's not always a good idea to include the call frame as part of the
1298 // stack frame. ARM (especially Thumb) has small immediate offset to
1299 // address the stack frame. So a large call frame can cause poor codegen
1300 // and may even makes it impossible to scavenge a register.
1301 if (CFSize >= ((1 << 12) - 1) / 2) // Half of imm12
1304 return !MF.getFrameInfo()->hasVarSizedObjects();
1307 // canSimplifyCallFramePseudos - If there is a reserved call frame, the
1308 // call frame pseudos can be simplified. Unlike most targets, having a FP
1309 // is not sufficient here since we still may reference some objects via SP
1310 // even when FP is available in Thumb2 mode.
1311 bool ARMBaseRegisterInfo::
1312 canSimplifyCallFramePseudos(const MachineFunction &MF) const {
1313 return hasReservedCallFrame(MF) || MF.getFrameInfo()->hasVarSizedObjects();
1317 emitSPUpdate(bool isARM,
1318 MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,
1319 DebugLoc dl, const ARMBaseInstrInfo &TII,
1321 ARMCC::CondCodes Pred = ARMCC::AL, unsigned PredReg = 0) {
1323 emitARMRegPlusImmediate(MBB, MBBI, dl, ARM::SP, ARM::SP, NumBytes,
1324 Pred, PredReg, TII);
1326 emitT2RegPlusImmediate(MBB, MBBI, dl, ARM::SP, ARM::SP, NumBytes,
1327 Pred, PredReg, TII);
1331 void ARMBaseRegisterInfo::
1332 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
1333 MachineBasicBlock::iterator I) const {
1334 if (!hasReservedCallFrame(MF)) {
1335 // If we have alloca, convert as follows:
1336 // ADJCALLSTACKDOWN -> sub, sp, sp, amount
1337 // ADJCALLSTACKUP -> add, sp, sp, amount
1338 MachineInstr *Old = I;
1339 DebugLoc dl = Old->getDebugLoc();
1340 unsigned Amount = Old->getOperand(0).getImm();
1342 // We need to keep the stack aligned properly. To do this, we round the
1343 // amount of space needed for the outgoing arguments up to the next
1344 // alignment boundary.
1345 unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
1346 Amount = (Amount+Align-1)/Align*Align;
1348 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1349 assert(!AFI->isThumb1OnlyFunction() &&
1350 "This eliminateCallFramePseudoInstr does not support Thumb1!");
1351 bool isARM = !AFI->isThumbFunction();
1353 // Replace the pseudo instruction with a new instruction...
1354 unsigned Opc = Old->getOpcode();
1355 int PIdx = Old->findFirstPredOperandIdx();
1356 ARMCC::CondCodes Pred = (PIdx == -1)
1357 ? ARMCC::AL : (ARMCC::CondCodes)Old->getOperand(PIdx).getImm();
1358 if (Opc == ARM::ADJCALLSTACKDOWN || Opc == ARM::tADJCALLSTACKDOWN) {
1359 // Note: PredReg is operand 2 for ADJCALLSTACKDOWN.
1360 unsigned PredReg = Old->getOperand(2).getReg();
1361 emitSPUpdate(isARM, MBB, I, dl, TII, -Amount, Pred, PredReg);
1363 // Note: PredReg is operand 3 for ADJCALLSTACKUP.
1364 unsigned PredReg = Old->getOperand(3).getReg();
1365 assert(Opc == ARM::ADJCALLSTACKUP || Opc == ARM::tADJCALLSTACKUP);
1366 emitSPUpdate(isARM, MBB, I, dl, TII, Amount, Pred, PredReg);
1374 int64_t ARMBaseRegisterInfo::
1375 getFrameIndexInstrOffset(MachineInstr *MI, int Idx) const {
1376 const TargetInstrDesc &Desc = MI->getDesc();
1377 unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
1378 int64_t InstrOffs = 0;;
1380 unsigned ImmIdx = 0;
1382 case ARMII::AddrModeT2_i8:
1383 case ARMII::AddrModeT2_i12:
1384 // i8 supports only negative, and i12 supports only positive, so
1385 // based on Offset sign, consider the appropriate instruction
1386 InstrOffs = MI->getOperand(Idx+1).getImm();
1389 case ARMII::AddrMode5: {
1390 // VFP address mode.
1391 const MachineOperand &OffOp = MI->getOperand(Idx+1);
1392 int InstrOffs = ARM_AM::getAM5Offset(OffOp.getImm());
1393 if (ARM_AM::getAM5Op(OffOp.getImm()) == ARM_AM::sub)
1394 InstrOffs = -InstrOffs;
1398 case ARMII::AddrMode2: {
1400 InstrOffs = ARM_AM::getAM2Offset(MI->getOperand(ImmIdx).getImm());
1401 if (ARM_AM::getAM2Op(MI->getOperand(ImmIdx).getImm()) == ARM_AM::sub)
1402 InstrOffs = -InstrOffs;
1405 case ARMII::AddrMode3: {
1407 InstrOffs = ARM_AM::getAM3Offset(MI->getOperand(ImmIdx).getImm());
1408 if (ARM_AM::getAM3Op(MI->getOperand(ImmIdx).getImm()) == ARM_AM::sub)
1409 InstrOffs = -InstrOffs;
1412 case ARMII::AddrModeT1_s: {
1414 InstrOffs = MI->getOperand(ImmIdx).getImm();
1419 llvm_unreachable("Unsupported addressing mode!");
1423 return InstrOffs * Scale;
1426 /// needsFrameBaseReg - Returns true if the instruction's frame index
1427 /// reference would be better served by a base register other than FP
1428 /// or SP. Used by LocalStackFrameAllocation to determine which frame index
1429 /// references it should create new base registers for.
1430 bool ARMBaseRegisterInfo::
1431 needsFrameBaseReg(MachineInstr *MI, unsigned operand) const {
1432 assert (MI->getOperand(operand).isFI() &&
1433 "needsFrameBaseReg() called on non Frame Index operand!");
1435 // It's the load/store FI references that cause issues, as it can be difficult
1436 // to materialize the offset if it won't fit in the literal field. Estimate
1437 // based on the size of the local frame and some conservative assumptions
1438 // about the rest of the stack frame (note, this is pre-regalloc, so
1439 // we don't know everything for certain yet) whether this offset is likely
1440 // to be out of range of the immediate. Return true if so.
1442 // We only generate virtual base registers for loads and stores, so
1443 // return false for everything else.
1444 unsigned Opc = MI->getOpcode();
1446 case ARM::LDR: case ARM::LDRH: case ARM::LDRB:
1447 case ARM::STR: case ARM::STRH: case ARM::STRB:
1448 case ARM::t2LDRi12: case ARM::t2LDRi8:
1449 case ARM::t2STRi12: case ARM::t2STRi8:
1450 case ARM::VLDRS: case ARM::VLDRD:
1451 case ARM::VSTRS: case ARM::VSTRD:
1452 case ARM::tSTRspi: case ARM::tLDRspi:
1453 if (ForceAllBaseRegAlloc)
1461 // Without a virtual base register, if the function has variable sized
1462 // objects, all fixed-size local references will be via the frame pointer,
1463 // otherwise via the stack pointer. Approximate the offset and see if it's
1464 // legal for the instruction.
1469 /// materializeFrameBaseRegister - Insert defining instruction(s) for
1470 /// BaseReg to be a pointer to FrameIdx before insertion point I.
1471 void ARMBaseRegisterInfo::
1472 materializeFrameBaseRegister(MachineBasicBlock::iterator I, unsigned BaseReg,
1473 int FrameIdx, int64_t Offset) const {
1474 ARMFunctionInfo *AFI =
1475 I->getParent()->getParent()->getInfo<ARMFunctionInfo>();
1476 unsigned ADDriOpc = !AFI->isThumbFunction() ? ARM::ADDri :
1477 (AFI->isThumb1OnlyFunction() ? ARM::tADDrSPi : ARM::t2ADDri);
1479 MachineInstrBuilder MIB =
1480 BuildMI(*I->getParent(), I, I->getDebugLoc(), TII.get(ADDriOpc), BaseReg)
1481 .addFrameIndex(FrameIdx).addImm(Offset);
1482 if (!AFI->isThumb1OnlyFunction())
1483 AddDefaultCC(AddDefaultPred(MIB));
1487 ARMBaseRegisterInfo::resolveFrameIndex(MachineBasicBlock::iterator I,
1488 unsigned BaseReg, int64_t Offset) const {
1489 MachineInstr &MI = *I;
1490 MachineBasicBlock &MBB = *MI.getParent();
1491 MachineFunction &MF = *MBB.getParent();
1492 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1493 int Off = Offset; // ARM doesn't need the general 64-bit offsets
1496 assert(!AFI->isThumb1OnlyFunction() &&
1497 "This resolveFrameIndex does not support Thumb1!");
1499 while (!MI.getOperand(i).isFI()) {
1501 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
1504 if (!AFI->isThumbFunction())
1505 Done = rewriteARMFrameIndex(MI, i, BaseReg, Off, TII);
1507 assert(AFI->isThumb2Function());
1508 Done = rewriteT2FrameIndex(MI, i, BaseReg, Off, TII);
1510 assert (Done && "Unable to resolve frame index!");
1513 bool ARMBaseRegisterInfo::isFrameOffsetLegal(const MachineInstr *MI,
1514 int64_t Offset) const {
1515 const TargetInstrDesc &Desc = MI->getDesc();
1516 unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
1519 while (!MI->getOperand(i).isFI()) {
1521 assert(i < MI->getNumOperands() &&"Instr doesn't have FrameIndex operand!");
1524 // AddrMode4 and AddrMode6 cannot handle any offset.
1525 if (AddrMode == ARMII::AddrMode4 || AddrMode == ARMII::AddrMode6)
1528 unsigned NumBits = 0;
1530 unsigned ImmIdx = 0;
1532 bool isSigned = true;
1534 case ARMII::AddrModeT2_i8:
1535 case ARMII::AddrModeT2_i12:
1536 // i8 supports only negative, and i12 supports only positive, so
1537 // based on Offset sign, consider the appropriate instruction
1538 InstrOffs = MI->getOperand(i+1).getImm();
1547 case ARMII::AddrMode5: {
1548 // VFP address mode.
1549 const MachineOperand &OffOp = MI->getOperand(i+1);
1550 int InstrOffs = ARM_AM::getAM5Offset(OffOp.getImm());
1551 if (ARM_AM::getAM5Op(OffOp.getImm()) == ARM_AM::sub)
1552 InstrOffs = -InstrOffs;
1557 case ARMII::AddrMode2: {
1559 InstrOffs = ARM_AM::getAM2Offset(MI->getOperand(ImmIdx).getImm());
1560 if (ARM_AM::getAM2Op(MI->getOperand(ImmIdx).getImm()) == ARM_AM::sub)
1561 InstrOffs = -InstrOffs;
1565 case ARMII::AddrMode3: {
1567 InstrOffs = ARM_AM::getAM3Offset(MI->getOperand(ImmIdx).getImm());
1568 if (ARM_AM::getAM3Op(MI->getOperand(ImmIdx).getImm()) == ARM_AM::sub)
1569 InstrOffs = -InstrOffs;
1573 case ARMII::AddrModeT1_s: {
1575 InstrOffs = MI->getOperand(ImmIdx).getImm();
1582 llvm_unreachable("Unsupported addressing mode!");
1586 Offset += InstrOffs * Scale;
1587 assert((Offset & (Scale-1)) == 0 && "Can't encode this offset!");
1588 if (isSigned && Offset < 0)
1591 unsigned Mask = (1 << NumBits) - 1;
1592 if ((unsigned)Offset <= Mask * Scale)
1599 ARMBaseRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
1600 int SPAdj, FrameIndexValue *Value,
1601 RegScavenger *RS) const {
1603 MachineInstr &MI = *II;
1604 MachineBasicBlock &MBB = *MI.getParent();
1605 MachineFunction &MF = *MBB.getParent();
1606 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1607 assert(!AFI->isThumb1OnlyFunction() &&
1608 "This eliminateFrameIndex does not support Thumb1!");
1610 while (!MI.getOperand(i).isFI()) {
1612 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
1615 int FrameIndex = MI.getOperand(i).getIndex();
1618 int Offset = ResolveFrameIndexReference(MF, FrameIndex, FrameReg, SPAdj);
1620 // Special handling of dbg_value instructions.
1621 if (MI.isDebugValue()) {
1622 MI.getOperand(i). ChangeToRegister(FrameReg, false /*isDef*/);
1623 MI.getOperand(i+1).ChangeToImmediate(Offset);
1627 // Modify MI as necessary to handle as much of 'Offset' as possible
1629 if (!AFI->isThumbFunction())
1630 Done = rewriteARMFrameIndex(MI, i, FrameReg, Offset, TII);
1632 assert(AFI->isThumb2Function());
1633 Done = rewriteT2FrameIndex(MI, i, FrameReg, Offset, TII);
1638 // If we get here, the immediate doesn't fit into the instruction. We folded
1639 // as much as possible above, handle the rest, providing a register that is
1642 (MI.getDesc().TSFlags & ARMII::AddrModeMask) == ARMII::AddrMode4 ||
1643 (MI.getDesc().TSFlags & ARMII::AddrModeMask) == ARMII::AddrMode6) &&
1644 "This code isn't needed if offset already handled!");
1646 unsigned ScratchReg = 0;
1647 int PIdx = MI.findFirstPredOperandIdx();
1648 ARMCC::CondCodes Pred = (PIdx == -1)
1649 ? ARMCC::AL : (ARMCC::CondCodes)MI.getOperand(PIdx).getImm();
1650 unsigned PredReg = (PIdx == -1) ? 0 : MI.getOperand(PIdx+1).getReg();
1652 // Must be addrmode4/6.
1653 MI.getOperand(i).ChangeToRegister(FrameReg, false, false, false);
1655 ScratchReg = MF.getRegInfo().createVirtualRegister(ARM::GPRRegisterClass);
1657 Value->first = FrameReg; // use the frame register as a kind indicator
1658 Value->second = Offset;
1660 if (!AFI->isThumbFunction())
1661 emitARMRegPlusImmediate(MBB, II, MI.getDebugLoc(), ScratchReg, FrameReg,
1662 Offset, Pred, PredReg, TII);
1664 assert(AFI->isThumb2Function());
1665 emitT2RegPlusImmediate(MBB, II, MI.getDebugLoc(), ScratchReg, FrameReg,
1666 Offset, Pred, PredReg, TII);
1668 MI.getOperand(i).ChangeToRegister(ScratchReg, false, false, true);
1669 if (!ReuseFrameIndexVals)
1675 /// Move iterator past the next bunch of callee save load / store ops for
1676 /// the particular spill area (1: integer area 1, 2: integer area 2,
1677 /// 3: fp area, 0: don't care).
1678 static void movePastCSLoadStoreOps(MachineBasicBlock &MBB,
1679 MachineBasicBlock::iterator &MBBI,
1680 int Opc1, int Opc2, unsigned Area,
1681 const ARMSubtarget &STI) {
1682 while (MBBI != MBB.end() &&
1683 ((MBBI->getOpcode() == Opc1) || (MBBI->getOpcode() == Opc2)) &&
1684 MBBI->getOperand(1).isFI()) {
1687 unsigned Category = 0;
1688 switch (MBBI->getOperand(0).getReg()) {
1689 case ARM::R4: case ARM::R5: case ARM::R6: case ARM::R7:
1693 case ARM::R8: case ARM::R9: case ARM::R10: case ARM::R11:
1694 Category = STI.isTargetDarwin() ? 2 : 1;
1696 case ARM::D8: case ARM::D9: case ARM::D10: case ARM::D11:
1697 case ARM::D12: case ARM::D13: case ARM::D14: case ARM::D15:
1704 if (Done || Category != Area)
1712 void ARMBaseRegisterInfo::
1713 emitPrologue(MachineFunction &MF) const {
1714 MachineBasicBlock &MBB = MF.front();
1715 MachineBasicBlock::iterator MBBI = MBB.begin();
1716 MachineFrameInfo *MFI = MF.getFrameInfo();
1717 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1718 assert(!AFI->isThumb1OnlyFunction() &&
1719 "This emitPrologue does not support Thumb1!");
1720 bool isARM = !AFI->isThumbFunction();
1721 unsigned VARegSaveSize = AFI->getVarArgsRegSaveSize();
1722 unsigned NumBytes = MFI->getStackSize();
1723 const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
1724 DebugLoc dl = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
1726 // Determine the sizes of each callee-save spill areas and record which frame
1727 // belongs to which callee-save spill areas.
1728 unsigned GPRCS1Size = 0, GPRCS2Size = 0, DPRCSSize = 0;
1729 int FramePtrSpillFI = 0;
1731 // Allocate the vararg register save area. This is not counted in NumBytes.
1733 emitSPUpdate(isARM, MBB, MBBI, dl, TII, -VARegSaveSize);
1735 if (!AFI->hasStackFrame()) {
1737 emitSPUpdate(isARM, MBB, MBBI, dl, TII, -NumBytes);
1741 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
1742 unsigned Reg = CSI[i].getReg();
1743 int FI = CSI[i].getFrameIdx();
1750 if (Reg == FramePtr)
1751 FramePtrSpillFI = FI;
1752 AFI->addGPRCalleeSavedArea1Frame(FI);
1759 if (Reg == FramePtr)
1760 FramePtrSpillFI = FI;
1761 if (STI.isTargetDarwin()) {
1762 AFI->addGPRCalleeSavedArea2Frame(FI);
1765 AFI->addGPRCalleeSavedArea1Frame(FI);
1770 AFI->addDPRCalleeSavedAreaFrame(FI);
1775 // Build the new SUBri to adjust SP for integer callee-save spill area 1.
1776 emitSPUpdate(isARM, MBB, MBBI, dl, TII, -GPRCS1Size);
1777 movePastCSLoadStoreOps(MBB, MBBI, ARM::STR, ARM::t2STRi12, 1, STI);
1779 // Set FP to point to the stack slot that contains the previous FP.
1780 // For Darwin, FP is R7, which has now been stored in spill area 1.
1781 // Otherwise, if this is not Darwin, all the callee-saved registers go
1782 // into spill area 1, including the FP in R11. In either case, it is
1783 // now safe to emit this assignment.
1784 bool HasFP = hasFP(MF);
1786 unsigned ADDriOpc = !AFI->isThumbFunction() ? ARM::ADDri : ARM::t2ADDri;
1787 MachineInstrBuilder MIB =
1788 BuildMI(MBB, MBBI, dl, TII.get(ADDriOpc), FramePtr)
1789 .addFrameIndex(FramePtrSpillFI).addImm(0);
1790 AddDefaultCC(AddDefaultPred(MIB));
1793 // Build the new SUBri to adjust SP for integer callee-save spill area 2.
1794 emitSPUpdate(isARM, MBB, MBBI, dl, TII, -GPRCS2Size);
1796 // Build the new SUBri to adjust SP for FP callee-save spill area.
1797 movePastCSLoadStoreOps(MBB, MBBI, ARM::STR, ARM::t2STRi12, 2, STI);
1798 emitSPUpdate(isARM, MBB, MBBI, dl, TII, -DPRCSSize);
1800 // Determine starting offsets of spill areas.
1801 unsigned DPRCSOffset = NumBytes - (GPRCS1Size + GPRCS2Size + DPRCSSize);
1802 unsigned GPRCS2Offset = DPRCSOffset + DPRCSSize;
1803 unsigned GPRCS1Offset = GPRCS2Offset + GPRCS2Size;
1805 AFI->setFramePtrSpillOffset(MFI->getObjectOffset(FramePtrSpillFI) +
1807 AFI->setGPRCalleeSavedArea1Offset(GPRCS1Offset);
1808 AFI->setGPRCalleeSavedArea2Offset(GPRCS2Offset);
1809 AFI->setDPRCalleeSavedAreaOffset(DPRCSOffset);
1811 movePastCSLoadStoreOps(MBB, MBBI, ARM::VSTRD, 0, 3, STI);
1812 NumBytes = DPRCSOffset;
1814 // Adjust SP after all the callee-save spills.
1815 emitSPUpdate(isARM, MBB, MBBI, dl, TII, -NumBytes);
1817 AFI->setShouldRestoreSPFromFP(true);
1820 if (STI.isTargetELF() && hasFP(MF)) {
1821 MFI->setOffsetAdjustment(MFI->getOffsetAdjustment() -
1822 AFI->getFramePtrSpillOffset());
1823 AFI->setShouldRestoreSPFromFP(true);
1826 AFI->setGPRCalleeSavedArea1Size(GPRCS1Size);
1827 AFI->setGPRCalleeSavedArea2Size(GPRCS2Size);
1828 AFI->setDPRCalleeSavedAreaSize(DPRCSSize);
1830 // If we need dynamic stack realignment, do it here.
1831 if (needsStackRealignment(MF)) {
1832 unsigned MaxAlign = MFI->getMaxAlignment();
1833 assert (!AFI->isThumb1OnlyFunction());
1834 if (!AFI->isThumbFunction()) {
1835 // Emit bic sp, sp, MaxAlign
1836 AddDefaultCC(AddDefaultPred(BuildMI(MBB, MBBI, dl,
1837 TII.get(ARM::BICri), ARM::SP)
1838 .addReg(ARM::SP, RegState::Kill)
1839 .addImm(MaxAlign-1)));
1841 // We cannot use sp as source/dest register here, thus we're emitting the
1842 // following sequence:
1844 // bic r4, r4, MaxAlign
1846 // FIXME: It will be better just to find spare register here.
1847 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVgpr2tgpr), ARM::R4)
1848 .addReg(ARM::SP, RegState::Kill);
1849 AddDefaultCC(AddDefaultPred(BuildMI(MBB, MBBI, dl,
1850 TII.get(ARM::t2BICri), ARM::R4)
1851 .addReg(ARM::R4, RegState::Kill)
1852 .addImm(MaxAlign-1)));
1853 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVtgpr2gpr), ARM::SP)
1854 .addReg(ARM::R4, RegState::Kill);
1857 AFI->setShouldRestoreSPFromFP(true);
1860 // If the frame has variable sized objects then the epilogue must restore
1862 if (!AFI->shouldRestoreSPFromFP() && MFI->hasVarSizedObjects())
1863 AFI->setShouldRestoreSPFromFP(true);
1866 static bool isCalleeSavedRegister(unsigned Reg, const unsigned *CSRegs) {
1867 for (unsigned i = 0; CSRegs[i]; ++i)
1868 if (Reg == CSRegs[i])
1873 static bool isCSRestore(MachineInstr *MI,
1874 const ARMBaseInstrInfo &TII,
1875 const unsigned *CSRegs) {
1876 return ((MI->getOpcode() == (int)ARM::VLDRD ||
1877 MI->getOpcode() == (int)ARM::LDR ||
1878 MI->getOpcode() == (int)ARM::t2LDRi12) &&
1879 MI->getOperand(1).isFI() &&
1880 isCalleeSavedRegister(MI->getOperand(0).getReg(), CSRegs));
1883 void ARMBaseRegisterInfo::
1884 emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const {
1885 MachineBasicBlock::iterator MBBI = prior(MBB.end());
1886 assert(MBBI->getDesc().isReturn() &&
1887 "Can only insert epilog into returning blocks");
1888 unsigned RetOpcode = MBBI->getOpcode();
1889 DebugLoc dl = MBBI->getDebugLoc();
1890 MachineFrameInfo *MFI = MF.getFrameInfo();
1891 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1892 assert(!AFI->isThumb1OnlyFunction() &&
1893 "This emitEpilogue does not support Thumb1!");
1894 bool isARM = !AFI->isThumbFunction();
1896 unsigned VARegSaveSize = AFI->getVarArgsRegSaveSize();
1897 int NumBytes = (int)MFI->getStackSize();
1899 if (!AFI->hasStackFrame()) {
1901 emitSPUpdate(isARM, MBB, MBBI, dl, TII, NumBytes);
1903 // Unwind MBBI to point to first LDR / VLDRD.
1904 const unsigned *CSRegs = getCalleeSavedRegs();
1905 if (MBBI != MBB.begin()) {
1908 while (MBBI != MBB.begin() && isCSRestore(MBBI, TII, CSRegs));
1909 if (!isCSRestore(MBBI, TII, CSRegs))
1913 // Move SP to start of FP callee save spill area.
1914 NumBytes -= (AFI->getGPRCalleeSavedArea1Size() +
1915 AFI->getGPRCalleeSavedArea2Size() +
1916 AFI->getDPRCalleeSavedAreaSize());
1918 // Reset SP based on frame pointer only if the stack frame extends beyond
1919 // frame pointer stack slot or target is ELF and the function has FP.
1920 if (AFI->shouldRestoreSPFromFP()) {
1921 NumBytes = AFI->getFramePtrSpillOffset() - NumBytes;
1924 emitARMRegPlusImmediate(MBB, MBBI, dl, ARM::SP, FramePtr, -NumBytes,
1927 emitT2RegPlusImmediate(MBB, MBBI, dl, ARM::SP, FramePtr, -NumBytes,
1932 BuildMI(MBB, MBBI, dl, TII.get(ARM::MOVr), ARM::SP)
1933 .addReg(FramePtr).addImm((unsigned)ARMCC::AL).addReg(0).addReg(0);
1935 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVgpr2gpr), ARM::SP)
1938 } else if (NumBytes)
1939 emitSPUpdate(isARM, MBB, MBBI, dl, TII, NumBytes);
1941 // Move SP to start of integer callee save spill area 2.
1942 movePastCSLoadStoreOps(MBB, MBBI, ARM::VLDRD, 0, 3, STI);
1943 emitSPUpdate(isARM, MBB, MBBI, dl, TII, AFI->getDPRCalleeSavedAreaSize());
1945 // Move SP to start of integer callee save spill area 1.
1946 movePastCSLoadStoreOps(MBB, MBBI, ARM::LDR, ARM::t2LDRi12, 2, STI);
1947 emitSPUpdate(isARM, MBB, MBBI, dl, TII, AFI->getGPRCalleeSavedArea2Size());
1949 // Move SP to SP upon entry to the function.
1950 movePastCSLoadStoreOps(MBB, MBBI, ARM::LDR, ARM::t2LDRi12, 1, STI);
1951 emitSPUpdate(isARM, MBB, MBBI, dl, TII, AFI->getGPRCalleeSavedArea1Size());
1954 if (RetOpcode == ARM::TCRETURNdi || RetOpcode == ARM::TCRETURNdiND ||
1955 RetOpcode == ARM::TCRETURNri || RetOpcode == ARM::TCRETURNriND) {
1956 // Tail call return: adjust the stack pointer and jump to callee.
1957 MBBI = prior(MBB.end());
1958 MachineOperand &JumpTarget = MBBI->getOperand(0);
1960 // Jump to label or value in register.
1961 if (RetOpcode == ARM::TCRETURNdi) {
1962 BuildMI(MBB, MBBI, dl,
1963 TII.get(STI.isThumb() ? ARM::TAILJMPdt : ARM::TAILJMPd)).
1964 addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset(),
1965 JumpTarget.getTargetFlags());
1966 } else if (RetOpcode == ARM::TCRETURNdiND) {
1967 BuildMI(MBB, MBBI, dl,
1968 TII.get(STI.isThumb() ? ARM::TAILJMPdNDt : ARM::TAILJMPdND)).
1969 addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset(),
1970 JumpTarget.getTargetFlags());
1971 } else if (RetOpcode == ARM::TCRETURNri) {
1972 BuildMI(MBB, MBBI, dl, TII.get(ARM::TAILJMPr)).
1973 addReg(JumpTarget.getReg(), RegState::Kill);
1974 } else if (RetOpcode == ARM::TCRETURNriND) {
1975 BuildMI(MBB, MBBI, dl, TII.get(ARM::TAILJMPrND)).
1976 addReg(JumpTarget.getReg(), RegState::Kill);
1979 MachineInstr *NewMI = prior(MBBI);
1980 for (unsigned i = 1, e = MBBI->getNumOperands(); i != e; ++i)
1981 NewMI->addOperand(MBBI->getOperand(i));
1983 // Delete the pseudo instruction TCRETURN.
1988 emitSPUpdate(isARM, MBB, MBBI, dl, TII, VARegSaveSize);
1991 #include "ARMGenRegisterInfo.inc"