1 //===- ARMBaseRegisterInfo.cpp - ARM Register Information -------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the base ARM implementation of TargetRegisterInfo class.
12 //===----------------------------------------------------------------------===//
15 #include "ARMAddressingModes.h"
16 #include "ARMBaseInstrInfo.h"
17 #include "ARMBaseRegisterInfo.h"
18 #include "ARMInstrInfo.h"
19 #include "ARMMachineFunctionInfo.h"
20 #include "ARMSubtarget.h"
21 #include "llvm/Constants.h"
22 #include "llvm/DerivedTypes.h"
23 #include "llvm/Function.h"
24 #include "llvm/LLVMContext.h"
25 #include "llvm/CodeGen/MachineConstantPool.h"
26 #include "llvm/CodeGen/MachineFrameInfo.h"
27 #include "llvm/CodeGen/MachineFunction.h"
28 #include "llvm/CodeGen/MachineInstrBuilder.h"
29 #include "llvm/CodeGen/MachineLocation.h"
30 #include "llvm/CodeGen/MachineRegisterInfo.h"
31 #include "llvm/CodeGen/RegisterScavenging.h"
32 #include "llvm/Support/ErrorHandling.h"
33 #include "llvm/Support/raw_ostream.h"
34 #include "llvm/Target/TargetFrameInfo.h"
35 #include "llvm/Target/TargetMachine.h"
36 #include "llvm/Target/TargetOptions.h"
37 #include "llvm/ADT/BitVector.h"
38 #include "llvm/ADT/SmallVector.h"
41 unsigned ARMBaseRegisterInfo::getRegisterNumbering(unsigned RegEnum,
49 llvm_unreachable("Unknown ARM register!");
50 case R0: case D0: case Q0: return 0;
51 case R1: case D1: case Q1: return 1;
52 case R2: case D2: case Q2: return 2;
53 case R3: case D3: case Q3: return 3;
54 case R4: case D4: case Q4: return 4;
55 case R5: case D5: case Q5: return 5;
56 case R6: case D6: case Q6: return 6;
57 case R7: case D7: case Q7: return 7;
58 case R8: case D8: case Q8: return 8;
59 case R9: case D9: case Q9: return 9;
60 case R10: case D10: case Q10: return 10;
61 case R11: case D11: case Q11: return 11;
62 case R12: case D12: case Q12: return 12;
63 case SP: case D13: case Q13: return 13;
64 case LR: case D14: case Q14: return 14;
65 case PC: case D15: case Q15: return 15;
84 case S0: case S1: case S2: case S3:
85 case S4: case S5: case S6: case S7:
86 case S8: case S9: case S10: case S11:
87 case S12: case S13: case S14: case S15:
88 case S16: case S17: case S18: case S19:
89 case S20: case S21: case S22: case S23:
90 case S24: case S25: case S26: case S27:
91 case S28: case S29: case S30: case S31: {
95 default: return 0; // Avoid compile time warning.
133 ARMBaseRegisterInfo::ARMBaseRegisterInfo(const ARMBaseInstrInfo &tii,
134 const ARMSubtarget &sti)
135 : ARMGenRegisterInfo(ARM::ADJCALLSTACKDOWN, ARM::ADJCALLSTACKUP),
137 FramePtr((STI.isTargetDarwin() || STI.isThumb()) ? ARM::R7 : ARM::R11) {
141 ARMBaseRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
142 static const unsigned CalleeSavedRegs[] = {
143 ARM::LR, ARM::R11, ARM::R10, ARM::R9, ARM::R8,
144 ARM::R7, ARM::R6, ARM::R5, ARM::R4,
146 ARM::D15, ARM::D14, ARM::D13, ARM::D12,
147 ARM::D11, ARM::D10, ARM::D9, ARM::D8,
151 static const unsigned DarwinCalleeSavedRegs[] = {
152 // Darwin ABI deviates from ARM standard ABI. R9 is not a callee-saved
154 ARM::LR, ARM::R7, ARM::R6, ARM::R5, ARM::R4,
155 ARM::R11, ARM::R10, ARM::R8,
157 ARM::D15, ARM::D14, ARM::D13, ARM::D12,
158 ARM::D11, ARM::D10, ARM::D9, ARM::D8,
161 return STI.isTargetDarwin() ? DarwinCalleeSavedRegs : CalleeSavedRegs;
164 const TargetRegisterClass* const *
165 ARMBaseRegisterInfo::getCalleeSavedRegClasses(const MachineFunction *MF) const {
166 static const TargetRegisterClass * const CalleeSavedRegClasses[] = {
167 ARM::GPRRegisterClass, ARM::GPRRegisterClass, ARM::GPRRegisterClass,
168 ARM::GPRRegisterClass, ARM::GPRRegisterClass, ARM::GPRRegisterClass,
169 ARM::GPRRegisterClass, ARM::GPRRegisterClass, ARM::GPRRegisterClass,
171 ARM::DPRRegisterClass, ARM::DPRRegisterClass, ARM::DPRRegisterClass,
172 ARM::DPRRegisterClass, ARM::DPRRegisterClass, ARM::DPRRegisterClass,
173 ARM::DPRRegisterClass, ARM::DPRRegisterClass,
177 static const TargetRegisterClass * const ThumbCalleeSavedRegClasses[] = {
178 ARM::GPRRegisterClass, ARM::GPRRegisterClass, ARM::GPRRegisterClass,
179 ARM::GPRRegisterClass, ARM::GPRRegisterClass, ARM::tGPRRegisterClass,
180 ARM::tGPRRegisterClass,ARM::tGPRRegisterClass,ARM::tGPRRegisterClass,
182 ARM::DPRRegisterClass, ARM::DPRRegisterClass, ARM::DPRRegisterClass,
183 ARM::DPRRegisterClass, ARM::DPRRegisterClass, ARM::DPRRegisterClass,
184 ARM::DPRRegisterClass, ARM::DPRRegisterClass,
188 static const TargetRegisterClass * const DarwinCalleeSavedRegClasses[] = {
189 ARM::GPRRegisterClass, ARM::GPRRegisterClass, ARM::GPRRegisterClass,
190 ARM::GPRRegisterClass, ARM::GPRRegisterClass, ARM::GPRRegisterClass,
191 ARM::GPRRegisterClass, ARM::GPRRegisterClass,
193 ARM::DPRRegisterClass, ARM::DPRRegisterClass, ARM::DPRRegisterClass,
194 ARM::DPRRegisterClass, ARM::DPRRegisterClass, ARM::DPRRegisterClass,
195 ARM::DPRRegisterClass, ARM::DPRRegisterClass,
199 static const TargetRegisterClass * const DarwinThumbCalleeSavedRegClasses[] ={
200 ARM::GPRRegisterClass, ARM::tGPRRegisterClass, ARM::tGPRRegisterClass,
201 ARM::tGPRRegisterClass, ARM::tGPRRegisterClass, ARM::GPRRegisterClass,
202 ARM::GPRRegisterClass, ARM::GPRRegisterClass,
204 ARM::DPRRegisterClass, ARM::DPRRegisterClass, ARM::DPRRegisterClass,
205 ARM::DPRRegisterClass, ARM::DPRRegisterClass, ARM::DPRRegisterClass,
206 ARM::DPRRegisterClass, ARM::DPRRegisterClass,
210 if (STI.isThumb1Only()) {
211 return STI.isTargetDarwin()
212 ? DarwinThumbCalleeSavedRegClasses : ThumbCalleeSavedRegClasses;
214 return STI.isTargetDarwin()
215 ? DarwinCalleeSavedRegClasses : CalleeSavedRegClasses;
218 BitVector ARMBaseRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
219 // FIXME: avoid re-calculating this everytime.
220 BitVector Reserved(getNumRegs());
221 Reserved.set(ARM::SP);
222 Reserved.set(ARM::PC);
223 if (STI.isTargetDarwin() || hasFP(MF))
224 Reserved.set(FramePtr);
225 // Some targets reserve R9.
226 if (STI.isR9Reserved())
227 Reserved.set(ARM::R9);
231 bool ARMBaseRegisterInfo::isReservedReg(const MachineFunction &MF,
232 unsigned Reg) const {
240 if (FramePtr == Reg && (STI.isTargetDarwin() || hasFP(MF)))
244 return STI.isR9Reserved();
250 const TargetRegisterClass *
251 ARMBaseRegisterInfo::getPointerRegClass(unsigned Kind) const {
252 return ARM::GPRRegisterClass;
255 /// getAllocationOrder - Returns the register allocation order for a specified
256 /// register class in the form of a pair of TargetRegisterClass iterators.
257 std::pair<TargetRegisterClass::iterator,TargetRegisterClass::iterator>
258 ARMBaseRegisterInfo::getAllocationOrder(const TargetRegisterClass *RC,
259 unsigned HintType, unsigned HintReg,
260 const MachineFunction &MF) const {
261 // Alternative register allocation orders when favoring even / odd registers
262 // of register pairs.
264 // No FP, R9 is available.
265 static const unsigned GPREven1[] = {
266 ARM::R0, ARM::R2, ARM::R4, ARM::R6, ARM::R8, ARM::R10,
267 ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R7,
270 static const unsigned GPROdd1[] = {
271 ARM::R1, ARM::R3, ARM::R5, ARM::R7, ARM::R9, ARM::R11,
272 ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6,
276 // FP is R7, R9 is available.
277 static const unsigned GPREven2[] = {
278 ARM::R0, ARM::R2, ARM::R4, ARM::R8, ARM::R10,
279 ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R6,
282 static const unsigned GPROdd2[] = {
283 ARM::R1, ARM::R3, ARM::R5, ARM::R9, ARM::R11,
284 ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6,
288 // FP is R11, R9 is available.
289 static const unsigned GPREven3[] = {
290 ARM::R0, ARM::R2, ARM::R4, ARM::R6, ARM::R8,
291 ARM::R1, ARM::R3, ARM::R10,ARM::R12,ARM::LR, ARM::R5, ARM::R7,
294 static const unsigned GPROdd3[] = {
295 ARM::R1, ARM::R3, ARM::R5, ARM::R6, ARM::R9,
296 ARM::R0, ARM::R2, ARM::R10,ARM::R12,ARM::LR, ARM::R4, ARM::R7,
300 // No FP, R9 is not available.
301 static const unsigned GPREven4[] = {
302 ARM::R0, ARM::R2, ARM::R4, ARM::R6, ARM::R10,
303 ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R7, ARM::R8,
306 static const unsigned GPROdd4[] = {
307 ARM::R1, ARM::R3, ARM::R5, ARM::R7, ARM::R11,
308 ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6, ARM::R8,
312 // FP is R7, R9 is not available.
313 static const unsigned GPREven5[] = {
314 ARM::R0, ARM::R2, ARM::R4, ARM::R10,
315 ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R6, ARM::R8,
318 static const unsigned GPROdd5[] = {
319 ARM::R1, ARM::R3, ARM::R5, ARM::R11,
320 ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6, ARM::R8,
324 // FP is R11, R9 is not available.
325 static const unsigned GPREven6[] = {
326 ARM::R0, ARM::R2, ARM::R4, ARM::R6,
327 ARM::R1, ARM::R3, ARM::R10,ARM::R12,ARM::LR, ARM::R5, ARM::R7, ARM::R8
329 static const unsigned GPROdd6[] = {
330 ARM::R1, ARM::R3, ARM::R5, ARM::R7,
331 ARM::R0, ARM::R2, ARM::R10,ARM::R12,ARM::LR, ARM::R4, ARM::R6, ARM::R8
335 if (HintType == ARMRI::RegPairEven) {
336 if (isPhysicalRegister(HintReg) && getRegisterPairEven(HintReg, MF) == 0)
337 // It's no longer possible to fulfill this hint. Return the default
339 return std::make_pair(RC->allocation_order_begin(MF),
340 RC->allocation_order_end(MF));
342 if (!STI.isTargetDarwin() && !hasFP(MF)) {
343 if (!STI.isR9Reserved())
344 return std::make_pair(GPREven1,
345 GPREven1 + (sizeof(GPREven1)/sizeof(unsigned)));
347 return std::make_pair(GPREven4,
348 GPREven4 + (sizeof(GPREven4)/sizeof(unsigned)));
349 } else if (FramePtr == ARM::R7) {
350 if (!STI.isR9Reserved())
351 return std::make_pair(GPREven2,
352 GPREven2 + (sizeof(GPREven2)/sizeof(unsigned)));
354 return std::make_pair(GPREven5,
355 GPREven5 + (sizeof(GPREven5)/sizeof(unsigned)));
356 } else { // FramePtr == ARM::R11
357 if (!STI.isR9Reserved())
358 return std::make_pair(GPREven3,
359 GPREven3 + (sizeof(GPREven3)/sizeof(unsigned)));
361 return std::make_pair(GPREven6,
362 GPREven6 + (sizeof(GPREven6)/sizeof(unsigned)));
364 } else if (HintType == ARMRI::RegPairOdd) {
365 if (isPhysicalRegister(HintReg) && getRegisterPairOdd(HintReg, MF) == 0)
366 // It's no longer possible to fulfill this hint. Return the default
368 return std::make_pair(RC->allocation_order_begin(MF),
369 RC->allocation_order_end(MF));
371 if (!STI.isTargetDarwin() && !hasFP(MF)) {
372 if (!STI.isR9Reserved())
373 return std::make_pair(GPROdd1,
374 GPROdd1 + (sizeof(GPROdd1)/sizeof(unsigned)));
376 return std::make_pair(GPROdd4,
377 GPROdd4 + (sizeof(GPROdd4)/sizeof(unsigned)));
378 } else if (FramePtr == ARM::R7) {
379 if (!STI.isR9Reserved())
380 return std::make_pair(GPROdd2,
381 GPROdd2 + (sizeof(GPROdd2)/sizeof(unsigned)));
383 return std::make_pair(GPROdd5,
384 GPROdd5 + (sizeof(GPROdd5)/sizeof(unsigned)));
385 } else { // FramePtr == ARM::R11
386 if (!STI.isR9Reserved())
387 return std::make_pair(GPROdd3,
388 GPROdd3 + (sizeof(GPROdd3)/sizeof(unsigned)));
390 return std::make_pair(GPROdd6,
391 GPROdd6 + (sizeof(GPROdd6)/sizeof(unsigned)));
394 return std::make_pair(RC->allocation_order_begin(MF),
395 RC->allocation_order_end(MF));
398 /// ResolveRegAllocHint - Resolves the specified register allocation hint
399 /// to a physical register. Returns the physical register if it is successful.
401 ARMBaseRegisterInfo::ResolveRegAllocHint(unsigned Type, unsigned Reg,
402 const MachineFunction &MF) const {
403 if (Reg == 0 || !isPhysicalRegister(Reg))
407 else if (Type == (unsigned)ARMRI::RegPairOdd)
409 return getRegisterPairOdd(Reg, MF);
410 else if (Type == (unsigned)ARMRI::RegPairEven)
412 return getRegisterPairEven(Reg, MF);
417 ARMBaseRegisterInfo::UpdateRegAllocHint(unsigned Reg, unsigned NewReg,
418 MachineFunction &MF) const {
419 MachineRegisterInfo *MRI = &MF.getRegInfo();
420 std::pair<unsigned, unsigned> Hint = MRI->getRegAllocationHint(Reg);
421 if ((Hint.first == (unsigned)ARMRI::RegPairOdd ||
422 Hint.first == (unsigned)ARMRI::RegPairEven) &&
423 Hint.second && TargetRegisterInfo::isVirtualRegister(Hint.second)) {
424 // If 'Reg' is one of the even / odd register pair and it's now changed
425 // (e.g. coalesced) into a different register. The other register of the
426 // pair allocation hint must be updated to reflect the relationship
428 unsigned OtherReg = Hint.second;
429 Hint = MRI->getRegAllocationHint(OtherReg);
430 if (Hint.second == Reg)
431 // Make sure the pair has not already divorced.
432 MRI->setRegAllocationHint(OtherReg, Hint.first, NewReg);
436 /// hasFP - Return true if the specified function should have a dedicated frame
437 /// pointer register. This is true if the function has variable sized allocas
438 /// or if frame pointer elimination is disabled.
440 bool ARMBaseRegisterInfo::hasFP(const MachineFunction &MF) const {
441 const MachineFrameInfo *MFI = MF.getFrameInfo();
442 return (NoFramePointerElim ||
443 MFI->hasVarSizedObjects() ||
444 MFI->isFrameAddressTaken());
447 bool ARMBaseRegisterInfo::cannotEliminateFrame(const MachineFunction &MF) const {
448 const MachineFrameInfo *MFI = MF.getFrameInfo();
449 if (NoFramePointerElim && MFI->hasCalls())
451 return MFI->hasVarSizedObjects() || MFI->isFrameAddressTaken();
454 /// estimateStackSize - Estimate and return the size of the frame.
455 static unsigned estimateStackSize(MachineFunction &MF, MachineFrameInfo *MFI) {
456 const MachineFrameInfo *FFI = MF.getFrameInfo();
458 for (int i = FFI->getObjectIndexBegin(); i != 0; ++i) {
459 int FixedOff = -FFI->getObjectOffset(i);
460 if (FixedOff > Offset) Offset = FixedOff;
462 for (unsigned i = 0, e = FFI->getObjectIndexEnd(); i != e; ++i) {
463 if (FFI->isDeadObjectIndex(i))
465 Offset += FFI->getObjectSize(i);
466 unsigned Align = FFI->getObjectAlignment(i);
467 // Adjust to alignment boundary
468 Offset = (Offset+Align-1)/Align*Align;
470 return (unsigned)Offset;
473 /// estimateRSStackSizeLimit - Look at each instruction that references stack
474 /// frames and return the stack size limit beyond which some of these
475 /// instructions will require scratch register during their expansion later.
477 ARMBaseRegisterInfo::estimateRSStackSizeLimit(MachineFunction &MF) const {
478 unsigned Limit = (1 << 12) - 1;
479 for (MachineFunction::iterator BB = MF.begin(),E = MF.end(); BB != E; ++BB) {
480 for (MachineBasicBlock::iterator I = BB->begin(), E = BB->end();
482 for (unsigned i = 0, e = I->getNumOperands(); i != e; ++i) {
483 if (!I->getOperand(i).isFI()) continue;
485 const TargetInstrDesc &Desc = TII.get(I->getOpcode());
486 unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
487 if (AddrMode == ARMII::AddrMode3 ||
488 AddrMode == ARMII::AddrModeT2_i8)
491 if (AddrMode == ARMII::AddrMode5 ||
492 AddrMode == ARMII::AddrModeT2_i8s4)
493 Limit = std::min(Limit, ((1U << 8) - 1) * 4);
495 if (AddrMode == ARMII::AddrModeT2_i12 && hasFP(MF))
496 // When the stack offset is negative, we will end up using
497 // the i8 instructions instead.
499 break; // At most one FI per instruction
508 ARMBaseRegisterInfo::processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
509 RegScavenger *RS) const {
510 // This tells PEI to spill the FP as if it is any other callee-save register
511 // to take advantage the eliminateFrameIndex machinery. This also ensures it
512 // is spilled in the order specified by getCalleeSavedRegs() to make it easier
513 // to combine multiple loads / stores.
514 bool CanEliminateFrame = true;
515 bool CS1Spilled = false;
516 bool LRSpilled = false;
517 unsigned NumGPRSpills = 0;
518 SmallVector<unsigned, 4> UnspilledCS1GPRs;
519 SmallVector<unsigned, 4> UnspilledCS2GPRs;
520 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
522 // Don't spill FP if the frame can be eliminated. This is determined
523 // by scanning the callee-save registers to see if any is used.
524 const unsigned *CSRegs = getCalleeSavedRegs();
525 const TargetRegisterClass* const *CSRegClasses = getCalleeSavedRegClasses();
526 for (unsigned i = 0; CSRegs[i]; ++i) {
527 unsigned Reg = CSRegs[i];
528 bool Spilled = false;
529 if (MF.getRegInfo().isPhysRegUsed(Reg)) {
530 AFI->setCSRegisterIsSpilled(Reg);
532 CanEliminateFrame = false;
534 // Check alias registers too.
535 for (const unsigned *Aliases = getAliasSet(Reg); *Aliases; ++Aliases) {
536 if (MF.getRegInfo().isPhysRegUsed(*Aliases)) {
538 CanEliminateFrame = false;
543 if (CSRegClasses[i] == ARM::GPRRegisterClass) {
547 if (!STI.isTargetDarwin()) {
554 // Keep track if LR and any of R4, R5, R6, and R7 is spilled.
569 if (!STI.isTargetDarwin()) {
570 UnspilledCS1GPRs.push_back(Reg);
580 UnspilledCS1GPRs.push_back(Reg);
583 UnspilledCS2GPRs.push_back(Reg);
590 bool ForceLRSpill = false;
591 if (!LRSpilled && AFI->isThumb1OnlyFunction()) {
592 unsigned FnSize = TII.GetFunctionSizeInBytes(MF);
593 // Force LR to be spilled if the Thumb function size is > 2048. This enables
594 // use of BL to implement far jump. If it turns out that it's not needed
595 // then the branch fix up path will undo it.
596 if (FnSize >= (1 << 11)) {
597 CanEliminateFrame = false;
602 bool ExtraCSSpill = false;
603 if (!CanEliminateFrame || cannotEliminateFrame(MF)) {
604 AFI->setHasStackFrame(true);
606 // If LR is not spilled, but at least one of R4, R5, R6, and R7 is spilled.
607 // Spill LR as well so we can fold BX_RET to the registers restore (LDM).
608 if (!LRSpilled && CS1Spilled) {
609 MF.getRegInfo().setPhysRegUsed(ARM::LR);
610 AFI->setCSRegisterIsSpilled(ARM::LR);
612 UnspilledCS1GPRs.erase(std::find(UnspilledCS1GPRs.begin(),
613 UnspilledCS1GPRs.end(), (unsigned)ARM::LR));
614 ForceLRSpill = false;
618 // Darwin ABI requires FP to point to the stack slot that contains the
620 if (STI.isTargetDarwin() || hasFP(MF)) {
621 MF.getRegInfo().setPhysRegUsed(FramePtr);
625 // If stack and double are 8-byte aligned and we are spilling an odd number
626 // of GPRs. Spill one extra callee save GPR so we won't have to pad between
627 // the integer and double callee save areas.
628 unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment();
629 if (TargetAlign == 8 && (NumGPRSpills & 1)) {
630 if (CS1Spilled && !UnspilledCS1GPRs.empty()) {
631 for (unsigned i = 0, e = UnspilledCS1GPRs.size(); i != e; ++i) {
632 unsigned Reg = UnspilledCS1GPRs[i];
633 // Don't spill high register if the function is thumb1
634 if (!AFI->isThumb1OnlyFunction() ||
635 isARMLowRegister(Reg) || Reg == ARM::LR) {
636 MF.getRegInfo().setPhysRegUsed(Reg);
637 AFI->setCSRegisterIsSpilled(Reg);
638 if (!isReservedReg(MF, Reg))
643 } else if (!UnspilledCS2GPRs.empty() &&
644 !AFI->isThumb1OnlyFunction()) {
645 unsigned Reg = UnspilledCS2GPRs.front();
646 MF.getRegInfo().setPhysRegUsed(Reg);
647 AFI->setCSRegisterIsSpilled(Reg);
648 if (!isReservedReg(MF, Reg))
653 // Estimate if we might need to scavenge a register at some point in order
654 // to materialize a stack offset. If so, either spill one additional
655 // callee-saved register or reserve a special spill slot to facilitate
656 // register scavenging.
657 if (RS && !ExtraCSSpill && !AFI->isThumb1OnlyFunction()) {
658 MachineFrameInfo *MFI = MF.getFrameInfo();
659 if (estimateStackSize(MF, MFI) >= estimateRSStackSizeLimit(MF)) {
660 // If any non-reserved CS register isn't spilled, just spill one or two
661 // extra. That should take care of it!
662 unsigned NumExtras = TargetAlign / 4;
663 SmallVector<unsigned, 2> Extras;
664 while (NumExtras && !UnspilledCS1GPRs.empty()) {
665 unsigned Reg = UnspilledCS1GPRs.back();
666 UnspilledCS1GPRs.pop_back();
667 if (!isReservedReg(MF, Reg)) {
668 Extras.push_back(Reg);
672 while (NumExtras && !UnspilledCS2GPRs.empty()) {
673 unsigned Reg = UnspilledCS2GPRs.back();
674 UnspilledCS2GPRs.pop_back();
675 if (!isReservedReg(MF, Reg)) {
676 Extras.push_back(Reg);
680 if (Extras.size() && NumExtras == 0) {
681 for (unsigned i = 0, e = Extras.size(); i != e; ++i) {
682 MF.getRegInfo().setPhysRegUsed(Extras[i]);
683 AFI->setCSRegisterIsSpilled(Extras[i]);
686 // Reserve a slot closest to SP or frame pointer.
687 const TargetRegisterClass *RC = ARM::GPRRegisterClass;
688 RS->setScavengingFrameIndex(MFI->CreateStackObject(RC->getSize(),
689 RC->getAlignment()));
696 MF.getRegInfo().setPhysRegUsed(ARM::LR);
697 AFI->setCSRegisterIsSpilled(ARM::LR);
698 AFI->setLRIsSpilledForFarJump(true);
702 unsigned ARMBaseRegisterInfo::getRARegister() const {
706 unsigned ARMBaseRegisterInfo::getFrameRegister(MachineFunction &MF) const {
707 if (STI.isTargetDarwin() || hasFP(MF))
712 unsigned ARMBaseRegisterInfo::getEHExceptionRegister() const {
713 llvm_unreachable("What is the exception register");
717 unsigned ARMBaseRegisterInfo::getEHHandlerRegister() const {
718 llvm_unreachable("What is the exception handler register");
722 int ARMBaseRegisterInfo::getDwarfRegNum(unsigned RegNum, bool isEH) const {
723 return ARMGenRegisterInfo::getDwarfRegNumFull(RegNum, 0);
726 unsigned ARMBaseRegisterInfo::getRegisterPairEven(unsigned Reg,
727 const MachineFunction &MF) const {
730 // Return 0 if either register of the pair is a special register.
736 return STI.isThumb1Only() ? 0 : ARM::R2;
740 return isReservedReg(MF, ARM::R7) ? 0 : ARM::R6;
742 return isReservedReg(MF, ARM::R9) ? 0 :ARM::R8;
744 return isReservedReg(MF, ARM::R11) ? 0 : ARM::R10;
816 unsigned ARMBaseRegisterInfo::getRegisterPairOdd(unsigned Reg,
817 const MachineFunction &MF) const {
820 // Return 0 if either register of the pair is a special register.
826 return STI.isThumb1Only() ? 0 : ARM::R3;
830 return isReservedReg(MF, ARM::R7) ? 0 : ARM::R7;
832 return isReservedReg(MF, ARM::R9) ? 0 :ARM::R9;
834 return isReservedReg(MF, ARM::R11) ? 0 : ARM::R11;
906 /// emitLoadConstPool - Emits a load from constpool to materialize the
907 /// specified immediate.
908 void ARMBaseRegisterInfo::
909 emitLoadConstPool(MachineBasicBlock &MBB,
910 MachineBasicBlock::iterator &MBBI,
912 unsigned DestReg, unsigned SubIdx, int Val,
913 ARMCC::CondCodes Pred,
914 unsigned PredReg) const {
915 MachineFunction &MF = *MBB.getParent();
916 MachineConstantPool *ConstantPool = MF.getConstantPool();
918 ConstantInt::get(Type::getInt32Ty(MF.getFunction()->getContext()), Val);
919 unsigned Idx = ConstantPool->getConstantPoolIndex(C, 4);
921 BuildMI(MBB, MBBI, dl, TII.get(ARM::LDRcp))
922 .addReg(DestReg, getDefRegState(true), SubIdx)
923 .addConstantPoolIndex(Idx)
924 .addReg(0).addImm(0).addImm(Pred).addReg(PredReg);
927 bool ARMBaseRegisterInfo::
928 requiresRegisterScavenging(const MachineFunction &MF) const {
932 // hasReservedCallFrame - Under normal circumstances, when a frame pointer is
933 // not required, we reserve argument space for call sites in the function
934 // immediately on entry to the current function. This eliminates the need for
935 // add/sub sp brackets around call sites. Returns true if the call frame is
936 // included as part of the stack frame.
937 bool ARMBaseRegisterInfo::
938 hasReservedCallFrame(MachineFunction &MF) const {
939 const MachineFrameInfo *FFI = MF.getFrameInfo();
940 unsigned CFSize = FFI->getMaxCallFrameSize();
941 // It's not always a good idea to include the call frame as part of the
942 // stack frame. ARM (especially Thumb) has small immediate offset to
943 // address the stack frame. So a large call frame can cause poor codegen
944 // and may even makes it impossible to scavenge a register.
945 if (CFSize >= ((1 << 12) - 1) / 2) // Half of imm12
948 return !MF.getFrameInfo()->hasVarSizedObjects();
952 emitSPUpdate(bool isARM,
953 MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,
954 DebugLoc dl, const ARMBaseInstrInfo &TII,
956 ARMCC::CondCodes Pred = ARMCC::AL, unsigned PredReg = 0) {
958 emitARMRegPlusImmediate(MBB, MBBI, dl, ARM::SP, ARM::SP, NumBytes,
961 emitT2RegPlusImmediate(MBB, MBBI, dl, ARM::SP, ARM::SP, NumBytes,
966 void ARMBaseRegisterInfo::
967 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
968 MachineBasicBlock::iterator I) const {
969 if (!hasReservedCallFrame(MF)) {
970 // If we have alloca, convert as follows:
971 // ADJCALLSTACKDOWN -> sub, sp, sp, amount
972 // ADJCALLSTACKUP -> add, sp, sp, amount
973 MachineInstr *Old = I;
974 DebugLoc dl = Old->getDebugLoc();
975 unsigned Amount = Old->getOperand(0).getImm();
977 // We need to keep the stack aligned properly. To do this, we round the
978 // amount of space needed for the outgoing arguments up to the next
979 // alignment boundary.
980 unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
981 Amount = (Amount+Align-1)/Align*Align;
983 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
984 assert(!AFI->isThumb1OnlyFunction() &&
985 "This eliminateCallFramePseudoInstr does not suppor Thumb1!");
986 bool isARM = !AFI->isThumbFunction();
988 // Replace the pseudo instruction with a new instruction...
989 unsigned Opc = Old->getOpcode();
990 ARMCC::CondCodes Pred = (ARMCC::CondCodes)Old->getOperand(1).getImm();
991 // FIXME: Thumb2 version of ADJCALLSTACKUP and ADJCALLSTACKDOWN?
992 if (Opc == ARM::ADJCALLSTACKDOWN || Opc == ARM::tADJCALLSTACKDOWN) {
993 // Note: PredReg is operand 2 for ADJCALLSTACKDOWN.
994 unsigned PredReg = Old->getOperand(2).getReg();
995 emitSPUpdate(isARM, MBB, I, dl, TII, -Amount, Pred, PredReg);
997 // Note: PredReg is operand 3 for ADJCALLSTACKUP.
998 unsigned PredReg = Old->getOperand(3).getReg();
999 assert(Opc == ARM::ADJCALLSTACKUP || Opc == ARM::tADJCALLSTACKUP);
1000 emitSPUpdate(isARM, MBB, I, dl, TII, Amount, Pred, PredReg);
1007 /// findScratchRegister - Find a 'free' ARM register. If register scavenger
1008 /// is not being used, R12 is available. Otherwise, try for a call-clobbered
1009 /// register first and then a spilled callee-saved register if that fails.
1011 unsigned findScratchRegister(RegScavenger *RS, const TargetRegisterClass *RC,
1012 ARMFunctionInfo *AFI) {
1013 unsigned Reg = RS ? RS->FindUnusedReg(RC) : (unsigned) ARM::R12;
1014 assert(!AFI->isThumb1OnlyFunction());
1019 ARMBaseRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
1020 int SPAdj, RegScavenger *RS) const {
1022 MachineInstr &MI = *II;
1023 MachineBasicBlock &MBB = *MI.getParent();
1024 MachineFunction &MF = *MBB.getParent();
1025 const MachineFrameInfo *MFI = MF.getFrameInfo();
1026 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1027 assert(!AFI->isThumb1OnlyFunction() &&
1028 "This eliminateFrameIndex does not suppor Thumb1!");
1030 while (!MI.getOperand(i).isFI()) {
1032 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
1035 unsigned FrameReg = ARM::SP;
1036 int FrameIndex = MI.getOperand(i).getIndex();
1037 int Offset = MFI->getObjectOffset(FrameIndex) + MFI->getStackSize() + SPAdj;
1039 if (AFI->isGPRCalleeSavedArea1Frame(FrameIndex))
1040 Offset -= AFI->getGPRCalleeSavedArea1Offset();
1041 else if (AFI->isGPRCalleeSavedArea2Frame(FrameIndex))
1042 Offset -= AFI->getGPRCalleeSavedArea2Offset();
1043 else if (AFI->isDPRCalleeSavedAreaFrame(FrameIndex))
1044 Offset -= AFI->getDPRCalleeSavedAreaOffset();
1045 else if (hasFP(MF) && AFI->hasStackFrame()) {
1046 assert(SPAdj == 0 && "Unexpected stack offset!");
1047 // Use frame pointer to reference fixed objects unless this is a
1048 // frameless function,
1049 FrameReg = getFrameRegister(MF);
1050 Offset -= AFI->getFramePtrSpillOffset();
1053 // modify MI as necessary to handle as much of 'Offset' as possible
1055 if (!AFI->isThumbFunction())
1056 Done = rewriteARMFrameIndex(MI, i, FrameReg, Offset, TII);
1058 assert(AFI->isThumb2Function());
1059 Done = rewriteT2FrameIndex(MI, i, FrameReg, Offset, TII);
1064 // If we get here, the immediate doesn't fit into the instruction. We folded
1065 // as much as possible above, handle the rest, providing a register that is
1068 (MI.getDesc().TSFlags & ARMII::AddrModeMask) == ARMII::AddrMode4) &&
1069 "This code isn't needed if offset already handled!");
1071 // Insert a set of r12 with the full address: r12 = sp + offset
1072 // If the offset we have is too large to fit into the instruction, we need
1073 // to form it with a series of ADDri's. Do this by taking 8-bit chunks
1075 unsigned ScratchReg = findScratchRegister(RS, ARM::GPRRegisterClass, AFI);
1076 if (ScratchReg == 0)
1077 // No register is "free". Scavenge a register.
1078 ScratchReg = RS->scavengeRegister(ARM::GPRRegisterClass, II, SPAdj);
1079 int PIdx = MI.findFirstPredOperandIdx();
1080 ARMCC::CondCodes Pred = (PIdx == -1)
1081 ? ARMCC::AL : (ARMCC::CondCodes)MI.getOperand(PIdx).getImm();
1082 unsigned PredReg = (PIdx == -1) ? 0 : MI.getOperand(PIdx+1).getReg();
1084 // Must be addrmode4.
1085 MI.getOperand(i).ChangeToRegister(FrameReg, false, false, false);
1087 if (!AFI->isThumbFunction())
1088 emitARMRegPlusImmediate(MBB, II, MI.getDebugLoc(), ScratchReg, FrameReg,
1089 Offset, Pred, PredReg, TII);
1091 assert(AFI->isThumb2Function());
1092 emitT2RegPlusImmediate(MBB, II, MI.getDebugLoc(), ScratchReg, FrameReg,
1093 Offset, Pred, PredReg, TII);
1095 MI.getOperand(i).ChangeToRegister(ScratchReg, false, false, true);
1099 /// Move iterator pass the next bunch of callee save load / store ops for
1100 /// the particular spill area (1: integer area 1, 2: integer area 2,
1101 /// 3: fp area, 0: don't care).
1102 static void movePastCSLoadStoreOps(MachineBasicBlock &MBB,
1103 MachineBasicBlock::iterator &MBBI,
1104 int Opc1, int Opc2, unsigned Area,
1105 const ARMSubtarget &STI) {
1106 while (MBBI != MBB.end() &&
1107 ((MBBI->getOpcode() == Opc1) || (MBBI->getOpcode() == Opc2)) &&
1108 MBBI->getOperand(1).isFI()) {
1111 unsigned Category = 0;
1112 switch (MBBI->getOperand(0).getReg()) {
1113 case ARM::R4: case ARM::R5: case ARM::R6: case ARM::R7:
1117 case ARM::R8: case ARM::R9: case ARM::R10: case ARM::R11:
1118 Category = STI.isTargetDarwin() ? 2 : 1;
1120 case ARM::D8: case ARM::D9: case ARM::D10: case ARM::D11:
1121 case ARM::D12: case ARM::D13: case ARM::D14: case ARM::D15:
1128 if (Done || Category != Area)
1136 void ARMBaseRegisterInfo::
1137 emitPrologue(MachineFunction &MF) const {
1138 MachineBasicBlock &MBB = MF.front();
1139 MachineBasicBlock::iterator MBBI = MBB.begin();
1140 MachineFrameInfo *MFI = MF.getFrameInfo();
1141 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1142 assert(!AFI->isThumb1OnlyFunction() &&
1143 "This emitPrologue does not suppor Thumb1!");
1144 bool isARM = !AFI->isThumbFunction();
1145 unsigned VARegSaveSize = AFI->getVarArgsRegSaveSize();
1146 unsigned NumBytes = MFI->getStackSize();
1147 const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
1148 DebugLoc dl = (MBBI != MBB.end() ?
1149 MBBI->getDebugLoc() : DebugLoc::getUnknownLoc());
1151 // Determine the sizes of each callee-save spill areas and record which frame
1152 // belongs to which callee-save spill areas.
1153 unsigned GPRCS1Size = 0, GPRCS2Size = 0, DPRCSSize = 0;
1154 int FramePtrSpillFI = 0;
1157 emitSPUpdate(isARM, MBB, MBBI, dl, TII, -VARegSaveSize);
1159 if (!AFI->hasStackFrame()) {
1161 emitSPUpdate(isARM, MBB, MBBI, dl, TII, -NumBytes);
1165 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
1166 unsigned Reg = CSI[i].getReg();
1167 int FI = CSI[i].getFrameIdx();
1174 if (Reg == FramePtr)
1175 FramePtrSpillFI = FI;
1176 AFI->addGPRCalleeSavedArea1Frame(FI);
1183 if (Reg == FramePtr)
1184 FramePtrSpillFI = FI;
1185 if (STI.isTargetDarwin()) {
1186 AFI->addGPRCalleeSavedArea2Frame(FI);
1189 AFI->addGPRCalleeSavedArea1Frame(FI);
1194 AFI->addDPRCalleeSavedAreaFrame(FI);
1199 // Build the new SUBri to adjust SP for integer callee-save spill area 1.
1200 emitSPUpdate(isARM, MBB, MBBI, dl, TII, -GPRCS1Size);
1201 movePastCSLoadStoreOps(MBB, MBBI, ARM::STR, ARM::t2STRi12, 1, STI);
1203 // Darwin ABI requires FP to point to the stack slot that contains the
1205 if (STI.isTargetDarwin() || hasFP(MF)) {
1206 unsigned ADDriOpc = !AFI->isThumbFunction() ? ARM::ADDri : ARM::t2ADDri;
1207 MachineInstrBuilder MIB =
1208 BuildMI(MBB, MBBI, dl, TII.get(ADDriOpc), FramePtr)
1209 .addFrameIndex(FramePtrSpillFI).addImm(0);
1210 AddDefaultCC(AddDefaultPred(MIB));
1213 // Build the new SUBri to adjust SP for integer callee-save spill area 2.
1214 emitSPUpdate(isARM, MBB, MBBI, dl, TII, -GPRCS2Size);
1216 // Build the new SUBri to adjust SP for FP callee-save spill area.
1217 movePastCSLoadStoreOps(MBB, MBBI, ARM::STR, ARM::t2STRi12, 2, STI);
1218 emitSPUpdate(isARM, MBB, MBBI, dl, TII, -DPRCSSize);
1220 // Determine starting offsets of spill areas.
1221 unsigned DPRCSOffset = NumBytes - (GPRCS1Size + GPRCS2Size + DPRCSSize);
1222 unsigned GPRCS2Offset = DPRCSOffset + DPRCSSize;
1223 unsigned GPRCS1Offset = GPRCS2Offset + GPRCS2Size;
1224 AFI->setFramePtrSpillOffset(MFI->getObjectOffset(FramePtrSpillFI) + NumBytes);
1225 AFI->setGPRCalleeSavedArea1Offset(GPRCS1Offset);
1226 AFI->setGPRCalleeSavedArea2Offset(GPRCS2Offset);
1227 AFI->setDPRCalleeSavedAreaOffset(DPRCSOffset);
1229 NumBytes = DPRCSOffset;
1231 // Insert it after all the callee-save spills.
1232 movePastCSLoadStoreOps(MBB, MBBI, ARM::FSTD, 0, 3, STI);
1233 emitSPUpdate(isARM, MBB, MBBI, dl, TII, -NumBytes);
1236 if (STI.isTargetELF() && hasFP(MF)) {
1237 MFI->setOffsetAdjustment(MFI->getOffsetAdjustment() -
1238 AFI->getFramePtrSpillOffset());
1241 AFI->setGPRCalleeSavedArea1Size(GPRCS1Size);
1242 AFI->setGPRCalleeSavedArea2Size(GPRCS2Size);
1243 AFI->setDPRCalleeSavedAreaSize(DPRCSSize);
1246 static bool isCalleeSavedRegister(unsigned Reg, const unsigned *CSRegs) {
1247 for (unsigned i = 0; CSRegs[i]; ++i)
1248 if (Reg == CSRegs[i])
1253 static bool isCSRestore(MachineInstr *MI,
1254 const ARMBaseInstrInfo &TII,
1255 const unsigned *CSRegs) {
1256 return ((MI->getOpcode() == (int)ARM::FLDD ||
1257 MI->getOpcode() == (int)ARM::LDR ||
1258 MI->getOpcode() == (int)ARM::t2LDRi12) &&
1259 MI->getOperand(1).isFI() &&
1260 isCalleeSavedRegister(MI->getOperand(0).getReg(), CSRegs));
1263 void ARMBaseRegisterInfo::
1264 emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const {
1265 MachineBasicBlock::iterator MBBI = prior(MBB.end());
1266 assert(MBBI->getDesc().isReturn() &&
1267 "Can only insert epilog into returning blocks");
1268 DebugLoc dl = MBBI->getDebugLoc();
1269 MachineFrameInfo *MFI = MF.getFrameInfo();
1270 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1271 assert(!AFI->isThumb1OnlyFunction() &&
1272 "This emitEpilogue does not suppor Thumb1!");
1273 bool isARM = !AFI->isThumbFunction();
1275 unsigned VARegSaveSize = AFI->getVarArgsRegSaveSize();
1276 int NumBytes = (int)MFI->getStackSize();
1278 if (!AFI->hasStackFrame()) {
1280 emitSPUpdate(isARM, MBB, MBBI, dl, TII, NumBytes);
1282 // Unwind MBBI to point to first LDR / FLDD.
1283 const unsigned *CSRegs = getCalleeSavedRegs();
1284 if (MBBI != MBB.begin()) {
1287 while (MBBI != MBB.begin() && isCSRestore(MBBI, TII, CSRegs));
1288 if (!isCSRestore(MBBI, TII, CSRegs))
1292 // Move SP to start of FP callee save spill area.
1293 NumBytes -= (AFI->getGPRCalleeSavedArea1Size() +
1294 AFI->getGPRCalleeSavedArea2Size() +
1295 AFI->getDPRCalleeSavedAreaSize());
1297 // Darwin ABI requires FP to point to the stack slot that contains the
1299 bool HasFP = hasFP(MF);
1300 if ((STI.isTargetDarwin() && NumBytes) || HasFP) {
1301 NumBytes = AFI->getFramePtrSpillOffset() - NumBytes;
1302 // Reset SP based on frame pointer only if the stack frame extends beyond
1303 // frame pointer stack slot or target is ELF and the function has FP.
1305 AFI->getGPRCalleeSavedArea2Size() ||
1306 AFI->getDPRCalleeSavedAreaSize() ||
1307 AFI->getDPRCalleeSavedAreaOffset()) {
1310 emitARMRegPlusImmediate(MBB, MBBI, dl, ARM::SP, FramePtr, -NumBytes,
1313 emitT2RegPlusImmediate(MBB, MBBI, dl, ARM::SP, FramePtr, -NumBytes,
1318 BuildMI(MBB, MBBI, dl, TII.get(ARM::MOVr), ARM::SP)
1320 .addImm((unsigned)ARMCC::AL).addReg(0).addReg(0);
1322 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVgpr2gpr), ARM::SP)
1326 } else if (NumBytes)
1327 emitSPUpdate(isARM, MBB, MBBI, dl, TII, NumBytes);
1329 // Move SP to start of integer callee save spill area 2.
1330 movePastCSLoadStoreOps(MBB, MBBI, ARM::FLDD, 0, 3, STI);
1331 emitSPUpdate(isARM, MBB, MBBI, dl, TII, AFI->getDPRCalleeSavedAreaSize());
1333 // Move SP to start of integer callee save spill area 1.
1334 movePastCSLoadStoreOps(MBB, MBBI, ARM::LDR, ARM::t2LDRi12, 2, STI);
1335 emitSPUpdate(isARM, MBB, MBBI, dl, TII, AFI->getGPRCalleeSavedArea2Size());
1337 // Move SP to SP upon entry to the function.
1338 movePastCSLoadStoreOps(MBB, MBBI, ARM::LDR, ARM::t2LDRi12, 1, STI);
1339 emitSPUpdate(isARM, MBB, MBBI, dl, TII, AFI->getGPRCalleeSavedArea1Size());
1343 emitSPUpdate(isARM, MBB, MBBI, dl, TII, VARegSaveSize);
1346 #include "ARMGenRegisterInfo.inc"