1 //===- ARMBaseRegisterInfo.cpp - ARM Register Information -------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the base ARM implementation of TargetRegisterInfo class.
12 //===----------------------------------------------------------------------===//
15 #include "ARMAddressingModes.h"
16 #include "ARMBaseInstrInfo.h"
17 #include "ARMBaseRegisterInfo.h"
18 #include "ARMFrameLowering.h"
19 #include "ARMInstrInfo.h"
20 #include "ARMMachineFunctionInfo.h"
21 #include "ARMSubtarget.h"
22 #include "llvm/Constants.h"
23 #include "llvm/DerivedTypes.h"
24 #include "llvm/Function.h"
25 #include "llvm/LLVMContext.h"
26 #include "llvm/CodeGen/MachineConstantPool.h"
27 #include "llvm/CodeGen/MachineFrameInfo.h"
28 #include "llvm/CodeGen/MachineFunction.h"
29 #include "llvm/CodeGen/MachineInstrBuilder.h"
30 #include "llvm/CodeGen/MachineLocation.h"
31 #include "llvm/CodeGen/MachineRegisterInfo.h"
32 #include "llvm/CodeGen/RegisterScavenging.h"
33 #include "llvm/Support/Debug.h"
34 #include "llvm/Support/ErrorHandling.h"
35 #include "llvm/Support/raw_ostream.h"
36 #include "llvm/Target/TargetFrameLowering.h"
37 #include "llvm/Target/TargetMachine.h"
38 #include "llvm/Target/TargetOptions.h"
39 #include "llvm/ADT/BitVector.h"
40 #include "llvm/ADT/SmallVector.h"
41 #include "llvm/Support/CommandLine.h"
46 ForceAllBaseRegAlloc("arm-force-base-reg-alloc", cl::Hidden, cl::init(false),
47 cl::desc("Force use of virtual base registers for stack load/store"));
49 EnableLocalStackAlloc("enable-local-stack-alloc", cl::init(true), cl::Hidden,
50 cl::desc("Enable pre-regalloc stack frame index allocation"));
52 EnableBasePointer("arm-use-base-pointer", cl::Hidden, cl::init(true),
53 cl::desc("Enable use of a base pointer for complex stack frames"));
55 ARMBaseRegisterInfo::ARMBaseRegisterInfo(const ARMBaseInstrInfo &tii,
56 const ARMSubtarget &sti)
57 : ARMGenRegisterInfo(ARM::ADJCALLSTACKDOWN, ARM::ADJCALLSTACKUP),
59 FramePtr((STI.isTargetDarwin() || STI.isThumb()) ? ARM::R7 : ARM::R11),
64 ARMBaseRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
65 static const unsigned CalleeSavedRegs[] = {
66 ARM::LR, ARM::R11, ARM::R10, ARM::R9, ARM::R8,
67 ARM::R7, ARM::R6, ARM::R5, ARM::R4,
69 ARM::D15, ARM::D14, ARM::D13, ARM::D12,
70 ARM::D11, ARM::D10, ARM::D9, ARM::D8,
74 static const unsigned DarwinCalleeSavedRegs[] = {
75 // Darwin ABI deviates from ARM standard ABI. R9 is not a callee-saved
77 ARM::LR, ARM::R7, ARM::R6, ARM::R5, ARM::R4,
78 ARM::R11, ARM::R10, ARM::R8,
80 ARM::D15, ARM::D14, ARM::D13, ARM::D12,
81 ARM::D11, ARM::D10, ARM::D9, ARM::D8,
84 return STI.isTargetDarwin() ? DarwinCalleeSavedRegs : CalleeSavedRegs;
87 BitVector ARMBaseRegisterInfo::
88 getReservedRegs(const MachineFunction &MF) const {
89 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
91 // FIXME: avoid re-calculating this every time.
92 BitVector Reserved(getNumRegs());
93 Reserved.set(ARM::SP);
94 Reserved.set(ARM::PC);
95 Reserved.set(ARM::FPSCR);
97 Reserved.set(FramePtr);
98 if (hasBasePointer(MF))
99 Reserved.set(BasePtr);
100 // Some targets reserve R9.
101 if (STI.isR9Reserved())
102 Reserved.set(ARM::R9);
106 bool ARMBaseRegisterInfo::isReservedReg(const MachineFunction &MF,
107 unsigned Reg) const {
108 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
116 if (hasBasePointer(MF))
121 if (FramePtr == Reg && TFI->hasFP(MF))
125 return STI.isR9Reserved();
131 const TargetRegisterClass *
132 ARMBaseRegisterInfo::getMatchingSuperRegClass(const TargetRegisterClass *A,
133 const TargetRegisterClass *B,
134 unsigned SubIdx) const {
142 if (A->getSize() == 8) {
143 if (B == &ARM::SPR_8RegClass)
144 return &ARM::DPR_8RegClass;
145 assert(B == &ARM::SPRRegClass && "Expecting SPR register class!");
146 if (A == &ARM::DPR_8RegClass)
148 return &ARM::DPR_VFP2RegClass;
151 if (A->getSize() == 16) {
152 if (B == &ARM::SPR_8RegClass)
153 return &ARM::QPR_8RegClass;
154 return &ARM::QPR_VFP2RegClass;
157 if (A->getSize() == 32) {
158 if (B == &ARM::SPR_8RegClass)
159 return 0; // Do not allow coalescing!
160 return &ARM::QQPR_VFP2RegClass;
163 assert(A->getSize() == 64 && "Expecting a QQQQ register class!");
164 return 0; // Do not allow coalescing!
171 if (A->getSize() == 16) {
172 if (B == &ARM::DPR_VFP2RegClass)
173 return &ARM::QPR_VFP2RegClass;
174 if (B == &ARM::DPR_8RegClass)
175 return 0; // Do not allow coalescing!
179 if (A->getSize() == 32) {
180 if (B == &ARM::DPR_VFP2RegClass)
181 return &ARM::QQPR_VFP2RegClass;
182 if (B == &ARM::DPR_8RegClass)
183 return 0; // Do not allow coalescing!
187 assert(A->getSize() == 64 && "Expecting a QQQQ register class!");
188 if (B != &ARM::DPRRegClass)
189 return 0; // Do not allow coalescing!
196 // D sub-registers of QQQQ registers.
197 if (A->getSize() == 64 && B == &ARM::DPRRegClass)
199 return 0; // Do not allow coalescing!
205 if (A->getSize() == 32) {
206 if (B == &ARM::QPR_VFP2RegClass)
207 return &ARM::QQPR_VFP2RegClass;
208 if (B == &ARM::QPR_8RegClass)
209 return 0; // Do not allow coalescing!
213 assert(A->getSize() == 64 && "Expecting a QQQQ register class!");
214 if (B == &ARM::QPRRegClass)
216 return 0; // Do not allow coalescing!
220 // Q sub-registers of QQQQ registers.
221 if (A->getSize() == 64 && B == &ARM::QPRRegClass)
223 return 0; // Do not allow coalescing!
230 ARMBaseRegisterInfo::canCombineSubRegIndices(const TargetRegisterClass *RC,
231 SmallVectorImpl<unsigned> &SubIndices,
232 unsigned &NewSubIdx) const {
234 unsigned Size = RC->getSize() * 8;
238 NewSubIdx = 0; // Whole register.
239 unsigned NumRegs = SubIndices.size();
241 // 8 D registers -> 1 QQQQ register.
242 return (Size == 512 &&
243 SubIndices[0] == ARM::dsub_0 &&
244 SubIndices[1] == ARM::dsub_1 &&
245 SubIndices[2] == ARM::dsub_2 &&
246 SubIndices[3] == ARM::dsub_3 &&
247 SubIndices[4] == ARM::dsub_4 &&
248 SubIndices[5] == ARM::dsub_5 &&
249 SubIndices[6] == ARM::dsub_6 &&
250 SubIndices[7] == ARM::dsub_7);
251 } else if (NumRegs == 4) {
252 if (SubIndices[0] == ARM::qsub_0) {
253 // 4 Q registers -> 1 QQQQ register.
254 return (Size == 512 &&
255 SubIndices[1] == ARM::qsub_1 &&
256 SubIndices[2] == ARM::qsub_2 &&
257 SubIndices[3] == ARM::qsub_3);
258 } else if (SubIndices[0] == ARM::dsub_0) {
259 // 4 D registers -> 1 QQ register.
261 SubIndices[1] == ARM::dsub_1 &&
262 SubIndices[2] == ARM::dsub_2 &&
263 SubIndices[3] == ARM::dsub_3) {
265 NewSubIdx = ARM::qqsub_0;
268 } else if (SubIndices[0] == ARM::dsub_4) {
269 // 4 D registers -> 1 QQ register (2nd).
271 SubIndices[1] == ARM::dsub_5 &&
272 SubIndices[2] == ARM::dsub_6 &&
273 SubIndices[3] == ARM::dsub_7) {
274 NewSubIdx = ARM::qqsub_1;
277 } else if (SubIndices[0] == ARM::ssub_0) {
278 // 4 S registers -> 1 Q register.
280 SubIndices[1] == ARM::ssub_1 &&
281 SubIndices[2] == ARM::ssub_2 &&
282 SubIndices[3] == ARM::ssub_3) {
284 NewSubIdx = ARM::qsub_0;
288 } else if (NumRegs == 2) {
289 if (SubIndices[0] == ARM::qsub_0) {
290 // 2 Q registers -> 1 QQ register.
291 if (Size >= 256 && SubIndices[1] == ARM::qsub_1) {
293 NewSubIdx = ARM::qqsub_0;
296 } else if (SubIndices[0] == ARM::qsub_2) {
297 // 2 Q registers -> 1 QQ register (2nd).
298 if (Size == 512 && SubIndices[1] == ARM::qsub_3) {
299 NewSubIdx = ARM::qqsub_1;
302 } else if (SubIndices[0] == ARM::dsub_0) {
303 // 2 D registers -> 1 Q register.
304 if (Size >= 128 && SubIndices[1] == ARM::dsub_1) {
306 NewSubIdx = ARM::qsub_0;
309 } else if (SubIndices[0] == ARM::dsub_2) {
310 // 2 D registers -> 1 Q register (2nd).
311 if (Size >= 256 && SubIndices[1] == ARM::dsub_3) {
312 NewSubIdx = ARM::qsub_1;
315 } else if (SubIndices[0] == ARM::dsub_4) {
316 // 2 D registers -> 1 Q register (3rd).
317 if (Size == 512 && SubIndices[1] == ARM::dsub_5) {
318 NewSubIdx = ARM::qsub_2;
321 } else if (SubIndices[0] == ARM::dsub_6) {
322 // 2 D registers -> 1 Q register (3rd).
323 if (Size == 512 && SubIndices[1] == ARM::dsub_7) {
324 NewSubIdx = ARM::qsub_3;
327 } else if (SubIndices[0] == ARM::ssub_0) {
328 // 2 S registers -> 1 D register.
329 if (SubIndices[1] == ARM::ssub_1) {
331 NewSubIdx = ARM::dsub_0;
334 } else if (SubIndices[0] == ARM::ssub_2) {
335 // 2 S registers -> 1 D register (2nd).
336 if (Size >= 128 && SubIndices[1] == ARM::ssub_3) {
337 NewSubIdx = ARM::dsub_1;
345 const TargetRegisterClass*
346 ARMBaseRegisterInfo::getLargestLegalSuperClass(const TargetRegisterClass *RC)
348 const TargetRegisterClass *Super = RC;
349 TargetRegisterClass::sc_iterator I = RC->superclasses_begin();
351 switch (Super->getID()) {
352 case ARM::GPRRegClassID:
353 case ARM::SPRRegClassID:
354 case ARM::DPRRegClassID:
355 case ARM::QPRRegClassID:
356 case ARM::QQPRRegClassID:
357 case ARM::QQQQPRRegClassID:
365 const TargetRegisterClass *
366 ARMBaseRegisterInfo::getPointerRegClass(unsigned Kind) const {
367 return ARM::GPRRegisterClass;
371 ARMBaseRegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC,
372 MachineFunction &MF) const {
373 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
375 switch (RC->getID()) {
378 case ARM::tGPRRegClassID:
379 return TFI->hasFP(MF) ? 4 : 5;
380 case ARM::GPRRegClassID: {
381 unsigned FP = TFI->hasFP(MF) ? 1 : 0;
382 return 10 - FP - (STI.isR9Reserved() ? 1 : 0);
384 case ARM::SPRRegClassID: // Currently not used as 'rep' register class.
385 case ARM::DPRRegClassID:
390 /// getAllocationOrder - Returns the register allocation order for a specified
391 /// register class in the form of a pair of TargetRegisterClass iterators.
392 std::pair<TargetRegisterClass::iterator,TargetRegisterClass::iterator>
393 ARMBaseRegisterInfo::getAllocationOrder(const TargetRegisterClass *RC,
394 unsigned HintType, unsigned HintReg,
395 const MachineFunction &MF) const {
396 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
397 // Alternative register allocation orders when favoring even / odd registers
398 // of register pairs.
400 // No FP, R9 is available.
401 static const unsigned GPREven1[] = {
402 ARM::R0, ARM::R2, ARM::R4, ARM::R6, ARM::R8, ARM::R10,
403 ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R7,
406 static const unsigned GPROdd1[] = {
407 ARM::R1, ARM::R3, ARM::R5, ARM::R7, ARM::R9, ARM::R11,
408 ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6,
412 // FP is R7, R9 is available.
413 static const unsigned GPREven2[] = {
414 ARM::R0, ARM::R2, ARM::R4, ARM::R8, ARM::R10,
415 ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R6,
418 static const unsigned GPROdd2[] = {
419 ARM::R1, ARM::R3, ARM::R5, ARM::R9, ARM::R11,
420 ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6,
424 // FP is R11, R9 is available.
425 static const unsigned GPREven3[] = {
426 ARM::R0, ARM::R2, ARM::R4, ARM::R6, ARM::R8,
427 ARM::R1, ARM::R3, ARM::R10,ARM::R12,ARM::LR, ARM::R5, ARM::R7,
430 static const unsigned GPROdd3[] = {
431 ARM::R1, ARM::R3, ARM::R5, ARM::R6, ARM::R9,
432 ARM::R0, ARM::R2, ARM::R10,ARM::R12,ARM::LR, ARM::R4, ARM::R7,
436 // No FP, R9 is not available.
437 static const unsigned GPREven4[] = {
438 ARM::R0, ARM::R2, ARM::R4, ARM::R6, ARM::R10,
439 ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R7, ARM::R8,
442 static const unsigned GPROdd4[] = {
443 ARM::R1, ARM::R3, ARM::R5, ARM::R7, ARM::R11,
444 ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6, ARM::R8,
448 // FP is R7, R9 is not available.
449 static const unsigned GPREven5[] = {
450 ARM::R0, ARM::R2, ARM::R4, ARM::R10,
451 ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R6, ARM::R8,
454 static const unsigned GPROdd5[] = {
455 ARM::R1, ARM::R3, ARM::R5, ARM::R11,
456 ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6, ARM::R8,
460 // FP is R11, R9 is not available.
461 static const unsigned GPREven6[] = {
462 ARM::R0, ARM::R2, ARM::R4, ARM::R6,
463 ARM::R1, ARM::R3, ARM::R10,ARM::R12,ARM::LR, ARM::R5, ARM::R7, ARM::R8
465 static const unsigned GPROdd6[] = {
466 ARM::R1, ARM::R3, ARM::R5, ARM::R7,
467 ARM::R0, ARM::R2, ARM::R10,ARM::R12,ARM::LR, ARM::R4, ARM::R6, ARM::R8
470 // We only support even/odd hints for GPR and rGPR.
471 if (RC != ARM::GPRRegisterClass && RC != ARM::rGPRRegisterClass)
472 return std::make_pair(RC->allocation_order_begin(MF),
473 RC->allocation_order_end(MF));
475 if (HintType == ARMRI::RegPairEven) {
476 if (isPhysicalRegister(HintReg) && getRegisterPairEven(HintReg, MF) == 0)
477 // It's no longer possible to fulfill this hint. Return the default
479 return std::make_pair(RC->allocation_order_begin(MF),
480 RC->allocation_order_end(MF));
482 if (!TFI->hasFP(MF)) {
483 if (!STI.isR9Reserved())
484 return std::make_pair(GPREven1,
485 GPREven1 + (sizeof(GPREven1)/sizeof(unsigned)));
487 return std::make_pair(GPREven4,
488 GPREven4 + (sizeof(GPREven4)/sizeof(unsigned)));
489 } else if (FramePtr == ARM::R7) {
490 if (!STI.isR9Reserved())
491 return std::make_pair(GPREven2,
492 GPREven2 + (sizeof(GPREven2)/sizeof(unsigned)));
494 return std::make_pair(GPREven5,
495 GPREven5 + (sizeof(GPREven5)/sizeof(unsigned)));
496 } else { // FramePtr == ARM::R11
497 if (!STI.isR9Reserved())
498 return std::make_pair(GPREven3,
499 GPREven3 + (sizeof(GPREven3)/sizeof(unsigned)));
501 return std::make_pair(GPREven6,
502 GPREven6 + (sizeof(GPREven6)/sizeof(unsigned)));
504 } else if (HintType == ARMRI::RegPairOdd) {
505 if (isPhysicalRegister(HintReg) && getRegisterPairOdd(HintReg, MF) == 0)
506 // It's no longer possible to fulfill this hint. Return the default
508 return std::make_pair(RC->allocation_order_begin(MF),
509 RC->allocation_order_end(MF));
511 if (!TFI->hasFP(MF)) {
512 if (!STI.isR9Reserved())
513 return std::make_pair(GPROdd1,
514 GPROdd1 + (sizeof(GPROdd1)/sizeof(unsigned)));
516 return std::make_pair(GPROdd4,
517 GPROdd4 + (sizeof(GPROdd4)/sizeof(unsigned)));
518 } else if (FramePtr == ARM::R7) {
519 if (!STI.isR9Reserved())
520 return std::make_pair(GPROdd2,
521 GPROdd2 + (sizeof(GPROdd2)/sizeof(unsigned)));
523 return std::make_pair(GPROdd5,
524 GPROdd5 + (sizeof(GPROdd5)/sizeof(unsigned)));
525 } else { // FramePtr == ARM::R11
526 if (!STI.isR9Reserved())
527 return std::make_pair(GPROdd3,
528 GPROdd3 + (sizeof(GPROdd3)/sizeof(unsigned)));
530 return std::make_pair(GPROdd6,
531 GPROdd6 + (sizeof(GPROdd6)/sizeof(unsigned)));
534 return std::make_pair(RC->allocation_order_begin(MF),
535 RC->allocation_order_end(MF));
538 /// ResolveRegAllocHint - Resolves the specified register allocation hint
539 /// to a physical register. Returns the physical register if it is successful.
541 ARMBaseRegisterInfo::ResolveRegAllocHint(unsigned Type, unsigned Reg,
542 const MachineFunction &MF) const {
543 if (Reg == 0 || !isPhysicalRegister(Reg))
547 else if (Type == (unsigned)ARMRI::RegPairOdd)
549 return getRegisterPairOdd(Reg, MF);
550 else if (Type == (unsigned)ARMRI::RegPairEven)
552 return getRegisterPairEven(Reg, MF);
557 ARMBaseRegisterInfo::UpdateRegAllocHint(unsigned Reg, unsigned NewReg,
558 MachineFunction &MF) const {
559 MachineRegisterInfo *MRI = &MF.getRegInfo();
560 std::pair<unsigned, unsigned> Hint = MRI->getRegAllocationHint(Reg);
561 if ((Hint.first == (unsigned)ARMRI::RegPairOdd ||
562 Hint.first == (unsigned)ARMRI::RegPairEven) &&
563 TargetRegisterInfo::isVirtualRegister(Hint.second)) {
564 // If 'Reg' is one of the even / odd register pair and it's now changed
565 // (e.g. coalesced) into a different register. The other register of the
566 // pair allocation hint must be updated to reflect the relationship
568 unsigned OtherReg = Hint.second;
569 Hint = MRI->getRegAllocationHint(OtherReg);
570 if (Hint.second == Reg)
571 // Make sure the pair has not already divorced.
572 MRI->setRegAllocationHint(OtherReg, Hint.first, NewReg);
577 ARMBaseRegisterInfo::avoidWriteAfterWrite(const TargetRegisterClass *RC) const {
578 // CortexA9 has a Write-after-write hazard for NEON registers.
579 if (!STI.isCortexA9())
582 switch (RC->getID()) {
583 case ARM::DPRRegClassID:
584 case ARM::DPR_8RegClassID:
585 case ARM::DPR_VFP2RegClassID:
586 case ARM::QPRRegClassID:
587 case ARM::QPR_8RegClassID:
588 case ARM::QPR_VFP2RegClassID:
589 case ARM::SPRRegClassID:
590 case ARM::SPR_8RegClassID:
591 // Avoid reusing S, D, and Q registers.
592 // Don't increase register pressure for QQ and QQQQ.
599 bool ARMBaseRegisterInfo::hasBasePointer(const MachineFunction &MF) const {
600 const MachineFrameInfo *MFI = MF.getFrameInfo();
601 const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
603 if (!EnableBasePointer)
606 if (needsStackRealignment(MF) && MFI->hasVarSizedObjects())
609 // Thumb has trouble with negative offsets from the FP. Thumb2 has a limited
610 // negative range for ldr/str (255), and thumb1 is positive offsets only.
611 // It's going to be better to use the SP or Base Pointer instead. When there
612 // are variable sized objects, we can't reference off of the SP, so we
613 // reserve a Base Pointer.
614 if (AFI->isThumbFunction() && MFI->hasVarSizedObjects()) {
615 // Conservatively estimate whether the negative offset from the frame
616 // pointer will be sufficient to reach. If a function has a smallish
617 // frame, it's less likely to have lots of spills and callee saved
618 // space, so it's all more likely to be within range of the frame pointer.
619 // If it's wrong, the scavenger will still enable access to work, it just
621 if (AFI->isThumb2Function() && MFI->getLocalFrameSize() < 128)
629 bool ARMBaseRegisterInfo::canRealignStack(const MachineFunction &MF) const {
630 const MachineFrameInfo *MFI = MF.getFrameInfo();
631 const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
632 // We can't realign the stack if:
633 // 1. Dynamic stack realignment is explicitly disabled,
634 // 2. This is a Thumb1 function (it's not useful, so we don't bother), or
635 // 3. There are VLAs in the function and the base pointer is disabled.
636 return (RealignStack && !AFI->isThumb1OnlyFunction() &&
637 (!MFI->hasVarSizedObjects() || EnableBasePointer));
640 bool ARMBaseRegisterInfo::
641 needsStackRealignment(const MachineFunction &MF) const {
642 const MachineFrameInfo *MFI = MF.getFrameInfo();
643 const Function *F = MF.getFunction();
644 unsigned StackAlign = MF.getTarget().getFrameLowering()->getStackAlignment();
645 bool requiresRealignment = ((MFI->getLocalFrameMaxAlign() > StackAlign) ||
646 F->hasFnAttr(Attribute::StackAlignment));
648 return requiresRealignment && canRealignStack(MF);
651 bool ARMBaseRegisterInfo::
652 cannotEliminateFrame(const MachineFunction &MF) const {
653 const MachineFrameInfo *MFI = MF.getFrameInfo();
654 if (DisableFramePointerElim(MF) && MFI->adjustsStack())
656 return MFI->hasVarSizedObjects() || MFI->isFrameAddressTaken()
657 || needsStackRealignment(MF);
660 unsigned ARMBaseRegisterInfo::getRARegister() const {
665 ARMBaseRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
666 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
673 unsigned ARMBaseRegisterInfo::getEHExceptionRegister() const {
674 llvm_unreachable("What is the exception register");
678 unsigned ARMBaseRegisterInfo::getEHHandlerRegister() const {
679 llvm_unreachable("What is the exception handler register");
683 int ARMBaseRegisterInfo::getDwarfRegNum(unsigned RegNum, bool isEH) const {
684 return ARMGenRegisterInfo::getDwarfRegNumFull(RegNum, 0);
687 int ARMBaseRegisterInfo::getLLVMRegNum(unsigned DwarfRegNo, bool isEH) const {
688 return ARMGenRegisterInfo::getLLVMRegNumFull(DwarfRegNo,0);
691 unsigned ARMBaseRegisterInfo::getRegisterPairEven(unsigned Reg,
692 const MachineFunction &MF) const {
695 // Return 0 if either register of the pair is a special register.
704 return (isReservedReg(MF, ARM::R7) || isReservedReg(MF, ARM::R6))
707 return isReservedReg(MF, ARM::R9) ? 0 :ARM::R8;
709 return isReservedReg(MF, ARM::R11) ? 0 : ARM::R10;
781 unsigned ARMBaseRegisterInfo::getRegisterPairOdd(unsigned Reg,
782 const MachineFunction &MF) const {
785 // Return 0 if either register of the pair is a special register.
794 return (isReservedReg(MF, ARM::R7) || isReservedReg(MF, ARM::R6))
797 return isReservedReg(MF, ARM::R9) ? 0 :ARM::R9;
799 return isReservedReg(MF, ARM::R11) ? 0 : ARM::R11;
871 /// emitLoadConstPool - Emits a load from constpool to materialize the
872 /// specified immediate.
873 void ARMBaseRegisterInfo::
874 emitLoadConstPool(MachineBasicBlock &MBB,
875 MachineBasicBlock::iterator &MBBI,
877 unsigned DestReg, unsigned SubIdx, int Val,
878 ARMCC::CondCodes Pred,
879 unsigned PredReg, unsigned MIFlags) const {
880 MachineFunction &MF = *MBB.getParent();
881 MachineConstantPool *ConstantPool = MF.getConstantPool();
883 ConstantInt::get(Type::getInt32Ty(MF.getFunction()->getContext()), Val);
884 unsigned Idx = ConstantPool->getConstantPoolIndex(C, 4);
886 BuildMI(MBB, MBBI, dl, TII.get(ARM::LDRcp))
887 .addReg(DestReg, getDefRegState(true), SubIdx)
888 .addConstantPoolIndex(Idx)
889 .addImm(0).addImm(Pred).addReg(PredReg)
890 .setMIFlags(MIFlags);
893 bool ARMBaseRegisterInfo::
894 requiresRegisterScavenging(const MachineFunction &MF) const {
898 bool ARMBaseRegisterInfo::
899 requiresFrameIndexScavenging(const MachineFunction &MF) const {
903 bool ARMBaseRegisterInfo::
904 requiresVirtualBaseRegisters(const MachineFunction &MF) const {
905 return EnableLocalStackAlloc;
909 emitSPUpdate(bool isARM,
910 MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,
911 DebugLoc dl, const ARMBaseInstrInfo &TII,
913 ARMCC::CondCodes Pred = ARMCC::AL, unsigned PredReg = 0) {
915 emitARMRegPlusImmediate(MBB, MBBI, dl, ARM::SP, ARM::SP, NumBytes,
918 emitT2RegPlusImmediate(MBB, MBBI, dl, ARM::SP, ARM::SP, NumBytes,
923 void ARMBaseRegisterInfo::
924 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
925 MachineBasicBlock::iterator I) const {
926 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
927 if (!TFI->hasReservedCallFrame(MF)) {
928 // If we have alloca, convert as follows:
929 // ADJCALLSTACKDOWN -> sub, sp, sp, amount
930 // ADJCALLSTACKUP -> add, sp, sp, amount
931 MachineInstr *Old = I;
932 DebugLoc dl = Old->getDebugLoc();
933 unsigned Amount = Old->getOperand(0).getImm();
935 // We need to keep the stack aligned properly. To do this, we round the
936 // amount of space needed for the outgoing arguments up to the next
937 // alignment boundary.
938 unsigned Align = TFI->getStackAlignment();
939 Amount = (Amount+Align-1)/Align*Align;
941 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
942 assert(!AFI->isThumb1OnlyFunction() &&
943 "This eliminateCallFramePseudoInstr does not support Thumb1!");
944 bool isARM = !AFI->isThumbFunction();
946 // Replace the pseudo instruction with a new instruction...
947 unsigned Opc = Old->getOpcode();
948 int PIdx = Old->findFirstPredOperandIdx();
949 ARMCC::CondCodes Pred = (PIdx == -1)
950 ? ARMCC::AL : (ARMCC::CondCodes)Old->getOperand(PIdx).getImm();
951 if (Opc == ARM::ADJCALLSTACKDOWN || Opc == ARM::tADJCALLSTACKDOWN) {
952 // Note: PredReg is operand 2 for ADJCALLSTACKDOWN.
953 unsigned PredReg = Old->getOperand(2).getReg();
954 emitSPUpdate(isARM, MBB, I, dl, TII, -Amount, Pred, PredReg);
956 // Note: PredReg is operand 3 for ADJCALLSTACKUP.
957 unsigned PredReg = Old->getOperand(3).getReg();
958 assert(Opc == ARM::ADJCALLSTACKUP || Opc == ARM::tADJCALLSTACKUP);
959 emitSPUpdate(isARM, MBB, I, dl, TII, Amount, Pred, PredReg);
966 int64_t ARMBaseRegisterInfo::
967 getFrameIndexInstrOffset(const MachineInstr *MI, int Idx) const {
968 const TargetInstrDesc &Desc = MI->getDesc();
969 unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
970 int64_t InstrOffs = 0;;
974 case ARMII::AddrModeT2_i8:
975 case ARMII::AddrModeT2_i12:
976 case ARMII::AddrMode_i12:
977 InstrOffs = MI->getOperand(Idx+1).getImm();
980 case ARMII::AddrMode5: {
982 const MachineOperand &OffOp = MI->getOperand(Idx+1);
983 InstrOffs = ARM_AM::getAM5Offset(OffOp.getImm());
984 if (ARM_AM::getAM5Op(OffOp.getImm()) == ARM_AM::sub)
985 InstrOffs = -InstrOffs;
989 case ARMII::AddrMode2: {
991 InstrOffs = ARM_AM::getAM2Offset(MI->getOperand(ImmIdx).getImm());
992 if (ARM_AM::getAM2Op(MI->getOperand(ImmIdx).getImm()) == ARM_AM::sub)
993 InstrOffs = -InstrOffs;
996 case ARMII::AddrMode3: {
998 InstrOffs = ARM_AM::getAM3Offset(MI->getOperand(ImmIdx).getImm());
999 if (ARM_AM::getAM3Op(MI->getOperand(ImmIdx).getImm()) == ARM_AM::sub)
1000 InstrOffs = -InstrOffs;
1003 case ARMII::AddrModeT1_s: {
1005 InstrOffs = MI->getOperand(ImmIdx).getImm();
1010 llvm_unreachable("Unsupported addressing mode!");
1014 return InstrOffs * Scale;
1017 /// needsFrameBaseReg - Returns true if the instruction's frame index
1018 /// reference would be better served by a base register other than FP
1019 /// or SP. Used by LocalStackFrameAllocation to determine which frame index
1020 /// references it should create new base registers for.
1021 bool ARMBaseRegisterInfo::
1022 needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const {
1023 for (unsigned i = 0; !MI->getOperand(i).isFI(); ++i) {
1024 assert(i < MI->getNumOperands() &&"Instr doesn't have FrameIndex operand!");
1027 // It's the load/store FI references that cause issues, as it can be difficult
1028 // to materialize the offset if it won't fit in the literal field. Estimate
1029 // based on the size of the local frame and some conservative assumptions
1030 // about the rest of the stack frame (note, this is pre-regalloc, so
1031 // we don't know everything for certain yet) whether this offset is likely
1032 // to be out of range of the immediate. Return true if so.
1034 // We only generate virtual base registers for loads and stores, so
1035 // return false for everything else.
1036 unsigned Opc = MI->getOpcode();
1038 case ARM::LDRi12: case ARM::LDRH: case ARM::LDRBi12:
1039 case ARM::STRi12: case ARM::STRH: case ARM::STRBi12:
1040 case ARM::t2LDRi12: case ARM::t2LDRi8:
1041 case ARM::t2STRi12: case ARM::t2STRi8:
1042 case ARM::VLDRS: case ARM::VLDRD:
1043 case ARM::VSTRS: case ARM::VSTRD:
1044 case ARM::tSTRspi: case ARM::tLDRspi:
1045 if (ForceAllBaseRegAlloc)
1052 // Without a virtual base register, if the function has variable sized
1053 // objects, all fixed-size local references will be via the frame pointer,
1054 // Approximate the offset and see if it's legal for the instruction.
1055 // Note that the incoming offset is based on the SP value at function entry,
1056 // so it'll be negative.
1057 MachineFunction &MF = *MI->getParent()->getParent();
1058 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
1059 MachineFrameInfo *MFI = MF.getFrameInfo();
1060 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1062 // Estimate an offset from the frame pointer.
1063 // Conservatively assume all callee-saved registers get pushed. R4-R6
1064 // will be earlier than the FP, so we ignore those.
1066 int64_t FPOffset = Offset - 8;
1067 // ARM and Thumb2 functions also need to consider R8-R11 and D8-D15
1068 if (!AFI->isThumbFunction() || !AFI->isThumb1OnlyFunction())
1070 // Estimate an offset from the stack pointer.
1071 // The incoming offset is relating to the SP at the start of the function,
1072 // but when we access the local it'll be relative to the SP after local
1073 // allocation, so adjust our SP-relative offset by that allocation size.
1075 Offset += MFI->getLocalFrameSize();
1076 // Assume that we'll have at least some spill slots allocated.
1077 // FIXME: This is a total SWAG number. We should run some statistics
1078 // and pick a real one.
1079 Offset += 128; // 128 bytes of spill slots
1081 // If there is a frame pointer, try using it.
1082 // The FP is only available if there is no dynamic realignment. We
1083 // don't know for sure yet whether we'll need that, so we guess based
1084 // on whether there are any local variables that would trigger it.
1085 unsigned StackAlign = TFI->getStackAlignment();
1086 if (TFI->hasFP(MF) &&
1087 !((MFI->getLocalFrameMaxAlign() > StackAlign) && canRealignStack(MF))) {
1088 if (isFrameOffsetLegal(MI, FPOffset))
1091 // If we can reference via the stack pointer, try that.
1092 // FIXME: This (and the code that resolves the references) can be improved
1093 // to only disallow SP relative references in the live range of
1094 // the VLA(s). In practice, it's unclear how much difference that
1095 // would make, but it may be worth doing.
1096 if (!MFI->hasVarSizedObjects() && isFrameOffsetLegal(MI, Offset))
1099 // The offset likely isn't legal, we want to allocate a virtual base register.
1103 /// materializeFrameBaseRegister - Insert defining instruction(s) for BaseReg to
1104 /// be a pointer to FrameIdx at the beginning of the basic block.
1105 void ARMBaseRegisterInfo::
1106 materializeFrameBaseRegister(MachineBasicBlock *MBB,
1107 unsigned BaseReg, int FrameIdx,
1108 int64_t Offset) const {
1109 ARMFunctionInfo *AFI = MBB->getParent()->getInfo<ARMFunctionInfo>();
1110 unsigned ADDriOpc = !AFI->isThumbFunction() ? ARM::ADDri :
1111 (AFI->isThumb1OnlyFunction() ? ARM::tADDrSPi : ARM::t2ADDri);
1113 MachineBasicBlock::iterator Ins = MBB->begin();
1114 DebugLoc DL; // Defaults to "unknown"
1115 if (Ins != MBB->end())
1116 DL = Ins->getDebugLoc();
1118 const TargetInstrDesc &TID = TII.get(ADDriOpc);
1119 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
1120 MRI.constrainRegClass(BaseReg, TID.OpInfo[0].getRegClass(this));
1122 MachineInstrBuilder MIB = BuildMI(*MBB, Ins, DL, TID, BaseReg)
1123 .addFrameIndex(FrameIdx).addImm(Offset);
1125 if (!AFI->isThumb1OnlyFunction())
1126 AddDefaultCC(AddDefaultPred(MIB));
1130 ARMBaseRegisterInfo::resolveFrameIndex(MachineBasicBlock::iterator I,
1131 unsigned BaseReg, int64_t Offset) const {
1132 MachineInstr &MI = *I;
1133 MachineBasicBlock &MBB = *MI.getParent();
1134 MachineFunction &MF = *MBB.getParent();
1135 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1136 int Off = Offset; // ARM doesn't need the general 64-bit offsets
1139 assert(!AFI->isThumb1OnlyFunction() &&
1140 "This resolveFrameIndex does not support Thumb1!");
1142 while (!MI.getOperand(i).isFI()) {
1144 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
1147 if (!AFI->isThumbFunction())
1148 Done = rewriteARMFrameIndex(MI, i, BaseReg, Off, TII);
1150 assert(AFI->isThumb2Function());
1151 Done = rewriteT2FrameIndex(MI, i, BaseReg, Off, TII);
1153 assert (Done && "Unable to resolve frame index!");
1156 bool ARMBaseRegisterInfo::isFrameOffsetLegal(const MachineInstr *MI,
1157 int64_t Offset) const {
1158 const TargetInstrDesc &Desc = MI->getDesc();
1159 unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
1162 while (!MI->getOperand(i).isFI()) {
1164 assert(i < MI->getNumOperands() &&"Instr doesn't have FrameIndex operand!");
1167 // AddrMode4 and AddrMode6 cannot handle any offset.
1168 if (AddrMode == ARMII::AddrMode4 || AddrMode == ARMII::AddrMode6)
1171 unsigned NumBits = 0;
1173 bool isSigned = true;
1175 case ARMII::AddrModeT2_i8:
1176 case ARMII::AddrModeT2_i12:
1177 // i8 supports only negative, and i12 supports only positive, so
1178 // based on Offset sign, consider the appropriate instruction
1187 case ARMII::AddrMode5:
1188 // VFP address mode.
1192 case ARMII::AddrMode_i12:
1193 case ARMII::AddrMode2:
1196 case ARMII::AddrMode3:
1199 case ARMII::AddrModeT1_s:
1205 llvm_unreachable("Unsupported addressing mode!");
1209 Offset += getFrameIndexInstrOffset(MI, i);
1210 // Make sure the offset is encodable for instructions that scale the
1212 if ((Offset & (Scale-1)) != 0)
1215 if (isSigned && Offset < 0)
1218 unsigned Mask = (1 << NumBits) - 1;
1219 if ((unsigned)Offset <= Mask * Scale)
1226 ARMBaseRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
1227 int SPAdj, RegScavenger *RS) const {
1229 MachineInstr &MI = *II;
1230 MachineBasicBlock &MBB = *MI.getParent();
1231 MachineFunction &MF = *MBB.getParent();
1232 const ARMFrameLowering *TFI =
1233 static_cast<const ARMFrameLowering*>(MF.getTarget().getFrameLowering());
1234 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1235 assert(!AFI->isThumb1OnlyFunction() &&
1236 "This eliminateFrameIndex does not support Thumb1!");
1238 while (!MI.getOperand(i).isFI()) {
1240 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
1243 int FrameIndex = MI.getOperand(i).getIndex();
1246 int Offset = TFI->ResolveFrameIndexReference(MF, FrameIndex, FrameReg, SPAdj);
1248 // Special handling of dbg_value instructions.
1249 if (MI.isDebugValue()) {
1250 MI.getOperand(i). ChangeToRegister(FrameReg, false /*isDef*/);
1251 MI.getOperand(i+1).ChangeToImmediate(Offset);
1255 // Modify MI as necessary to handle as much of 'Offset' as possible
1257 if (!AFI->isThumbFunction())
1258 Done = rewriteARMFrameIndex(MI, i, FrameReg, Offset, TII);
1260 assert(AFI->isThumb2Function());
1261 Done = rewriteT2FrameIndex(MI, i, FrameReg, Offset, TII);
1266 // If we get here, the immediate doesn't fit into the instruction. We folded
1267 // as much as possible above, handle the rest, providing a register that is
1270 (MI.getDesc().TSFlags & ARMII::AddrModeMask) == ARMII::AddrMode4 ||
1271 (MI.getDesc().TSFlags & ARMII::AddrModeMask) == ARMII::AddrMode6) &&
1272 "This code isn't needed if offset already handled!");
1274 unsigned ScratchReg = 0;
1275 int PIdx = MI.findFirstPredOperandIdx();
1276 ARMCC::CondCodes Pred = (PIdx == -1)
1277 ? ARMCC::AL : (ARMCC::CondCodes)MI.getOperand(PIdx).getImm();
1278 unsigned PredReg = (PIdx == -1) ? 0 : MI.getOperand(PIdx+1).getReg();
1280 // Must be addrmode4/6.
1281 MI.getOperand(i).ChangeToRegister(FrameReg, false, false, false);
1283 ScratchReg = MF.getRegInfo().createVirtualRegister(ARM::GPRRegisterClass);
1284 if (!AFI->isThumbFunction())
1285 emitARMRegPlusImmediate(MBB, II, MI.getDebugLoc(), ScratchReg, FrameReg,
1286 Offset, Pred, PredReg, TII);
1288 assert(AFI->isThumb2Function());
1289 emitT2RegPlusImmediate(MBB, II, MI.getDebugLoc(), ScratchReg, FrameReg,
1290 Offset, Pred, PredReg, TII);
1292 // Update the original instruction to use the scratch register.
1293 MI.getOperand(i).ChangeToRegister(ScratchReg, false, false, true);
1294 if (MI.getOpcode() == ARM::t2ADDrSPi)
1295 MI.setDesc(TII.get(ARM::t2ADDri));
1296 else if (MI.getOpcode() == ARM::t2SUBrSPi)
1297 MI.setDesc(TII.get(ARM::t2SUBri));
1301 #include "ARMGenRegisterInfo.inc"