1 //===-- ARMBaseRegisterInfo.cpp - ARM Register Information ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the base ARM implementation of TargetRegisterInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "ARMBaseRegisterInfo.h"
16 #include "ARMBaseInstrInfo.h"
17 #include "ARMFrameLowering.h"
18 #include "ARMMachineFunctionInfo.h"
19 #include "ARMSubtarget.h"
20 #include "MCTargetDesc/ARMAddressingModes.h"
21 #include "llvm/ADT/BitVector.h"
22 #include "llvm/ADT/SmallVector.h"
23 #include "llvm/CodeGen/MachineConstantPool.h"
24 #include "llvm/CodeGen/MachineFrameInfo.h"
25 #include "llvm/CodeGen/MachineFunction.h"
26 #include "llvm/CodeGen/MachineInstrBuilder.h"
27 #include "llvm/CodeGen/MachineRegisterInfo.h"
28 #include "llvm/CodeGen/RegisterScavenging.h"
29 #include "llvm/CodeGen/VirtRegMap.h"
30 #include "llvm/IR/Constants.h"
31 #include "llvm/IR/DerivedTypes.h"
32 #include "llvm/IR/Function.h"
33 #include "llvm/IR/LLVMContext.h"
34 #include "llvm/Support/Debug.h"
35 #include "llvm/Support/ErrorHandling.h"
36 #include "llvm/Support/raw_ostream.h"
37 #include "llvm/Target/TargetFrameLowering.h"
38 #include "llvm/Target/TargetMachine.h"
39 #include "llvm/Target/TargetOptions.h"
41 #define DEBUG_TYPE "arm-register-info"
43 #define GET_REGINFO_TARGET_DESC
44 #include "ARMGenRegisterInfo.inc"
48 ARMBaseRegisterInfo::ARMBaseRegisterInfo()
49 : ARMGenRegisterInfo(ARM::LR, 0, 0, ARM::PC), BasePtr(ARM::R6) {}
51 static unsigned getFramePointerReg(const ARMSubtarget &STI) {
52 if (STI.isTargetMachO()) {
53 if (STI.isTargetDarwin() || STI.isThumb1Only())
57 } else if (STI.isTargetWindows())
60 return STI.isThumb() ? ARM::R7 : ARM::R11;
64 ARMBaseRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
65 const ARMSubtarget &STI = MF->getSubtarget<ARMSubtarget>();
66 const MCPhysReg *RegList =
67 STI.isTargetDarwin() ? CSR_iOS_SaveList : CSR_AAPCS_SaveList;
69 const Function *F = MF->getFunction();
70 if (F->getCallingConv() == CallingConv::GHC) {
71 // GHC set of callee saved regs is empty as all those regs are
72 // used for passing STG regs around
73 return CSR_NoRegs_SaveList;
74 } else if (F->hasFnAttribute("interrupt")) {
76 // M-class CPUs have hardware which saves the registers needed to allow a
77 // function conforming to the AAPCS to function as a handler.
78 return CSR_AAPCS_SaveList;
79 } else if (F->getFnAttribute("interrupt").getValueAsString() == "FIQ") {
80 // Fast interrupt mode gives the handler a private copy of R8-R14, so less
81 // need to be saved to restore user-mode state.
82 return CSR_FIQ_SaveList;
84 // Generally only R13-R14 (i.e. SP, LR) are automatically preserved by
85 // exception handling.
86 return CSR_GenericInt_SaveList;
94 ARMBaseRegisterInfo::getCallPreservedMask(const MachineFunction &MF,
95 CallingConv::ID CC) const {
96 const ARMSubtarget &STI = MF.getSubtarget<ARMSubtarget>();
97 if (CC == CallingConv::GHC)
98 // This is academic becase all GHC calls are (supposed to be) tail calls
99 return CSR_NoRegs_RegMask;
100 return STI.isTargetDarwin() ? CSR_iOS_RegMask : CSR_AAPCS_RegMask;
104 ARMBaseRegisterInfo::getNoPreservedMask() const {
105 return CSR_NoRegs_RegMask;
109 ARMBaseRegisterInfo::getThisReturnPreservedMask(const MachineFunction &MF,
110 CallingConv::ID CC) const {
111 const ARMSubtarget &STI = MF.getSubtarget<ARMSubtarget>();
112 // This should return a register mask that is the same as that returned by
113 // getCallPreservedMask but that additionally preserves the register used for
114 // the first i32 argument (which must also be the register used to return a
115 // single i32 return value)
117 // In case that the calling convention does not use the same register for
118 // both or otherwise does not want to enable this optimization, the function
119 // should return NULL
120 if (CC == CallingConv::GHC)
121 // This is academic becase all GHC calls are (supposed to be) tail calls
123 return STI.isTargetDarwin() ? CSR_iOS_ThisReturn_RegMask
124 : CSR_AAPCS_ThisReturn_RegMask;
127 BitVector ARMBaseRegisterInfo::
128 getReservedRegs(const MachineFunction &MF) const {
129 const ARMSubtarget &STI = MF.getSubtarget<ARMSubtarget>();
130 const TargetFrameLowering *TFI = STI.getFrameLowering();
132 // FIXME: avoid re-calculating this every time.
133 BitVector Reserved(getNumRegs());
134 Reserved.set(ARM::SP);
135 Reserved.set(ARM::PC);
136 Reserved.set(ARM::FPSCR);
137 Reserved.set(ARM::APSR_NZCV);
139 Reserved.set(getFramePointerReg(STI));
140 if (hasBasePointer(MF))
141 Reserved.set(BasePtr);
142 // Some targets reserve R9.
143 if (STI.isR9Reserved())
144 Reserved.set(ARM::R9);
145 // Reserve D16-D31 if the subtarget doesn't support them.
146 if (!STI.hasVFP3() || STI.hasD16()) {
147 assert(ARM::D31 == ARM::D16 + 15);
148 for (unsigned i = 0; i != 16; ++i)
149 Reserved.set(ARM::D16 + i);
151 const TargetRegisterClass *RC = &ARM::GPRPairRegClass;
152 for(TargetRegisterClass::iterator I = RC->begin(), E = RC->end(); I!=E; ++I)
153 for (MCSubRegIterator SI(*I, this); SI.isValid(); ++SI)
154 if (Reserved.test(*SI)) Reserved.set(*I);
159 const TargetRegisterClass *
160 ARMBaseRegisterInfo::getLargestLegalSuperClass(const TargetRegisterClass *RC,
161 const MachineFunction &) const {
162 const TargetRegisterClass *Super = RC;
163 TargetRegisterClass::sc_iterator I = RC->getSuperClasses();
165 switch (Super->getID()) {
166 case ARM::GPRRegClassID:
167 case ARM::SPRRegClassID:
168 case ARM::DPRRegClassID:
169 case ARM::QPRRegClassID:
170 case ARM::QQPRRegClassID:
171 case ARM::QQQQPRRegClassID:
172 case ARM::GPRPairRegClassID:
180 const TargetRegisterClass *
181 ARMBaseRegisterInfo::getPointerRegClass(const MachineFunction &MF, unsigned Kind)
183 return &ARM::GPRRegClass;
186 const TargetRegisterClass *
187 ARMBaseRegisterInfo::getCrossCopyRegClass(const TargetRegisterClass *RC) const {
188 if (RC == &ARM::CCRRegClass)
189 return &ARM::rGPRRegClass; // Can't copy CCR registers.
194 ARMBaseRegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC,
195 MachineFunction &MF) const {
196 const ARMSubtarget &STI = MF.getSubtarget<ARMSubtarget>();
197 const TargetFrameLowering *TFI = STI.getFrameLowering();
199 switch (RC->getID()) {
202 case ARM::tGPRRegClassID:
203 return TFI->hasFP(MF) ? 4 : 5;
204 case ARM::GPRRegClassID: {
205 unsigned FP = TFI->hasFP(MF) ? 1 : 0;
206 return 10 - FP - (STI.isR9Reserved() ? 1 : 0);
208 case ARM::SPRRegClassID: // Currently not used as 'rep' register class.
209 case ARM::DPRRegClassID:
214 // Get the other register in a GPRPair.
215 static unsigned getPairedGPR(unsigned Reg, bool Odd, const MCRegisterInfo *RI) {
216 for (MCSuperRegIterator Supers(Reg, RI); Supers.isValid(); ++Supers)
217 if (ARM::GPRPairRegClass.contains(*Supers))
218 return RI->getSubReg(*Supers, Odd ? ARM::gsub_1 : ARM::gsub_0);
222 // Resolve the RegPairEven / RegPairOdd register allocator hints.
224 ARMBaseRegisterInfo::getRegAllocationHints(unsigned VirtReg,
225 ArrayRef<MCPhysReg> Order,
226 SmallVectorImpl<MCPhysReg> &Hints,
227 const MachineFunction &MF,
228 const VirtRegMap *VRM) const {
229 const MachineRegisterInfo &MRI = MF.getRegInfo();
230 std::pair<unsigned, unsigned> Hint = MRI.getRegAllocationHint(VirtReg);
233 switch (Hint.first) {
234 case ARMRI::RegPairEven:
237 case ARMRI::RegPairOdd:
241 TargetRegisterInfo::getRegAllocationHints(VirtReg, Order, Hints, MF, VRM);
245 // This register should preferably be even (Odd == 0) or odd (Odd == 1).
246 // Check if the other part of the pair has already been assigned, and provide
247 // the paired register as the first hint.
248 unsigned Paired = Hint.second;
252 unsigned PairedPhys = 0;
253 if (TargetRegisterInfo::isPhysicalRegister(Paired)) {
255 } else if (VRM && VRM->hasPhys(Paired)) {
256 PairedPhys = getPairedGPR(VRM->getPhys(Paired), Odd, this);
259 // First prefer the paired physreg.
261 std::find(Order.begin(), Order.end(), PairedPhys) != Order.end())
262 Hints.push_back(PairedPhys);
264 // Then prefer even or odd registers.
265 for (unsigned I = 0, E = Order.size(); I != E; ++I) {
266 unsigned Reg = Order[I];
267 if (Reg == PairedPhys || (getEncodingValue(Reg) & 1) != Odd)
269 // Don't provide hints that are paired to a reserved register.
270 unsigned Paired = getPairedGPR(Reg, !Odd, this);
271 if (!Paired || MRI.isReserved(Paired))
273 Hints.push_back(Reg);
278 ARMBaseRegisterInfo::updateRegAllocHint(unsigned Reg, unsigned NewReg,
279 MachineFunction &MF) const {
280 MachineRegisterInfo *MRI = &MF.getRegInfo();
281 std::pair<unsigned, unsigned> Hint = MRI->getRegAllocationHint(Reg);
282 if ((Hint.first == (unsigned)ARMRI::RegPairOdd ||
283 Hint.first == (unsigned)ARMRI::RegPairEven) &&
284 TargetRegisterInfo::isVirtualRegister(Hint.second)) {
285 // If 'Reg' is one of the even / odd register pair and it's now changed
286 // (e.g. coalesced) into a different register. The other register of the
287 // pair allocation hint must be updated to reflect the relationship
289 unsigned OtherReg = Hint.second;
290 Hint = MRI->getRegAllocationHint(OtherReg);
291 // Make sure the pair has not already divorced.
292 if (Hint.second == Reg) {
293 MRI->setRegAllocationHint(OtherReg, Hint.first, NewReg);
294 if (TargetRegisterInfo::isVirtualRegister(NewReg))
295 MRI->setRegAllocationHint(NewReg,
296 Hint.first == (unsigned)ARMRI::RegPairOdd ? ARMRI::RegPairEven
297 : ARMRI::RegPairOdd, OtherReg);
302 bool ARMBaseRegisterInfo::hasBasePointer(const MachineFunction &MF) const {
303 const MachineFrameInfo *MFI = MF.getFrameInfo();
304 const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
305 const TargetFrameLowering *TFI = MF.getSubtarget().getFrameLowering();
307 // When outgoing call frames are so large that we adjust the stack pointer
308 // around the call, we can no longer use the stack pointer to reach the
309 // emergency spill slot.
310 if (needsStackRealignment(MF) && !TFI->hasReservedCallFrame(MF))
313 // Thumb has trouble with negative offsets from the FP. Thumb2 has a limited
314 // negative range for ldr/str (255), and thumb1 is positive offsets only.
315 // It's going to be better to use the SP or Base Pointer instead. When there
316 // are variable sized objects, we can't reference off of the SP, so we
317 // reserve a Base Pointer.
318 if (AFI->isThumbFunction() && MFI->hasVarSizedObjects()) {
319 // Conservatively estimate whether the negative offset from the frame
320 // pointer will be sufficient to reach. If a function has a smallish
321 // frame, it's less likely to have lots of spills and callee saved
322 // space, so it's all more likely to be within range of the frame pointer.
323 // If it's wrong, the scavenger will still enable access to work, it just
325 if (AFI->isThumb2Function() && MFI->getLocalFrameSize() < 128)
333 bool ARMBaseRegisterInfo::canRealignStack(const MachineFunction &MF) const {
334 const MachineRegisterInfo *MRI = &MF.getRegInfo();
335 const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
336 // We can't realign the stack if:
337 // 1. Dynamic stack realignment is explicitly disabled,
338 // 2. This is a Thumb1 function (it's not useful, so we don't bother), or
339 // 3. There are VLAs in the function and the base pointer is disabled.
340 if (MF.getFunction()->hasFnAttribute("no-realign-stack"))
342 if (AFI->isThumb1OnlyFunction())
344 // Stack realignment requires a frame pointer. If we already started
345 // register allocation with frame pointer elimination, it is too late now.
346 if (!MRI->canReserveReg(getFramePointerReg(MF.getSubtarget<ARMSubtarget>())))
348 // We may also need a base pointer if there are dynamic allocas or stack
349 // pointer adjustments around calls.
350 if (MF.getSubtarget().getFrameLowering()->hasReservedCallFrame(MF))
352 // A base pointer is required and allowed. Check that it isn't too late to
354 return MRI->canReserveReg(BasePtr);
357 bool ARMBaseRegisterInfo::
358 needsStackRealignment(const MachineFunction &MF) const {
359 const MachineFrameInfo *MFI = MF.getFrameInfo();
360 const Function *F = MF.getFunction();
361 unsigned StackAlign =
362 MF.getSubtarget().getFrameLowering()->getStackAlignment();
363 bool requiresRealignment = ((MFI->getMaxAlignment() > StackAlign) ||
364 F->hasFnAttribute(Attribute::StackAlignment));
366 return requiresRealignment && canRealignStack(MF);
369 bool ARMBaseRegisterInfo::
370 cannotEliminateFrame(const MachineFunction &MF) const {
371 const MachineFrameInfo *MFI = MF.getFrameInfo();
372 if (MF.getTarget().Options.DisableFramePointerElim(MF) && MFI->adjustsStack())
374 return MFI->hasVarSizedObjects() || MFI->isFrameAddressTaken()
375 || needsStackRealignment(MF);
379 ARMBaseRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
380 const ARMSubtarget &STI = MF.getSubtarget<ARMSubtarget>();
381 const TargetFrameLowering *TFI = STI.getFrameLowering();
384 return getFramePointerReg(STI);
388 /// emitLoadConstPool - Emits a load from constpool to materialize the
389 /// specified immediate.
390 void ARMBaseRegisterInfo::
391 emitLoadConstPool(MachineBasicBlock &MBB,
392 MachineBasicBlock::iterator &MBBI,
394 unsigned DestReg, unsigned SubIdx, int Val,
395 ARMCC::CondCodes Pred,
396 unsigned PredReg, unsigned MIFlags) const {
397 MachineFunction &MF = *MBB.getParent();
398 const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
399 MachineConstantPool *ConstantPool = MF.getConstantPool();
401 ConstantInt::get(Type::getInt32Ty(MF.getFunction()->getContext()), Val);
402 unsigned Idx = ConstantPool->getConstantPoolIndex(C, 4);
404 BuildMI(MBB, MBBI, dl, TII.get(ARM::LDRcp))
405 .addReg(DestReg, getDefRegState(true), SubIdx)
406 .addConstantPoolIndex(Idx)
407 .addImm(0).addImm(Pred).addReg(PredReg)
408 .setMIFlags(MIFlags);
411 bool ARMBaseRegisterInfo::
412 requiresRegisterScavenging(const MachineFunction &MF) const {
416 bool ARMBaseRegisterInfo::
417 trackLivenessAfterRegAlloc(const MachineFunction &MF) const {
421 bool ARMBaseRegisterInfo::
422 requiresFrameIndexScavenging(const MachineFunction &MF) const {
426 bool ARMBaseRegisterInfo::
427 requiresVirtualBaseRegisters(const MachineFunction &MF) const {
431 int64_t ARMBaseRegisterInfo::
432 getFrameIndexInstrOffset(const MachineInstr *MI, int Idx) const {
433 const MCInstrDesc &Desc = MI->getDesc();
434 unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
435 int64_t InstrOffs = 0;
439 case ARMII::AddrModeT2_i8:
440 case ARMII::AddrModeT2_i12:
441 case ARMII::AddrMode_i12:
442 InstrOffs = MI->getOperand(Idx+1).getImm();
445 case ARMII::AddrMode5: {
447 const MachineOperand &OffOp = MI->getOperand(Idx+1);
448 InstrOffs = ARM_AM::getAM5Offset(OffOp.getImm());
449 if (ARM_AM::getAM5Op(OffOp.getImm()) == ARM_AM::sub)
450 InstrOffs = -InstrOffs;
454 case ARMII::AddrMode2: {
456 InstrOffs = ARM_AM::getAM2Offset(MI->getOperand(ImmIdx).getImm());
457 if (ARM_AM::getAM2Op(MI->getOperand(ImmIdx).getImm()) == ARM_AM::sub)
458 InstrOffs = -InstrOffs;
461 case ARMII::AddrMode3: {
463 InstrOffs = ARM_AM::getAM3Offset(MI->getOperand(ImmIdx).getImm());
464 if (ARM_AM::getAM3Op(MI->getOperand(ImmIdx).getImm()) == ARM_AM::sub)
465 InstrOffs = -InstrOffs;
468 case ARMII::AddrModeT1_s: {
470 InstrOffs = MI->getOperand(ImmIdx).getImm();
475 llvm_unreachable("Unsupported addressing mode!");
478 return InstrOffs * Scale;
481 /// needsFrameBaseReg - Returns true if the instruction's frame index
482 /// reference would be better served by a base register other than FP
483 /// or SP. Used by LocalStackFrameAllocation to determine which frame index
484 /// references it should create new base registers for.
485 bool ARMBaseRegisterInfo::
486 needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const {
487 for (unsigned i = 0; !MI->getOperand(i).isFI(); ++i) {
488 assert(i < MI->getNumOperands() &&"Instr doesn't have FrameIndex operand!");
491 // It's the load/store FI references that cause issues, as it can be difficult
492 // to materialize the offset if it won't fit in the literal field. Estimate
493 // based on the size of the local frame and some conservative assumptions
494 // about the rest of the stack frame (note, this is pre-regalloc, so
495 // we don't know everything for certain yet) whether this offset is likely
496 // to be out of range of the immediate. Return true if so.
498 // We only generate virtual base registers for loads and stores, so
499 // return false for everything else.
500 unsigned Opc = MI->getOpcode();
502 case ARM::LDRi12: case ARM::LDRH: case ARM::LDRBi12:
503 case ARM::STRi12: case ARM::STRH: case ARM::STRBi12:
504 case ARM::t2LDRi12: case ARM::t2LDRi8:
505 case ARM::t2STRi12: case ARM::t2STRi8:
506 case ARM::VLDRS: case ARM::VLDRD:
507 case ARM::VSTRS: case ARM::VSTRD:
508 case ARM::tSTRspi: case ARM::tLDRspi:
514 // Without a virtual base register, if the function has variable sized
515 // objects, all fixed-size local references will be via the frame pointer,
516 // Approximate the offset and see if it's legal for the instruction.
517 // Note that the incoming offset is based on the SP value at function entry,
518 // so it'll be negative.
519 MachineFunction &MF = *MI->getParent()->getParent();
520 const TargetFrameLowering *TFI = MF.getSubtarget().getFrameLowering();
521 MachineFrameInfo *MFI = MF.getFrameInfo();
522 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
524 // Estimate an offset from the frame pointer.
525 // Conservatively assume all callee-saved registers get pushed. R4-R6
526 // will be earlier than the FP, so we ignore those.
528 int64_t FPOffset = Offset - 8;
529 // ARM and Thumb2 functions also need to consider R8-R11 and D8-D15
530 if (!AFI->isThumbFunction() || !AFI->isThumb1OnlyFunction())
532 // Estimate an offset from the stack pointer.
533 // The incoming offset is relating to the SP at the start of the function,
534 // but when we access the local it'll be relative to the SP after local
535 // allocation, so adjust our SP-relative offset by that allocation size.
536 Offset += MFI->getLocalFrameSize();
537 // Assume that we'll have at least some spill slots allocated.
538 // FIXME: This is a total SWAG number. We should run some statistics
539 // and pick a real one.
540 Offset += 128; // 128 bytes of spill slots
542 // If there's a frame pointer and the addressing mode allows it, try using it.
543 // The FP is only available if there is no dynamic realignment. We
544 // don't know for sure yet whether we'll need that, so we guess based
545 // on whether there are any local variables that would trigger it.
546 unsigned StackAlign = TFI->getStackAlignment();
547 if (TFI->hasFP(MF) &&
548 !((MFI->getLocalFrameMaxAlign() > StackAlign) && canRealignStack(MF))) {
549 if (isFrameOffsetLegal(MI, getFrameRegister(MF), FPOffset))
552 // If we can reference via the stack pointer, try that.
553 // FIXME: This (and the code that resolves the references) can be improved
554 // to only disallow SP relative references in the live range of
555 // the VLA(s). In practice, it's unclear how much difference that
556 // would make, but it may be worth doing.
557 if (!MFI->hasVarSizedObjects() && isFrameOffsetLegal(MI, ARM::SP, Offset))
560 // The offset likely isn't legal, we want to allocate a virtual base register.
564 /// materializeFrameBaseRegister - Insert defining instruction(s) for BaseReg to
565 /// be a pointer to FrameIdx at the beginning of the basic block.
566 void ARMBaseRegisterInfo::
567 materializeFrameBaseRegister(MachineBasicBlock *MBB,
568 unsigned BaseReg, int FrameIdx,
569 int64_t Offset) const {
570 ARMFunctionInfo *AFI = MBB->getParent()->getInfo<ARMFunctionInfo>();
571 unsigned ADDriOpc = !AFI->isThumbFunction() ? ARM::ADDri :
572 (AFI->isThumb1OnlyFunction() ? ARM::tADDframe : ARM::t2ADDri);
574 MachineBasicBlock::iterator Ins = MBB->begin();
575 DebugLoc DL; // Defaults to "unknown"
576 if (Ins != MBB->end())
577 DL = Ins->getDebugLoc();
579 const MachineFunction &MF = *MBB->getParent();
580 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
581 const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
582 const MCInstrDesc &MCID = TII.get(ADDriOpc);
583 MRI.constrainRegClass(BaseReg, TII.getRegClass(MCID, 0, this, MF));
585 MachineInstrBuilder MIB = BuildMI(*MBB, Ins, DL, MCID, BaseReg)
586 .addFrameIndex(FrameIdx).addImm(Offset);
588 if (!AFI->isThumb1OnlyFunction())
589 AddDefaultCC(AddDefaultPred(MIB));
592 void ARMBaseRegisterInfo::resolveFrameIndex(MachineInstr &MI, unsigned BaseReg,
593 int64_t Offset) const {
594 MachineBasicBlock &MBB = *MI.getParent();
595 MachineFunction &MF = *MBB.getParent();
596 const ARMBaseInstrInfo &TII =
597 *static_cast<const ARMBaseInstrInfo *>(MF.getSubtarget().getInstrInfo());
598 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
599 int Off = Offset; // ARM doesn't need the general 64-bit offsets
602 assert(!AFI->isThumb1OnlyFunction() &&
603 "This resolveFrameIndex does not support Thumb1!");
605 while (!MI.getOperand(i).isFI()) {
607 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
610 if (!AFI->isThumbFunction())
611 Done = rewriteARMFrameIndex(MI, i, BaseReg, Off, TII);
613 assert(AFI->isThumb2Function());
614 Done = rewriteT2FrameIndex(MI, i, BaseReg, Off, TII);
616 assert (Done && "Unable to resolve frame index!");
620 bool ARMBaseRegisterInfo::isFrameOffsetLegal(const MachineInstr *MI, unsigned BaseReg,
621 int64_t Offset) const {
622 const MCInstrDesc &Desc = MI->getDesc();
623 unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
626 while (!MI->getOperand(i).isFI()) {
628 assert(i < MI->getNumOperands() &&"Instr doesn't have FrameIndex operand!");
631 // AddrMode4 and AddrMode6 cannot handle any offset.
632 if (AddrMode == ARMII::AddrMode4 || AddrMode == ARMII::AddrMode6)
635 unsigned NumBits = 0;
637 bool isSigned = true;
639 case ARMII::AddrModeT2_i8:
640 case ARMII::AddrModeT2_i12:
641 // i8 supports only negative, and i12 supports only positive, so
642 // based on Offset sign, consider the appropriate instruction
651 case ARMII::AddrMode5:
656 case ARMII::AddrMode_i12:
657 case ARMII::AddrMode2:
660 case ARMII::AddrMode3:
663 case ARMII::AddrModeT1_s:
664 NumBits = (BaseReg == ARM::SP ? 8 : 5);
669 llvm_unreachable("Unsupported addressing mode!");
672 Offset += getFrameIndexInstrOffset(MI, i);
673 // Make sure the offset is encodable for instructions that scale the
675 if ((Offset & (Scale-1)) != 0)
678 if (isSigned && Offset < 0)
681 unsigned Mask = (1 << NumBits) - 1;
682 if ((unsigned)Offset <= Mask * Scale)
689 ARMBaseRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
690 int SPAdj, unsigned FIOperandNum,
691 RegScavenger *RS) const {
692 MachineInstr &MI = *II;
693 MachineBasicBlock &MBB = *MI.getParent();
694 MachineFunction &MF = *MBB.getParent();
695 const ARMBaseInstrInfo &TII =
696 *static_cast<const ARMBaseInstrInfo *>(MF.getSubtarget().getInstrInfo());
697 const ARMFrameLowering *TFI = static_cast<const ARMFrameLowering *>(
698 MF.getSubtarget().getFrameLowering());
699 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
700 assert(!AFI->isThumb1OnlyFunction() &&
701 "This eliminateFrameIndex does not support Thumb1!");
702 int FrameIndex = MI.getOperand(FIOperandNum).getIndex();
705 int Offset = TFI->ResolveFrameIndexReference(MF, FrameIndex, FrameReg, SPAdj);
707 // PEI::scavengeFrameVirtualRegs() cannot accurately track SPAdj because the
708 // call frame setup/destroy instructions have already been eliminated. That
709 // means the stack pointer cannot be used to access the emergency spill slot
710 // when !hasReservedCallFrame().
712 if (RS && FrameReg == ARM::SP && RS->isScavengingFrameIndex(FrameIndex)){
713 assert(TFI->hasReservedCallFrame(MF) &&
714 "Cannot use SP to access the emergency spill slot in "
715 "functions without a reserved call frame");
716 assert(!MF.getFrameInfo()->hasVarSizedObjects() &&
717 "Cannot use SP to access the emergency spill slot in "
718 "functions with variable sized frame objects");
722 assert(!MI.isDebugValue() && "DBG_VALUEs should be handled in target-independent code");
724 // Modify MI as necessary to handle as much of 'Offset' as possible
726 if (!AFI->isThumbFunction())
727 Done = rewriteARMFrameIndex(MI, FIOperandNum, FrameReg, Offset, TII);
729 assert(AFI->isThumb2Function());
730 Done = rewriteT2FrameIndex(MI, FIOperandNum, FrameReg, Offset, TII);
735 // If we get here, the immediate doesn't fit into the instruction. We folded
736 // as much as possible above, handle the rest, providing a register that is
739 (MI.getDesc().TSFlags & ARMII::AddrModeMask) == ARMII::AddrMode4 ||
740 (MI.getDesc().TSFlags & ARMII::AddrModeMask) == ARMII::AddrMode6) &&
741 "This code isn't needed if offset already handled!");
743 unsigned ScratchReg = 0;
744 int PIdx = MI.findFirstPredOperandIdx();
745 ARMCC::CondCodes Pred = (PIdx == -1)
746 ? ARMCC::AL : (ARMCC::CondCodes)MI.getOperand(PIdx).getImm();
747 unsigned PredReg = (PIdx == -1) ? 0 : MI.getOperand(PIdx+1).getReg();
749 // Must be addrmode4/6.
750 MI.getOperand(FIOperandNum).ChangeToRegister(FrameReg, false, false, false);
752 ScratchReg = MF.getRegInfo().createVirtualRegister(&ARM::GPRRegClass);
753 if (!AFI->isThumbFunction())
754 emitARMRegPlusImmediate(MBB, II, MI.getDebugLoc(), ScratchReg, FrameReg,
755 Offset, Pred, PredReg, TII);
757 assert(AFI->isThumb2Function());
758 emitT2RegPlusImmediate(MBB, II, MI.getDebugLoc(), ScratchReg, FrameReg,
759 Offset, Pred, PredReg, TII);
761 // Update the original instruction to use the scratch register.
762 MI.getOperand(FIOperandNum).ChangeToRegister(ScratchReg, false, false,true);
766 bool ARMBaseRegisterInfo::shouldCoalesce(MachineInstr *MI,
767 const TargetRegisterClass *SrcRC,
769 const TargetRegisterClass *DstRC,
771 const TargetRegisterClass *NewRC) const {
772 auto MBB = MI->getParent();
773 auto MF = MBB->getParent();
774 const MachineRegisterInfo &MRI = MF->getRegInfo();
775 // If not copying into a sub-register this should be ok because we shouldn't
776 // need to split the reg.
779 // Small registers don't frequently cause a problem, so we can coalesce them.
780 if (NewRC->getSize() < 32 && DstRC->getSize() < 32 && SrcRC->getSize() < 32)
784 MRI.getTargetRegisterInfo()->getRegClassWeight(NewRC);
786 MRI.getTargetRegisterInfo()->getRegClassWeight(SrcRC);
788 MRI.getTargetRegisterInfo()->getRegClassWeight(DstRC);
789 // If the source register class is more expensive than the destination, the
790 // coalescing is probably profitable.
791 if (SrcRCWeight.RegWeight > NewRCWeight.RegWeight)
793 if (DstRCWeight.RegWeight > NewRCWeight.RegWeight)
796 // If the register allocator isn't constrained, we can always allow coalescing
797 // unfortunately we don't know yet if we will be constrained.
798 // The goal of this heuristic is to restrict how many expensive registers
799 // we allow to coalesce in a given basic block.
800 auto AFI = MF->getInfo<ARMFunctionInfo>();
801 auto It = AFI->getCoalescedWeight(MBB);
803 DEBUG(dbgs() << "\tARM::shouldCoalesce - Coalesced Weight: "
804 << It->second << "\n");
805 DEBUG(dbgs() << "\tARM::shouldCoalesce - Reg Weight: "
806 << NewRCWeight.RegWeight << "\n");
808 // This number is the largest round number that which meets the criteria:
809 // (1) addresses PR18825
810 // (2) generates better code in some test cases (like vldm-shed-a9.ll)
811 // (3) Doesn't regress any test cases (in-tree, test-suite, and SPEC)
812 // In practice the SizeMultiplier will only factor in for straight line code
813 // that uses a lot of NEON vectors, which isn't terribly common.
814 unsigned SizeMultiplier = MBB->size()/100;
815 SizeMultiplier = SizeMultiplier ? SizeMultiplier : 1;
816 if (It->second < NewRCWeight.WeightLimit * SizeMultiplier) {
817 It->second += NewRCWeight.RegWeight;