1 //===- ARMBaseInstrInfo.h - ARM Base Instruction Information ----*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Base ARM implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #ifndef ARMBASEINSTRUCTIONINFO_H
15 #define ARMBASEINSTRUCTIONINFO_H
18 #include "llvm/CodeGen/MachineInstrBuilder.h"
19 #include "llvm/Target/TargetInstrInfo.h"
20 #include "llvm/ADT/DenseMap.h"
21 #include "llvm/ADT/SmallSet.h"
25 class ARMBaseRegisterInfo;
27 /// ARMII - This namespace holds all of the target specific flags that
28 /// instruction info tracks.
32 //===------------------------------------------------------------------===//
35 //===------------------------------------------------------------------===//
36 // This four-bit field describes the addressing mode used.
37 AddrModeMask = 0x1f, // The AddrMode enums are declared in ARMBaseInfo.h
39 // Size* - Flags to keep track of the size of an instruction.
41 SizeMask = 7 << SizeShift,
42 SizeSpecial = 1, // 0 byte pseudo or special case.
47 // IndexMode - Unindex, pre-indexed, or post-indexed are valid for load
48 // and store ops only. Generic "updating" flag is used for ld/st multiple.
50 IndexModeMask = 3 << IndexModeShift,
55 //===------------------------------------------------------------------===//
56 // Instruction encoding formats.
59 FormMask = 0x3f << FormShift,
61 // Pseudo instructions
62 Pseudo = 0 << FormShift,
64 // Multiply instructions
65 MulFrm = 1 << FormShift,
67 // Branch instructions
68 BrFrm = 2 << FormShift,
69 BrMiscFrm = 3 << FormShift,
71 // Data Processing instructions
72 DPFrm = 4 << FormShift,
73 DPSoRegFrm = 5 << FormShift,
76 LdFrm = 6 << FormShift,
77 StFrm = 7 << FormShift,
78 LdMiscFrm = 8 << FormShift,
79 StMiscFrm = 9 << FormShift,
80 LdStMulFrm = 10 << FormShift,
82 LdStExFrm = 11 << FormShift,
84 // Miscellaneous arithmetic instructions
85 ArithMiscFrm = 12 << FormShift,
86 SatFrm = 13 << FormShift,
88 // Extend instructions
89 ExtFrm = 14 << FormShift,
92 VFPUnaryFrm = 15 << FormShift,
93 VFPBinaryFrm = 16 << FormShift,
94 VFPConv1Frm = 17 << FormShift,
95 VFPConv2Frm = 18 << FormShift,
96 VFPConv3Frm = 19 << FormShift,
97 VFPConv4Frm = 20 << FormShift,
98 VFPConv5Frm = 21 << FormShift,
99 VFPLdStFrm = 22 << FormShift,
100 VFPLdStMulFrm = 23 << FormShift,
101 VFPMiscFrm = 24 << FormShift,
104 ThumbFrm = 25 << FormShift,
106 // Miscelleaneous format
107 MiscFrm = 26 << FormShift,
110 NGetLnFrm = 27 << FormShift,
111 NSetLnFrm = 28 << FormShift,
112 NDupFrm = 29 << FormShift,
113 NLdStFrm = 30 << FormShift,
114 N1RegModImmFrm= 31 << FormShift,
115 N2RegFrm = 32 << FormShift,
116 NVCVTFrm = 33 << FormShift,
117 NVDupLnFrm = 34 << FormShift,
118 N2RegVShLFrm = 35 << FormShift,
119 N2RegVShRFrm = 36 << FormShift,
120 N3RegFrm = 37 << FormShift,
121 N3RegVShFrm = 38 << FormShift,
122 NVExtFrm = 39 << FormShift,
123 NVMulSLFrm = 40 << FormShift,
124 NVTBLFrm = 41 << FormShift,
126 //===------------------------------------------------------------------===//
129 // UnaryDP - Indicates this is a unary data processing instruction, i.e.
130 // it doesn't have a Rn operand.
133 // Xform16Bit - Indicates this Thumb2 instruction may be transformed into
134 // a 16-bit Thumb instruction if certain conditions are met.
135 Xform16Bit = 1 << 17,
137 //===------------------------------------------------------------------===//
140 DomainMask = 7 << DomainShift,
141 DomainGeneral = 0 << DomainShift,
142 DomainVFP = 1 << DomainShift,
143 DomainNEON = 2 << DomainShift,
144 DomainNEONA8 = 4 << DomainShift,
146 //===------------------------------------------------------------------===//
147 // Field shifts - such shifts are used to set field while generating
148 // machine instructions.
150 // FIXME: This list will need adjusting/fixing as the MC code emitter
151 // takes shape and the ARMCodeEmitter.cpp bits go away.
177 class ARMBaseInstrInfo : public TargetInstrInfoImpl {
178 const ARMSubtarget &Subtarget;
181 // Can be only subclassed.
182 explicit ARMBaseInstrInfo(const ARMSubtarget &STI);
185 // Return the non-pre/post incrementing version of 'Opc'. Return 0
186 // if there is not such an opcode.
187 virtual unsigned getUnindexedOpcode(unsigned Opc) const =0;
189 virtual MachineInstr *convertToThreeAddress(MachineFunction::iterator &MFI,
190 MachineBasicBlock::iterator &MBBI,
191 LiveVariables *LV) const;
193 virtual const ARMBaseRegisterInfo &getRegisterInfo() const =0;
194 const ARMSubtarget &getSubtarget() const { return Subtarget; }
196 ScheduleHazardRecognizer *
197 CreateTargetHazardRecognizer(const TargetMachine *TM,
198 const ScheduleDAG *DAG) const;
200 ScheduleHazardRecognizer *
201 CreateTargetPostRAHazardRecognizer(const InstrItineraryData *II,
202 const ScheduleDAG *DAG) const;
205 virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
206 MachineBasicBlock *&FBB,
207 SmallVectorImpl<MachineOperand> &Cond,
208 bool AllowModify = false) const;
209 virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const;
210 virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
211 MachineBasicBlock *FBB,
212 const SmallVectorImpl<MachineOperand> &Cond,
216 bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const;
218 // Predication support.
219 bool isPredicated(const MachineInstr *MI) const {
220 int PIdx = MI->findFirstPredOperandIdx();
221 return PIdx != -1 && MI->getOperand(PIdx).getImm() != ARMCC::AL;
224 ARMCC::CondCodes getPredicate(const MachineInstr *MI) const {
225 int PIdx = MI->findFirstPredOperandIdx();
226 return PIdx != -1 ? (ARMCC::CondCodes)MI->getOperand(PIdx).getImm()
231 bool PredicateInstruction(MachineInstr *MI,
232 const SmallVectorImpl<MachineOperand> &Pred) const;
235 bool SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1,
236 const SmallVectorImpl<MachineOperand> &Pred2) const;
238 virtual bool DefinesPredicate(MachineInstr *MI,
239 std::vector<MachineOperand> &Pred) const;
241 virtual bool isPredicable(MachineInstr *MI) const;
243 /// GetInstSize - Returns the size of the specified MachineInstr.
245 virtual unsigned GetInstSizeInBytes(const MachineInstr* MI) const;
247 virtual unsigned isLoadFromStackSlot(const MachineInstr *MI,
248 int &FrameIndex) const;
249 virtual unsigned isStoreToStackSlot(const MachineInstr *MI,
250 int &FrameIndex) const;
252 virtual void copyPhysReg(MachineBasicBlock &MBB,
253 MachineBasicBlock::iterator I, DebugLoc DL,
254 unsigned DestReg, unsigned SrcReg,
257 virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
258 MachineBasicBlock::iterator MBBI,
259 unsigned SrcReg, bool isKill, int FrameIndex,
260 const TargetRegisterClass *RC,
261 const TargetRegisterInfo *TRI) const;
263 virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
264 MachineBasicBlock::iterator MBBI,
265 unsigned DestReg, int FrameIndex,
266 const TargetRegisterClass *RC,
267 const TargetRegisterInfo *TRI) const;
269 virtual MachineInstr *emitFrameIndexDebugValue(MachineFunction &MF,
275 virtual void reMaterialize(MachineBasicBlock &MBB,
276 MachineBasicBlock::iterator MI,
277 unsigned DestReg, unsigned SubIdx,
278 const MachineInstr *Orig,
279 const TargetRegisterInfo &TRI) const;
281 MachineInstr *duplicate(MachineInstr *Orig, MachineFunction &MF) const;
283 virtual bool produceSameValue(const MachineInstr *MI0,
284 const MachineInstr *MI1,
285 const MachineRegisterInfo *MRI) const;
287 /// areLoadsFromSameBasePtr - This is used by the pre-regalloc scheduler to
288 /// determine if two loads are loading from the same base address. It should
289 /// only return true if the base pointers are the same and the only
290 /// differences between the two addresses is the offset. It also returns the
291 /// offsets by reference.
292 virtual bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2,
293 int64_t &Offset1, int64_t &Offset2)const;
295 /// shouldScheduleLoadsNear - This is a used by the pre-regalloc scheduler to
296 /// determine (in conjuction with areLoadsFromSameBasePtr) if two loads should
297 /// be scheduled togther. On some targets if two loads are loading from
298 /// addresses in the same cache line, it's better if they are scheduled
299 /// together. This function takes two integers that represent the load offsets
300 /// from the common base address. It returns true if it decides it's desirable
301 /// to schedule the two loads together. "NumLoads" is the number of loads that
302 /// have already been scheduled after Load1.
303 virtual bool shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,
304 int64_t Offset1, int64_t Offset2,
305 unsigned NumLoads) const;
307 virtual bool isSchedulingBoundary(const MachineInstr *MI,
308 const MachineBasicBlock *MBB,
309 const MachineFunction &MF) const;
311 virtual bool isProfitableToIfCvt(MachineBasicBlock &MBB,
312 unsigned NumCyles, unsigned ExtraPredCycles,
313 float Prob, float Confidence) const;
315 virtual bool isProfitableToIfCvt(MachineBasicBlock &TMBB,
316 unsigned NumT, unsigned ExtraT,
317 MachineBasicBlock &FMBB,
318 unsigned NumF, unsigned ExtraF,
319 float Probability, float Confidence) const;
321 virtual bool isProfitableToDupForIfCvt(MachineBasicBlock &MBB,
324 float Confidence) const {
325 return NumCyles == 1;
328 /// AnalyzeCompare - For a comparison instruction, return the source register
329 /// in SrcReg and the value it compares against in CmpValue. Return true if
330 /// the comparison instruction can be analyzed.
331 virtual bool AnalyzeCompare(const MachineInstr *MI, unsigned &SrcReg,
332 int &CmpMask, int &CmpValue) const;
334 /// OptimizeCompareInstr - Convert the instruction to set the zero flag so
335 /// that we can remove a "comparison with zero".
336 virtual bool OptimizeCompareInstr(MachineInstr *CmpInstr, unsigned SrcReg,
337 int CmpMask, int CmpValue,
338 const MachineRegisterInfo *MRI) const;
340 /// FoldImmediate - 'Reg' is known to be defined by a move immediate
341 /// instruction, try to fold the immediate into the use instruction.
342 virtual bool FoldImmediate(MachineInstr *UseMI, MachineInstr *DefMI,
343 unsigned Reg, MachineRegisterInfo *MRI) const;
345 virtual unsigned getNumMicroOps(const InstrItineraryData *ItinData,
346 const MachineInstr *MI) const;
349 int getOperandLatency(const InstrItineraryData *ItinData,
350 const MachineInstr *DefMI, unsigned DefIdx,
351 const MachineInstr *UseMI, unsigned UseIdx) const;
353 int getOperandLatency(const InstrItineraryData *ItinData,
354 SDNode *DefNode, unsigned DefIdx,
355 SDNode *UseNode, unsigned UseIdx) const;
357 int getVLDMDefCycle(const InstrItineraryData *ItinData,
358 const TargetInstrDesc &DefTID,
360 unsigned DefIdx, unsigned DefAlign) const;
361 int getLDMDefCycle(const InstrItineraryData *ItinData,
362 const TargetInstrDesc &DefTID,
364 unsigned DefIdx, unsigned DefAlign) const;
365 int getVSTMUseCycle(const InstrItineraryData *ItinData,
366 const TargetInstrDesc &UseTID,
368 unsigned UseIdx, unsigned UseAlign) const;
369 int getSTMUseCycle(const InstrItineraryData *ItinData,
370 const TargetInstrDesc &UseTID,
372 unsigned UseIdx, unsigned UseAlign) const;
373 int getOperandLatency(const InstrItineraryData *ItinData,
374 const TargetInstrDesc &DefTID,
375 unsigned DefIdx, unsigned DefAlign,
376 const TargetInstrDesc &UseTID,
377 unsigned UseIdx, unsigned UseAlign) const;
379 int getInstrLatency(const InstrItineraryData *ItinData,
380 const MachineInstr *MI, unsigned *PredCost = 0) const;
382 int getInstrLatency(const InstrItineraryData *ItinData,
385 bool hasHighOperandLatency(const InstrItineraryData *ItinData,
386 const MachineRegisterInfo *MRI,
387 const MachineInstr *DefMI, unsigned DefIdx,
388 const MachineInstr *UseMI, unsigned UseIdx) const;
389 bool hasLowDefLatency(const InstrItineraryData *ItinData,
390 const MachineInstr *DefMI, unsigned DefIdx) const;
393 /// Modeling special VFP / NEON fp MLA / MLS hazards.
395 /// MLxEntryMap - Map fp MLA / MLS to the corresponding entry in the internal
397 DenseMap<unsigned, unsigned> MLxEntryMap;
399 /// MLxHazardOpcodes - Set of add / sub and multiply opcodes that would cause
400 /// stalls when scheduled together with fp MLA / MLS opcodes.
401 SmallSet<unsigned, 16> MLxHazardOpcodes;
404 /// isFpMLxInstruction - Return true if the specified opcode is a fp MLA / MLS
406 bool isFpMLxInstruction(unsigned Opcode) const {
407 return MLxEntryMap.count(Opcode);
410 /// isFpMLxInstruction - This version also returns the multiply opcode and the
411 /// addition / subtraction opcode to expand to. Return true for 'HasLane' for
412 /// the MLX instructions with an extra lane operand.
413 bool isFpMLxInstruction(unsigned Opcode, unsigned &MulOpc,
414 unsigned &AddSubOpc, bool &NegAcc,
415 bool &HasLane) const;
417 /// canCauseFpMLxStall - Return true if an instruction of the specified opcode
418 /// will cause stalls when scheduled after (within 4-cycle window) a fp
419 /// MLA / MLS instruction.
420 bool canCauseFpMLxStall(unsigned Opcode) const {
421 return MLxHazardOpcodes.count(Opcode);
426 const MachineInstrBuilder &AddDefaultPred(const MachineInstrBuilder &MIB) {
427 return MIB.addImm((int64_t)ARMCC::AL).addReg(0);
431 const MachineInstrBuilder &AddDefaultCC(const MachineInstrBuilder &MIB) {
432 return MIB.addReg(0);
436 const MachineInstrBuilder &AddDefaultT1CC(const MachineInstrBuilder &MIB,
437 bool isDead = false) {
438 return MIB.addReg(ARM::CPSR, getDefRegState(true) | getDeadRegState(isDead));
442 const MachineInstrBuilder &AddNoT1CC(const MachineInstrBuilder &MIB) {
443 return MIB.addReg(0);
447 bool isUncondBranchOpcode(int Opc) {
448 return Opc == ARM::B || Opc == ARM::tB || Opc == ARM::t2B;
452 bool isCondBranchOpcode(int Opc) {
453 return Opc == ARM::Bcc || Opc == ARM::tBcc || Opc == ARM::t2Bcc;
457 bool isJumpTableBranchOpcode(int Opc) {
458 return Opc == ARM::BR_JTr || Opc == ARM::BR_JTm || Opc == ARM::BR_JTadd ||
459 Opc == ARM::tBR_JTr || Opc == ARM::t2BR_JT;
463 bool isIndirectBranchOpcode(int Opc) {
464 return Opc == ARM::BX || Opc == ARM::MOVPCRX || Opc == ARM::tBRIND;
467 /// getInstrPredicate - If instruction is predicated, returns its predicate
468 /// condition, otherwise returns AL. It also returns the condition code
469 /// register by reference.
470 ARMCC::CondCodes getInstrPredicate(const MachineInstr *MI, unsigned &PredReg);
472 int getMatchingCondBranchOpcode(int Opc);
474 /// emitARMRegPlusImmediate / emitT2RegPlusImmediate - Emits a series of
475 /// instructions to materializea destreg = basereg + immediate in ARM / Thumb2
477 void emitARMRegPlusImmediate(MachineBasicBlock &MBB,
478 MachineBasicBlock::iterator &MBBI, DebugLoc dl,
479 unsigned DestReg, unsigned BaseReg, int NumBytes,
480 ARMCC::CondCodes Pred, unsigned PredReg,
481 const ARMBaseInstrInfo &TII, unsigned MIFlags = 0);
483 void emitT2RegPlusImmediate(MachineBasicBlock &MBB,
484 MachineBasicBlock::iterator &MBBI, DebugLoc dl,
485 unsigned DestReg, unsigned BaseReg, int NumBytes,
486 ARMCC::CondCodes Pred, unsigned PredReg,
487 const ARMBaseInstrInfo &TII, unsigned MIFlags = 0);
488 void emitThumbRegPlusImmediate(MachineBasicBlock &MBB,
489 MachineBasicBlock::iterator &MBBI, DebugLoc dl,
490 unsigned DestReg, unsigned BaseReg,
491 int NumBytes, const TargetInstrInfo &TII,
492 const ARMBaseRegisterInfo& MRI,
493 unsigned MIFlags = 0);
496 /// rewriteARMFrameIndex / rewriteT2FrameIndex -
497 /// Rewrite MI to access 'Offset' bytes from the FP. Return false if the
498 /// offset could not be handled directly in MI, and return the left-over
499 /// portion by reference.
500 bool rewriteARMFrameIndex(MachineInstr &MI, unsigned FrameRegIdx,
501 unsigned FrameReg, int &Offset,
502 const ARMBaseInstrInfo &TII);
504 bool rewriteT2FrameIndex(MachineInstr &MI, unsigned FrameRegIdx,
505 unsigned FrameReg, int &Offset,
506 const ARMBaseInstrInfo &TII);
508 } // End llvm namespace