1 //===- ARMBaseInstrInfo.h - ARM Base Instruction Information ----*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Base ARM implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #ifndef ARMBASEINSTRUCTIONINFO_H
15 #define ARMBASEINSTRUCTIONINFO_H
18 #include "ARMRegisterInfo.h"
19 #include "llvm/CodeGen/MachineInstrBuilder.h"
20 #include "llvm/Target/TargetInstrInfo.h"
24 /// ARMII - This namespace holds all of the target specific flags that
25 /// instruction info tracks.
29 //===------------------------------------------------------------------===//
32 //===------------------------------------------------------------------===//
33 // This four-bit field describes the addressing mode used.
46 AddrModeT1_s = 10, // i8 * 4 for pc and sp relative data
50 AddrModeT2_pc = 14, // +/- i12 for pc relative data
51 AddrModeT2_i8s4 = 15, // i8 * 4
53 // Size* - Flags to keep track of the size of an instruction.
55 SizeMask = 7 << SizeShift,
56 SizeSpecial = 1, // 0 byte pseudo or special case.
61 // IndexMode - Unindex, pre-indexed, or post-indexed are valid for load
62 // and store ops only. Generic "updating" flag is used for ld/st multiple.
64 IndexModeMask = 3 << IndexModeShift,
69 //===------------------------------------------------------------------===//
70 // Instruction encoding formats.
73 FormMask = 0x3f << FormShift,
75 // Pseudo instructions
76 Pseudo = 0 << FormShift,
78 // Multiply instructions
79 MulFrm = 1 << FormShift,
81 // Branch instructions
82 BrFrm = 2 << FormShift,
83 BrMiscFrm = 3 << FormShift,
85 // Data Processing instructions
86 DPFrm = 4 << FormShift,
87 DPSoRegFrm = 5 << FormShift,
90 LdFrm = 6 << FormShift,
91 StFrm = 7 << FormShift,
92 LdMiscFrm = 8 << FormShift,
93 StMiscFrm = 9 << FormShift,
94 LdStMulFrm = 10 << FormShift,
96 LdStExFrm = 11 << FormShift,
98 // Miscellaneous arithmetic instructions
99 ArithMiscFrm = 12 << FormShift,
101 // Extend instructions
102 ExtFrm = 13 << FormShift,
105 VFPUnaryFrm = 14 << FormShift,
106 VFPBinaryFrm = 15 << FormShift,
107 VFPConv1Frm = 16 << FormShift,
108 VFPConv2Frm = 17 << FormShift,
109 VFPConv3Frm = 18 << FormShift,
110 VFPConv4Frm = 19 << FormShift,
111 VFPConv5Frm = 20 << FormShift,
112 VFPLdStFrm = 21 << FormShift,
113 VFPLdStMulFrm = 22 << FormShift,
114 VFPMiscFrm = 23 << FormShift,
117 ThumbFrm = 24 << FormShift,
120 NEONFrm = 25 << FormShift,
121 NEONGetLnFrm = 26 << FormShift,
122 NEONSetLnFrm = 27 << FormShift,
123 NEONDupFrm = 28 << FormShift,
124 NLdStFrm = 31 << FormShift,
125 N1RegModImmFrm= 32 << FormShift,
126 N2RegFrm = 33 << FormShift,
127 NVCVTFrm = 34 << FormShift,
128 NVDupLnFrm = 35 << FormShift,
129 N2RegVShLFrm = 36 << FormShift,
130 N2RegVShRFrm = 37 << FormShift,
131 N3RegFrm = 38 << FormShift,
132 N3RegVShFrm = 39 << FormShift,
133 NVExtFrm = 40 << FormShift,
134 NVMulSLFrm = 41 << FormShift,
135 NVTBLFrm = 42 << FormShift,
137 //===------------------------------------------------------------------===//
140 // UnaryDP - Indicates this is a unary data processing instruction, i.e.
141 // it doesn't have a Rn operand.
144 // Xform16Bit - Indicates this Thumb2 instruction may be transformed into
145 // a 16-bit Thumb instruction if certain conditions are met.
146 Xform16Bit = 1 << 16,
148 //===------------------------------------------------------------------===//
151 DomainMask = 3 << DomainShift,
152 DomainGeneral = 0 << DomainShift,
153 DomainVFP = 1 << DomainShift,
154 DomainNEON = 2 << DomainShift,
156 //===------------------------------------------------------------------===//
157 // Field shifts - such shifts are used to set field while generating
158 // machine instructions.
181 /// Target Operand Flag enum.
183 //===------------------------------------------------------------------===//
184 // ARM Specific MachineOperand flags.
188 /// MO_LO16 - On a symbol operand, this represents a relocation containing
189 /// lower 16 bit of the address. Used only via movw instruction.
192 /// MO_HI16 - On a symbol operand, this represents a relocation containing
193 /// higher 16 bit of the address. Used only via movt instruction.
198 class ARMBaseInstrInfo : public TargetInstrInfoImpl {
199 const ARMSubtarget& Subtarget;
201 // Can be only subclassed.
202 explicit ARMBaseInstrInfo(const ARMSubtarget &STI);
204 // Return the non-pre/post incrementing version of 'Opc'. Return 0
205 // if there is not such an opcode.
206 virtual unsigned getUnindexedOpcode(unsigned Opc) const =0;
208 virtual MachineInstr *convertToThreeAddress(MachineFunction::iterator &MFI,
209 MachineBasicBlock::iterator &MBBI,
210 LiveVariables *LV) const;
212 virtual const ARMBaseRegisterInfo &getRegisterInfo() const =0;
213 const ARMSubtarget &getSubtarget() const { return Subtarget; }
215 bool spillCalleeSavedRegisters(MachineBasicBlock &MBB,
216 MachineBasicBlock::iterator MI,
217 const std::vector<CalleeSavedInfo> &CSI,
218 const TargetRegisterInfo *TRI) const;
221 virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
222 MachineBasicBlock *&FBB,
223 SmallVectorImpl<MachineOperand> &Cond,
224 bool AllowModify) const;
225 virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const;
226 virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
227 MachineBasicBlock *FBB,
228 const SmallVectorImpl<MachineOperand> &Cond) const;
231 bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const;
233 // Predication support.
234 bool isPredicated(const MachineInstr *MI) const {
235 int PIdx = MI->findFirstPredOperandIdx();
236 return PIdx != -1 && MI->getOperand(PIdx).getImm() != ARMCC::AL;
239 ARMCC::CondCodes getPredicate(const MachineInstr *MI) const {
240 int PIdx = MI->findFirstPredOperandIdx();
241 return PIdx != -1 ? (ARMCC::CondCodes)MI->getOperand(PIdx).getImm()
246 bool PredicateInstruction(MachineInstr *MI,
247 const SmallVectorImpl<MachineOperand> &Pred) const;
250 bool SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1,
251 const SmallVectorImpl<MachineOperand> &Pred2) const;
253 virtual bool DefinesPredicate(MachineInstr *MI,
254 std::vector<MachineOperand> &Pred) const;
256 virtual bool isPredicable(MachineInstr *MI) const;
258 /// GetInstSize - Returns the size of the specified MachineInstr.
260 virtual unsigned GetInstSizeInBytes(const MachineInstr* MI) const;
262 /// Return true if the instruction is a register to register move and return
263 /// the source and dest operands and their sub-register indices by reference.
264 virtual bool isMoveInstr(const MachineInstr &MI,
265 unsigned &SrcReg, unsigned &DstReg,
266 unsigned &SrcSubIdx, unsigned &DstSubIdx) const;
268 virtual unsigned isLoadFromStackSlot(const MachineInstr *MI,
269 int &FrameIndex) const;
270 virtual unsigned isStoreToStackSlot(const MachineInstr *MI,
271 int &FrameIndex) const;
273 virtual bool copyRegToReg(MachineBasicBlock &MBB,
274 MachineBasicBlock::iterator I,
275 unsigned DestReg, unsigned SrcReg,
276 const TargetRegisterClass *DestRC,
277 const TargetRegisterClass *SrcRC,
280 virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
281 MachineBasicBlock::iterator MBBI,
282 unsigned SrcReg, bool isKill, int FrameIndex,
283 const TargetRegisterClass *RC,
284 const TargetRegisterInfo *TRI) const;
286 virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
287 MachineBasicBlock::iterator MBBI,
288 unsigned DestReg, int FrameIndex,
289 const TargetRegisterClass *RC,
290 const TargetRegisterInfo *TRI) const;
292 virtual MachineInstr *emitFrameIndexDebugValue(MachineFunction &MF,
298 virtual bool canFoldMemoryOperand(const MachineInstr *MI,
299 const SmallVectorImpl<unsigned> &Ops) const;
301 virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF,
303 const SmallVectorImpl<unsigned> &Ops,
304 int FrameIndex) const;
306 virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF,
308 const SmallVectorImpl<unsigned> &Ops,
309 MachineInstr* LoadMI) const;
311 virtual void reMaterialize(MachineBasicBlock &MBB,
312 MachineBasicBlock::iterator MI,
313 unsigned DestReg, unsigned SubIdx,
314 const MachineInstr *Orig,
315 const TargetRegisterInfo &TRI) const;
317 MachineInstr *duplicate(MachineInstr *Orig, MachineFunction &MF) const;
319 virtual bool produceSameValue(const MachineInstr *MI0,
320 const MachineInstr *MI1) const;
324 const MachineInstrBuilder &AddDefaultPred(const MachineInstrBuilder &MIB) {
325 return MIB.addImm((int64_t)ARMCC::AL).addReg(0);
329 const MachineInstrBuilder &AddDefaultCC(const MachineInstrBuilder &MIB) {
330 return MIB.addReg(0);
334 const MachineInstrBuilder &AddDefaultT1CC(const MachineInstrBuilder &MIB,
335 bool isDead = false) {
336 return MIB.addReg(ARM::CPSR, getDefRegState(true) | getDeadRegState(isDead));
340 const MachineInstrBuilder &AddNoT1CC(const MachineInstrBuilder &MIB) {
341 return MIB.addReg(0);
345 bool isUncondBranchOpcode(int Opc) {
346 return Opc == ARM::B || Opc == ARM::tB || Opc == ARM::t2B;
350 bool isCondBranchOpcode(int Opc) {
351 return Opc == ARM::Bcc || Opc == ARM::tBcc || Opc == ARM::t2Bcc;
355 bool isJumpTableBranchOpcode(int Opc) {
356 return Opc == ARM::BR_JTr || Opc == ARM::BR_JTm || Opc == ARM::BR_JTadd ||
357 Opc == ARM::tBR_JTr || Opc == ARM::t2BR_JT;
361 bool isIndirectBranchOpcode(int Opc) {
362 return Opc == ARM::BRIND || Opc == ARM::MOVPCRX || Opc == ARM::tBRIND;
365 /// getInstrPredicate - If instruction is predicated, returns its predicate
366 /// condition, otherwise returns AL. It also returns the condition code
367 /// register by reference.
368 ARMCC::CondCodes getInstrPredicate(const MachineInstr *MI, unsigned &PredReg);
370 int getMatchingCondBranchOpcode(int Opc);
372 /// emitARMRegPlusImmediate / emitT2RegPlusImmediate - Emits a series of
373 /// instructions to materializea destreg = basereg + immediate in ARM / Thumb2
375 void emitARMRegPlusImmediate(MachineBasicBlock &MBB,
376 MachineBasicBlock::iterator &MBBI, DebugLoc dl,
377 unsigned DestReg, unsigned BaseReg, int NumBytes,
378 ARMCC::CondCodes Pred, unsigned PredReg,
379 const ARMBaseInstrInfo &TII);
381 void emitT2RegPlusImmediate(MachineBasicBlock &MBB,
382 MachineBasicBlock::iterator &MBBI, DebugLoc dl,
383 unsigned DestReg, unsigned BaseReg, int NumBytes,
384 ARMCC::CondCodes Pred, unsigned PredReg,
385 const ARMBaseInstrInfo &TII);
388 /// rewriteARMFrameIndex / rewriteT2FrameIndex -
389 /// Rewrite MI to access 'Offset' bytes from the FP. Return false if the
390 /// offset could not be handled directly in MI, and return the left-over
391 /// portion by reference.
392 bool rewriteARMFrameIndex(MachineInstr &MI, unsigned FrameRegIdx,
393 unsigned FrameReg, int &Offset,
394 const ARMBaseInstrInfo &TII);
396 bool rewriteT2FrameIndex(MachineInstr &MI, unsigned FrameRegIdx,
397 unsigned FrameReg, int &Offset,
398 const ARMBaseInstrInfo &TII);
400 } // End llvm namespace