1 //===- ARMBaseInstrInfo.cpp - ARM Instruction Information -------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Base ARM implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "ARMBaseInstrInfo.h"
16 #include "ARMConstantPoolValue.h"
17 #include "ARMHazardRecognizer.h"
18 #include "ARMMachineFunctionInfo.h"
19 #include "ARMRegisterInfo.h"
20 #include "MCTargetDesc/ARMAddressingModes.h"
21 #include "llvm/Constants.h"
22 #include "llvm/Function.h"
23 #include "llvm/GlobalValue.h"
24 #include "llvm/CodeGen/LiveVariables.h"
25 #include "llvm/CodeGen/MachineConstantPool.h"
26 #include "llvm/CodeGen/MachineFrameInfo.h"
27 #include "llvm/CodeGen/MachineInstrBuilder.h"
28 #include "llvm/CodeGen/MachineJumpTableInfo.h"
29 #include "llvm/CodeGen/MachineMemOperand.h"
30 #include "llvm/CodeGen/MachineRegisterInfo.h"
31 #include "llvm/CodeGen/PseudoSourceValue.h"
32 #include "llvm/CodeGen/SelectionDAGNodes.h"
33 #include "llvm/MC/MCAsmInfo.h"
34 #include "llvm/Support/BranchProbability.h"
35 #include "llvm/Support/CommandLine.h"
36 #include "llvm/Support/Debug.h"
37 #include "llvm/Support/ErrorHandling.h"
38 #include "llvm/ADT/STLExtras.h"
40 #define GET_INSTRINFO_CTOR
41 #include "ARMGenInstrInfo.inc"
46 EnableARM3Addr("enable-arm-3-addr-conv", cl::Hidden,
47 cl::desc("Enable ARM 2-addr to 3-addr conv"));
50 WidenVMOVS("widen-vmovs", cl::Hidden,
51 cl::desc("Widen ARM vmovs to vmovd when possible"));
53 /// ARM_MLxEntry - Record information about MLA / MLS instructions.
55 unsigned MLxOpc; // MLA / MLS opcode
56 unsigned MulOpc; // Expanded multiplication opcode
57 unsigned AddSubOpc; // Expanded add / sub opcode
58 bool NegAcc; // True if the acc is negated before the add / sub.
59 bool HasLane; // True if instruction has an extra "lane" operand.
62 static const ARM_MLxEntry ARM_MLxTable[] = {
63 // MLxOpc, MulOpc, AddSubOpc, NegAcc, HasLane
65 { ARM::VMLAS, ARM::VMULS, ARM::VADDS, false, false },
66 { ARM::VMLSS, ARM::VMULS, ARM::VSUBS, false, false },
67 { ARM::VMLAD, ARM::VMULD, ARM::VADDD, false, false },
68 { ARM::VMLSD, ARM::VMULD, ARM::VSUBD, false, false },
69 { ARM::VNMLAS, ARM::VNMULS, ARM::VSUBS, true, false },
70 { ARM::VNMLSS, ARM::VMULS, ARM::VSUBS, true, false },
71 { ARM::VNMLAD, ARM::VNMULD, ARM::VSUBD, true, false },
72 { ARM::VNMLSD, ARM::VMULD, ARM::VSUBD, true, false },
75 { ARM::VMLAfd, ARM::VMULfd, ARM::VADDfd, false, false },
76 { ARM::VMLSfd, ARM::VMULfd, ARM::VSUBfd, false, false },
77 { ARM::VMLAfq, ARM::VMULfq, ARM::VADDfq, false, false },
78 { ARM::VMLSfq, ARM::VMULfq, ARM::VSUBfq, false, false },
79 { ARM::VMLAslfd, ARM::VMULslfd, ARM::VADDfd, false, true },
80 { ARM::VMLSslfd, ARM::VMULslfd, ARM::VSUBfd, false, true },
81 { ARM::VMLAslfq, ARM::VMULslfq, ARM::VADDfq, false, true },
82 { ARM::VMLSslfq, ARM::VMULslfq, ARM::VSUBfq, false, true },
85 ARMBaseInstrInfo::ARMBaseInstrInfo(const ARMSubtarget& STI)
86 : ARMGenInstrInfo(ARM::ADJCALLSTACKDOWN, ARM::ADJCALLSTACKUP),
88 for (unsigned i = 0, e = array_lengthof(ARM_MLxTable); i != e; ++i) {
89 if (!MLxEntryMap.insert(std::make_pair(ARM_MLxTable[i].MLxOpc, i)).second)
90 assert(false && "Duplicated entries?");
91 MLxHazardOpcodes.insert(ARM_MLxTable[i].AddSubOpc);
92 MLxHazardOpcodes.insert(ARM_MLxTable[i].MulOpc);
96 // Use a ScoreboardHazardRecognizer for prepass ARM scheduling. TargetInstrImpl
97 // currently defaults to no prepass hazard recognizer.
98 ScheduleHazardRecognizer *ARMBaseInstrInfo::
99 CreateTargetHazardRecognizer(const TargetMachine *TM,
100 const ScheduleDAG *DAG) const {
101 if (usePreRAHazardRecognizer()) {
102 const InstrItineraryData *II = TM->getInstrItineraryData();
103 return new ScoreboardHazardRecognizer(II, DAG, "pre-RA-sched");
105 return TargetInstrInfoImpl::CreateTargetHazardRecognizer(TM, DAG);
108 ScheduleHazardRecognizer *ARMBaseInstrInfo::
109 CreateTargetPostRAHazardRecognizer(const InstrItineraryData *II,
110 const ScheduleDAG *DAG) const {
111 if (Subtarget.isThumb2() || Subtarget.hasVFP2())
112 return (ScheduleHazardRecognizer *)
113 new ARMHazardRecognizer(II, *this, getRegisterInfo(), Subtarget, DAG);
114 return TargetInstrInfoImpl::CreateTargetPostRAHazardRecognizer(II, DAG);
118 ARMBaseInstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
119 MachineBasicBlock::iterator &MBBI,
120 LiveVariables *LV) const {
121 // FIXME: Thumb2 support.
126 MachineInstr *MI = MBBI;
127 MachineFunction &MF = *MI->getParent()->getParent();
128 uint64_t TSFlags = MI->getDesc().TSFlags;
130 switch ((TSFlags & ARMII::IndexModeMask) >> ARMII::IndexModeShift) {
131 default: return NULL;
132 case ARMII::IndexModePre:
135 case ARMII::IndexModePost:
139 // Try splitting an indexed load/store to an un-indexed one plus an add/sub
141 unsigned MemOpc = getUnindexedOpcode(MI->getOpcode());
145 MachineInstr *UpdateMI = NULL;
146 MachineInstr *MemMI = NULL;
147 unsigned AddrMode = (TSFlags & ARMII::AddrModeMask);
148 const MCInstrDesc &MCID = MI->getDesc();
149 unsigned NumOps = MCID.getNumOperands();
150 bool isLoad = !MCID.mayStore();
151 const MachineOperand &WB = isLoad ? MI->getOperand(1) : MI->getOperand(0);
152 const MachineOperand &Base = MI->getOperand(2);
153 const MachineOperand &Offset = MI->getOperand(NumOps-3);
154 unsigned WBReg = WB.getReg();
155 unsigned BaseReg = Base.getReg();
156 unsigned OffReg = Offset.getReg();
157 unsigned OffImm = MI->getOperand(NumOps-2).getImm();
158 ARMCC::CondCodes Pred = (ARMCC::CondCodes)MI->getOperand(NumOps-1).getImm();
161 assert(false && "Unknown indexed op!");
163 case ARMII::AddrMode2: {
164 bool isSub = ARM_AM::getAM2Op(OffImm) == ARM_AM::sub;
165 unsigned Amt = ARM_AM::getAM2Offset(OffImm);
167 if (ARM_AM::getSOImmVal(Amt) == -1)
168 // Can't encode it in a so_imm operand. This transformation will
169 // add more than 1 instruction. Abandon!
171 UpdateMI = BuildMI(MF, MI->getDebugLoc(),
172 get(isSub ? ARM::SUBri : ARM::ADDri), WBReg)
173 .addReg(BaseReg).addImm(Amt)
174 .addImm(Pred).addReg(0).addReg(0);
175 } else if (Amt != 0) {
176 ARM_AM::ShiftOpc ShOpc = ARM_AM::getAM2ShiftOpc(OffImm);
177 unsigned SOOpc = ARM_AM::getSORegOpc(ShOpc, Amt);
178 UpdateMI = BuildMI(MF, MI->getDebugLoc(),
179 get(isSub ? ARM::SUBrsi : ARM::ADDrsi), WBReg)
180 .addReg(BaseReg).addReg(OffReg).addReg(0).addImm(SOOpc)
181 .addImm(Pred).addReg(0).addReg(0);
183 UpdateMI = BuildMI(MF, MI->getDebugLoc(),
184 get(isSub ? ARM::SUBrr : ARM::ADDrr), WBReg)
185 .addReg(BaseReg).addReg(OffReg)
186 .addImm(Pred).addReg(0).addReg(0);
189 case ARMII::AddrMode3 : {
190 bool isSub = ARM_AM::getAM3Op(OffImm) == ARM_AM::sub;
191 unsigned Amt = ARM_AM::getAM3Offset(OffImm);
193 // Immediate is 8-bits. It's guaranteed to fit in a so_imm operand.
194 UpdateMI = BuildMI(MF, MI->getDebugLoc(),
195 get(isSub ? ARM::SUBri : ARM::ADDri), WBReg)
196 .addReg(BaseReg).addImm(Amt)
197 .addImm(Pred).addReg(0).addReg(0);
199 UpdateMI = BuildMI(MF, MI->getDebugLoc(),
200 get(isSub ? ARM::SUBrr : ARM::ADDrr), WBReg)
201 .addReg(BaseReg).addReg(OffReg)
202 .addImm(Pred).addReg(0).addReg(0);
207 std::vector<MachineInstr*> NewMIs;
210 MemMI = BuildMI(MF, MI->getDebugLoc(),
211 get(MemOpc), MI->getOperand(0).getReg())
212 .addReg(WBReg).addImm(0).addImm(Pred);
214 MemMI = BuildMI(MF, MI->getDebugLoc(),
215 get(MemOpc)).addReg(MI->getOperand(1).getReg())
216 .addReg(WBReg).addReg(0).addImm(0).addImm(Pred);
217 NewMIs.push_back(MemMI);
218 NewMIs.push_back(UpdateMI);
221 MemMI = BuildMI(MF, MI->getDebugLoc(),
222 get(MemOpc), MI->getOperand(0).getReg())
223 .addReg(BaseReg).addImm(0).addImm(Pred);
225 MemMI = BuildMI(MF, MI->getDebugLoc(),
226 get(MemOpc)).addReg(MI->getOperand(1).getReg())
227 .addReg(BaseReg).addReg(0).addImm(0).addImm(Pred);
229 UpdateMI->getOperand(0).setIsDead();
230 NewMIs.push_back(UpdateMI);
231 NewMIs.push_back(MemMI);
234 // Transfer LiveVariables states, kill / dead info.
236 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
237 MachineOperand &MO = MI->getOperand(i);
238 if (MO.isReg() && TargetRegisterInfo::isVirtualRegister(MO.getReg())) {
239 unsigned Reg = MO.getReg();
241 LiveVariables::VarInfo &VI = LV->getVarInfo(Reg);
243 MachineInstr *NewMI = (Reg == WBReg) ? UpdateMI : MemMI;
245 LV->addVirtualRegisterDead(Reg, NewMI);
247 if (MO.isUse() && MO.isKill()) {
248 for (unsigned j = 0; j < 2; ++j) {
249 // Look at the two new MI's in reverse order.
250 MachineInstr *NewMI = NewMIs[j];
251 if (!NewMI->readsRegister(Reg))
253 LV->addVirtualRegisterKilled(Reg, NewMI);
254 if (VI.removeKill(MI))
255 VI.Kills.push_back(NewMI);
263 MFI->insert(MBBI, NewMIs[1]);
264 MFI->insert(MBBI, NewMIs[0]);
270 ARMBaseInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB,
271 MachineBasicBlock *&FBB,
272 SmallVectorImpl<MachineOperand> &Cond,
273 bool AllowModify) const {
274 // If the block has no terminators, it just falls into the block after it.
275 MachineBasicBlock::iterator I = MBB.end();
276 if (I == MBB.begin())
279 while (I->isDebugValue()) {
280 if (I == MBB.begin())
284 if (!isUnpredicatedTerminator(I))
287 // Get the last instruction in the block.
288 MachineInstr *LastInst = I;
290 // If there is only one terminator instruction, process it.
291 unsigned LastOpc = LastInst->getOpcode();
292 if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) {
293 if (isUncondBranchOpcode(LastOpc)) {
294 TBB = LastInst->getOperand(0).getMBB();
297 if (isCondBranchOpcode(LastOpc)) {
298 // Block ends with fall-through condbranch.
299 TBB = LastInst->getOperand(0).getMBB();
300 Cond.push_back(LastInst->getOperand(1));
301 Cond.push_back(LastInst->getOperand(2));
304 return true; // Can't handle indirect branch.
307 // Get the instruction before it if it is a terminator.
308 MachineInstr *SecondLastInst = I;
309 unsigned SecondLastOpc = SecondLastInst->getOpcode();
311 // If AllowModify is true and the block ends with two or more unconditional
312 // branches, delete all but the first unconditional branch.
313 if (AllowModify && isUncondBranchOpcode(LastOpc)) {
314 while (isUncondBranchOpcode(SecondLastOpc)) {
315 LastInst->eraseFromParent();
316 LastInst = SecondLastInst;
317 LastOpc = LastInst->getOpcode();
318 if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) {
319 // Return now the only terminator is an unconditional branch.
320 TBB = LastInst->getOperand(0).getMBB();
324 SecondLastOpc = SecondLastInst->getOpcode();
329 // If there are three terminators, we don't know what sort of block this is.
330 if (SecondLastInst && I != MBB.begin() && isUnpredicatedTerminator(--I))
333 // If the block ends with a B and a Bcc, handle it.
334 if (isCondBranchOpcode(SecondLastOpc) && isUncondBranchOpcode(LastOpc)) {
335 TBB = SecondLastInst->getOperand(0).getMBB();
336 Cond.push_back(SecondLastInst->getOperand(1));
337 Cond.push_back(SecondLastInst->getOperand(2));
338 FBB = LastInst->getOperand(0).getMBB();
342 // If the block ends with two unconditional branches, handle it. The second
343 // one is not executed, so remove it.
344 if (isUncondBranchOpcode(SecondLastOpc) && isUncondBranchOpcode(LastOpc)) {
345 TBB = SecondLastInst->getOperand(0).getMBB();
348 I->eraseFromParent();
352 // ...likewise if it ends with a branch table followed by an unconditional
353 // branch. The branch folder can create these, and we must get rid of them for
354 // correctness of Thumb constant islands.
355 if ((isJumpTableBranchOpcode(SecondLastOpc) ||
356 isIndirectBranchOpcode(SecondLastOpc)) &&
357 isUncondBranchOpcode(LastOpc)) {
360 I->eraseFromParent();
364 // Otherwise, can't handle this.
369 unsigned ARMBaseInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
370 MachineBasicBlock::iterator I = MBB.end();
371 if (I == MBB.begin()) return 0;
373 while (I->isDebugValue()) {
374 if (I == MBB.begin())
378 if (!isUncondBranchOpcode(I->getOpcode()) &&
379 !isCondBranchOpcode(I->getOpcode()))
382 // Remove the branch.
383 I->eraseFromParent();
387 if (I == MBB.begin()) return 1;
389 if (!isCondBranchOpcode(I->getOpcode()))
392 // Remove the branch.
393 I->eraseFromParent();
398 ARMBaseInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
399 MachineBasicBlock *FBB,
400 const SmallVectorImpl<MachineOperand> &Cond,
402 ARMFunctionInfo *AFI = MBB.getParent()->getInfo<ARMFunctionInfo>();
403 int BOpc = !AFI->isThumbFunction()
404 ? ARM::B : (AFI->isThumb2Function() ? ARM::t2B : ARM::tB);
405 int BccOpc = !AFI->isThumbFunction()
406 ? ARM::Bcc : (AFI->isThumb2Function() ? ARM::t2Bcc : ARM::tBcc);
407 bool isThumb = AFI->isThumbFunction() || AFI->isThumb2Function();
409 // Shouldn't be a fall through.
410 assert(TBB && "InsertBranch must not be told to insert a fallthrough");
411 assert((Cond.size() == 2 || Cond.size() == 0) &&
412 "ARM branch conditions have two components!");
415 if (Cond.empty()) { // Unconditional branch?
417 BuildMI(&MBB, DL, get(BOpc)).addMBB(TBB).addImm(ARMCC::AL).addReg(0);
419 BuildMI(&MBB, DL, get(BOpc)).addMBB(TBB);
421 BuildMI(&MBB, DL, get(BccOpc)).addMBB(TBB)
422 .addImm(Cond[0].getImm()).addReg(Cond[1].getReg());
426 // Two-way conditional branch.
427 BuildMI(&MBB, DL, get(BccOpc)).addMBB(TBB)
428 .addImm(Cond[0].getImm()).addReg(Cond[1].getReg());
430 BuildMI(&MBB, DL, get(BOpc)).addMBB(FBB).addImm(ARMCC::AL).addReg(0);
432 BuildMI(&MBB, DL, get(BOpc)).addMBB(FBB);
436 bool ARMBaseInstrInfo::
437 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
438 ARMCC::CondCodes CC = (ARMCC::CondCodes)(int)Cond[0].getImm();
439 Cond[0].setImm(ARMCC::getOppositeCondition(CC));
443 bool ARMBaseInstrInfo::
444 PredicateInstruction(MachineInstr *MI,
445 const SmallVectorImpl<MachineOperand> &Pred) const {
446 unsigned Opc = MI->getOpcode();
447 if (isUncondBranchOpcode(Opc)) {
448 MI->setDesc(get(getMatchingCondBranchOpcode(Opc)));
449 MI->addOperand(MachineOperand::CreateImm(Pred[0].getImm()));
450 MI->addOperand(MachineOperand::CreateReg(Pred[1].getReg(), false));
454 int PIdx = MI->findFirstPredOperandIdx();
456 MachineOperand &PMO = MI->getOperand(PIdx);
457 PMO.setImm(Pred[0].getImm());
458 MI->getOperand(PIdx+1).setReg(Pred[1].getReg());
464 bool ARMBaseInstrInfo::
465 SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1,
466 const SmallVectorImpl<MachineOperand> &Pred2) const {
467 if (Pred1.size() > 2 || Pred2.size() > 2)
470 ARMCC::CondCodes CC1 = (ARMCC::CondCodes)Pred1[0].getImm();
471 ARMCC::CondCodes CC2 = (ARMCC::CondCodes)Pred2[0].getImm();
481 return CC2 == ARMCC::HI;
483 return CC2 == ARMCC::LO || CC2 == ARMCC::EQ;
485 return CC2 == ARMCC::GT;
487 return CC2 == ARMCC::LT;
491 bool ARMBaseInstrInfo::DefinesPredicate(MachineInstr *MI,
492 std::vector<MachineOperand> &Pred) const {
493 // FIXME: This confuses implicit_def with optional CPSR def.
494 const MCInstrDesc &MCID = MI->getDesc();
495 if (!MCID.getImplicitDefs() && !MCID.hasOptionalDef())
499 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
500 const MachineOperand &MO = MI->getOperand(i);
501 if (MO.isReg() && MO.getReg() == ARM::CPSR) {
510 /// isPredicable - Return true if the specified instruction can be predicated.
511 /// By default, this returns true for every instruction with a
512 /// PredicateOperand.
513 bool ARMBaseInstrInfo::isPredicable(MachineInstr *MI) const {
514 const MCInstrDesc &MCID = MI->getDesc();
515 if (!MCID.isPredicable())
518 if ((MCID.TSFlags & ARMII::DomainMask) == ARMII::DomainNEON) {
519 ARMFunctionInfo *AFI =
520 MI->getParent()->getParent()->getInfo<ARMFunctionInfo>();
521 return AFI->isThumb2Function();
526 /// FIXME: Works around a gcc miscompilation with -fstrict-aliasing.
527 LLVM_ATTRIBUTE_NOINLINE
528 static unsigned getNumJTEntries(const std::vector<MachineJumpTableEntry> &JT,
530 static unsigned getNumJTEntries(const std::vector<MachineJumpTableEntry> &JT,
532 assert(JTI < JT.size());
533 return JT[JTI].MBBs.size();
536 /// GetInstSize - Return the size of the specified MachineInstr.
538 unsigned ARMBaseInstrInfo::GetInstSizeInBytes(const MachineInstr *MI) const {
539 const MachineBasicBlock &MBB = *MI->getParent();
540 const MachineFunction *MF = MBB.getParent();
541 const MCAsmInfo *MAI = MF->getTarget().getMCAsmInfo();
543 const MCInstrDesc &MCID = MI->getDesc();
545 return MCID.getSize();
547 // If this machine instr is an inline asm, measure it.
548 if (MI->getOpcode() == ARM::INLINEASM)
549 return getInlineAsmLength(MI->getOperand(0).getSymbolName(), *MAI);
552 unsigned Opc = MI->getOpcode();
554 case TargetOpcode::IMPLICIT_DEF:
555 case TargetOpcode::KILL:
556 case TargetOpcode::PROLOG_LABEL:
557 case TargetOpcode::EH_LABEL:
558 case TargetOpcode::DBG_VALUE:
560 case ARM::MOVi16_ga_pcrel:
561 case ARM::MOVTi16_ga_pcrel:
562 case ARM::t2MOVi16_ga_pcrel:
563 case ARM::t2MOVTi16_ga_pcrel:
566 case ARM::t2MOVi32imm:
568 case ARM::CONSTPOOL_ENTRY:
569 // If this machine instr is a constant pool entry, its size is recorded as
571 return MI->getOperand(2).getImm();
572 case ARM::Int_eh_sjlj_longjmp:
574 case ARM::tInt_eh_sjlj_longjmp:
576 case ARM::Int_eh_sjlj_setjmp:
577 case ARM::Int_eh_sjlj_setjmp_nofp:
579 case ARM::tInt_eh_sjlj_setjmp:
580 case ARM::t2Int_eh_sjlj_setjmp:
581 case ARM::t2Int_eh_sjlj_setjmp_nofp:
589 case ARM::t2TBH_JT: {
590 // These are jumptable branches, i.e. a branch followed by an inlined
591 // jumptable. The size is 4 + 4 * number of entries. For TBB, each
592 // entry is one byte; TBH two byte each.
593 unsigned EntrySize = (Opc == ARM::t2TBB_JT)
594 ? 1 : ((Opc == ARM::t2TBH_JT) ? 2 : 4);
595 unsigned NumOps = MCID.getNumOperands();
596 MachineOperand JTOP =
597 MI->getOperand(NumOps - (MCID.isPredicable() ? 3 : 2));
598 unsigned JTI = JTOP.getIndex();
599 const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
601 const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
602 assert(JTI < JT.size());
603 // Thumb instructions are 2 byte aligned, but JT entries are 4 byte
604 // 4 aligned. The assembler / linker may add 2 byte padding just before
605 // the JT entries. The size does not include this padding; the
606 // constant islands pass does separate bookkeeping for it.
607 // FIXME: If we know the size of the function is less than (1 << 16) *2
608 // bytes, we can use 16-bit entries instead. Then there won't be an
610 unsigned InstSize = (Opc == ARM::tBR_JTr || Opc == ARM::t2BR_JT) ? 2 : 4;
611 unsigned NumEntries = getNumJTEntries(JT, JTI);
612 if (Opc == ARM::t2TBB_JT && (NumEntries & 1))
613 // Make sure the instruction that follows TBB is 2-byte aligned.
614 // FIXME: Constant island pass should insert an "ALIGN" instruction
617 return NumEntries * EntrySize + InstSize;
620 // Otherwise, pseudo-instruction sizes are zero.
623 return 0; // Not reached
626 void ARMBaseInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
627 MachineBasicBlock::iterator I, DebugLoc DL,
628 unsigned DestReg, unsigned SrcReg,
629 bool KillSrc) const {
630 bool GPRDest = ARM::GPRRegClass.contains(DestReg);
631 bool GPRSrc = ARM::GPRRegClass.contains(SrcReg);
633 if (GPRDest && GPRSrc) {
634 AddDefaultCC(AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::MOVr), DestReg)
635 .addReg(SrcReg, getKillRegState(KillSrc))));
639 bool SPRDest = ARM::SPRRegClass.contains(DestReg);
640 bool SPRSrc = ARM::SPRRegClass.contains(SrcReg);
643 if (SPRDest && SPRSrc) {
646 // An even S-S copy may be feeding a NEON v2f32 instruction being used for
647 // f32 operations. In that case, it is better to copy the full D-regs with
648 // a VMOVD since that can be converted to a NEON-domain move by
649 // NEONMoveFix.cpp. Check that MI is the original COPY instruction, and
650 // that it really defines the whole D-register.
652 (DestReg - ARM::S0) % 2 == 0 && (SrcReg - ARM::S0) % 2 == 0 &&
653 I != MBB.end() && I->isCopy() &&
654 I->getOperand(0).getReg() == DestReg &&
655 I->getOperand(1).getReg() == SrcReg) {
656 // I is pointing to the ortiginal COPY instruction.
657 // Find the parent D-registers.
658 const TargetRegisterInfo *TRI = &getRegisterInfo();
659 unsigned SrcD = TRI->getMatchingSuperReg(SrcReg, ARM::ssub_0,
661 unsigned DestD = TRI->getMatchingSuperReg(DestReg, ARM::ssub_0,
663 // Be careful to not clobber an INSERT_SUBREG that reads and redefines a
664 // D-register. There must be an <imp-def> of destD, and no <imp-use>.
665 if (I->definesRegister(DestD, TRI) && !I->readsRegister(DestD, TRI)) {
670 KillSrc = I->killsRegister(SrcReg, TRI);
673 } else if (GPRDest && SPRSrc)
675 else if (SPRDest && GPRSrc)
677 else if (ARM::DPRRegClass.contains(DestReg, SrcReg))
679 else if (ARM::QPRRegClass.contains(DestReg, SrcReg))
683 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(Opc), DestReg);
684 MIB.addReg(SrcReg, getKillRegState(KillSrc));
685 if (Opc == ARM::VORRq)
686 MIB.addReg(SrcReg, getKillRegState(KillSrc));
691 // Generate instructions for VMOVQQ and VMOVQQQQ pseudos in place.
692 if (ARM::QQPRRegClass.contains(DestReg, SrcReg) ||
693 ARM::QQQQPRRegClass.contains(DestReg, SrcReg)) {
694 const TargetRegisterInfo *TRI = &getRegisterInfo();
695 assert(ARM::qsub_0 + 3 == ARM::qsub_3 && "Expected contiguous enum.");
696 unsigned EndSubReg = ARM::QQPRRegClass.contains(DestReg, SrcReg) ?
697 ARM::qsub_1 : ARM::qsub_3;
698 for (unsigned i = ARM::qsub_0, e = EndSubReg + 1; i != e; ++i) {
699 unsigned Dst = TRI->getSubReg(DestReg, i);
700 unsigned Src = TRI->getSubReg(SrcReg, i);
701 MachineInstrBuilder Mov =
702 AddDefaultPred(BuildMI(MBB, I, I->getDebugLoc(), get(ARM::VORRq))
703 .addReg(Dst, RegState::Define)
704 .addReg(Src, getKillRegState(KillSrc))
705 .addReg(Src, getKillRegState(KillSrc)));
706 if (i == EndSubReg) {
707 Mov->addRegisterDefined(DestReg, TRI);
709 Mov->addRegisterKilled(SrcReg, TRI);
714 llvm_unreachable("Impossible reg-to-reg copy");
718 MachineInstrBuilder &AddDReg(MachineInstrBuilder &MIB,
719 unsigned Reg, unsigned SubIdx, unsigned State,
720 const TargetRegisterInfo *TRI) {
722 return MIB.addReg(Reg, State);
724 if (TargetRegisterInfo::isPhysicalRegister(Reg))
725 return MIB.addReg(TRI->getSubReg(Reg, SubIdx), State);
726 return MIB.addReg(Reg, State, SubIdx);
729 void ARMBaseInstrInfo::
730 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
731 unsigned SrcReg, bool isKill, int FI,
732 const TargetRegisterClass *RC,
733 const TargetRegisterInfo *TRI) const {
735 if (I != MBB.end()) DL = I->getDebugLoc();
736 MachineFunction &MF = *MBB.getParent();
737 MachineFrameInfo &MFI = *MF.getFrameInfo();
738 unsigned Align = MFI.getObjectAlignment(FI);
740 MachineMemOperand *MMO =
741 MF.getMachineMemOperand(MachinePointerInfo(
742 PseudoSourceValue::getFixedStack(FI)),
743 MachineMemOperand::MOStore,
744 MFI.getObjectSize(FI),
747 switch (RC->getSize()) {
749 if (ARM::GPRRegClass.hasSubClassEq(RC)) {
750 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::STRi12))
751 .addReg(SrcReg, getKillRegState(isKill))
752 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
753 } else if (ARM::SPRRegClass.hasSubClassEq(RC)) {
754 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTRS))
755 .addReg(SrcReg, getKillRegState(isKill))
756 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
758 llvm_unreachable("Unknown reg class!");
761 if (ARM::DPRRegClass.hasSubClassEq(RC)) {
762 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTRD))
763 .addReg(SrcReg, getKillRegState(isKill))
764 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
766 llvm_unreachable("Unknown reg class!");
769 if (ARM::QPRRegClass.hasSubClassEq(RC)) {
770 if (Align >= 16 && getRegisterInfo().needsStackRealignment(MF)) {
771 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VST1q64Pseudo))
772 .addFrameIndex(FI).addImm(16)
773 .addReg(SrcReg, getKillRegState(isKill))
774 .addMemOperand(MMO));
776 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTMQIA))
777 .addReg(SrcReg, getKillRegState(isKill))
779 .addMemOperand(MMO));
782 llvm_unreachable("Unknown reg class!");
785 if (ARM::QQPRRegClass.hasSubClassEq(RC)) {
786 if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) {
787 // FIXME: It's possible to only store part of the QQ register if the
788 // spilled def has a sub-register index.
789 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VST1d64QPseudo))
790 .addFrameIndex(FI).addImm(16)
791 .addReg(SrcReg, getKillRegState(isKill))
792 .addMemOperand(MMO));
794 MachineInstrBuilder MIB =
795 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTMDIA))
798 MIB = AddDReg(MIB, SrcReg, ARM::dsub_0, getKillRegState(isKill), TRI);
799 MIB = AddDReg(MIB, SrcReg, ARM::dsub_1, 0, TRI);
800 MIB = AddDReg(MIB, SrcReg, ARM::dsub_2, 0, TRI);
801 AddDReg(MIB, SrcReg, ARM::dsub_3, 0, TRI);
804 llvm_unreachable("Unknown reg class!");
807 if (ARM::QQQQPRRegClass.hasSubClassEq(RC)) {
808 MachineInstrBuilder MIB =
809 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTMDIA))
812 MIB = AddDReg(MIB, SrcReg, ARM::dsub_0, getKillRegState(isKill), TRI);
813 MIB = AddDReg(MIB, SrcReg, ARM::dsub_1, 0, TRI);
814 MIB = AddDReg(MIB, SrcReg, ARM::dsub_2, 0, TRI);
815 MIB = AddDReg(MIB, SrcReg, ARM::dsub_3, 0, TRI);
816 MIB = AddDReg(MIB, SrcReg, ARM::dsub_4, 0, TRI);
817 MIB = AddDReg(MIB, SrcReg, ARM::dsub_5, 0, TRI);
818 MIB = AddDReg(MIB, SrcReg, ARM::dsub_6, 0, TRI);
819 AddDReg(MIB, SrcReg, ARM::dsub_7, 0, TRI);
821 llvm_unreachable("Unknown reg class!");
824 llvm_unreachable("Unknown reg class!");
829 ARMBaseInstrInfo::isStoreToStackSlot(const MachineInstr *MI,
830 int &FrameIndex) const {
831 switch (MI->getOpcode()) {
834 case ARM::t2STRs: // FIXME: don't use t2STRs to access frame.
835 if (MI->getOperand(1).isFI() &&
836 MI->getOperand(2).isReg() &&
837 MI->getOperand(3).isImm() &&
838 MI->getOperand(2).getReg() == 0 &&
839 MI->getOperand(3).getImm() == 0) {
840 FrameIndex = MI->getOperand(1).getIndex();
841 return MI->getOperand(0).getReg();
849 if (MI->getOperand(1).isFI() &&
850 MI->getOperand(2).isImm() &&
851 MI->getOperand(2).getImm() == 0) {
852 FrameIndex = MI->getOperand(1).getIndex();
853 return MI->getOperand(0).getReg();
856 case ARM::VST1q64Pseudo:
857 if (MI->getOperand(0).isFI() &&
858 MI->getOperand(2).getSubReg() == 0) {
859 FrameIndex = MI->getOperand(0).getIndex();
860 return MI->getOperand(2).getReg();
864 if (MI->getOperand(1).isFI() &&
865 MI->getOperand(0).getSubReg() == 0) {
866 FrameIndex = MI->getOperand(1).getIndex();
867 return MI->getOperand(0).getReg();
875 unsigned ARMBaseInstrInfo::isStoreToStackSlotPostFE(const MachineInstr *MI,
876 int &FrameIndex) const {
877 const MachineMemOperand *Dummy;
878 return MI->getDesc().mayStore() && hasStoreToStackSlot(MI, Dummy, FrameIndex);
881 void ARMBaseInstrInfo::
882 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
883 unsigned DestReg, int FI,
884 const TargetRegisterClass *RC,
885 const TargetRegisterInfo *TRI) const {
887 if (I != MBB.end()) DL = I->getDebugLoc();
888 MachineFunction &MF = *MBB.getParent();
889 MachineFrameInfo &MFI = *MF.getFrameInfo();
890 unsigned Align = MFI.getObjectAlignment(FI);
891 MachineMemOperand *MMO =
892 MF.getMachineMemOperand(
893 MachinePointerInfo(PseudoSourceValue::getFixedStack(FI)),
894 MachineMemOperand::MOLoad,
895 MFI.getObjectSize(FI),
898 switch (RC->getSize()) {
900 if (ARM::GPRRegClass.hasSubClassEq(RC)) {
901 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::LDRi12), DestReg)
902 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
904 } else if (ARM::SPRRegClass.hasSubClassEq(RC)) {
905 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDRS), DestReg)
906 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
908 llvm_unreachable("Unknown reg class!");
911 if (ARM::DPRRegClass.hasSubClassEq(RC)) {
912 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDRD), DestReg)
913 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
915 llvm_unreachable("Unknown reg class!");
918 if (ARM::QPRRegClass.hasSubClassEq(RC)) {
919 if (Align >= 16 && getRegisterInfo().needsStackRealignment(MF)) {
920 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLD1q64Pseudo), DestReg)
921 .addFrameIndex(FI).addImm(16)
922 .addMemOperand(MMO));
924 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDMQIA), DestReg)
926 .addMemOperand(MMO));
929 llvm_unreachable("Unknown reg class!");
932 if (ARM::QQPRRegClass.hasSubClassEq(RC)) {
933 if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) {
934 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLD1d64QPseudo), DestReg)
935 .addFrameIndex(FI).addImm(16)
936 .addMemOperand(MMO));
938 MachineInstrBuilder MIB =
939 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDMDIA))
942 MIB = AddDReg(MIB, DestReg, ARM::dsub_0, RegState::Define, TRI);
943 MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::Define, TRI);
944 MIB = AddDReg(MIB, DestReg, ARM::dsub_2, RegState::Define, TRI);
945 MIB = AddDReg(MIB, DestReg, ARM::dsub_3, RegState::Define, TRI);
946 MIB.addReg(DestReg, RegState::Define | RegState::Implicit);
949 llvm_unreachable("Unknown reg class!");
952 if (ARM::QQQQPRRegClass.hasSubClassEq(RC)) {
953 MachineInstrBuilder MIB =
954 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDMDIA))
957 MIB = AddDReg(MIB, DestReg, ARM::dsub_0, RegState::Define, TRI);
958 MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::Define, TRI);
959 MIB = AddDReg(MIB, DestReg, ARM::dsub_2, RegState::Define, TRI);
960 MIB = AddDReg(MIB, DestReg, ARM::dsub_3, RegState::Define, TRI);
961 MIB = AddDReg(MIB, DestReg, ARM::dsub_4, RegState::Define, TRI);
962 MIB = AddDReg(MIB, DestReg, ARM::dsub_5, RegState::Define, TRI);
963 MIB = AddDReg(MIB, DestReg, ARM::dsub_6, RegState::Define, TRI);
964 MIB = AddDReg(MIB, DestReg, ARM::dsub_7, RegState::Define, TRI);
965 MIB.addReg(DestReg, RegState::Define | RegState::Implicit);
967 llvm_unreachable("Unknown reg class!");
970 llvm_unreachable("Unknown regclass!");
975 ARMBaseInstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
976 int &FrameIndex) const {
977 switch (MI->getOpcode()) {
980 case ARM::t2LDRs: // FIXME: don't use t2LDRs to access frame.
981 if (MI->getOperand(1).isFI() &&
982 MI->getOperand(2).isReg() &&
983 MI->getOperand(3).isImm() &&
984 MI->getOperand(2).getReg() == 0 &&
985 MI->getOperand(3).getImm() == 0) {
986 FrameIndex = MI->getOperand(1).getIndex();
987 return MI->getOperand(0).getReg();
995 if (MI->getOperand(1).isFI() &&
996 MI->getOperand(2).isImm() &&
997 MI->getOperand(2).getImm() == 0) {
998 FrameIndex = MI->getOperand(1).getIndex();
999 return MI->getOperand(0).getReg();
1002 case ARM::VLD1q64Pseudo:
1003 if (MI->getOperand(1).isFI() &&
1004 MI->getOperand(0).getSubReg() == 0) {
1005 FrameIndex = MI->getOperand(1).getIndex();
1006 return MI->getOperand(0).getReg();
1010 if (MI->getOperand(1).isFI() &&
1011 MI->getOperand(0).getSubReg() == 0) {
1012 FrameIndex = MI->getOperand(1).getIndex();
1013 return MI->getOperand(0).getReg();
1021 unsigned ARMBaseInstrInfo::isLoadFromStackSlotPostFE(const MachineInstr *MI,
1022 int &FrameIndex) const {
1023 const MachineMemOperand *Dummy;
1024 return MI->getDesc().mayLoad() && hasLoadFromStackSlot(MI, Dummy, FrameIndex);
1028 ARMBaseInstrInfo::emitFrameIndexDebugValue(MachineFunction &MF,
1029 int FrameIx, uint64_t Offset,
1030 const MDNode *MDPtr,
1031 DebugLoc DL) const {
1032 MachineInstrBuilder MIB = BuildMI(MF, DL, get(ARM::DBG_VALUE))
1033 .addFrameIndex(FrameIx).addImm(0).addImm(Offset).addMetadata(MDPtr);
1037 /// Create a copy of a const pool value. Update CPI to the new index and return
1039 static unsigned duplicateCPV(MachineFunction &MF, unsigned &CPI) {
1040 MachineConstantPool *MCP = MF.getConstantPool();
1041 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1043 const MachineConstantPoolEntry &MCPE = MCP->getConstants()[CPI];
1044 assert(MCPE.isMachineConstantPoolEntry() &&
1045 "Expecting a machine constantpool entry!");
1046 ARMConstantPoolValue *ACPV =
1047 static_cast<ARMConstantPoolValue*>(MCPE.Val.MachineCPVal);
1049 unsigned PCLabelId = AFI->createPICLabelUId();
1050 ARMConstantPoolValue *NewCPV = 0;
1051 // FIXME: The below assumes PIC relocation model and that the function
1052 // is Thumb mode (t1 or t2). PCAdjustment would be 8 for ARM mode PIC, and
1053 // zero for non-PIC in ARM or Thumb. The callers are all of thumb LDR
1054 // instructions, so that's probably OK, but is PIC always correct when
1056 if (ACPV->isGlobalValue())
1057 NewCPV = new ARMConstantPoolValue(ACPV->getGV(), PCLabelId,
1059 else if (ACPV->isExtSymbol())
1060 NewCPV = new ARMConstantPoolValue(MF.getFunction()->getContext(),
1061 ACPV->getSymbol(), PCLabelId, 4);
1062 else if (ACPV->isBlockAddress())
1063 NewCPV = new ARMConstantPoolValue(ACPV->getBlockAddress(), PCLabelId,
1064 ARMCP::CPBlockAddress, 4);
1065 else if (ACPV->isLSDA())
1066 NewCPV = new ARMConstantPoolValue(MF.getFunction(), PCLabelId,
1068 else if (ACPV->isMachineBasicBlock())
1069 NewCPV = new ARMConstantPoolValue(MF.getFunction()->getContext(),
1070 ACPV->getMBB(), PCLabelId,
1071 ARMCP::CPMachineBasicBlock, 4);
1073 llvm_unreachable("Unexpected ARM constantpool value type!!");
1074 CPI = MCP->getConstantPoolIndex(NewCPV, MCPE.getAlignment());
1078 void ARMBaseInstrInfo::
1079 reMaterialize(MachineBasicBlock &MBB,
1080 MachineBasicBlock::iterator I,
1081 unsigned DestReg, unsigned SubIdx,
1082 const MachineInstr *Orig,
1083 const TargetRegisterInfo &TRI) const {
1084 unsigned Opcode = Orig->getOpcode();
1087 MachineInstr *MI = MBB.getParent()->CloneMachineInstr(Orig);
1088 MI->substituteRegister(Orig->getOperand(0).getReg(), DestReg, SubIdx, TRI);
1092 case ARM::tLDRpci_pic:
1093 case ARM::t2LDRpci_pic: {
1094 MachineFunction &MF = *MBB.getParent();
1095 unsigned CPI = Orig->getOperand(1).getIndex();
1096 unsigned PCLabelId = duplicateCPV(MF, CPI);
1097 MachineInstrBuilder MIB = BuildMI(MBB, I, Orig->getDebugLoc(), get(Opcode),
1099 .addConstantPoolIndex(CPI).addImm(PCLabelId);
1100 MIB->setMemRefs(Orig->memoperands_begin(), Orig->memoperands_end());
1107 ARMBaseInstrInfo::duplicate(MachineInstr *Orig, MachineFunction &MF) const {
1108 MachineInstr *MI = TargetInstrInfoImpl::duplicate(Orig, MF);
1109 switch(Orig->getOpcode()) {
1110 case ARM::tLDRpci_pic:
1111 case ARM::t2LDRpci_pic: {
1112 unsigned CPI = Orig->getOperand(1).getIndex();
1113 unsigned PCLabelId = duplicateCPV(MF, CPI);
1114 Orig->getOperand(1).setIndex(CPI);
1115 Orig->getOperand(2).setImm(PCLabelId);
1122 bool ARMBaseInstrInfo::produceSameValue(const MachineInstr *MI0,
1123 const MachineInstr *MI1,
1124 const MachineRegisterInfo *MRI) const {
1125 int Opcode = MI0->getOpcode();
1126 if (Opcode == ARM::t2LDRpci ||
1127 Opcode == ARM::t2LDRpci_pic ||
1128 Opcode == ARM::tLDRpci ||
1129 Opcode == ARM::tLDRpci_pic ||
1130 Opcode == ARM::MOV_ga_dyn ||
1131 Opcode == ARM::MOV_ga_pcrel ||
1132 Opcode == ARM::MOV_ga_pcrel_ldr ||
1133 Opcode == ARM::t2MOV_ga_dyn ||
1134 Opcode == ARM::t2MOV_ga_pcrel) {
1135 if (MI1->getOpcode() != Opcode)
1137 if (MI0->getNumOperands() != MI1->getNumOperands())
1140 const MachineOperand &MO0 = MI0->getOperand(1);
1141 const MachineOperand &MO1 = MI1->getOperand(1);
1142 if (MO0.getOffset() != MO1.getOffset())
1145 if (Opcode == ARM::MOV_ga_dyn ||
1146 Opcode == ARM::MOV_ga_pcrel ||
1147 Opcode == ARM::MOV_ga_pcrel_ldr ||
1148 Opcode == ARM::t2MOV_ga_dyn ||
1149 Opcode == ARM::t2MOV_ga_pcrel)
1150 // Ignore the PC labels.
1151 return MO0.getGlobal() == MO1.getGlobal();
1153 const MachineFunction *MF = MI0->getParent()->getParent();
1154 const MachineConstantPool *MCP = MF->getConstantPool();
1155 int CPI0 = MO0.getIndex();
1156 int CPI1 = MO1.getIndex();
1157 const MachineConstantPoolEntry &MCPE0 = MCP->getConstants()[CPI0];
1158 const MachineConstantPoolEntry &MCPE1 = MCP->getConstants()[CPI1];
1159 bool isARMCP0 = MCPE0.isMachineConstantPoolEntry();
1160 bool isARMCP1 = MCPE1.isMachineConstantPoolEntry();
1161 if (isARMCP0 && isARMCP1) {
1162 ARMConstantPoolValue *ACPV0 =
1163 static_cast<ARMConstantPoolValue*>(MCPE0.Val.MachineCPVal);
1164 ARMConstantPoolValue *ACPV1 =
1165 static_cast<ARMConstantPoolValue*>(MCPE1.Val.MachineCPVal);
1166 return ACPV0->hasSameValue(ACPV1);
1167 } else if (!isARMCP0 && !isARMCP1) {
1168 return MCPE0.Val.ConstVal == MCPE1.Val.ConstVal;
1171 } else if (Opcode == ARM::PICLDR) {
1172 if (MI1->getOpcode() != Opcode)
1174 if (MI0->getNumOperands() != MI1->getNumOperands())
1177 unsigned Addr0 = MI0->getOperand(1).getReg();
1178 unsigned Addr1 = MI1->getOperand(1).getReg();
1179 if (Addr0 != Addr1) {
1181 !TargetRegisterInfo::isVirtualRegister(Addr0) ||
1182 !TargetRegisterInfo::isVirtualRegister(Addr1))
1185 // This assumes SSA form.
1186 MachineInstr *Def0 = MRI->getVRegDef(Addr0);
1187 MachineInstr *Def1 = MRI->getVRegDef(Addr1);
1188 // Check if the loaded value, e.g. a constantpool of a global address, are
1190 if (!produceSameValue(Def0, Def1, MRI))
1194 for (unsigned i = 3, e = MI0->getNumOperands(); i != e; ++i) {
1195 // %vreg12<def> = PICLDR %vreg11, 0, pred:14, pred:%noreg
1196 const MachineOperand &MO0 = MI0->getOperand(i);
1197 const MachineOperand &MO1 = MI1->getOperand(i);
1198 if (!MO0.isIdenticalTo(MO1))
1204 return MI0->isIdenticalTo(MI1, MachineInstr::IgnoreVRegDefs);
1207 /// areLoadsFromSameBasePtr - This is used by the pre-regalloc scheduler to
1208 /// determine if two loads are loading from the same base address. It should
1209 /// only return true if the base pointers are the same and the only differences
1210 /// between the two addresses is the offset. It also returns the offsets by
1212 bool ARMBaseInstrInfo::areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2,
1214 int64_t &Offset2) const {
1215 // Don't worry about Thumb: just ARM and Thumb2.
1216 if (Subtarget.isThumb1Only()) return false;
1218 if (!Load1->isMachineOpcode() || !Load2->isMachineOpcode())
1221 switch (Load1->getMachineOpcode()) {
1234 case ARM::t2LDRSHi8:
1236 case ARM::t2LDRSHi12:
1240 switch (Load2->getMachineOpcode()) {
1253 case ARM::t2LDRSHi8:
1255 case ARM::t2LDRSHi12:
1259 // Check if base addresses and chain operands match.
1260 if (Load1->getOperand(0) != Load2->getOperand(0) ||
1261 Load1->getOperand(4) != Load2->getOperand(4))
1264 // Index should be Reg0.
1265 if (Load1->getOperand(3) != Load2->getOperand(3))
1268 // Determine the offsets.
1269 if (isa<ConstantSDNode>(Load1->getOperand(1)) &&
1270 isa<ConstantSDNode>(Load2->getOperand(1))) {
1271 Offset1 = cast<ConstantSDNode>(Load1->getOperand(1))->getSExtValue();
1272 Offset2 = cast<ConstantSDNode>(Load2->getOperand(1))->getSExtValue();
1279 /// shouldScheduleLoadsNear - This is a used by the pre-regalloc scheduler to
1280 /// determine (in conjunction with areLoadsFromSameBasePtr) if two loads should
1281 /// be scheduled togther. On some targets if two loads are loading from
1282 /// addresses in the same cache line, it's better if they are scheduled
1283 /// together. This function takes two integers that represent the load offsets
1284 /// from the common base address. It returns true if it decides it's desirable
1285 /// to schedule the two loads together. "NumLoads" is the number of loads that
1286 /// have already been scheduled after Load1.
1287 bool ARMBaseInstrInfo::shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,
1288 int64_t Offset1, int64_t Offset2,
1289 unsigned NumLoads) const {
1290 // Don't worry about Thumb: just ARM and Thumb2.
1291 if (Subtarget.isThumb1Only()) return false;
1293 assert(Offset2 > Offset1);
1295 if ((Offset2 - Offset1) / 8 > 64)
1298 if (Load1->getMachineOpcode() != Load2->getMachineOpcode())
1299 return false; // FIXME: overly conservative?
1301 // Four loads in a row should be sufficient.
1308 bool ARMBaseInstrInfo::isSchedulingBoundary(const MachineInstr *MI,
1309 const MachineBasicBlock *MBB,
1310 const MachineFunction &MF) const {
1311 // Debug info is never a scheduling boundary. It's necessary to be explicit
1312 // due to the special treatment of IT instructions below, otherwise a
1313 // dbg_value followed by an IT will result in the IT instruction being
1314 // considered a scheduling hazard, which is wrong. It should be the actual
1315 // instruction preceding the dbg_value instruction(s), just like it is
1316 // when debug info is not present.
1317 if (MI->isDebugValue())
1320 // Terminators and labels can't be scheduled around.
1321 if (MI->getDesc().isTerminator() || MI->isLabel())
1324 // Treat the start of the IT block as a scheduling boundary, but schedule
1325 // t2IT along with all instructions following it.
1326 // FIXME: This is a big hammer. But the alternative is to add all potential
1327 // true and anti dependencies to IT block instructions as implicit operands
1328 // to the t2IT instruction. The added compile time and complexity does not
1330 MachineBasicBlock::const_iterator I = MI;
1331 // Make sure to skip any dbg_value instructions
1332 while (++I != MBB->end() && I->isDebugValue())
1334 if (I != MBB->end() && I->getOpcode() == ARM::t2IT)
1337 // Don't attempt to schedule around any instruction that defines
1338 // a stack-oriented pointer, as it's unlikely to be profitable. This
1339 // saves compile time, because it doesn't require every single
1340 // stack slot reference to depend on the instruction that does the
1342 if (MI->definesRegister(ARM::SP))
1348 bool ARMBaseInstrInfo::
1349 isProfitableToIfCvt(MachineBasicBlock &MBB,
1350 unsigned NumCycles, unsigned ExtraPredCycles,
1351 const BranchProbability &Probability) const {
1355 // Attempt to estimate the relative costs of predication versus branching.
1356 unsigned UnpredCost = Probability.getNumerator() * NumCycles;
1357 UnpredCost /= Probability.getDenominator();
1358 UnpredCost += 1; // The branch itself
1359 UnpredCost += Subtarget.getMispredictionPenalty() / 10;
1361 return (NumCycles + ExtraPredCycles) <= UnpredCost;
1364 bool ARMBaseInstrInfo::
1365 isProfitableToIfCvt(MachineBasicBlock &TMBB,
1366 unsigned TCycles, unsigned TExtra,
1367 MachineBasicBlock &FMBB,
1368 unsigned FCycles, unsigned FExtra,
1369 const BranchProbability &Probability) const {
1370 if (!TCycles || !FCycles)
1373 // Attempt to estimate the relative costs of predication versus branching.
1374 unsigned TUnpredCost = Probability.getNumerator() * TCycles;
1375 TUnpredCost /= Probability.getDenominator();
1377 uint32_t Comp = Probability.getDenominator() - Probability.getNumerator();
1378 unsigned FUnpredCost = Comp * FCycles;
1379 FUnpredCost /= Probability.getDenominator();
1381 unsigned UnpredCost = TUnpredCost + FUnpredCost;
1382 UnpredCost += 1; // The branch itself
1383 UnpredCost += Subtarget.getMispredictionPenalty() / 10;
1385 return (TCycles + FCycles + TExtra + FExtra) <= UnpredCost;
1388 /// getInstrPredicate - If instruction is predicated, returns its predicate
1389 /// condition, otherwise returns AL. It also returns the condition code
1390 /// register by reference.
1392 llvm::getInstrPredicate(const MachineInstr *MI, unsigned &PredReg) {
1393 int PIdx = MI->findFirstPredOperandIdx();
1399 PredReg = MI->getOperand(PIdx+1).getReg();
1400 return (ARMCC::CondCodes)MI->getOperand(PIdx).getImm();
1404 int llvm::getMatchingCondBranchOpcode(int Opc) {
1407 else if (Opc == ARM::tB)
1409 else if (Opc == ARM::t2B)
1412 llvm_unreachable("Unknown unconditional branch opcode!");
1417 /// Map pseudo instructions that imply an 'S' bit onto real opcodes. Whether the
1418 /// instruction is encoded with an 'S' bit is determined by the optional CPSR
1421 /// This will go away once we can teach tblgen how to set the optional CPSR def
1423 struct AddSubFlagsOpcodePair {
1425 unsigned MachineOpc;
1428 static AddSubFlagsOpcodePair AddSubFlagsOpcodeMap[] = {
1429 {ARM::ADDSri, ARM::ADDri},
1430 {ARM::ADDSrr, ARM::ADDrr},
1431 {ARM::ADDSrsi, ARM::ADDrsi},
1432 {ARM::ADDSrsr, ARM::ADDrsr},
1434 {ARM::SUBSri, ARM::SUBri},
1435 {ARM::SUBSrr, ARM::SUBrr},
1436 {ARM::SUBSrsi, ARM::SUBrsi},
1437 {ARM::SUBSrsr, ARM::SUBrsr},
1439 {ARM::RSBSri, ARM::RSBri},
1440 {ARM::RSBSrr, ARM::RSBrr},
1441 {ARM::RSBSrsi, ARM::RSBrsi},
1442 {ARM::RSBSrsr, ARM::RSBrsr},
1444 {ARM::t2ADDSri, ARM::t2ADDri},
1445 {ARM::t2ADDSrr, ARM::t2ADDrr},
1446 {ARM::t2ADDSrs, ARM::t2ADDrs},
1448 {ARM::t2SUBSri, ARM::t2SUBri},
1449 {ARM::t2SUBSrr, ARM::t2SUBrr},
1450 {ARM::t2SUBSrs, ARM::t2SUBrs},
1452 {ARM::t2RSBSri, ARM::t2RSBri},
1453 {ARM::t2RSBSrs, ARM::t2RSBrs},
1456 unsigned llvm::convertAddSubFlagsOpcode(unsigned OldOpc) {
1457 static const int NPairs =
1458 sizeof(AddSubFlagsOpcodeMap) / sizeof(AddSubFlagsOpcodePair);
1459 for (AddSubFlagsOpcodePair *OpcPair = &AddSubFlagsOpcodeMap[0],
1460 *End = &AddSubFlagsOpcodeMap[NPairs]; OpcPair != End; ++OpcPair) {
1461 if (OldOpc == OpcPair->PseudoOpc) {
1462 return OpcPair->MachineOpc;
1468 void llvm::emitARMRegPlusImmediate(MachineBasicBlock &MBB,
1469 MachineBasicBlock::iterator &MBBI, DebugLoc dl,
1470 unsigned DestReg, unsigned BaseReg, int NumBytes,
1471 ARMCC::CondCodes Pred, unsigned PredReg,
1472 const ARMBaseInstrInfo &TII, unsigned MIFlags) {
1473 bool isSub = NumBytes < 0;
1474 if (isSub) NumBytes = -NumBytes;
1477 unsigned RotAmt = ARM_AM::getSOImmValRotate(NumBytes);
1478 unsigned ThisVal = NumBytes & ARM_AM::rotr32(0xFF, RotAmt);
1479 assert(ThisVal && "Didn't extract field correctly");
1481 // We will handle these bits from offset, clear them.
1482 NumBytes &= ~ThisVal;
1484 assert(ARM_AM::getSOImmVal(ThisVal) != -1 && "Bit extraction didn't work?");
1486 // Build the new ADD / SUB.
1487 unsigned Opc = isSub ? ARM::SUBri : ARM::ADDri;
1488 BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg)
1489 .addReg(BaseReg, RegState::Kill).addImm(ThisVal)
1490 .addImm((unsigned)Pred).addReg(PredReg).addReg(0)
1491 .setMIFlags(MIFlags);
1496 bool llvm::rewriteARMFrameIndex(MachineInstr &MI, unsigned FrameRegIdx,
1497 unsigned FrameReg, int &Offset,
1498 const ARMBaseInstrInfo &TII) {
1499 unsigned Opcode = MI.getOpcode();
1500 const MCInstrDesc &Desc = MI.getDesc();
1501 unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
1504 // Memory operands in inline assembly always use AddrMode2.
1505 if (Opcode == ARM::INLINEASM)
1506 AddrMode = ARMII::AddrMode2;
1508 if (Opcode == ARM::ADDri) {
1509 Offset += MI.getOperand(FrameRegIdx+1).getImm();
1511 // Turn it into a move.
1512 MI.setDesc(TII.get(ARM::MOVr));
1513 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
1514 MI.RemoveOperand(FrameRegIdx+1);
1517 } else if (Offset < 0) {
1520 MI.setDesc(TII.get(ARM::SUBri));
1523 // Common case: small offset, fits into instruction.
1524 if (ARM_AM::getSOImmVal(Offset) != -1) {
1525 // Replace the FrameIndex with sp / fp
1526 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
1527 MI.getOperand(FrameRegIdx+1).ChangeToImmediate(Offset);
1532 // Otherwise, pull as much of the immedidate into this ADDri/SUBri
1534 unsigned RotAmt = ARM_AM::getSOImmValRotate(Offset);
1535 unsigned ThisImmVal = Offset & ARM_AM::rotr32(0xFF, RotAmt);
1537 // We will handle these bits from offset, clear them.
1538 Offset &= ~ThisImmVal;
1540 // Get the properly encoded SOImmVal field.
1541 assert(ARM_AM::getSOImmVal(ThisImmVal) != -1 &&
1542 "Bit extraction didn't work?");
1543 MI.getOperand(FrameRegIdx+1).ChangeToImmediate(ThisImmVal);
1545 unsigned ImmIdx = 0;
1547 unsigned NumBits = 0;
1550 case ARMII::AddrMode_i12: {
1551 ImmIdx = FrameRegIdx + 1;
1552 InstrOffs = MI.getOperand(ImmIdx).getImm();
1556 case ARMII::AddrMode2: {
1557 ImmIdx = FrameRegIdx+2;
1558 InstrOffs = ARM_AM::getAM2Offset(MI.getOperand(ImmIdx).getImm());
1559 if (ARM_AM::getAM2Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub)
1564 case ARMII::AddrMode3: {
1565 ImmIdx = FrameRegIdx+2;
1566 InstrOffs = ARM_AM::getAM3Offset(MI.getOperand(ImmIdx).getImm());
1567 if (ARM_AM::getAM3Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub)
1572 case ARMII::AddrMode4:
1573 case ARMII::AddrMode6:
1574 // Can't fold any offset even if it's zero.
1576 case ARMII::AddrMode5: {
1577 ImmIdx = FrameRegIdx+1;
1578 InstrOffs = ARM_AM::getAM5Offset(MI.getOperand(ImmIdx).getImm());
1579 if (ARM_AM::getAM5Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub)
1586 llvm_unreachable("Unsupported addressing mode!");
1590 Offset += InstrOffs * Scale;
1591 assert((Offset & (Scale-1)) == 0 && "Can't encode this offset!");
1597 // Attempt to fold address comp. if opcode has offset bits
1599 // Common case: small offset, fits into instruction.
1600 MachineOperand &ImmOp = MI.getOperand(ImmIdx);
1601 int ImmedOffset = Offset / Scale;
1602 unsigned Mask = (1 << NumBits) - 1;
1603 if ((unsigned)Offset <= Mask * Scale) {
1604 // Replace the FrameIndex with sp
1605 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
1606 // FIXME: When addrmode2 goes away, this will simplify (like the
1607 // T2 version), as the LDR.i12 versions don't need the encoding
1608 // tricks for the offset value.
1610 if (AddrMode == ARMII::AddrMode_i12)
1611 ImmedOffset = -ImmedOffset;
1613 ImmedOffset |= 1 << NumBits;
1615 ImmOp.ChangeToImmediate(ImmedOffset);
1620 // Otherwise, it didn't fit. Pull in what we can to simplify the immed.
1621 ImmedOffset = ImmedOffset & Mask;
1623 if (AddrMode == ARMII::AddrMode_i12)
1624 ImmedOffset = -ImmedOffset;
1626 ImmedOffset |= 1 << NumBits;
1628 ImmOp.ChangeToImmediate(ImmedOffset);
1629 Offset &= ~(Mask*Scale);
1633 Offset = (isSub) ? -Offset : Offset;
1637 bool ARMBaseInstrInfo::
1638 AnalyzeCompare(const MachineInstr *MI, unsigned &SrcReg, int &CmpMask,
1639 int &CmpValue) const {
1640 switch (MI->getOpcode()) {
1644 SrcReg = MI->getOperand(0).getReg();
1646 CmpValue = MI->getOperand(1).getImm();
1650 SrcReg = MI->getOperand(0).getReg();
1651 CmpMask = MI->getOperand(1).getImm();
1659 /// isSuitableForMask - Identify a suitable 'and' instruction that
1660 /// operates on the given source register and applies the same mask
1661 /// as a 'tst' instruction. Provide a limited look-through for copies.
1662 /// When successful, MI will hold the found instruction.
1663 static bool isSuitableForMask(MachineInstr *&MI, unsigned SrcReg,
1664 int CmpMask, bool CommonUse) {
1665 switch (MI->getOpcode()) {
1668 if (CmpMask != MI->getOperand(2).getImm())
1670 if (SrcReg == MI->getOperand(CommonUse ? 1 : 0).getReg())
1674 // Walk down one instruction which is potentially an 'and'.
1675 const MachineInstr &Copy = *MI;
1676 MachineBasicBlock::iterator AND(
1677 llvm::next(MachineBasicBlock::iterator(MI)));
1678 if (AND == MI->getParent()->end()) return false;
1680 return isSuitableForMask(MI, Copy.getOperand(0).getReg(),
1688 /// OptimizeCompareInstr - Convert the instruction supplying the argument to the
1689 /// comparison into one that sets the zero bit in the flags register.
1690 bool ARMBaseInstrInfo::
1691 OptimizeCompareInstr(MachineInstr *CmpInstr, unsigned SrcReg, int CmpMask,
1692 int CmpValue, const MachineRegisterInfo *MRI) const {
1696 MachineRegisterInfo::def_iterator DI = MRI->def_begin(SrcReg);
1697 if (llvm::next(DI) != MRI->def_end())
1698 // Only support one definition.
1701 MachineInstr *MI = &*DI;
1703 // Masked compares sometimes use the same register as the corresponding 'and'.
1704 if (CmpMask != ~0) {
1705 if (!isSuitableForMask(MI, SrcReg, CmpMask, false)) {
1707 for (MachineRegisterInfo::use_iterator UI = MRI->use_begin(SrcReg),
1708 UE = MRI->use_end(); UI != UE; ++UI) {
1709 if (UI->getParent() != CmpInstr->getParent()) continue;
1710 MachineInstr *PotentialAND = &*UI;
1711 if (!isSuitableForMask(PotentialAND, SrcReg, CmpMask, true))
1716 if (!MI) return false;
1720 // Conservatively refuse to convert an instruction which isn't in the same BB
1721 // as the comparison.
1722 if (MI->getParent() != CmpInstr->getParent())
1725 // Check that CPSR isn't set between the comparison instruction and the one we
1727 MachineBasicBlock::const_iterator I = CmpInstr, E = MI,
1728 B = MI->getParent()->begin();
1730 // Early exit if CmpInstr is at the beginning of the BB.
1731 if (I == B) return false;
1734 for (; I != E; --I) {
1735 const MachineInstr &Instr = *I;
1737 for (unsigned IO = 0, EO = Instr.getNumOperands(); IO != EO; ++IO) {
1738 const MachineOperand &MO = Instr.getOperand(IO);
1739 if (!MO.isReg()) continue;
1741 // This instruction modifies or uses CPSR after the one we want to
1742 // change. We can't do this transformation.
1743 if (MO.getReg() == ARM::CPSR)
1748 // The 'and' is below the comparison instruction.
1752 // Set the "zero" bit in CPSR.
1753 switch (MI->getOpcode()) {
1787 case ARM::t2EORri: {
1788 // Scan forward for the use of CPSR, if it's a conditional code requires
1789 // checking of V bit, then this is not safe to do. If we can't find the
1790 // CPSR use (i.e. used in another block), then it's not safe to perform
1791 // the optimization.
1792 bool isSafe = false;
1794 E = MI->getParent()->end();
1795 while (!isSafe && ++I != E) {
1796 const MachineInstr &Instr = *I;
1797 for (unsigned IO = 0, EO = Instr.getNumOperands();
1798 !isSafe && IO != EO; ++IO) {
1799 const MachineOperand &MO = Instr.getOperand(IO);
1800 if (!MO.isReg() || MO.getReg() != ARM::CPSR)
1806 // Condition code is after the operand before CPSR.
1807 ARMCC::CondCodes CC = (ARMCC::CondCodes)Instr.getOperand(IO-1).getImm();
1826 // Toggle the optional operand to CPSR.
1827 MI->getOperand(5).setReg(ARM::CPSR);
1828 MI->getOperand(5).setIsDef(true);
1829 CmpInstr->eraseFromParent();
1837 bool ARMBaseInstrInfo::FoldImmediate(MachineInstr *UseMI,
1838 MachineInstr *DefMI, unsigned Reg,
1839 MachineRegisterInfo *MRI) const {
1840 // Fold large immediates into add, sub, or, xor.
1841 unsigned DefOpc = DefMI->getOpcode();
1842 if (DefOpc != ARM::t2MOVi32imm && DefOpc != ARM::MOVi32imm)
1844 if (!DefMI->getOperand(1).isImm())
1845 // Could be t2MOVi32imm <ga:xx>
1848 if (!MRI->hasOneNonDBGUse(Reg))
1851 unsigned UseOpc = UseMI->getOpcode();
1852 unsigned NewUseOpc = 0;
1853 uint32_t ImmVal = (uint32_t)DefMI->getOperand(1).getImm();
1854 uint32_t SOImmValV1 = 0, SOImmValV2 = 0;
1855 bool Commute = false;
1857 default: return false;
1865 case ARM::t2EORrr: {
1866 Commute = UseMI->getOperand(2).getReg() != Reg;
1873 NewUseOpc = ARM::SUBri;
1879 if (!ARM_AM::isSOImmTwoPartVal(ImmVal))
1881 SOImmValV1 = (uint32_t)ARM_AM::getSOImmTwoPartFirst(ImmVal);
1882 SOImmValV2 = (uint32_t)ARM_AM::getSOImmTwoPartSecond(ImmVal);
1885 case ARM::ADDrr: NewUseOpc = ARM::ADDri; break;
1886 case ARM::ORRrr: NewUseOpc = ARM::ORRri; break;
1887 case ARM::EORrr: NewUseOpc = ARM::EORri; break;
1891 case ARM::t2SUBrr: {
1895 NewUseOpc = ARM::t2SUBri;
1900 case ARM::t2EORrr: {
1901 if (!ARM_AM::isT2SOImmTwoPartVal(ImmVal))
1903 SOImmValV1 = (uint32_t)ARM_AM::getT2SOImmTwoPartFirst(ImmVal);
1904 SOImmValV2 = (uint32_t)ARM_AM::getT2SOImmTwoPartSecond(ImmVal);
1907 case ARM::t2ADDrr: NewUseOpc = ARM::t2ADDri; break;
1908 case ARM::t2ORRrr: NewUseOpc = ARM::t2ORRri; break;
1909 case ARM::t2EORrr: NewUseOpc = ARM::t2EORri; break;
1917 unsigned OpIdx = Commute ? 2 : 1;
1918 unsigned Reg1 = UseMI->getOperand(OpIdx).getReg();
1919 bool isKill = UseMI->getOperand(OpIdx).isKill();
1920 unsigned NewReg = MRI->createVirtualRegister(MRI->getRegClass(Reg));
1921 AddDefaultCC(AddDefaultPred(BuildMI(*UseMI->getParent(),
1922 *UseMI, UseMI->getDebugLoc(),
1923 get(NewUseOpc), NewReg)
1924 .addReg(Reg1, getKillRegState(isKill))
1925 .addImm(SOImmValV1)));
1926 UseMI->setDesc(get(NewUseOpc));
1927 UseMI->getOperand(1).setReg(NewReg);
1928 UseMI->getOperand(1).setIsKill();
1929 UseMI->getOperand(2).ChangeToImmediate(SOImmValV2);
1930 DefMI->eraseFromParent();
1935 ARMBaseInstrInfo::getNumMicroOps(const InstrItineraryData *ItinData,
1936 const MachineInstr *MI) const {
1937 if (!ItinData || ItinData->isEmpty())
1940 const MCInstrDesc &Desc = MI->getDesc();
1941 unsigned Class = Desc.getSchedClass();
1942 unsigned UOps = ItinData->Itineraries[Class].NumMicroOps;
1946 unsigned Opc = MI->getOpcode();
1949 llvm_unreachable("Unexpected multi-uops instruction!");
1955 // The number of uOps for load / store multiple are determined by the number
1958 // On Cortex-A8, each pair of register loads / stores can be scheduled on the
1959 // same cycle. The scheduling for the first load / store must be done
1960 // separately by assuming the the address is not 64-bit aligned.
1962 // On Cortex-A9, the formula is simply (#reg / 2) + (#reg % 2). If the address
1963 // is not 64-bit aligned, then AGU would take an extra cycle. For VFP / NEON
1964 // load / store multiple, the formula is (#reg / 2) + (#reg % 2) + 1.
1966 case ARM::VLDMDIA_UPD:
1967 case ARM::VLDMDDB_UPD:
1969 case ARM::VLDMSIA_UPD:
1970 case ARM::VLDMSDB_UPD:
1972 case ARM::VSTMDIA_UPD:
1973 case ARM::VSTMDDB_UPD:
1975 case ARM::VSTMSIA_UPD:
1976 case ARM::VSTMSDB_UPD: {
1977 unsigned NumRegs = MI->getNumOperands() - Desc.getNumOperands();
1978 return (NumRegs / 2) + (NumRegs % 2) + 1;
1981 case ARM::LDMIA_RET:
1986 case ARM::LDMIA_UPD:
1987 case ARM::LDMDA_UPD:
1988 case ARM::LDMDB_UPD:
1989 case ARM::LDMIB_UPD:
1994 case ARM::STMIA_UPD:
1995 case ARM::STMDA_UPD:
1996 case ARM::STMDB_UPD:
1997 case ARM::STMIB_UPD:
1999 case ARM::tLDMIA_UPD:
2000 case ARM::tSTMIA_UPD:
2004 case ARM::t2LDMIA_RET:
2007 case ARM::t2LDMIA_UPD:
2008 case ARM::t2LDMDB_UPD:
2011 case ARM::t2STMIA_UPD:
2012 case ARM::t2STMDB_UPD: {
2013 unsigned NumRegs = MI->getNumOperands() - Desc.getNumOperands() + 1;
2014 if (Subtarget.isCortexA8()) {
2017 // 4 registers would be issued: 2, 2.
2018 // 5 registers would be issued: 2, 2, 1.
2019 UOps = (NumRegs / 2);
2023 } else if (Subtarget.isCortexA9()) {
2024 UOps = (NumRegs / 2);
2025 // If there are odd number of registers or if it's not 64-bit aligned,
2026 // then it takes an extra AGU (Address Generation Unit) cycle.
2027 if ((NumRegs % 2) ||
2028 !MI->hasOneMemOperand() ||
2029 (*MI->memoperands_begin())->getAlignment() < 8)
2033 // Assume the worst.
2041 ARMBaseInstrInfo::getVLDMDefCycle(const InstrItineraryData *ItinData,
2042 const MCInstrDesc &DefMCID,
2044 unsigned DefIdx, unsigned DefAlign) const {
2045 int RegNo = (int)(DefIdx+1) - DefMCID.getNumOperands() + 1;
2047 // Def is the address writeback.
2048 return ItinData->getOperandCycle(DefClass, DefIdx);
2051 if (Subtarget.isCortexA8()) {
2052 // (regno / 2) + (regno % 2) + 1
2053 DefCycle = RegNo / 2 + 1;
2056 } else if (Subtarget.isCortexA9()) {
2058 bool isSLoad = false;
2060 switch (DefMCID.getOpcode()) {
2063 case ARM::VLDMSIA_UPD:
2064 case ARM::VLDMSDB_UPD:
2069 // If there are odd number of 'S' registers or if it's not 64-bit aligned,
2070 // then it takes an extra cycle.
2071 if ((isSLoad && (RegNo % 2)) || DefAlign < 8)
2074 // Assume the worst.
2075 DefCycle = RegNo + 2;
2082 ARMBaseInstrInfo::getLDMDefCycle(const InstrItineraryData *ItinData,
2083 const MCInstrDesc &DefMCID,
2085 unsigned DefIdx, unsigned DefAlign) const {
2086 int RegNo = (int)(DefIdx+1) - DefMCID.getNumOperands() + 1;
2088 // Def is the address writeback.
2089 return ItinData->getOperandCycle(DefClass, DefIdx);
2092 if (Subtarget.isCortexA8()) {
2093 // 4 registers would be issued: 1, 2, 1.
2094 // 5 registers would be issued: 1, 2, 2.
2095 DefCycle = RegNo / 2;
2098 // Result latency is issue cycle + 2: E2.
2100 } else if (Subtarget.isCortexA9()) {
2101 DefCycle = (RegNo / 2);
2102 // If there are odd number of registers or if it's not 64-bit aligned,
2103 // then it takes an extra AGU (Address Generation Unit) cycle.
2104 if ((RegNo % 2) || DefAlign < 8)
2106 // Result latency is AGU cycles + 2.
2109 // Assume the worst.
2110 DefCycle = RegNo + 2;
2117 ARMBaseInstrInfo::getVSTMUseCycle(const InstrItineraryData *ItinData,
2118 const MCInstrDesc &UseMCID,
2120 unsigned UseIdx, unsigned UseAlign) const {
2121 int RegNo = (int)(UseIdx+1) - UseMCID.getNumOperands() + 1;
2123 return ItinData->getOperandCycle(UseClass, UseIdx);
2126 if (Subtarget.isCortexA8()) {
2127 // (regno / 2) + (regno % 2) + 1
2128 UseCycle = RegNo / 2 + 1;
2131 } else if (Subtarget.isCortexA9()) {
2133 bool isSStore = false;
2135 switch (UseMCID.getOpcode()) {
2138 case ARM::VSTMSIA_UPD:
2139 case ARM::VSTMSDB_UPD:
2144 // If there are odd number of 'S' registers or if it's not 64-bit aligned,
2145 // then it takes an extra cycle.
2146 if ((isSStore && (RegNo % 2)) || UseAlign < 8)
2149 // Assume the worst.
2150 UseCycle = RegNo + 2;
2157 ARMBaseInstrInfo::getSTMUseCycle(const InstrItineraryData *ItinData,
2158 const MCInstrDesc &UseMCID,
2160 unsigned UseIdx, unsigned UseAlign) const {
2161 int RegNo = (int)(UseIdx+1) - UseMCID.getNumOperands() + 1;
2163 return ItinData->getOperandCycle(UseClass, UseIdx);
2166 if (Subtarget.isCortexA8()) {
2167 UseCycle = RegNo / 2;
2172 } else if (Subtarget.isCortexA9()) {
2173 UseCycle = (RegNo / 2);
2174 // If there are odd number of registers or if it's not 64-bit aligned,
2175 // then it takes an extra AGU (Address Generation Unit) cycle.
2176 if ((RegNo % 2) || UseAlign < 8)
2179 // Assume the worst.
2186 ARMBaseInstrInfo::getOperandLatency(const InstrItineraryData *ItinData,
2187 const MCInstrDesc &DefMCID,
2188 unsigned DefIdx, unsigned DefAlign,
2189 const MCInstrDesc &UseMCID,
2190 unsigned UseIdx, unsigned UseAlign) const {
2191 unsigned DefClass = DefMCID.getSchedClass();
2192 unsigned UseClass = UseMCID.getSchedClass();
2194 if (DefIdx < DefMCID.getNumDefs() && UseIdx < UseMCID.getNumOperands())
2195 return ItinData->getOperandLatency(DefClass, DefIdx, UseClass, UseIdx);
2197 // This may be a def / use of a variable_ops instruction, the operand
2198 // latency might be determinable dynamically. Let the target try to
2201 bool LdmBypass = false;
2202 switch (DefMCID.getOpcode()) {
2204 DefCycle = ItinData->getOperandCycle(DefClass, DefIdx);
2208 case ARM::VLDMDIA_UPD:
2209 case ARM::VLDMDDB_UPD:
2211 case ARM::VLDMSIA_UPD:
2212 case ARM::VLDMSDB_UPD:
2213 DefCycle = getVLDMDefCycle(ItinData, DefMCID, DefClass, DefIdx, DefAlign);
2216 case ARM::LDMIA_RET:
2221 case ARM::LDMIA_UPD:
2222 case ARM::LDMDA_UPD:
2223 case ARM::LDMDB_UPD:
2224 case ARM::LDMIB_UPD:
2226 case ARM::tLDMIA_UPD:
2228 case ARM::t2LDMIA_RET:
2231 case ARM::t2LDMIA_UPD:
2232 case ARM::t2LDMDB_UPD:
2234 DefCycle = getLDMDefCycle(ItinData, DefMCID, DefClass, DefIdx, DefAlign);
2239 // We can't seem to determine the result latency of the def, assume it's 2.
2243 switch (UseMCID.getOpcode()) {
2245 UseCycle = ItinData->getOperandCycle(UseClass, UseIdx);
2249 case ARM::VSTMDIA_UPD:
2250 case ARM::VSTMDDB_UPD:
2252 case ARM::VSTMSIA_UPD:
2253 case ARM::VSTMSDB_UPD:
2254 UseCycle = getVSTMUseCycle(ItinData, UseMCID, UseClass, UseIdx, UseAlign);
2261 case ARM::STMIA_UPD:
2262 case ARM::STMDA_UPD:
2263 case ARM::STMDB_UPD:
2264 case ARM::STMIB_UPD:
2265 case ARM::tSTMIA_UPD:
2270 case ARM::t2STMIA_UPD:
2271 case ARM::t2STMDB_UPD:
2272 UseCycle = getSTMUseCycle(ItinData, UseMCID, UseClass, UseIdx, UseAlign);
2277 // Assume it's read in the first stage.
2280 UseCycle = DefCycle - UseCycle + 1;
2283 // It's a variable_ops instruction so we can't use DefIdx here. Just use
2284 // first def operand.
2285 if (ItinData->hasPipelineForwarding(DefClass, DefMCID.getNumOperands()-1,
2288 } else if (ItinData->hasPipelineForwarding(DefClass, DefIdx,
2289 UseClass, UseIdx)) {
2298 ARMBaseInstrInfo::getOperandLatency(const InstrItineraryData *ItinData,
2299 const MachineInstr *DefMI, unsigned DefIdx,
2300 const MachineInstr *UseMI, unsigned UseIdx) const {
2301 if (DefMI->isCopyLike() || DefMI->isInsertSubreg() ||
2302 DefMI->isRegSequence() || DefMI->isImplicitDef())
2305 const MCInstrDesc &DefMCID = DefMI->getDesc();
2306 if (!ItinData || ItinData->isEmpty())
2307 return DefMCID.mayLoad() ? 3 : 1;
2309 const MCInstrDesc &UseMCID = UseMI->getDesc();
2310 const MachineOperand &DefMO = DefMI->getOperand(DefIdx);
2311 if (DefMO.getReg() == ARM::CPSR) {
2312 if (DefMI->getOpcode() == ARM::FMSTAT) {
2313 // fpscr -> cpsr stalls over 20 cycles on A8 (and earlier?)
2314 return Subtarget.isCortexA9() ? 1 : 20;
2317 // CPSR set and branch can be paired in the same cycle.
2318 if (UseMCID.isBranch())
2322 unsigned DefAlign = DefMI->hasOneMemOperand()
2323 ? (*DefMI->memoperands_begin())->getAlignment() : 0;
2324 unsigned UseAlign = UseMI->hasOneMemOperand()
2325 ? (*UseMI->memoperands_begin())->getAlignment() : 0;
2326 int Latency = getOperandLatency(ItinData, DefMCID, DefIdx, DefAlign,
2327 UseMCID, UseIdx, UseAlign);
2330 (Subtarget.isCortexA8() || Subtarget.isCortexA9())) {
2331 // FIXME: Shifter op hack: no shift (i.e. [r +/- r]) or [r + r << 2]
2332 // variants are one cycle cheaper.
2333 switch (DefMCID.getOpcode()) {
2337 unsigned ShOpVal = DefMI->getOperand(3).getImm();
2338 unsigned ShImm = ARM_AM::getAM2Offset(ShOpVal);
2340 (ShImm == 2 && ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl))
2347 case ARM::t2LDRSHs: {
2348 // Thumb2 mode: lsl only.
2349 unsigned ShAmt = DefMI->getOperand(3).getImm();
2350 if (ShAmt == 0 || ShAmt == 2)
2357 if (DefAlign < 8 && Subtarget.isCortexA9())
2358 switch (DefMCID.getOpcode()) {
2364 case ARM::VLD1q8_UPD:
2365 case ARM::VLD1q16_UPD:
2366 case ARM::VLD1q32_UPD:
2367 case ARM::VLD1q64_UPD:
2374 case ARM::VLD2d8_UPD:
2375 case ARM::VLD2d16_UPD:
2376 case ARM::VLD2d32_UPD:
2377 case ARM::VLD2q8_UPD:
2378 case ARM::VLD2q16_UPD:
2379 case ARM::VLD2q32_UPD:
2384 case ARM::VLD3d8_UPD:
2385 case ARM::VLD3d16_UPD:
2386 case ARM::VLD3d32_UPD:
2387 case ARM::VLD1d64T_UPD:
2388 case ARM::VLD3q8_UPD:
2389 case ARM::VLD3q16_UPD:
2390 case ARM::VLD3q32_UPD:
2395 case ARM::VLD4d8_UPD:
2396 case ARM::VLD4d16_UPD:
2397 case ARM::VLD4d32_UPD:
2398 case ARM::VLD1d64Q_UPD:
2399 case ARM::VLD4q8_UPD:
2400 case ARM::VLD4q16_UPD:
2401 case ARM::VLD4q32_UPD:
2402 case ARM::VLD1DUPq8:
2403 case ARM::VLD1DUPq16:
2404 case ARM::VLD1DUPq32:
2405 case ARM::VLD1DUPq8_UPD:
2406 case ARM::VLD1DUPq16_UPD:
2407 case ARM::VLD1DUPq32_UPD:
2408 case ARM::VLD2DUPd8:
2409 case ARM::VLD2DUPd16:
2410 case ARM::VLD2DUPd32:
2411 case ARM::VLD2DUPd8_UPD:
2412 case ARM::VLD2DUPd16_UPD:
2413 case ARM::VLD2DUPd32_UPD:
2414 case ARM::VLD4DUPd8:
2415 case ARM::VLD4DUPd16:
2416 case ARM::VLD4DUPd32:
2417 case ARM::VLD4DUPd8_UPD:
2418 case ARM::VLD4DUPd16_UPD:
2419 case ARM::VLD4DUPd32_UPD:
2421 case ARM::VLD1LNd16:
2422 case ARM::VLD1LNd32:
2423 case ARM::VLD1LNd8_UPD:
2424 case ARM::VLD1LNd16_UPD:
2425 case ARM::VLD1LNd32_UPD:
2427 case ARM::VLD2LNd16:
2428 case ARM::VLD2LNd32:
2429 case ARM::VLD2LNq16:
2430 case ARM::VLD2LNq32:
2431 case ARM::VLD2LNd8_UPD:
2432 case ARM::VLD2LNd16_UPD:
2433 case ARM::VLD2LNd32_UPD:
2434 case ARM::VLD2LNq16_UPD:
2435 case ARM::VLD2LNq32_UPD:
2437 case ARM::VLD4LNd16:
2438 case ARM::VLD4LNd32:
2439 case ARM::VLD4LNq16:
2440 case ARM::VLD4LNq32:
2441 case ARM::VLD4LNd8_UPD:
2442 case ARM::VLD4LNd16_UPD:
2443 case ARM::VLD4LNd32_UPD:
2444 case ARM::VLD4LNq16_UPD:
2445 case ARM::VLD4LNq32_UPD:
2446 // If the address is not 64-bit aligned, the latencies of these
2447 // instructions increases by one.
2456 ARMBaseInstrInfo::getOperandLatency(const InstrItineraryData *ItinData,
2457 SDNode *DefNode, unsigned DefIdx,
2458 SDNode *UseNode, unsigned UseIdx) const {
2459 if (!DefNode->isMachineOpcode())
2462 const MCInstrDesc &DefMCID = get(DefNode->getMachineOpcode());
2464 if (isZeroCost(DefMCID.Opcode))
2467 if (!ItinData || ItinData->isEmpty())
2468 return DefMCID.mayLoad() ? 3 : 1;
2470 if (!UseNode->isMachineOpcode()) {
2471 int Latency = ItinData->getOperandCycle(DefMCID.getSchedClass(), DefIdx);
2472 if (Subtarget.isCortexA9())
2473 return Latency <= 2 ? 1 : Latency - 1;
2475 return Latency <= 3 ? 1 : Latency - 2;
2478 const MCInstrDesc &UseMCID = get(UseNode->getMachineOpcode());
2479 const MachineSDNode *DefMN = dyn_cast<MachineSDNode>(DefNode);
2480 unsigned DefAlign = !DefMN->memoperands_empty()
2481 ? (*DefMN->memoperands_begin())->getAlignment() : 0;
2482 const MachineSDNode *UseMN = dyn_cast<MachineSDNode>(UseNode);
2483 unsigned UseAlign = !UseMN->memoperands_empty()
2484 ? (*UseMN->memoperands_begin())->getAlignment() : 0;
2485 int Latency = getOperandLatency(ItinData, DefMCID, DefIdx, DefAlign,
2486 UseMCID, UseIdx, UseAlign);
2489 (Subtarget.isCortexA8() || Subtarget.isCortexA9())) {
2490 // FIXME: Shifter op hack: no shift (i.e. [r +/- r]) or [r + r << 2]
2491 // variants are one cycle cheaper.
2492 switch (DefMCID.getOpcode()) {
2497 cast<ConstantSDNode>(DefNode->getOperand(2))->getZExtValue();
2498 unsigned ShImm = ARM_AM::getAM2Offset(ShOpVal);
2500 (ShImm == 2 && ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl))
2507 case ARM::t2LDRSHs: {
2508 // Thumb2 mode: lsl only.
2510 cast<ConstantSDNode>(DefNode->getOperand(2))->getZExtValue();
2511 if (ShAmt == 0 || ShAmt == 2)
2518 if (DefAlign < 8 && Subtarget.isCortexA9())
2519 switch (DefMCID.getOpcode()) {
2521 case ARM::VLD1q8Pseudo:
2522 case ARM::VLD1q16Pseudo:
2523 case ARM::VLD1q32Pseudo:
2524 case ARM::VLD1q64Pseudo:
2525 case ARM::VLD1q8Pseudo_UPD:
2526 case ARM::VLD1q16Pseudo_UPD:
2527 case ARM::VLD1q32Pseudo_UPD:
2528 case ARM::VLD1q64Pseudo_UPD:
2529 case ARM::VLD2d8Pseudo:
2530 case ARM::VLD2d16Pseudo:
2531 case ARM::VLD2d32Pseudo:
2532 case ARM::VLD2q8Pseudo:
2533 case ARM::VLD2q16Pseudo:
2534 case ARM::VLD2q32Pseudo:
2535 case ARM::VLD2d8Pseudo_UPD:
2536 case ARM::VLD2d16Pseudo_UPD:
2537 case ARM::VLD2d32Pseudo_UPD:
2538 case ARM::VLD2q8Pseudo_UPD:
2539 case ARM::VLD2q16Pseudo_UPD:
2540 case ARM::VLD2q32Pseudo_UPD:
2541 case ARM::VLD3d8Pseudo:
2542 case ARM::VLD3d16Pseudo:
2543 case ARM::VLD3d32Pseudo:
2544 case ARM::VLD1d64TPseudo:
2545 case ARM::VLD3d8Pseudo_UPD:
2546 case ARM::VLD3d16Pseudo_UPD:
2547 case ARM::VLD3d32Pseudo_UPD:
2548 case ARM::VLD1d64TPseudo_UPD:
2549 case ARM::VLD3q8Pseudo_UPD:
2550 case ARM::VLD3q16Pseudo_UPD:
2551 case ARM::VLD3q32Pseudo_UPD:
2552 case ARM::VLD3q8oddPseudo:
2553 case ARM::VLD3q16oddPseudo:
2554 case ARM::VLD3q32oddPseudo:
2555 case ARM::VLD3q8oddPseudo_UPD:
2556 case ARM::VLD3q16oddPseudo_UPD:
2557 case ARM::VLD3q32oddPseudo_UPD:
2558 case ARM::VLD4d8Pseudo:
2559 case ARM::VLD4d16Pseudo:
2560 case ARM::VLD4d32Pseudo:
2561 case ARM::VLD1d64QPseudo:
2562 case ARM::VLD4d8Pseudo_UPD:
2563 case ARM::VLD4d16Pseudo_UPD:
2564 case ARM::VLD4d32Pseudo_UPD:
2565 case ARM::VLD1d64QPseudo_UPD:
2566 case ARM::VLD4q8Pseudo_UPD:
2567 case ARM::VLD4q16Pseudo_UPD:
2568 case ARM::VLD4q32Pseudo_UPD:
2569 case ARM::VLD4q8oddPseudo:
2570 case ARM::VLD4q16oddPseudo:
2571 case ARM::VLD4q32oddPseudo:
2572 case ARM::VLD4q8oddPseudo_UPD:
2573 case ARM::VLD4q16oddPseudo_UPD:
2574 case ARM::VLD4q32oddPseudo_UPD:
2575 case ARM::VLD1DUPq8Pseudo:
2576 case ARM::VLD1DUPq16Pseudo:
2577 case ARM::VLD1DUPq32Pseudo:
2578 case ARM::VLD1DUPq8Pseudo_UPD:
2579 case ARM::VLD1DUPq16Pseudo_UPD:
2580 case ARM::VLD1DUPq32Pseudo_UPD:
2581 case ARM::VLD2DUPd8Pseudo:
2582 case ARM::VLD2DUPd16Pseudo:
2583 case ARM::VLD2DUPd32Pseudo:
2584 case ARM::VLD2DUPd8Pseudo_UPD:
2585 case ARM::VLD2DUPd16Pseudo_UPD:
2586 case ARM::VLD2DUPd32Pseudo_UPD:
2587 case ARM::VLD4DUPd8Pseudo:
2588 case ARM::VLD4DUPd16Pseudo:
2589 case ARM::VLD4DUPd32Pseudo:
2590 case ARM::VLD4DUPd8Pseudo_UPD:
2591 case ARM::VLD4DUPd16Pseudo_UPD:
2592 case ARM::VLD4DUPd32Pseudo_UPD:
2593 case ARM::VLD1LNq8Pseudo:
2594 case ARM::VLD1LNq16Pseudo:
2595 case ARM::VLD1LNq32Pseudo:
2596 case ARM::VLD1LNq8Pseudo_UPD:
2597 case ARM::VLD1LNq16Pseudo_UPD:
2598 case ARM::VLD1LNq32Pseudo_UPD:
2599 case ARM::VLD2LNd8Pseudo:
2600 case ARM::VLD2LNd16Pseudo:
2601 case ARM::VLD2LNd32Pseudo:
2602 case ARM::VLD2LNq16Pseudo:
2603 case ARM::VLD2LNq32Pseudo:
2604 case ARM::VLD2LNd8Pseudo_UPD:
2605 case ARM::VLD2LNd16Pseudo_UPD:
2606 case ARM::VLD2LNd32Pseudo_UPD:
2607 case ARM::VLD2LNq16Pseudo_UPD:
2608 case ARM::VLD2LNq32Pseudo_UPD:
2609 case ARM::VLD4LNd8Pseudo:
2610 case ARM::VLD4LNd16Pseudo:
2611 case ARM::VLD4LNd32Pseudo:
2612 case ARM::VLD4LNq16Pseudo:
2613 case ARM::VLD4LNq32Pseudo:
2614 case ARM::VLD4LNd8Pseudo_UPD:
2615 case ARM::VLD4LNd16Pseudo_UPD:
2616 case ARM::VLD4LNd32Pseudo_UPD:
2617 case ARM::VLD4LNq16Pseudo_UPD:
2618 case ARM::VLD4LNq32Pseudo_UPD:
2619 // If the address is not 64-bit aligned, the latencies of these
2620 // instructions increases by one.
2628 int ARMBaseInstrInfo::getInstrLatency(const InstrItineraryData *ItinData,
2629 const MachineInstr *MI,
2630 unsigned *PredCost) const {
2631 if (MI->isCopyLike() || MI->isInsertSubreg() ||
2632 MI->isRegSequence() || MI->isImplicitDef())
2635 if (!ItinData || ItinData->isEmpty())
2638 const MCInstrDesc &MCID = MI->getDesc();
2639 unsigned Class = MCID.getSchedClass();
2640 unsigned UOps = ItinData->Itineraries[Class].NumMicroOps;
2641 if (PredCost && MCID.hasImplicitDefOfPhysReg(ARM::CPSR))
2642 // When predicated, CPSR is an additional source operand for CPSR updating
2643 // instructions, this apparently increases their latencies.
2646 return ItinData->getStageLatency(Class);
2647 return getNumMicroOps(ItinData, MI);
2650 int ARMBaseInstrInfo::getInstrLatency(const InstrItineraryData *ItinData,
2651 SDNode *Node) const {
2652 if (!Node->isMachineOpcode())
2655 if (!ItinData || ItinData->isEmpty())
2658 unsigned Opcode = Node->getMachineOpcode();
2661 return ItinData->getStageLatency(get(Opcode).getSchedClass());
2668 bool ARMBaseInstrInfo::
2669 hasHighOperandLatency(const InstrItineraryData *ItinData,
2670 const MachineRegisterInfo *MRI,
2671 const MachineInstr *DefMI, unsigned DefIdx,
2672 const MachineInstr *UseMI, unsigned UseIdx) const {
2673 unsigned DDomain = DefMI->getDesc().TSFlags & ARMII::DomainMask;
2674 unsigned UDomain = UseMI->getDesc().TSFlags & ARMII::DomainMask;
2675 if (Subtarget.isCortexA8() &&
2676 (DDomain == ARMII::DomainVFP || UDomain == ARMII::DomainVFP))
2677 // CortexA8 VFP instructions are not pipelined.
2680 // Hoist VFP / NEON instructions with 4 or higher latency.
2681 int Latency = getOperandLatency(ItinData, DefMI, DefIdx, UseMI, UseIdx);
2684 return DDomain == ARMII::DomainVFP || DDomain == ARMII::DomainNEON ||
2685 UDomain == ARMII::DomainVFP || UDomain == ARMII::DomainNEON;
2688 bool ARMBaseInstrInfo::
2689 hasLowDefLatency(const InstrItineraryData *ItinData,
2690 const MachineInstr *DefMI, unsigned DefIdx) const {
2691 if (!ItinData || ItinData->isEmpty())
2694 unsigned DDomain = DefMI->getDesc().TSFlags & ARMII::DomainMask;
2695 if (DDomain == ARMII::DomainGeneral) {
2696 unsigned DefClass = DefMI->getDesc().getSchedClass();
2697 int DefCycle = ItinData->getOperandCycle(DefClass, DefIdx);
2698 return (DefCycle != -1 && DefCycle <= 2);
2703 bool ARMBaseInstrInfo::verifyInstruction(const MachineInstr *MI,
2704 StringRef &ErrInfo) const {
2705 if (convertAddSubFlagsOpcode(MI->getOpcode())) {
2706 ErrInfo = "Pseudo flag setting opcodes only exist in Selection DAG";
2713 ARMBaseInstrInfo::isFpMLxInstruction(unsigned Opcode, unsigned &MulOpc,
2714 unsigned &AddSubOpc,
2715 bool &NegAcc, bool &HasLane) const {
2716 DenseMap<unsigned, unsigned>::const_iterator I = MLxEntryMap.find(Opcode);
2717 if (I == MLxEntryMap.end())
2720 const ARM_MLxEntry &Entry = ARM_MLxTable[I->second];
2721 MulOpc = Entry.MulOpc;
2722 AddSubOpc = Entry.AddSubOpc;
2723 NegAcc = Entry.NegAcc;
2724 HasLane = Entry.HasLane;
2728 //===----------------------------------------------------------------------===//
2729 // Execution domains.
2730 //===----------------------------------------------------------------------===//
2732 // Some instructions go down the NEON pipeline, some go down the VFP pipeline,
2733 // and some can go down both. The vmov instructions go down the VFP pipeline,
2734 // but they can be changed to vorr equivalents that are executed by the NEON
2737 // We use the following execution domain numbering:
2745 // Also see ARMInstrFormats.td and Domain* enums in ARMBaseInfo.h
2747 std::pair<uint16_t, uint16_t>
2748 ARMBaseInstrInfo::getExecutionDomain(const MachineInstr *MI) const {
2749 // VMOVD is a VFP instruction, but can be changed to NEON if it isn't
2751 if (MI->getOpcode() == ARM::VMOVD && !isPredicated(MI))
2752 return std::make_pair(ExeVFP, (1<<ExeVFP) | (1<<ExeNEON));
2754 // No other instructions can be swizzled, so just determine their domain.
2755 unsigned Domain = MI->getDesc().TSFlags & ARMII::DomainMask;
2757 if (Domain & ARMII::DomainNEON)
2758 return std::make_pair(ExeNEON, 0);
2760 // Certain instructions can go either way on Cortex-A8.
2761 // Treat them as NEON instructions.
2762 if ((Domain & ARMII::DomainNEONA8) && Subtarget.isCortexA8())
2763 return std::make_pair(ExeNEON, 0);
2765 if (Domain & ARMII::DomainVFP)
2766 return std::make_pair(ExeVFP, 0);
2768 return std::make_pair(ExeGeneric, 0);
2772 ARMBaseInstrInfo::setExecutionDomain(MachineInstr *MI, unsigned Domain) const {
2773 // We only know how to change VMOVD into VORR.
2774 assert(MI->getOpcode() == ARM::VMOVD && "Can only swizzle VMOVD");
2775 if (Domain != ExeNEON)
2778 // Zap the predicate operands.
2779 assert(!isPredicated(MI) && "Cannot predicate a VORRd");
2780 MI->RemoveOperand(3);
2781 MI->RemoveOperand(2);
2783 // Change to a VORRd which requires two identical use operands.
2784 MI->setDesc(get(ARM::VORRd));
2786 // Add the extra source operand and new predicates.
2787 // This will go before any implicit ops.
2788 AddDefaultPred(MachineInstrBuilder(MI).addReg(MI->getOperand(1).getReg()));