1 //===-- ARMBaseInstrInfo.cpp - ARM Instruction Information ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Base ARM implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
15 #include "ARMBaseInstrInfo.h"
16 #include "ARMBaseRegisterInfo.h"
17 #include "ARMConstantPoolValue.h"
18 #include "ARMFeatures.h"
19 #include "ARMHazardRecognizer.h"
20 #include "ARMMachineFunctionInfo.h"
21 #include "MCTargetDesc/ARMAddressingModes.h"
22 #include "llvm/ADT/STLExtras.h"
23 #include "llvm/CodeGen/LiveVariables.h"
24 #include "llvm/CodeGen/MachineConstantPool.h"
25 #include "llvm/CodeGen/MachineFrameInfo.h"
26 #include "llvm/CodeGen/MachineInstrBuilder.h"
27 #include "llvm/CodeGen/MachineJumpTableInfo.h"
28 #include "llvm/CodeGen/MachineMemOperand.h"
29 #include "llvm/CodeGen/MachineRegisterInfo.h"
30 #include "llvm/CodeGen/SelectionDAGNodes.h"
31 #include "llvm/CodeGen/TargetSchedule.h"
32 #include "llvm/IR/Constants.h"
33 #include "llvm/IR/Function.h"
34 #include "llvm/IR/GlobalValue.h"
35 #include "llvm/MC/MCAsmInfo.h"
36 #include "llvm/MC/MCExpr.h"
37 #include "llvm/Support/BranchProbability.h"
38 #include "llvm/Support/CommandLine.h"
39 #include "llvm/Support/Debug.h"
40 #include "llvm/Support/ErrorHandling.h"
41 #include "llvm/Support/raw_ostream.h"
45 #define DEBUG_TYPE "arm-instrinfo"
47 #define GET_INSTRINFO_CTOR_DTOR
48 #include "ARMGenInstrInfo.inc"
51 EnableARM3Addr("enable-arm-3-addr-conv", cl::Hidden,
52 cl::desc("Enable ARM 2-addr to 3-addr conv"));
55 WidenVMOVS("widen-vmovs", cl::Hidden, cl::init(true),
56 cl::desc("Widen ARM vmovs to vmovd when possible"));
58 static cl::opt<unsigned>
59 SwiftPartialUpdateClearance("swift-partial-update-clearance",
60 cl::Hidden, cl::init(12),
61 cl::desc("Clearance before partial register updates"));
63 /// ARM_MLxEntry - Record information about MLA / MLS instructions.
65 uint16_t MLxOpc; // MLA / MLS opcode
66 uint16_t MulOpc; // Expanded multiplication opcode
67 uint16_t AddSubOpc; // Expanded add / sub opcode
68 bool NegAcc; // True if the acc is negated before the add / sub.
69 bool HasLane; // True if instruction has an extra "lane" operand.
72 static const ARM_MLxEntry ARM_MLxTable[] = {
73 // MLxOpc, MulOpc, AddSubOpc, NegAcc, HasLane
75 { ARM::VMLAS, ARM::VMULS, ARM::VADDS, false, false },
76 { ARM::VMLSS, ARM::VMULS, ARM::VSUBS, false, false },
77 { ARM::VMLAD, ARM::VMULD, ARM::VADDD, false, false },
78 { ARM::VMLSD, ARM::VMULD, ARM::VSUBD, false, false },
79 { ARM::VNMLAS, ARM::VNMULS, ARM::VSUBS, true, false },
80 { ARM::VNMLSS, ARM::VMULS, ARM::VSUBS, true, false },
81 { ARM::VNMLAD, ARM::VNMULD, ARM::VSUBD, true, false },
82 { ARM::VNMLSD, ARM::VMULD, ARM::VSUBD, true, false },
85 { ARM::VMLAfd, ARM::VMULfd, ARM::VADDfd, false, false },
86 { ARM::VMLSfd, ARM::VMULfd, ARM::VSUBfd, false, false },
87 { ARM::VMLAfq, ARM::VMULfq, ARM::VADDfq, false, false },
88 { ARM::VMLSfq, ARM::VMULfq, ARM::VSUBfq, false, false },
89 { ARM::VMLAslfd, ARM::VMULslfd, ARM::VADDfd, false, true },
90 { ARM::VMLSslfd, ARM::VMULslfd, ARM::VSUBfd, false, true },
91 { ARM::VMLAslfq, ARM::VMULslfq, ARM::VADDfq, false, true },
92 { ARM::VMLSslfq, ARM::VMULslfq, ARM::VSUBfq, false, true },
95 ARMBaseInstrInfo::ARMBaseInstrInfo(const ARMSubtarget& STI)
96 : ARMGenInstrInfo(ARM::ADJCALLSTACKDOWN, ARM::ADJCALLSTACKUP),
98 for (unsigned i = 0, e = array_lengthof(ARM_MLxTable); i != e; ++i) {
99 if (!MLxEntryMap.insert(std::make_pair(ARM_MLxTable[i].MLxOpc, i)).second)
100 assert(false && "Duplicated entries?");
101 MLxHazardOpcodes.insert(ARM_MLxTable[i].AddSubOpc);
102 MLxHazardOpcodes.insert(ARM_MLxTable[i].MulOpc);
106 // Use a ScoreboardHazardRecognizer for prepass ARM scheduling. TargetInstrImpl
107 // currently defaults to no prepass hazard recognizer.
108 ScheduleHazardRecognizer *
109 ARMBaseInstrInfo::CreateTargetHazardRecognizer(const TargetSubtargetInfo *STI,
110 const ScheduleDAG *DAG) const {
111 if (usePreRAHazardRecognizer()) {
112 const InstrItineraryData *II =
113 static_cast<const ARMSubtarget *>(STI)->getInstrItineraryData();
114 return new ScoreboardHazardRecognizer(II, DAG, "pre-RA-sched");
116 return TargetInstrInfo::CreateTargetHazardRecognizer(STI, DAG);
119 ScheduleHazardRecognizer *ARMBaseInstrInfo::
120 CreateTargetPostRAHazardRecognizer(const InstrItineraryData *II,
121 const ScheduleDAG *DAG) const {
122 if (Subtarget.isThumb2() || Subtarget.hasVFP2())
123 return (ScheduleHazardRecognizer *)new ARMHazardRecognizer(II, DAG);
124 return TargetInstrInfo::CreateTargetPostRAHazardRecognizer(II, DAG);
128 ARMBaseInstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
129 MachineBasicBlock::iterator &MBBI,
130 LiveVariables *LV) const {
131 // FIXME: Thumb2 support.
136 MachineInstr *MI = MBBI;
137 MachineFunction &MF = *MI->getParent()->getParent();
138 uint64_t TSFlags = MI->getDesc().TSFlags;
140 switch ((TSFlags & ARMII::IndexModeMask) >> ARMII::IndexModeShift) {
141 default: return nullptr;
142 case ARMII::IndexModePre:
145 case ARMII::IndexModePost:
149 // Try splitting an indexed load/store to an un-indexed one plus an add/sub
151 unsigned MemOpc = getUnindexedOpcode(MI->getOpcode());
155 MachineInstr *UpdateMI = nullptr;
156 MachineInstr *MemMI = nullptr;
157 unsigned AddrMode = (TSFlags & ARMII::AddrModeMask);
158 const MCInstrDesc &MCID = MI->getDesc();
159 unsigned NumOps = MCID.getNumOperands();
160 bool isLoad = !MI->mayStore();
161 const MachineOperand &WB = isLoad ? MI->getOperand(1) : MI->getOperand(0);
162 const MachineOperand &Base = MI->getOperand(2);
163 const MachineOperand &Offset = MI->getOperand(NumOps-3);
164 unsigned WBReg = WB.getReg();
165 unsigned BaseReg = Base.getReg();
166 unsigned OffReg = Offset.getReg();
167 unsigned OffImm = MI->getOperand(NumOps-2).getImm();
168 ARMCC::CondCodes Pred = (ARMCC::CondCodes)MI->getOperand(NumOps-1).getImm();
170 default: llvm_unreachable("Unknown indexed op!");
171 case ARMII::AddrMode2: {
172 bool isSub = ARM_AM::getAM2Op(OffImm) == ARM_AM::sub;
173 unsigned Amt = ARM_AM::getAM2Offset(OffImm);
175 if (ARM_AM::getSOImmVal(Amt) == -1)
176 // Can't encode it in a so_imm operand. This transformation will
177 // add more than 1 instruction. Abandon!
179 UpdateMI = BuildMI(MF, MI->getDebugLoc(),
180 get(isSub ? ARM::SUBri : ARM::ADDri), WBReg)
181 .addReg(BaseReg).addImm(Amt)
182 .addImm(Pred).addReg(0).addReg(0);
183 } else if (Amt != 0) {
184 ARM_AM::ShiftOpc ShOpc = ARM_AM::getAM2ShiftOpc(OffImm);
185 unsigned SOOpc = ARM_AM::getSORegOpc(ShOpc, Amt);
186 UpdateMI = BuildMI(MF, MI->getDebugLoc(),
187 get(isSub ? ARM::SUBrsi : ARM::ADDrsi), WBReg)
188 .addReg(BaseReg).addReg(OffReg).addReg(0).addImm(SOOpc)
189 .addImm(Pred).addReg(0).addReg(0);
191 UpdateMI = BuildMI(MF, MI->getDebugLoc(),
192 get(isSub ? ARM::SUBrr : ARM::ADDrr), WBReg)
193 .addReg(BaseReg).addReg(OffReg)
194 .addImm(Pred).addReg(0).addReg(0);
197 case ARMII::AddrMode3 : {
198 bool isSub = ARM_AM::getAM3Op(OffImm) == ARM_AM::sub;
199 unsigned Amt = ARM_AM::getAM3Offset(OffImm);
201 // Immediate is 8-bits. It's guaranteed to fit in a so_imm operand.
202 UpdateMI = BuildMI(MF, MI->getDebugLoc(),
203 get(isSub ? ARM::SUBri : ARM::ADDri), WBReg)
204 .addReg(BaseReg).addImm(Amt)
205 .addImm(Pred).addReg(0).addReg(0);
207 UpdateMI = BuildMI(MF, MI->getDebugLoc(),
208 get(isSub ? ARM::SUBrr : ARM::ADDrr), WBReg)
209 .addReg(BaseReg).addReg(OffReg)
210 .addImm(Pred).addReg(0).addReg(0);
215 std::vector<MachineInstr*> NewMIs;
218 MemMI = BuildMI(MF, MI->getDebugLoc(),
219 get(MemOpc), MI->getOperand(0).getReg())
220 .addReg(WBReg).addImm(0).addImm(Pred);
222 MemMI = BuildMI(MF, MI->getDebugLoc(),
223 get(MemOpc)).addReg(MI->getOperand(1).getReg())
224 .addReg(WBReg).addReg(0).addImm(0).addImm(Pred);
225 NewMIs.push_back(MemMI);
226 NewMIs.push_back(UpdateMI);
229 MemMI = BuildMI(MF, MI->getDebugLoc(),
230 get(MemOpc), MI->getOperand(0).getReg())
231 .addReg(BaseReg).addImm(0).addImm(Pred);
233 MemMI = BuildMI(MF, MI->getDebugLoc(),
234 get(MemOpc)).addReg(MI->getOperand(1).getReg())
235 .addReg(BaseReg).addReg(0).addImm(0).addImm(Pred);
237 UpdateMI->getOperand(0).setIsDead();
238 NewMIs.push_back(UpdateMI);
239 NewMIs.push_back(MemMI);
242 // Transfer LiveVariables states, kill / dead info.
244 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
245 MachineOperand &MO = MI->getOperand(i);
246 if (MO.isReg() && TargetRegisterInfo::isVirtualRegister(MO.getReg())) {
247 unsigned Reg = MO.getReg();
249 LiveVariables::VarInfo &VI = LV->getVarInfo(Reg);
251 MachineInstr *NewMI = (Reg == WBReg) ? UpdateMI : MemMI;
253 LV->addVirtualRegisterDead(Reg, NewMI);
255 if (MO.isUse() && MO.isKill()) {
256 for (unsigned j = 0; j < 2; ++j) {
257 // Look at the two new MI's in reverse order.
258 MachineInstr *NewMI = NewMIs[j];
259 if (!NewMI->readsRegister(Reg))
261 LV->addVirtualRegisterKilled(Reg, NewMI);
262 if (VI.removeKill(MI))
263 VI.Kills.push_back(NewMI);
271 MFI->insert(MBBI, NewMIs[1]);
272 MFI->insert(MBBI, NewMIs[0]);
278 ARMBaseInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB,
279 MachineBasicBlock *&FBB,
280 SmallVectorImpl<MachineOperand> &Cond,
281 bool AllowModify) const {
285 MachineBasicBlock::iterator I = MBB.end();
286 if (I == MBB.begin())
287 return false; // Empty blocks are easy.
290 // Walk backwards from the end of the basic block until the branch is
291 // analyzed or we give up.
292 while (isPredicated(I) || I->isTerminator() || I->isDebugValue()) {
294 // Flag to be raised on unanalyzeable instructions. This is useful in cases
295 // where we want to clean up on the end of the basic block before we bail
297 bool CantAnalyze = false;
299 // Skip over DEBUG values and predicated nonterminators.
300 while (I->isDebugValue() || !I->isTerminator()) {
301 if (I == MBB.begin())
306 if (isIndirectBranchOpcode(I->getOpcode()) ||
307 isJumpTableBranchOpcode(I->getOpcode())) {
308 // Indirect branches and jump tables can't be analyzed, but we still want
309 // to clean up any instructions at the tail of the basic block.
311 } else if (isUncondBranchOpcode(I->getOpcode())) {
312 TBB = I->getOperand(0).getMBB();
313 } else if (isCondBranchOpcode(I->getOpcode())) {
314 // Bail out if we encounter multiple conditional branches.
318 assert(!FBB && "FBB should have been null.");
320 TBB = I->getOperand(0).getMBB();
321 Cond.push_back(I->getOperand(1));
322 Cond.push_back(I->getOperand(2));
323 } else if (I->isReturn()) {
324 // Returns can't be analyzed, but we should run cleanup.
325 CantAnalyze = !isPredicated(I);
327 // We encountered other unrecognized terminator. Bail out immediately.
331 // Cleanup code - to be run for unpredicated unconditional branches and
333 if (!isPredicated(I) &&
334 (isUncondBranchOpcode(I->getOpcode()) ||
335 isIndirectBranchOpcode(I->getOpcode()) ||
336 isJumpTableBranchOpcode(I->getOpcode()) ||
338 // Forget any previous condition branch information - it no longer applies.
342 // If we can modify the function, delete everything below this
343 // unconditional branch.
345 MachineBasicBlock::iterator DI = std::next(I);
346 while (DI != MBB.end()) {
347 MachineInstr *InstToDelete = DI;
349 InstToDelete->eraseFromParent();
357 if (I == MBB.begin())
363 // We made it past the terminators without bailing out - we must have
364 // analyzed this branch successfully.
369 unsigned ARMBaseInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
370 MachineBasicBlock::iterator I = MBB.getLastNonDebugInstr();
374 if (!isUncondBranchOpcode(I->getOpcode()) &&
375 !isCondBranchOpcode(I->getOpcode()))
378 // Remove the branch.
379 I->eraseFromParent();
383 if (I == MBB.begin()) return 1;
385 if (!isCondBranchOpcode(I->getOpcode()))
388 // Remove the branch.
389 I->eraseFromParent();
394 ARMBaseInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
395 MachineBasicBlock *FBB,
396 ArrayRef<MachineOperand> Cond,
398 ARMFunctionInfo *AFI = MBB.getParent()->getInfo<ARMFunctionInfo>();
399 int BOpc = !AFI->isThumbFunction()
400 ? ARM::B : (AFI->isThumb2Function() ? ARM::t2B : ARM::tB);
401 int BccOpc = !AFI->isThumbFunction()
402 ? ARM::Bcc : (AFI->isThumb2Function() ? ARM::t2Bcc : ARM::tBcc);
403 bool isThumb = AFI->isThumbFunction() || AFI->isThumb2Function();
405 // Shouldn't be a fall through.
406 assert(TBB && "InsertBranch must not be told to insert a fallthrough");
407 assert((Cond.size() == 2 || Cond.size() == 0) &&
408 "ARM branch conditions have two components!");
410 // For conditional branches, we use addOperand to preserve CPSR flags.
413 if (Cond.empty()) { // Unconditional branch?
415 BuildMI(&MBB, DL, get(BOpc)).addMBB(TBB).addImm(ARMCC::AL).addReg(0);
417 BuildMI(&MBB, DL, get(BOpc)).addMBB(TBB);
419 BuildMI(&MBB, DL, get(BccOpc)).addMBB(TBB)
420 .addImm(Cond[0].getImm()).addOperand(Cond[1]);
424 // Two-way conditional branch.
425 BuildMI(&MBB, DL, get(BccOpc)).addMBB(TBB)
426 .addImm(Cond[0].getImm()).addOperand(Cond[1]);
428 BuildMI(&MBB, DL, get(BOpc)).addMBB(FBB).addImm(ARMCC::AL).addReg(0);
430 BuildMI(&MBB, DL, get(BOpc)).addMBB(FBB);
434 bool ARMBaseInstrInfo::
435 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
436 ARMCC::CondCodes CC = (ARMCC::CondCodes)(int)Cond[0].getImm();
437 Cond[0].setImm(ARMCC::getOppositeCondition(CC));
441 bool ARMBaseInstrInfo::isPredicated(const MachineInstr *MI) const {
442 if (MI->isBundle()) {
443 MachineBasicBlock::const_instr_iterator I = MI;
444 MachineBasicBlock::const_instr_iterator E = MI->getParent()->instr_end();
445 while (++I != E && I->isInsideBundle()) {
446 int PIdx = I->findFirstPredOperandIdx();
447 if (PIdx != -1 && I->getOperand(PIdx).getImm() != ARMCC::AL)
453 int PIdx = MI->findFirstPredOperandIdx();
454 return PIdx != -1 && MI->getOperand(PIdx).getImm() != ARMCC::AL;
457 bool ARMBaseInstrInfo::
458 PredicateInstruction(MachineInstr *MI, ArrayRef<MachineOperand> Pred) const {
459 unsigned Opc = MI->getOpcode();
460 if (isUncondBranchOpcode(Opc)) {
461 MI->setDesc(get(getMatchingCondBranchOpcode(Opc)));
462 MachineInstrBuilder(*MI->getParent()->getParent(), MI)
463 .addImm(Pred[0].getImm())
464 .addReg(Pred[1].getReg());
468 int PIdx = MI->findFirstPredOperandIdx();
470 MachineOperand &PMO = MI->getOperand(PIdx);
471 PMO.setImm(Pred[0].getImm());
472 MI->getOperand(PIdx+1).setReg(Pred[1].getReg());
478 bool ARMBaseInstrInfo::SubsumesPredicate(ArrayRef<MachineOperand> Pred1,
479 ArrayRef<MachineOperand> Pred2) const {
480 if (Pred1.size() > 2 || Pred2.size() > 2)
483 ARMCC::CondCodes CC1 = (ARMCC::CondCodes)Pred1[0].getImm();
484 ARMCC::CondCodes CC2 = (ARMCC::CondCodes)Pred2[0].getImm();
494 return CC2 == ARMCC::HI;
496 return CC2 == ARMCC::LO || CC2 == ARMCC::EQ;
498 return CC2 == ARMCC::GT;
500 return CC2 == ARMCC::LT;
504 bool ARMBaseInstrInfo::DefinesPredicate(MachineInstr *MI,
505 std::vector<MachineOperand> &Pred) const {
507 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
508 const MachineOperand &MO = MI->getOperand(i);
509 if ((MO.isRegMask() && MO.clobbersPhysReg(ARM::CPSR)) ||
510 (MO.isReg() && MO.isDef() && MO.getReg() == ARM::CPSR)) {
519 static bool isCPSRDefined(const MachineInstr *MI) {
520 for (const auto &MO : MI->operands())
521 if (MO.isReg() && MO.getReg() == ARM::CPSR && MO.isDef() && !MO.isDead())
526 static bool isEligibleForITBlock(const MachineInstr *MI) {
527 switch (MI->getOpcode()) {
528 default: return true;
529 case ARM::tADC: // ADC (register) T1
530 case ARM::tADDi3: // ADD (immediate) T1
531 case ARM::tADDi8: // ADD (immediate) T2
532 case ARM::tADDrr: // ADD (register) T1
533 case ARM::tAND: // AND (register) T1
534 case ARM::tASRri: // ASR (immediate) T1
535 case ARM::tASRrr: // ASR (register) T1
536 case ARM::tBIC: // BIC (register) T1
537 case ARM::tEOR: // EOR (register) T1
538 case ARM::tLSLri: // LSL (immediate) T1
539 case ARM::tLSLrr: // LSL (register) T1
540 case ARM::tLSRri: // LSR (immediate) T1
541 case ARM::tLSRrr: // LSR (register) T1
542 case ARM::tMUL: // MUL T1
543 case ARM::tMVN: // MVN (register) T1
544 case ARM::tORR: // ORR (register) T1
545 case ARM::tROR: // ROR (register) T1
546 case ARM::tRSB: // RSB (immediate) T1
547 case ARM::tSBC: // SBC (register) T1
548 case ARM::tSUBi3: // SUB (immediate) T1
549 case ARM::tSUBi8: // SUB (immediate) T2
550 case ARM::tSUBrr: // SUB (register) T1
551 return !isCPSRDefined(MI);
555 /// isPredicable - Return true if the specified instruction can be predicated.
556 /// By default, this returns true for every instruction with a
557 /// PredicateOperand.
558 bool ARMBaseInstrInfo::isPredicable(MachineInstr *MI) const {
559 if (!MI->isPredicable())
562 if (!isEligibleForITBlock(MI))
565 ARMFunctionInfo *AFI =
566 MI->getParent()->getParent()->getInfo<ARMFunctionInfo>();
568 if (AFI->isThumb2Function()) {
569 if (getSubtarget().restrictIT())
570 return isV8EligibleForIT(MI);
571 } else { // non-Thumb
572 if ((MI->getDesc().TSFlags & ARMII::DomainMask) == ARMII::DomainNEON)
580 template <> bool IsCPSRDead<MachineInstr>(MachineInstr *MI) {
581 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
582 const MachineOperand &MO = MI->getOperand(i);
583 if (!MO.isReg() || MO.isUndef() || MO.isUse())
585 if (MO.getReg() != ARM::CPSR)
590 // all definitions of CPSR are dead
595 /// GetInstSize - Return the size of the specified MachineInstr.
597 unsigned ARMBaseInstrInfo::GetInstSizeInBytes(const MachineInstr *MI) const {
598 const MachineBasicBlock &MBB = *MI->getParent();
599 const MachineFunction *MF = MBB.getParent();
600 const MCAsmInfo *MAI = MF->getTarget().getMCAsmInfo();
602 const MCInstrDesc &MCID = MI->getDesc();
604 return MCID.getSize();
606 // If this machine instr is an inline asm, measure it.
607 if (MI->getOpcode() == ARM::INLINEASM)
608 return getInlineAsmLength(MI->getOperand(0).getSymbolName(), *MAI);
609 unsigned Opc = MI->getOpcode();
612 // pseudo-instruction sizes are zero.
614 case TargetOpcode::BUNDLE:
615 return getInstBundleLength(MI);
616 case ARM::MOVi16_ga_pcrel:
617 case ARM::MOVTi16_ga_pcrel:
618 case ARM::t2MOVi16_ga_pcrel:
619 case ARM::t2MOVTi16_ga_pcrel:
622 case ARM::t2MOVi32imm:
624 case ARM::CONSTPOOL_ENTRY:
625 case ARM::JUMPTABLE_INSTS:
626 case ARM::JUMPTABLE_ADDRS:
627 case ARM::JUMPTABLE_TBB:
628 case ARM::JUMPTABLE_TBH:
629 // If this machine instr is a constant pool entry, its size is recorded as
631 return MI->getOperand(2).getImm();
632 case ARM::Int_eh_sjlj_longjmp:
634 case ARM::tInt_eh_sjlj_longjmp:
636 case ARM::Int_eh_sjlj_setjmp:
637 case ARM::Int_eh_sjlj_setjmp_nofp:
639 case ARM::tInt_eh_sjlj_setjmp:
640 case ARM::t2Int_eh_sjlj_setjmp:
641 case ARM::t2Int_eh_sjlj_setjmp_nofp:
644 return MI->getOperand(1).getImm();
648 unsigned ARMBaseInstrInfo::getInstBundleLength(const MachineInstr *MI) const {
650 MachineBasicBlock::const_instr_iterator I = MI;
651 MachineBasicBlock::const_instr_iterator E = MI->getParent()->instr_end();
652 while (++I != E && I->isInsideBundle()) {
653 assert(!I->isBundle() && "No nested bundle!");
654 Size += GetInstSizeInBytes(&*I);
659 void ARMBaseInstrInfo::copyFromCPSR(MachineBasicBlock &MBB,
660 MachineBasicBlock::iterator I,
661 unsigned DestReg, bool KillSrc,
662 const ARMSubtarget &Subtarget) const {
663 unsigned Opc = Subtarget.isThumb()
664 ? (Subtarget.isMClass() ? ARM::t2MRS_M : ARM::t2MRS_AR)
667 MachineInstrBuilder MIB =
668 BuildMI(MBB, I, I->getDebugLoc(), get(Opc), DestReg);
670 // There is only 1 A/R class MRS instruction, and it always refers to
671 // APSR. However, there are lots of other possibilities on M-class cores.
672 if (Subtarget.isMClass())
677 MIB.addReg(ARM::CPSR, RegState::Implicit | getKillRegState(KillSrc));
680 void ARMBaseInstrInfo::copyToCPSR(MachineBasicBlock &MBB,
681 MachineBasicBlock::iterator I,
682 unsigned SrcReg, bool KillSrc,
683 const ARMSubtarget &Subtarget) const {
684 unsigned Opc = Subtarget.isThumb()
685 ? (Subtarget.isMClass() ? ARM::t2MSR_M : ARM::t2MSR_AR)
688 MachineInstrBuilder MIB = BuildMI(MBB, I, I->getDebugLoc(), get(Opc));
690 if (Subtarget.isMClass())
695 MIB.addReg(SrcReg, getKillRegState(KillSrc));
699 MIB.addReg(ARM::CPSR, RegState::Implicit | RegState::Define);
702 void ARMBaseInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
703 MachineBasicBlock::iterator I, DebugLoc DL,
704 unsigned DestReg, unsigned SrcReg,
705 bool KillSrc) const {
706 bool GPRDest = ARM::GPRRegClass.contains(DestReg);
707 bool GPRSrc = ARM::GPRRegClass.contains(SrcReg);
709 if (GPRDest && GPRSrc) {
710 AddDefaultCC(AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::MOVr), DestReg)
711 .addReg(SrcReg, getKillRegState(KillSrc))));
715 bool SPRDest = ARM::SPRRegClass.contains(DestReg);
716 bool SPRSrc = ARM::SPRRegClass.contains(SrcReg);
719 if (SPRDest && SPRSrc)
721 else if (GPRDest && SPRSrc)
723 else if (SPRDest && GPRSrc)
725 else if (ARM::DPRRegClass.contains(DestReg, SrcReg) && !Subtarget.isFPOnlySP())
727 else if (ARM::QPRRegClass.contains(DestReg, SrcReg))
731 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(Opc), DestReg);
732 MIB.addReg(SrcReg, getKillRegState(KillSrc));
733 if (Opc == ARM::VORRq)
734 MIB.addReg(SrcReg, getKillRegState(KillSrc));
739 // Handle register classes that require multiple instructions.
740 unsigned BeginIdx = 0;
741 unsigned SubRegs = 0;
744 // Use VORRq when possible.
745 if (ARM::QQPRRegClass.contains(DestReg, SrcReg)) {
747 BeginIdx = ARM::qsub_0;
749 } else if (ARM::QQQQPRRegClass.contains(DestReg, SrcReg)) {
751 BeginIdx = ARM::qsub_0;
753 // Fall back to VMOVD.
754 } else if (ARM::DPairRegClass.contains(DestReg, SrcReg)) {
756 BeginIdx = ARM::dsub_0;
758 } else if (ARM::DTripleRegClass.contains(DestReg, SrcReg)) {
760 BeginIdx = ARM::dsub_0;
762 } else if (ARM::DQuadRegClass.contains(DestReg, SrcReg)) {
764 BeginIdx = ARM::dsub_0;
766 } else if (ARM::GPRPairRegClass.contains(DestReg, SrcReg)) {
767 Opc = Subtarget.isThumb2() ? ARM::tMOVr : ARM::MOVr;
768 BeginIdx = ARM::gsub_0;
770 } else if (ARM::DPairSpcRegClass.contains(DestReg, SrcReg)) {
772 BeginIdx = ARM::dsub_0;
775 } else if (ARM::DTripleSpcRegClass.contains(DestReg, SrcReg)) {
777 BeginIdx = ARM::dsub_0;
780 } else if (ARM::DQuadSpcRegClass.contains(DestReg, SrcReg)) {
782 BeginIdx = ARM::dsub_0;
785 } else if (ARM::DPRRegClass.contains(DestReg, SrcReg) && Subtarget.isFPOnlySP()) {
787 BeginIdx = ARM::ssub_0;
789 } else if (SrcReg == ARM::CPSR) {
790 copyFromCPSR(MBB, I, DestReg, KillSrc, Subtarget);
792 } else if (DestReg == ARM::CPSR) {
793 copyToCPSR(MBB, I, SrcReg, KillSrc, Subtarget);
797 assert(Opc && "Impossible reg-to-reg copy");
799 const TargetRegisterInfo *TRI = &getRegisterInfo();
800 MachineInstrBuilder Mov;
802 // Copy register tuples backward when the first Dest reg overlaps with SrcReg.
803 if (TRI->regsOverlap(SrcReg, TRI->getSubReg(DestReg, BeginIdx))) {
804 BeginIdx = BeginIdx + ((SubRegs - 1) * Spacing);
808 SmallSet<unsigned, 4> DstRegs;
810 for (unsigned i = 0; i != SubRegs; ++i) {
811 unsigned Dst = TRI->getSubReg(DestReg, BeginIdx + i * Spacing);
812 unsigned Src = TRI->getSubReg(SrcReg, BeginIdx + i * Spacing);
813 assert(Dst && Src && "Bad sub-register");
815 assert(!DstRegs.count(Src) && "destructive vector copy");
818 Mov = BuildMI(MBB, I, I->getDebugLoc(), get(Opc), Dst).addReg(Src);
819 // VORR takes two source operands.
820 if (Opc == ARM::VORRq)
822 Mov = AddDefaultPred(Mov);
824 if (Opc == ARM::MOVr)
825 Mov = AddDefaultCC(Mov);
827 // Add implicit super-register defs and kills to the last instruction.
828 Mov->addRegisterDefined(DestReg, TRI);
830 Mov->addRegisterKilled(SrcReg, TRI);
833 const MachineInstrBuilder &
834 ARMBaseInstrInfo::AddDReg(MachineInstrBuilder &MIB, unsigned Reg,
835 unsigned SubIdx, unsigned State,
836 const TargetRegisterInfo *TRI) const {
838 return MIB.addReg(Reg, State);
840 if (TargetRegisterInfo::isPhysicalRegister(Reg))
841 return MIB.addReg(TRI->getSubReg(Reg, SubIdx), State);
842 return MIB.addReg(Reg, State, SubIdx);
845 void ARMBaseInstrInfo::
846 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
847 unsigned SrcReg, bool isKill, int FI,
848 const TargetRegisterClass *RC,
849 const TargetRegisterInfo *TRI) const {
851 if (I != MBB.end()) DL = I->getDebugLoc();
852 MachineFunction &MF = *MBB.getParent();
853 MachineFrameInfo &MFI = *MF.getFrameInfo();
854 unsigned Align = MFI.getObjectAlignment(FI);
856 MachineMemOperand *MMO = MF.getMachineMemOperand(
857 MachinePointerInfo::getFixedStack(MF, FI), MachineMemOperand::MOStore,
858 MFI.getObjectSize(FI), Align);
860 switch (RC->getSize()) {
862 if (ARM::GPRRegClass.hasSubClassEq(RC)) {
863 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::STRi12))
864 .addReg(SrcReg, getKillRegState(isKill))
865 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
866 } else if (ARM::SPRRegClass.hasSubClassEq(RC)) {
867 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTRS))
868 .addReg(SrcReg, getKillRegState(isKill))
869 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
871 llvm_unreachable("Unknown reg class!");
874 if (ARM::DPRRegClass.hasSubClassEq(RC)) {
875 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTRD))
876 .addReg(SrcReg, getKillRegState(isKill))
877 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
878 } else if (ARM::GPRPairRegClass.hasSubClassEq(RC)) {
879 if (Subtarget.hasV5TEOps()) {
880 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(ARM::STRD));
881 AddDReg(MIB, SrcReg, ARM::gsub_0, getKillRegState(isKill), TRI);
882 AddDReg(MIB, SrcReg, ARM::gsub_1, 0, TRI);
883 MIB.addFrameIndex(FI).addReg(0).addImm(0).addMemOperand(MMO);
887 // Fallback to STM instruction, which has existed since the dawn of
889 MachineInstrBuilder MIB =
890 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::STMIA))
891 .addFrameIndex(FI).addMemOperand(MMO));
892 AddDReg(MIB, SrcReg, ARM::gsub_0, getKillRegState(isKill), TRI);
893 AddDReg(MIB, SrcReg, ARM::gsub_1, 0, TRI);
896 llvm_unreachable("Unknown reg class!");
899 if (ARM::DPairRegClass.hasSubClassEq(RC)) {
900 // Use aligned spills if the stack can be realigned.
901 if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) {
902 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VST1q64))
903 .addFrameIndex(FI).addImm(16)
904 .addReg(SrcReg, getKillRegState(isKill))
905 .addMemOperand(MMO));
907 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTMQIA))
908 .addReg(SrcReg, getKillRegState(isKill))
910 .addMemOperand(MMO));
913 llvm_unreachable("Unknown reg class!");
916 if (ARM::DTripleRegClass.hasSubClassEq(RC)) {
917 // Use aligned spills if the stack can be realigned.
918 if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) {
919 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VST1d64TPseudo))
920 .addFrameIndex(FI).addImm(16)
921 .addReg(SrcReg, getKillRegState(isKill))
922 .addMemOperand(MMO));
924 MachineInstrBuilder MIB =
925 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTMDIA))
928 MIB = AddDReg(MIB, SrcReg, ARM::dsub_0, getKillRegState(isKill), TRI);
929 MIB = AddDReg(MIB, SrcReg, ARM::dsub_1, 0, TRI);
930 AddDReg(MIB, SrcReg, ARM::dsub_2, 0, TRI);
933 llvm_unreachable("Unknown reg class!");
936 if (ARM::QQPRRegClass.hasSubClassEq(RC) || ARM::DQuadRegClass.hasSubClassEq(RC)) {
937 if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) {
938 // FIXME: It's possible to only store part of the QQ register if the
939 // spilled def has a sub-register index.
940 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VST1d64QPseudo))
941 .addFrameIndex(FI).addImm(16)
942 .addReg(SrcReg, getKillRegState(isKill))
943 .addMemOperand(MMO));
945 MachineInstrBuilder MIB =
946 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTMDIA))
949 MIB = AddDReg(MIB, SrcReg, ARM::dsub_0, getKillRegState(isKill), TRI);
950 MIB = AddDReg(MIB, SrcReg, ARM::dsub_1, 0, TRI);
951 MIB = AddDReg(MIB, SrcReg, ARM::dsub_2, 0, TRI);
952 AddDReg(MIB, SrcReg, ARM::dsub_3, 0, TRI);
955 llvm_unreachable("Unknown reg class!");
958 if (ARM::QQQQPRRegClass.hasSubClassEq(RC)) {
959 MachineInstrBuilder MIB =
960 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTMDIA))
963 MIB = AddDReg(MIB, SrcReg, ARM::dsub_0, getKillRegState(isKill), TRI);
964 MIB = AddDReg(MIB, SrcReg, ARM::dsub_1, 0, TRI);
965 MIB = AddDReg(MIB, SrcReg, ARM::dsub_2, 0, TRI);
966 MIB = AddDReg(MIB, SrcReg, ARM::dsub_3, 0, TRI);
967 MIB = AddDReg(MIB, SrcReg, ARM::dsub_4, 0, TRI);
968 MIB = AddDReg(MIB, SrcReg, ARM::dsub_5, 0, TRI);
969 MIB = AddDReg(MIB, SrcReg, ARM::dsub_6, 0, TRI);
970 AddDReg(MIB, SrcReg, ARM::dsub_7, 0, TRI);
972 llvm_unreachable("Unknown reg class!");
975 llvm_unreachable("Unknown reg class!");
980 ARMBaseInstrInfo::isStoreToStackSlot(const MachineInstr *MI,
981 int &FrameIndex) const {
982 switch (MI->getOpcode()) {
985 case ARM::t2STRs: // FIXME: don't use t2STRs to access frame.
986 if (MI->getOperand(1).isFI() &&
987 MI->getOperand(2).isReg() &&
988 MI->getOperand(3).isImm() &&
989 MI->getOperand(2).getReg() == 0 &&
990 MI->getOperand(3).getImm() == 0) {
991 FrameIndex = MI->getOperand(1).getIndex();
992 return MI->getOperand(0).getReg();
1000 if (MI->getOperand(1).isFI() &&
1001 MI->getOperand(2).isImm() &&
1002 MI->getOperand(2).getImm() == 0) {
1003 FrameIndex = MI->getOperand(1).getIndex();
1004 return MI->getOperand(0).getReg();
1008 case ARM::VST1d64TPseudo:
1009 case ARM::VST1d64QPseudo:
1010 if (MI->getOperand(0).isFI() &&
1011 MI->getOperand(2).getSubReg() == 0) {
1012 FrameIndex = MI->getOperand(0).getIndex();
1013 return MI->getOperand(2).getReg();
1017 if (MI->getOperand(1).isFI() &&
1018 MI->getOperand(0).getSubReg() == 0) {
1019 FrameIndex = MI->getOperand(1).getIndex();
1020 return MI->getOperand(0).getReg();
1028 unsigned ARMBaseInstrInfo::isStoreToStackSlotPostFE(const MachineInstr *MI,
1029 int &FrameIndex) const {
1030 const MachineMemOperand *Dummy;
1031 return MI->mayStore() && hasStoreToStackSlot(MI, Dummy, FrameIndex);
1034 void ARMBaseInstrInfo::
1035 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
1036 unsigned DestReg, int FI,
1037 const TargetRegisterClass *RC,
1038 const TargetRegisterInfo *TRI) const {
1040 if (I != MBB.end()) DL = I->getDebugLoc();
1041 MachineFunction &MF = *MBB.getParent();
1042 MachineFrameInfo &MFI = *MF.getFrameInfo();
1043 unsigned Align = MFI.getObjectAlignment(FI);
1044 MachineMemOperand *MMO = MF.getMachineMemOperand(
1045 MachinePointerInfo::getFixedStack(MF, FI), MachineMemOperand::MOLoad,
1046 MFI.getObjectSize(FI), Align);
1048 switch (RC->getSize()) {
1050 if (ARM::GPRRegClass.hasSubClassEq(RC)) {
1051 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::LDRi12), DestReg)
1052 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
1054 } else if (ARM::SPRRegClass.hasSubClassEq(RC)) {
1055 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDRS), DestReg)
1056 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
1058 llvm_unreachable("Unknown reg class!");
1061 if (ARM::DPRRegClass.hasSubClassEq(RC)) {
1062 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDRD), DestReg)
1063 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
1064 } else if (ARM::GPRPairRegClass.hasSubClassEq(RC)) {
1065 MachineInstrBuilder MIB;
1067 if (Subtarget.hasV5TEOps()) {
1068 MIB = BuildMI(MBB, I, DL, get(ARM::LDRD));
1069 AddDReg(MIB, DestReg, ARM::gsub_0, RegState::DefineNoRead, TRI);
1070 AddDReg(MIB, DestReg, ARM::gsub_1, RegState::DefineNoRead, TRI);
1071 MIB.addFrameIndex(FI).addReg(0).addImm(0).addMemOperand(MMO);
1073 AddDefaultPred(MIB);
1075 // Fallback to LDM instruction, which has existed since the dawn of
1077 MIB = AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::LDMIA))
1078 .addFrameIndex(FI).addMemOperand(MMO));
1079 MIB = AddDReg(MIB, DestReg, ARM::gsub_0, RegState::DefineNoRead, TRI);
1080 MIB = AddDReg(MIB, DestReg, ARM::gsub_1, RegState::DefineNoRead, TRI);
1083 if (TargetRegisterInfo::isPhysicalRegister(DestReg))
1084 MIB.addReg(DestReg, RegState::ImplicitDefine);
1086 llvm_unreachable("Unknown reg class!");
1089 if (ARM::DPairRegClass.hasSubClassEq(RC)) {
1090 if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) {
1091 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLD1q64), DestReg)
1092 .addFrameIndex(FI).addImm(16)
1093 .addMemOperand(MMO));
1095 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDMQIA), DestReg)
1097 .addMemOperand(MMO));
1100 llvm_unreachable("Unknown reg class!");
1103 if (ARM::DTripleRegClass.hasSubClassEq(RC)) {
1104 if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) {
1105 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLD1d64TPseudo), DestReg)
1106 .addFrameIndex(FI).addImm(16)
1107 .addMemOperand(MMO));
1109 MachineInstrBuilder MIB =
1110 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDMDIA))
1112 .addMemOperand(MMO));
1113 MIB = AddDReg(MIB, DestReg, ARM::dsub_0, RegState::DefineNoRead, TRI);
1114 MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::DefineNoRead, TRI);
1115 MIB = AddDReg(MIB, DestReg, ARM::dsub_2, RegState::DefineNoRead, TRI);
1116 if (TargetRegisterInfo::isPhysicalRegister(DestReg))
1117 MIB.addReg(DestReg, RegState::ImplicitDefine);
1120 llvm_unreachable("Unknown reg class!");
1123 if (ARM::QQPRRegClass.hasSubClassEq(RC) || ARM::DQuadRegClass.hasSubClassEq(RC)) {
1124 if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) {
1125 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLD1d64QPseudo), DestReg)
1126 .addFrameIndex(FI).addImm(16)
1127 .addMemOperand(MMO));
1129 MachineInstrBuilder MIB =
1130 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDMDIA))
1132 .addMemOperand(MMO);
1133 MIB = AddDReg(MIB, DestReg, ARM::dsub_0, RegState::DefineNoRead, TRI);
1134 MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::DefineNoRead, TRI);
1135 MIB = AddDReg(MIB, DestReg, ARM::dsub_2, RegState::DefineNoRead, TRI);
1136 MIB = AddDReg(MIB, DestReg, ARM::dsub_3, RegState::DefineNoRead, TRI);
1137 if (TargetRegisterInfo::isPhysicalRegister(DestReg))
1138 MIB.addReg(DestReg, RegState::ImplicitDefine);
1141 llvm_unreachable("Unknown reg class!");
1144 if (ARM::QQQQPRRegClass.hasSubClassEq(RC)) {
1145 MachineInstrBuilder MIB =
1146 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDMDIA))
1148 .addMemOperand(MMO);
1149 MIB = AddDReg(MIB, DestReg, ARM::dsub_0, RegState::DefineNoRead, TRI);
1150 MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::DefineNoRead, TRI);
1151 MIB = AddDReg(MIB, DestReg, ARM::dsub_2, RegState::DefineNoRead, TRI);
1152 MIB = AddDReg(MIB, DestReg, ARM::dsub_3, RegState::DefineNoRead, TRI);
1153 MIB = AddDReg(MIB, DestReg, ARM::dsub_4, RegState::DefineNoRead, TRI);
1154 MIB = AddDReg(MIB, DestReg, ARM::dsub_5, RegState::DefineNoRead, TRI);
1155 MIB = AddDReg(MIB, DestReg, ARM::dsub_6, RegState::DefineNoRead, TRI);
1156 MIB = AddDReg(MIB, DestReg, ARM::dsub_7, RegState::DefineNoRead, TRI);
1157 if (TargetRegisterInfo::isPhysicalRegister(DestReg))
1158 MIB.addReg(DestReg, RegState::ImplicitDefine);
1160 llvm_unreachable("Unknown reg class!");
1163 llvm_unreachable("Unknown regclass!");
1168 ARMBaseInstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
1169 int &FrameIndex) const {
1170 switch (MI->getOpcode()) {
1173 case ARM::t2LDRs: // FIXME: don't use t2LDRs to access frame.
1174 if (MI->getOperand(1).isFI() &&
1175 MI->getOperand(2).isReg() &&
1176 MI->getOperand(3).isImm() &&
1177 MI->getOperand(2).getReg() == 0 &&
1178 MI->getOperand(3).getImm() == 0) {
1179 FrameIndex = MI->getOperand(1).getIndex();
1180 return MI->getOperand(0).getReg();
1188 if (MI->getOperand(1).isFI() &&
1189 MI->getOperand(2).isImm() &&
1190 MI->getOperand(2).getImm() == 0) {
1191 FrameIndex = MI->getOperand(1).getIndex();
1192 return MI->getOperand(0).getReg();
1196 case ARM::VLD1d64TPseudo:
1197 case ARM::VLD1d64QPseudo:
1198 if (MI->getOperand(1).isFI() &&
1199 MI->getOperand(0).getSubReg() == 0) {
1200 FrameIndex = MI->getOperand(1).getIndex();
1201 return MI->getOperand(0).getReg();
1205 if (MI->getOperand(1).isFI() &&
1206 MI->getOperand(0).getSubReg() == 0) {
1207 FrameIndex = MI->getOperand(1).getIndex();
1208 return MI->getOperand(0).getReg();
1216 unsigned ARMBaseInstrInfo::isLoadFromStackSlotPostFE(const MachineInstr *MI,
1217 int &FrameIndex) const {
1218 const MachineMemOperand *Dummy;
1219 return MI->mayLoad() && hasLoadFromStackSlot(MI, Dummy, FrameIndex);
1223 ARMBaseInstrInfo::expandPostRAPseudo(MachineBasicBlock::iterator MI) const {
1224 MachineFunction &MF = *MI->getParent()->getParent();
1225 Reloc::Model RM = MF.getTarget().getRelocationModel();
1227 if (MI->getOpcode() == TargetOpcode::LOAD_STACK_GUARD) {
1228 assert(getSubtarget().getTargetTriple().isOSBinFormatMachO() &&
1229 "LOAD_STACK_GUARD currently supported only for MachO.");
1230 expandLoadStackGuard(MI, RM);
1231 MI->getParent()->erase(MI);
1235 // This hook gets to expand COPY instructions before they become
1236 // copyPhysReg() calls. Look for VMOVS instructions that can legally be
1237 // widened to VMOVD. We prefer the VMOVD when possible because it may be
1238 // changed into a VORR that can go down the NEON pipeline.
1239 if (!WidenVMOVS || !MI->isCopy() || Subtarget.isCortexA15() ||
1240 Subtarget.isFPOnlySP())
1243 // Look for a copy between even S-registers. That is where we keep floats
1244 // when using NEON v2f32 instructions for f32 arithmetic.
1245 unsigned DstRegS = MI->getOperand(0).getReg();
1246 unsigned SrcRegS = MI->getOperand(1).getReg();
1247 if (!ARM::SPRRegClass.contains(DstRegS, SrcRegS))
1250 const TargetRegisterInfo *TRI = &getRegisterInfo();
1251 unsigned DstRegD = TRI->getMatchingSuperReg(DstRegS, ARM::ssub_0,
1253 unsigned SrcRegD = TRI->getMatchingSuperReg(SrcRegS, ARM::ssub_0,
1255 if (!DstRegD || !SrcRegD)
1258 // We want to widen this into a DstRegD = VMOVD SrcRegD copy. This is only
1259 // legal if the COPY already defines the full DstRegD, and it isn't a
1260 // sub-register insertion.
1261 if (!MI->definesRegister(DstRegD, TRI) || MI->readsRegister(DstRegD, TRI))
1264 // A dead copy shouldn't show up here, but reject it just in case.
1265 if (MI->getOperand(0).isDead())
1268 // All clear, widen the COPY.
1269 DEBUG(dbgs() << "widening: " << *MI);
1270 MachineInstrBuilder MIB(*MI->getParent()->getParent(), MI);
1272 // Get rid of the old <imp-def> of DstRegD. Leave it if it defines a Q-reg
1273 // or some other super-register.
1274 int ImpDefIdx = MI->findRegisterDefOperandIdx(DstRegD);
1275 if (ImpDefIdx != -1)
1276 MI->RemoveOperand(ImpDefIdx);
1278 // Change the opcode and operands.
1279 MI->setDesc(get(ARM::VMOVD));
1280 MI->getOperand(0).setReg(DstRegD);
1281 MI->getOperand(1).setReg(SrcRegD);
1282 AddDefaultPred(MIB);
1284 // We are now reading SrcRegD instead of SrcRegS. This may upset the
1285 // register scavenger and machine verifier, so we need to indicate that we
1286 // are reading an undefined value from SrcRegD, but a proper value from
1288 MI->getOperand(1).setIsUndef();
1289 MIB.addReg(SrcRegS, RegState::Implicit);
1291 // SrcRegD may actually contain an unrelated value in the ssub_1
1292 // sub-register. Don't kill it. Only kill the ssub_0 sub-register.
1293 if (MI->getOperand(1).isKill()) {
1294 MI->getOperand(1).setIsKill(false);
1295 MI->addRegisterKilled(SrcRegS, TRI, true);
1298 DEBUG(dbgs() << "replaced by: " << *MI);
1302 /// Create a copy of a const pool value. Update CPI to the new index and return
1304 static unsigned duplicateCPV(MachineFunction &MF, unsigned &CPI) {
1305 MachineConstantPool *MCP = MF.getConstantPool();
1306 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1308 const MachineConstantPoolEntry &MCPE = MCP->getConstants()[CPI];
1309 assert(MCPE.isMachineConstantPoolEntry() &&
1310 "Expecting a machine constantpool entry!");
1311 ARMConstantPoolValue *ACPV =
1312 static_cast<ARMConstantPoolValue*>(MCPE.Val.MachineCPVal);
1314 unsigned PCLabelId = AFI->createPICLabelUId();
1315 ARMConstantPoolValue *NewCPV = nullptr;
1317 // FIXME: The below assumes PIC relocation model and that the function
1318 // is Thumb mode (t1 or t2). PCAdjustment would be 8 for ARM mode PIC, and
1319 // zero for non-PIC in ARM or Thumb. The callers are all of thumb LDR
1320 // instructions, so that's probably OK, but is PIC always correct when
1322 if (ACPV->isGlobalValue())
1323 NewCPV = ARMConstantPoolConstant::
1324 Create(cast<ARMConstantPoolConstant>(ACPV)->getGV(), PCLabelId,
1326 else if (ACPV->isExtSymbol())
1327 NewCPV = ARMConstantPoolSymbol::
1328 Create(MF.getFunction()->getContext(),
1329 cast<ARMConstantPoolSymbol>(ACPV)->getSymbol(), PCLabelId, 4);
1330 else if (ACPV->isBlockAddress())
1331 NewCPV = ARMConstantPoolConstant::
1332 Create(cast<ARMConstantPoolConstant>(ACPV)->getBlockAddress(), PCLabelId,
1333 ARMCP::CPBlockAddress, 4);
1334 else if (ACPV->isLSDA())
1335 NewCPV = ARMConstantPoolConstant::Create(MF.getFunction(), PCLabelId,
1337 else if (ACPV->isMachineBasicBlock())
1338 NewCPV = ARMConstantPoolMBB::
1339 Create(MF.getFunction()->getContext(),
1340 cast<ARMConstantPoolMBB>(ACPV)->getMBB(), PCLabelId, 4);
1342 llvm_unreachable("Unexpected ARM constantpool value type!!");
1343 CPI = MCP->getConstantPoolIndex(NewCPV, MCPE.getAlignment());
1347 void ARMBaseInstrInfo::
1348 reMaterialize(MachineBasicBlock &MBB,
1349 MachineBasicBlock::iterator I,
1350 unsigned DestReg, unsigned SubIdx,
1351 const MachineInstr *Orig,
1352 const TargetRegisterInfo &TRI) const {
1353 unsigned Opcode = Orig->getOpcode();
1356 MachineInstr *MI = MBB.getParent()->CloneMachineInstr(Orig);
1357 MI->substituteRegister(Orig->getOperand(0).getReg(), DestReg, SubIdx, TRI);
1361 case ARM::tLDRpci_pic:
1362 case ARM::t2LDRpci_pic: {
1363 MachineFunction &MF = *MBB.getParent();
1364 unsigned CPI = Orig->getOperand(1).getIndex();
1365 unsigned PCLabelId = duplicateCPV(MF, CPI);
1366 MachineInstrBuilder MIB = BuildMI(MBB, I, Orig->getDebugLoc(), get(Opcode),
1368 .addConstantPoolIndex(CPI).addImm(PCLabelId);
1369 MIB->setMemRefs(Orig->memoperands_begin(), Orig->memoperands_end());
1376 ARMBaseInstrInfo::duplicate(MachineInstr *Orig, MachineFunction &MF) const {
1377 MachineInstr *MI = TargetInstrInfo::duplicate(Orig, MF);
1378 switch(Orig->getOpcode()) {
1379 case ARM::tLDRpci_pic:
1380 case ARM::t2LDRpci_pic: {
1381 unsigned CPI = Orig->getOperand(1).getIndex();
1382 unsigned PCLabelId = duplicateCPV(MF, CPI);
1383 Orig->getOperand(1).setIndex(CPI);
1384 Orig->getOperand(2).setImm(PCLabelId);
1391 bool ARMBaseInstrInfo::produceSameValue(const MachineInstr *MI0,
1392 const MachineInstr *MI1,
1393 const MachineRegisterInfo *MRI) const {
1394 unsigned Opcode = MI0->getOpcode();
1395 if (Opcode == ARM::t2LDRpci ||
1396 Opcode == ARM::t2LDRpci_pic ||
1397 Opcode == ARM::tLDRpci ||
1398 Opcode == ARM::tLDRpci_pic ||
1399 Opcode == ARM::LDRLIT_ga_pcrel ||
1400 Opcode == ARM::LDRLIT_ga_pcrel_ldr ||
1401 Opcode == ARM::tLDRLIT_ga_pcrel ||
1402 Opcode == ARM::MOV_ga_pcrel ||
1403 Opcode == ARM::MOV_ga_pcrel_ldr ||
1404 Opcode == ARM::t2MOV_ga_pcrel) {
1405 if (MI1->getOpcode() != Opcode)
1407 if (MI0->getNumOperands() != MI1->getNumOperands())
1410 const MachineOperand &MO0 = MI0->getOperand(1);
1411 const MachineOperand &MO1 = MI1->getOperand(1);
1412 if (MO0.getOffset() != MO1.getOffset())
1415 if (Opcode == ARM::LDRLIT_ga_pcrel ||
1416 Opcode == ARM::LDRLIT_ga_pcrel_ldr ||
1417 Opcode == ARM::tLDRLIT_ga_pcrel ||
1418 Opcode == ARM::MOV_ga_pcrel ||
1419 Opcode == ARM::MOV_ga_pcrel_ldr ||
1420 Opcode == ARM::t2MOV_ga_pcrel)
1421 // Ignore the PC labels.
1422 return MO0.getGlobal() == MO1.getGlobal();
1424 const MachineFunction *MF = MI0->getParent()->getParent();
1425 const MachineConstantPool *MCP = MF->getConstantPool();
1426 int CPI0 = MO0.getIndex();
1427 int CPI1 = MO1.getIndex();
1428 const MachineConstantPoolEntry &MCPE0 = MCP->getConstants()[CPI0];
1429 const MachineConstantPoolEntry &MCPE1 = MCP->getConstants()[CPI1];
1430 bool isARMCP0 = MCPE0.isMachineConstantPoolEntry();
1431 bool isARMCP1 = MCPE1.isMachineConstantPoolEntry();
1432 if (isARMCP0 && isARMCP1) {
1433 ARMConstantPoolValue *ACPV0 =
1434 static_cast<ARMConstantPoolValue*>(MCPE0.Val.MachineCPVal);
1435 ARMConstantPoolValue *ACPV1 =
1436 static_cast<ARMConstantPoolValue*>(MCPE1.Val.MachineCPVal);
1437 return ACPV0->hasSameValue(ACPV1);
1438 } else if (!isARMCP0 && !isARMCP1) {
1439 return MCPE0.Val.ConstVal == MCPE1.Val.ConstVal;
1442 } else if (Opcode == ARM::PICLDR) {
1443 if (MI1->getOpcode() != Opcode)
1445 if (MI0->getNumOperands() != MI1->getNumOperands())
1448 unsigned Addr0 = MI0->getOperand(1).getReg();
1449 unsigned Addr1 = MI1->getOperand(1).getReg();
1450 if (Addr0 != Addr1) {
1452 !TargetRegisterInfo::isVirtualRegister(Addr0) ||
1453 !TargetRegisterInfo::isVirtualRegister(Addr1))
1456 // This assumes SSA form.
1457 MachineInstr *Def0 = MRI->getVRegDef(Addr0);
1458 MachineInstr *Def1 = MRI->getVRegDef(Addr1);
1459 // Check if the loaded value, e.g. a constantpool of a global address, are
1461 if (!produceSameValue(Def0, Def1, MRI))
1465 for (unsigned i = 3, e = MI0->getNumOperands(); i != e; ++i) {
1466 // %vreg12<def> = PICLDR %vreg11, 0, pred:14, pred:%noreg
1467 const MachineOperand &MO0 = MI0->getOperand(i);
1468 const MachineOperand &MO1 = MI1->getOperand(i);
1469 if (!MO0.isIdenticalTo(MO1))
1475 return MI0->isIdenticalTo(MI1, MachineInstr::IgnoreVRegDefs);
1478 /// areLoadsFromSameBasePtr - This is used by the pre-regalloc scheduler to
1479 /// determine if two loads are loading from the same base address. It should
1480 /// only return true if the base pointers are the same and the only differences
1481 /// between the two addresses is the offset. It also returns the offsets by
1484 /// FIXME: remove this in favor of the MachineInstr interface once pre-RA-sched
1485 /// is permanently disabled.
1486 bool ARMBaseInstrInfo::areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2,
1488 int64_t &Offset2) const {
1489 // Don't worry about Thumb: just ARM and Thumb2.
1490 if (Subtarget.isThumb1Only()) return false;
1492 if (!Load1->isMachineOpcode() || !Load2->isMachineOpcode())
1495 switch (Load1->getMachineOpcode()) {
1509 case ARM::t2LDRSHi8:
1511 case ARM::t2LDRBi12:
1512 case ARM::t2LDRSHi12:
1516 switch (Load2->getMachineOpcode()) {
1529 case ARM::t2LDRSHi8:
1531 case ARM::t2LDRBi12:
1532 case ARM::t2LDRSHi12:
1536 // Check if base addresses and chain operands match.
1537 if (Load1->getOperand(0) != Load2->getOperand(0) ||
1538 Load1->getOperand(4) != Load2->getOperand(4))
1541 // Index should be Reg0.
1542 if (Load1->getOperand(3) != Load2->getOperand(3))
1545 // Determine the offsets.
1546 if (isa<ConstantSDNode>(Load1->getOperand(1)) &&
1547 isa<ConstantSDNode>(Load2->getOperand(1))) {
1548 Offset1 = cast<ConstantSDNode>(Load1->getOperand(1))->getSExtValue();
1549 Offset2 = cast<ConstantSDNode>(Load2->getOperand(1))->getSExtValue();
1556 /// shouldScheduleLoadsNear - This is a used by the pre-regalloc scheduler to
1557 /// determine (in conjunction with areLoadsFromSameBasePtr) if two loads should
1558 /// be scheduled togther. On some targets if two loads are loading from
1559 /// addresses in the same cache line, it's better if they are scheduled
1560 /// together. This function takes two integers that represent the load offsets
1561 /// from the common base address. It returns true if it decides it's desirable
1562 /// to schedule the two loads together. "NumLoads" is the number of loads that
1563 /// have already been scheduled after Load1.
1565 /// FIXME: remove this in favor of the MachineInstr interface once pre-RA-sched
1566 /// is permanently disabled.
1567 bool ARMBaseInstrInfo::shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,
1568 int64_t Offset1, int64_t Offset2,
1569 unsigned NumLoads) const {
1570 // Don't worry about Thumb: just ARM and Thumb2.
1571 if (Subtarget.isThumb1Only()) return false;
1573 assert(Offset2 > Offset1);
1575 if ((Offset2 - Offset1) / 8 > 64)
1578 // Check if the machine opcodes are different. If they are different
1579 // then we consider them to not be of the same base address,
1580 // EXCEPT in the case of Thumb2 byte loads where one is LDRBi8 and the other LDRBi12.
1581 // In this case, they are considered to be the same because they are different
1582 // encoding forms of the same basic instruction.
1583 if ((Load1->getMachineOpcode() != Load2->getMachineOpcode()) &&
1584 !((Load1->getMachineOpcode() == ARM::t2LDRBi8 &&
1585 Load2->getMachineOpcode() == ARM::t2LDRBi12) ||
1586 (Load1->getMachineOpcode() == ARM::t2LDRBi12 &&
1587 Load2->getMachineOpcode() == ARM::t2LDRBi8)))
1588 return false; // FIXME: overly conservative?
1590 // Four loads in a row should be sufficient.
1597 bool ARMBaseInstrInfo::isSchedulingBoundary(const MachineInstr *MI,
1598 const MachineBasicBlock *MBB,
1599 const MachineFunction &MF) const {
1600 // Debug info is never a scheduling boundary. It's necessary to be explicit
1601 // due to the special treatment of IT instructions below, otherwise a
1602 // dbg_value followed by an IT will result in the IT instruction being
1603 // considered a scheduling hazard, which is wrong. It should be the actual
1604 // instruction preceding the dbg_value instruction(s), just like it is
1605 // when debug info is not present.
1606 if (MI->isDebugValue())
1609 // Terminators and labels can't be scheduled around.
1610 if (MI->isTerminator() || MI->isPosition())
1613 // Treat the start of the IT block as a scheduling boundary, but schedule
1614 // t2IT along with all instructions following it.
1615 // FIXME: This is a big hammer. But the alternative is to add all potential
1616 // true and anti dependencies to IT block instructions as implicit operands
1617 // to the t2IT instruction. The added compile time and complexity does not
1619 MachineBasicBlock::const_iterator I = MI;
1620 // Make sure to skip any dbg_value instructions
1621 while (++I != MBB->end() && I->isDebugValue())
1623 if (I != MBB->end() && I->getOpcode() == ARM::t2IT)
1626 // Don't attempt to schedule around any instruction that defines
1627 // a stack-oriented pointer, as it's unlikely to be profitable. This
1628 // saves compile time, because it doesn't require every single
1629 // stack slot reference to depend on the instruction that does the
1631 // Calls don't actually change the stack pointer, even if they have imp-defs.
1632 // No ARM calling conventions change the stack pointer. (X86 calling
1633 // conventions sometimes do).
1634 if (!MI->isCall() && MI->definesRegister(ARM::SP))
1640 bool ARMBaseInstrInfo::
1641 isProfitableToIfCvt(MachineBasicBlock &MBB,
1642 unsigned NumCycles, unsigned ExtraPredCycles,
1643 BranchProbability Probability) const {
1647 // If we are optimizing for size, see if the branch in the predecessor can be
1648 // lowered to cbn?z by the constant island lowering pass, and return false if
1649 // so. This results in a shorter instruction sequence.
1650 if (MBB.getParent()->getFunction()->optForSize()) {
1651 MachineBasicBlock *Pred = *MBB.pred_begin();
1652 if (!Pred->empty()) {
1653 MachineInstr *LastMI = &*Pred->rbegin();
1654 if (LastMI->getOpcode() == ARM::t2Bcc) {
1655 MachineBasicBlock::iterator CmpMI = LastMI;
1656 if (CmpMI != Pred->begin()) {
1658 if (CmpMI->getOpcode() == ARM::tCMPi8 ||
1659 CmpMI->getOpcode() == ARM::t2CMPri) {
1660 unsigned Reg = CmpMI->getOperand(0).getReg();
1661 unsigned PredReg = 0;
1662 ARMCC::CondCodes P = getInstrPredicate(CmpMI, PredReg);
1663 if (P == ARMCC::AL && CmpMI->getOperand(1).getImm() == 0 &&
1664 isARMLowRegister(Reg))
1672 // Attempt to estimate the relative costs of predication versus branching.
1673 // Here we scale up each component of UnpredCost to avoid precision issue when
1674 // scaling NumCycles by Probability.
1675 const unsigned ScalingUpFactor = 1024;
1676 unsigned UnpredCost = Probability.scale(NumCycles * ScalingUpFactor);
1677 UnpredCost += ScalingUpFactor; // The branch itself
1678 UnpredCost += Subtarget.getMispredictionPenalty() * ScalingUpFactor / 10;
1680 return (NumCycles + ExtraPredCycles) * ScalingUpFactor <= UnpredCost;
1683 bool ARMBaseInstrInfo::
1684 isProfitableToIfCvt(MachineBasicBlock &TMBB,
1685 unsigned TCycles, unsigned TExtra,
1686 MachineBasicBlock &FMBB,
1687 unsigned FCycles, unsigned FExtra,
1688 BranchProbability Probability) const {
1689 if (!TCycles || !FCycles)
1692 // Attempt to estimate the relative costs of predication versus branching.
1693 // Here we scale up each component of UnpredCost to avoid precision issue when
1694 // scaling TCycles/FCycles by Probability.
1695 const unsigned ScalingUpFactor = 1024;
1696 unsigned TUnpredCost = Probability.scale(TCycles * ScalingUpFactor);
1697 unsigned FUnpredCost =
1698 Probability.getCompl().scale(FCycles * ScalingUpFactor);
1699 unsigned UnpredCost = TUnpredCost + FUnpredCost;
1700 UnpredCost += 1 * ScalingUpFactor; // The branch itself
1701 UnpredCost += Subtarget.getMispredictionPenalty() * ScalingUpFactor / 10;
1703 return (TCycles + FCycles + TExtra + FExtra) * ScalingUpFactor <= UnpredCost;
1707 ARMBaseInstrInfo::isProfitableToUnpredicate(MachineBasicBlock &TMBB,
1708 MachineBasicBlock &FMBB) const {
1709 // Reduce false anti-dependencies to let Swift's out-of-order execution
1710 // engine do its thing.
1711 return Subtarget.isSwift();
1714 /// getInstrPredicate - If instruction is predicated, returns its predicate
1715 /// condition, otherwise returns AL. It also returns the condition code
1716 /// register by reference.
1718 llvm::getInstrPredicate(const MachineInstr *MI, unsigned &PredReg) {
1719 int PIdx = MI->findFirstPredOperandIdx();
1725 PredReg = MI->getOperand(PIdx+1).getReg();
1726 return (ARMCC::CondCodes)MI->getOperand(PIdx).getImm();
1730 unsigned llvm::getMatchingCondBranchOpcode(unsigned Opc) {
1735 if (Opc == ARM::t2B)
1738 llvm_unreachable("Unknown unconditional branch opcode!");
1741 MachineInstr *ARMBaseInstrInfo::commuteInstructionImpl(MachineInstr *MI,
1744 unsigned OpIdx2) const {
1745 switch (MI->getOpcode()) {
1747 case ARM::t2MOVCCr: {
1748 // MOVCC can be commuted by inverting the condition.
1749 unsigned PredReg = 0;
1750 ARMCC::CondCodes CC = getInstrPredicate(MI, PredReg);
1751 // MOVCC AL can't be inverted. Shouldn't happen.
1752 if (CC == ARMCC::AL || PredReg != ARM::CPSR)
1754 MI = TargetInstrInfo::commuteInstructionImpl(MI, NewMI, OpIdx1, OpIdx2);
1757 // After swapping the MOVCC operands, also invert the condition.
1758 MI->getOperand(MI->findFirstPredOperandIdx())
1759 .setImm(ARMCC::getOppositeCondition(CC));
1763 return TargetInstrInfo::commuteInstructionImpl(MI, NewMI, OpIdx1, OpIdx2);
1766 /// Identify instructions that can be folded into a MOVCC instruction, and
1767 /// return the defining instruction.
1768 static MachineInstr *canFoldIntoMOVCC(unsigned Reg,
1769 const MachineRegisterInfo &MRI,
1770 const TargetInstrInfo *TII) {
1771 if (!TargetRegisterInfo::isVirtualRegister(Reg))
1773 if (!MRI.hasOneNonDBGUse(Reg))
1775 MachineInstr *MI = MRI.getVRegDef(Reg);
1778 // MI is folded into the MOVCC by predicating it.
1779 if (!MI->isPredicable())
1781 // Check if MI has any non-dead defs or physreg uses. This also detects
1782 // predicated instructions which will be reading CPSR.
1783 for (unsigned i = 1, e = MI->getNumOperands(); i != e; ++i) {
1784 const MachineOperand &MO = MI->getOperand(i);
1785 // Reject frame index operands, PEI can't handle the predicated pseudos.
1786 if (MO.isFI() || MO.isCPI() || MO.isJTI())
1790 // MI can't have any tied operands, that would conflict with predication.
1793 if (TargetRegisterInfo::isPhysicalRegister(MO.getReg()))
1795 if (MO.isDef() && !MO.isDead())
1798 bool DontMoveAcrossStores = true;
1799 if (!MI->isSafeToMove(/* AliasAnalysis = */ nullptr, DontMoveAcrossStores))
1804 bool ARMBaseInstrInfo::analyzeSelect(const MachineInstr *MI,
1805 SmallVectorImpl<MachineOperand> &Cond,
1806 unsigned &TrueOp, unsigned &FalseOp,
1807 bool &Optimizable) const {
1808 assert((MI->getOpcode() == ARM::MOVCCr || MI->getOpcode() == ARM::t2MOVCCr) &&
1809 "Unknown select instruction");
1814 // 3: Condition code.
1818 Cond.push_back(MI->getOperand(3));
1819 Cond.push_back(MI->getOperand(4));
1820 // We can always fold a def.
1826 ARMBaseInstrInfo::optimizeSelect(MachineInstr *MI,
1827 SmallPtrSetImpl<MachineInstr *> &SeenMIs,
1828 bool PreferFalse) const {
1829 assert((MI->getOpcode() == ARM::MOVCCr || MI->getOpcode() == ARM::t2MOVCCr) &&
1830 "Unknown select instruction");
1831 MachineRegisterInfo &MRI = MI->getParent()->getParent()->getRegInfo();
1832 MachineInstr *DefMI = canFoldIntoMOVCC(MI->getOperand(2).getReg(), MRI, this);
1833 bool Invert = !DefMI;
1835 DefMI = canFoldIntoMOVCC(MI->getOperand(1).getReg(), MRI, this);
1839 // Find new register class to use.
1840 MachineOperand FalseReg = MI->getOperand(Invert ? 2 : 1);
1841 unsigned DestReg = MI->getOperand(0).getReg();
1842 const TargetRegisterClass *PreviousClass = MRI.getRegClass(FalseReg.getReg());
1843 if (!MRI.constrainRegClass(DestReg, PreviousClass))
1846 // Create a new predicated version of DefMI.
1847 // Rfalse is the first use.
1848 MachineInstrBuilder NewMI = BuildMI(*MI->getParent(), MI, MI->getDebugLoc(),
1849 DefMI->getDesc(), DestReg);
1851 // Copy all the DefMI operands, excluding its (null) predicate.
1852 const MCInstrDesc &DefDesc = DefMI->getDesc();
1853 for (unsigned i = 1, e = DefDesc.getNumOperands();
1854 i != e && !DefDesc.OpInfo[i].isPredicate(); ++i)
1855 NewMI.addOperand(DefMI->getOperand(i));
1857 unsigned CondCode = MI->getOperand(3).getImm();
1859 NewMI.addImm(ARMCC::getOppositeCondition(ARMCC::CondCodes(CondCode)));
1861 NewMI.addImm(CondCode);
1862 NewMI.addOperand(MI->getOperand(4));
1864 // DefMI is not the -S version that sets CPSR, so add an optional %noreg.
1865 if (NewMI->hasOptionalDef())
1866 AddDefaultCC(NewMI);
1868 // The output register value when the predicate is false is an implicit
1869 // register operand tied to the first def.
1870 // The tie makes the register allocator ensure the FalseReg is allocated the
1871 // same register as operand 0.
1872 FalseReg.setImplicit();
1873 NewMI.addOperand(FalseReg);
1874 NewMI->tieOperands(0, NewMI->getNumOperands() - 1);
1876 // Update SeenMIs set: register newly created MI and erase removed DefMI.
1877 SeenMIs.insert(NewMI);
1878 SeenMIs.erase(DefMI);
1880 // If MI is inside a loop, and DefMI is outside the loop, then kill flags on
1881 // DefMI would be invalid when tranferred inside the loop. Checking for a
1882 // loop is expensive, but at least remove kill flags if they are in different
1884 if (DefMI->getParent() != MI->getParent())
1885 NewMI->clearKillInfo();
1887 // The caller will erase MI, but not DefMI.
1888 DefMI->eraseFromParent();
1892 /// Map pseudo instructions that imply an 'S' bit onto real opcodes. Whether the
1893 /// instruction is encoded with an 'S' bit is determined by the optional CPSR
1896 /// This will go away once we can teach tblgen how to set the optional CPSR def
1898 struct AddSubFlagsOpcodePair {
1900 uint16_t MachineOpc;
1903 static const AddSubFlagsOpcodePair AddSubFlagsOpcodeMap[] = {
1904 {ARM::ADDSri, ARM::ADDri},
1905 {ARM::ADDSrr, ARM::ADDrr},
1906 {ARM::ADDSrsi, ARM::ADDrsi},
1907 {ARM::ADDSrsr, ARM::ADDrsr},
1909 {ARM::SUBSri, ARM::SUBri},
1910 {ARM::SUBSrr, ARM::SUBrr},
1911 {ARM::SUBSrsi, ARM::SUBrsi},
1912 {ARM::SUBSrsr, ARM::SUBrsr},
1914 {ARM::RSBSri, ARM::RSBri},
1915 {ARM::RSBSrsi, ARM::RSBrsi},
1916 {ARM::RSBSrsr, ARM::RSBrsr},
1918 {ARM::t2ADDSri, ARM::t2ADDri},
1919 {ARM::t2ADDSrr, ARM::t2ADDrr},
1920 {ARM::t2ADDSrs, ARM::t2ADDrs},
1922 {ARM::t2SUBSri, ARM::t2SUBri},
1923 {ARM::t2SUBSrr, ARM::t2SUBrr},
1924 {ARM::t2SUBSrs, ARM::t2SUBrs},
1926 {ARM::t2RSBSri, ARM::t2RSBri},
1927 {ARM::t2RSBSrs, ARM::t2RSBrs},
1930 unsigned llvm::convertAddSubFlagsOpcode(unsigned OldOpc) {
1931 for (unsigned i = 0, e = array_lengthof(AddSubFlagsOpcodeMap); i != e; ++i)
1932 if (OldOpc == AddSubFlagsOpcodeMap[i].PseudoOpc)
1933 return AddSubFlagsOpcodeMap[i].MachineOpc;
1937 void llvm::emitARMRegPlusImmediate(MachineBasicBlock &MBB,
1938 MachineBasicBlock::iterator &MBBI, DebugLoc dl,
1939 unsigned DestReg, unsigned BaseReg, int NumBytes,
1940 ARMCC::CondCodes Pred, unsigned PredReg,
1941 const ARMBaseInstrInfo &TII, unsigned MIFlags) {
1942 if (NumBytes == 0 && DestReg != BaseReg) {
1943 BuildMI(MBB, MBBI, dl, TII.get(ARM::MOVr), DestReg)
1944 .addReg(BaseReg, RegState::Kill)
1945 .addImm((unsigned)Pred).addReg(PredReg).addReg(0)
1946 .setMIFlags(MIFlags);
1950 bool isSub = NumBytes < 0;
1951 if (isSub) NumBytes = -NumBytes;
1954 unsigned RotAmt = ARM_AM::getSOImmValRotate(NumBytes);
1955 unsigned ThisVal = NumBytes & ARM_AM::rotr32(0xFF, RotAmt);
1956 assert(ThisVal && "Didn't extract field correctly");
1958 // We will handle these bits from offset, clear them.
1959 NumBytes &= ~ThisVal;
1961 assert(ARM_AM::getSOImmVal(ThisVal) != -1 && "Bit extraction didn't work?");
1963 // Build the new ADD / SUB.
1964 unsigned Opc = isSub ? ARM::SUBri : ARM::ADDri;
1965 BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg)
1966 .addReg(BaseReg, RegState::Kill).addImm(ThisVal)
1967 .addImm((unsigned)Pred).addReg(PredReg).addReg(0)
1968 .setMIFlags(MIFlags);
1973 static bool isAnySubRegLive(unsigned Reg, const TargetRegisterInfo *TRI,
1975 for (MCSubRegIterator Subreg(Reg, TRI, /* IncludeSelf */ true);
1976 Subreg.isValid(); ++Subreg)
1977 if (MI->getParent()->computeRegisterLiveness(TRI, *Subreg, MI) !=
1978 MachineBasicBlock::LQR_Dead)
1982 bool llvm::tryFoldSPUpdateIntoPushPop(const ARMSubtarget &Subtarget,
1983 MachineFunction &MF, MachineInstr *MI,
1984 unsigned NumBytes) {
1985 // This optimisation potentially adds lots of load and store
1986 // micro-operations, it's only really a great benefit to code-size.
1987 if (!MF.getFunction()->optForMinSize())
1990 // If only one register is pushed/popped, LLVM can use an LDR/STR
1991 // instead. We can't modify those so make sure we're dealing with an
1992 // instruction we understand.
1993 bool IsPop = isPopOpcode(MI->getOpcode());
1994 bool IsPush = isPushOpcode(MI->getOpcode());
1995 if (!IsPush && !IsPop)
1998 bool IsVFPPushPop = MI->getOpcode() == ARM::VSTMDDB_UPD ||
1999 MI->getOpcode() == ARM::VLDMDIA_UPD;
2000 bool IsT1PushPop = MI->getOpcode() == ARM::tPUSH ||
2001 MI->getOpcode() == ARM::tPOP ||
2002 MI->getOpcode() == ARM::tPOP_RET;
2004 assert((IsT1PushPop || (MI->getOperand(0).getReg() == ARM::SP &&
2005 MI->getOperand(1).getReg() == ARM::SP)) &&
2006 "trying to fold sp update into non-sp-updating push/pop");
2008 // The VFP push & pop act on D-registers, so we can only fold an adjustment
2009 // by a multiple of 8 bytes in correctly. Similarly rN is 4-bytes. Don't try
2010 // if this is violated.
2011 if (NumBytes % (IsVFPPushPop ? 8 : 4) != 0)
2014 // ARM and Thumb2 push/pop insts have explicit "sp, sp" operands (+
2015 // pred) so the list starts at 4. Thumb1 starts after the predicate.
2016 int RegListIdx = IsT1PushPop ? 2 : 4;
2018 // Calculate the space we'll need in terms of registers.
2019 unsigned FirstReg = MI->getOperand(RegListIdx).getReg();
2020 unsigned RD0Reg, RegsNeeded;
2023 RegsNeeded = NumBytes / 8;
2026 RegsNeeded = NumBytes / 4;
2029 // We're going to have to strip all list operands off before
2030 // re-adding them since the order matters, so save the existing ones
2032 SmallVector<MachineOperand, 4> RegList;
2033 for (int i = MI->getNumOperands() - 1; i >= RegListIdx; --i)
2034 RegList.push_back(MI->getOperand(i));
2036 const TargetRegisterInfo *TRI = MF.getRegInfo().getTargetRegisterInfo();
2037 const MCPhysReg *CSRegs = TRI->getCalleeSavedRegs(&MF);
2039 // Now try to find enough space in the reglist to allocate NumBytes.
2040 for (unsigned CurReg = FirstReg - 1; CurReg >= RD0Reg && RegsNeeded;
2043 // Pushing any register is completely harmless, mark the
2044 // register involved as undef since we don't care about it in
2046 RegList.push_back(MachineOperand::CreateReg(CurReg, false, false,
2047 false, false, true));
2052 // However, we can only pop an extra register if it's not live. For
2053 // registers live within the function we might clobber a return value
2054 // register; the other way a register can be live here is if it's
2056 // TODO: Currently, computeRegisterLiveness() does not report "live" if a
2057 // sub reg is live. When computeRegisterLiveness() works for sub reg, it
2058 // can replace isAnySubRegLive().
2059 if (isCalleeSavedRegister(CurReg, CSRegs) ||
2060 isAnySubRegLive(CurReg, TRI, MI)) {
2061 // VFP pops don't allow holes in the register list, so any skip is fatal
2062 // for our transformation. GPR pops do, so we should just keep looking.
2069 // Mark the unimportant registers as <def,dead> in the POP.
2070 RegList.push_back(MachineOperand::CreateReg(CurReg, true, false, false,
2078 // Finally we know we can profitably perform the optimisation so go
2079 // ahead: strip all existing registers off and add them back again
2080 // in the right order.
2081 for (int i = MI->getNumOperands() - 1; i >= RegListIdx; --i)
2082 MI->RemoveOperand(i);
2084 // Add the complete list back in.
2085 MachineInstrBuilder MIB(MF, &*MI);
2086 for (int i = RegList.size() - 1; i >= 0; --i)
2087 MIB.addOperand(RegList[i]);
2092 bool llvm::rewriteARMFrameIndex(MachineInstr &MI, unsigned FrameRegIdx,
2093 unsigned FrameReg, int &Offset,
2094 const ARMBaseInstrInfo &TII) {
2095 unsigned Opcode = MI.getOpcode();
2096 const MCInstrDesc &Desc = MI.getDesc();
2097 unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
2100 // Memory operands in inline assembly always use AddrMode2.
2101 if (Opcode == ARM::INLINEASM)
2102 AddrMode = ARMII::AddrMode2;
2104 if (Opcode == ARM::ADDri) {
2105 Offset += MI.getOperand(FrameRegIdx+1).getImm();
2107 // Turn it into a move.
2108 MI.setDesc(TII.get(ARM::MOVr));
2109 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
2110 MI.RemoveOperand(FrameRegIdx+1);
2113 } else if (Offset < 0) {
2116 MI.setDesc(TII.get(ARM::SUBri));
2119 // Common case: small offset, fits into instruction.
2120 if (ARM_AM::getSOImmVal(Offset) != -1) {
2121 // Replace the FrameIndex with sp / fp
2122 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
2123 MI.getOperand(FrameRegIdx+1).ChangeToImmediate(Offset);
2128 // Otherwise, pull as much of the immedidate into this ADDri/SUBri
2130 unsigned RotAmt = ARM_AM::getSOImmValRotate(Offset);
2131 unsigned ThisImmVal = Offset & ARM_AM::rotr32(0xFF, RotAmt);
2133 // We will handle these bits from offset, clear them.
2134 Offset &= ~ThisImmVal;
2136 // Get the properly encoded SOImmVal field.
2137 assert(ARM_AM::getSOImmVal(ThisImmVal) != -1 &&
2138 "Bit extraction didn't work?");
2139 MI.getOperand(FrameRegIdx+1).ChangeToImmediate(ThisImmVal);
2141 unsigned ImmIdx = 0;
2143 unsigned NumBits = 0;
2146 case ARMII::AddrMode_i12: {
2147 ImmIdx = FrameRegIdx + 1;
2148 InstrOffs = MI.getOperand(ImmIdx).getImm();
2152 case ARMII::AddrMode2: {
2153 ImmIdx = FrameRegIdx+2;
2154 InstrOffs = ARM_AM::getAM2Offset(MI.getOperand(ImmIdx).getImm());
2155 if (ARM_AM::getAM2Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub)
2160 case ARMII::AddrMode3: {
2161 ImmIdx = FrameRegIdx+2;
2162 InstrOffs = ARM_AM::getAM3Offset(MI.getOperand(ImmIdx).getImm());
2163 if (ARM_AM::getAM3Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub)
2168 case ARMII::AddrMode4:
2169 case ARMII::AddrMode6:
2170 // Can't fold any offset even if it's zero.
2172 case ARMII::AddrMode5: {
2173 ImmIdx = FrameRegIdx+1;
2174 InstrOffs = ARM_AM::getAM5Offset(MI.getOperand(ImmIdx).getImm());
2175 if (ARM_AM::getAM5Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub)
2182 llvm_unreachable("Unsupported addressing mode!");
2185 Offset += InstrOffs * Scale;
2186 assert((Offset & (Scale-1)) == 0 && "Can't encode this offset!");
2192 // Attempt to fold address comp. if opcode has offset bits
2194 // Common case: small offset, fits into instruction.
2195 MachineOperand &ImmOp = MI.getOperand(ImmIdx);
2196 int ImmedOffset = Offset / Scale;
2197 unsigned Mask = (1 << NumBits) - 1;
2198 if ((unsigned)Offset <= Mask * Scale) {
2199 // Replace the FrameIndex with sp
2200 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
2201 // FIXME: When addrmode2 goes away, this will simplify (like the
2202 // T2 version), as the LDR.i12 versions don't need the encoding
2203 // tricks for the offset value.
2205 if (AddrMode == ARMII::AddrMode_i12)
2206 ImmedOffset = -ImmedOffset;
2208 ImmedOffset |= 1 << NumBits;
2210 ImmOp.ChangeToImmediate(ImmedOffset);
2215 // Otherwise, it didn't fit. Pull in what we can to simplify the immed.
2216 ImmedOffset = ImmedOffset & Mask;
2218 if (AddrMode == ARMII::AddrMode_i12)
2219 ImmedOffset = -ImmedOffset;
2221 ImmedOffset |= 1 << NumBits;
2223 ImmOp.ChangeToImmediate(ImmedOffset);
2224 Offset &= ~(Mask*Scale);
2228 Offset = (isSub) ? -Offset : Offset;
2232 /// analyzeCompare - For a comparison instruction, return the source registers
2233 /// in SrcReg and SrcReg2 if having two register operands, and the value it
2234 /// compares against in CmpValue. Return true if the comparison instruction
2235 /// can be analyzed.
2236 bool ARMBaseInstrInfo::
2237 analyzeCompare(const MachineInstr *MI, unsigned &SrcReg, unsigned &SrcReg2,
2238 int &CmpMask, int &CmpValue) const {
2239 switch (MI->getOpcode()) {
2243 SrcReg = MI->getOperand(0).getReg();
2246 CmpValue = MI->getOperand(1).getImm();
2250 SrcReg = MI->getOperand(0).getReg();
2251 SrcReg2 = MI->getOperand(1).getReg();
2257 SrcReg = MI->getOperand(0).getReg();
2259 CmpMask = MI->getOperand(1).getImm();
2267 /// isSuitableForMask - Identify a suitable 'and' instruction that
2268 /// operates on the given source register and applies the same mask
2269 /// as a 'tst' instruction. Provide a limited look-through for copies.
2270 /// When successful, MI will hold the found instruction.
2271 static bool isSuitableForMask(MachineInstr *&MI, unsigned SrcReg,
2272 int CmpMask, bool CommonUse) {
2273 switch (MI->getOpcode()) {
2276 if (CmpMask != MI->getOperand(2).getImm())
2278 if (SrcReg == MI->getOperand(CommonUse ? 1 : 0).getReg())
2286 /// getSwappedCondition - assume the flags are set by MI(a,b), return
2287 /// the condition code if we modify the instructions such that flags are
2289 inline static ARMCC::CondCodes getSwappedCondition(ARMCC::CondCodes CC) {
2291 default: return ARMCC::AL;
2292 case ARMCC::EQ: return ARMCC::EQ;
2293 case ARMCC::NE: return ARMCC::NE;
2294 case ARMCC::HS: return ARMCC::LS;
2295 case ARMCC::LO: return ARMCC::HI;
2296 case ARMCC::HI: return ARMCC::LO;
2297 case ARMCC::LS: return ARMCC::HS;
2298 case ARMCC::GE: return ARMCC::LE;
2299 case ARMCC::LT: return ARMCC::GT;
2300 case ARMCC::GT: return ARMCC::LT;
2301 case ARMCC::LE: return ARMCC::GE;
2305 /// isRedundantFlagInstr - check whether the first instruction, whose only
2306 /// purpose is to update flags, can be made redundant.
2307 /// CMPrr can be made redundant by SUBrr if the operands are the same.
2308 /// CMPri can be made redundant by SUBri if the operands are the same.
2309 /// This function can be extended later on.
2310 inline static bool isRedundantFlagInstr(MachineInstr *CmpI, unsigned SrcReg,
2311 unsigned SrcReg2, int ImmValue,
2313 if ((CmpI->getOpcode() == ARM::CMPrr ||
2314 CmpI->getOpcode() == ARM::t2CMPrr) &&
2315 (OI->getOpcode() == ARM::SUBrr ||
2316 OI->getOpcode() == ARM::t2SUBrr) &&
2317 ((OI->getOperand(1).getReg() == SrcReg &&
2318 OI->getOperand(2).getReg() == SrcReg2) ||
2319 (OI->getOperand(1).getReg() == SrcReg2 &&
2320 OI->getOperand(2).getReg() == SrcReg)))
2323 if ((CmpI->getOpcode() == ARM::CMPri ||
2324 CmpI->getOpcode() == ARM::t2CMPri) &&
2325 (OI->getOpcode() == ARM::SUBri ||
2326 OI->getOpcode() == ARM::t2SUBri) &&
2327 OI->getOperand(1).getReg() == SrcReg &&
2328 OI->getOperand(2).getImm() == ImmValue)
2333 /// optimizeCompareInstr - Convert the instruction supplying the argument to the
2334 /// comparison into one that sets the zero bit in the flags register;
2335 /// Remove a redundant Compare instruction if an earlier instruction can set the
2336 /// flags in the same way as Compare.
2337 /// E.g. SUBrr(r1,r2) and CMPrr(r1,r2). We also handle the case where two
2338 /// operands are swapped: SUBrr(r1,r2) and CMPrr(r2,r1), by updating the
2339 /// condition code of instructions which use the flags.
2340 bool ARMBaseInstrInfo::
2341 optimizeCompareInstr(MachineInstr *CmpInstr, unsigned SrcReg, unsigned SrcReg2,
2342 int CmpMask, int CmpValue,
2343 const MachineRegisterInfo *MRI) const {
2344 // Get the unique definition of SrcReg.
2345 MachineInstr *MI = MRI->getUniqueVRegDef(SrcReg);
2346 if (!MI) return false;
2348 // Masked compares sometimes use the same register as the corresponding 'and'.
2349 if (CmpMask != ~0) {
2350 if (!isSuitableForMask(MI, SrcReg, CmpMask, false) || isPredicated(MI)) {
2352 for (MachineRegisterInfo::use_instr_iterator
2353 UI = MRI->use_instr_begin(SrcReg), UE = MRI->use_instr_end();
2355 if (UI->getParent() != CmpInstr->getParent()) continue;
2356 MachineInstr *PotentialAND = &*UI;
2357 if (!isSuitableForMask(PotentialAND, SrcReg, CmpMask, true) ||
2358 isPredicated(PotentialAND))
2363 if (!MI) return false;
2367 // Get ready to iterate backward from CmpInstr.
2368 MachineBasicBlock::iterator I = CmpInstr, E = MI,
2369 B = CmpInstr->getParent()->begin();
2371 // Early exit if CmpInstr is at the beginning of the BB.
2372 if (I == B) return false;
2374 // There are two possible candidates which can be changed to set CPSR:
2375 // One is MI, the other is a SUB instruction.
2376 // For CMPrr(r1,r2), we are looking for SUB(r1,r2) or SUB(r2,r1).
2377 // For CMPri(r1, CmpValue), we are looking for SUBri(r1, CmpValue).
2378 MachineInstr *Sub = nullptr;
2380 // MI is not a candidate for CMPrr.
2382 else if (MI->getParent() != CmpInstr->getParent() || CmpValue != 0) {
2383 // Conservatively refuse to convert an instruction which isn't in the same
2384 // BB as the comparison.
2385 // For CMPri w/ CmpValue != 0, a Sub may still be a candidate.
2386 // Thus we cannot return here.
2387 if (CmpInstr->getOpcode() == ARM::CMPri ||
2388 CmpInstr->getOpcode() == ARM::t2CMPri)
2394 // Check that CPSR isn't set between the comparison instruction and the one we
2395 // want to change. At the same time, search for Sub.
2396 const TargetRegisterInfo *TRI = &getRegisterInfo();
2398 for (; I != E; --I) {
2399 const MachineInstr &Instr = *I;
2401 if (Instr.modifiesRegister(ARM::CPSR, TRI) ||
2402 Instr.readsRegister(ARM::CPSR, TRI))
2403 // This instruction modifies or uses CPSR after the one we want to
2404 // change. We can't do this transformation.
2407 // Check whether CmpInstr can be made redundant by the current instruction.
2408 if (isRedundantFlagInstr(CmpInstr, SrcReg, SrcReg2, CmpValue, &*I)) {
2414 // The 'and' is below the comparison instruction.
2418 // Return false if no candidates exist.
2422 // The single candidate is called MI.
2425 // We can't use a predicated instruction - it doesn't always write the flags.
2426 if (isPredicated(MI))
2429 switch (MI->getOpcode()) {
2463 case ARM::t2EORri: {
2464 // Scan forward for the use of CPSR
2465 // When checking against MI: if it's a conditional code that requires
2466 // checking of the V bit or C bit, then this is not safe to do.
2467 // It is safe to remove CmpInstr if CPSR is redefined or killed.
2468 // If we are done with the basic block, we need to check whether CPSR is
2470 SmallVector<std::pair<MachineOperand*, ARMCC::CondCodes>, 4>
2472 bool isSafe = false;
2474 E = CmpInstr->getParent()->end();
2475 while (!isSafe && ++I != E) {
2476 const MachineInstr &Instr = *I;
2477 for (unsigned IO = 0, EO = Instr.getNumOperands();
2478 !isSafe && IO != EO; ++IO) {
2479 const MachineOperand &MO = Instr.getOperand(IO);
2480 if (MO.isRegMask() && MO.clobbersPhysReg(ARM::CPSR)) {
2484 if (!MO.isReg() || MO.getReg() != ARM::CPSR)
2490 // Condition code is after the operand before CPSR except for VSELs.
2491 ARMCC::CondCodes CC;
2492 bool IsInstrVSel = true;
2493 switch (Instr.getOpcode()) {
2495 IsInstrVSel = false;
2496 CC = (ARMCC::CondCodes)Instr.getOperand(IO - 1).getImm();
2517 ARMCC::CondCodes NewCC = getSwappedCondition(CC);
2518 if (NewCC == ARMCC::AL)
2520 // If we have SUB(r1, r2) and CMP(r2, r1), the condition code based
2521 // on CMP needs to be updated to be based on SUB.
2522 // Push the condition code operands to OperandsToUpdate.
2523 // If it is safe to remove CmpInstr, the condition code of these
2524 // operands will be modified.
2525 if (SrcReg2 != 0 && Sub->getOperand(1).getReg() == SrcReg2 &&
2526 Sub->getOperand(2).getReg() == SrcReg) {
2527 // VSel doesn't support condition code update.
2530 OperandsToUpdate.push_back(
2531 std::make_pair(&((*I).getOperand(IO - 1)), NewCC));
2534 // No Sub, so this is x = <op> y, z; cmp x, 0.
2536 case ARMCC::EQ: // Z
2537 case ARMCC::NE: // Z
2538 case ARMCC::MI: // N
2539 case ARMCC::PL: // N
2540 case ARMCC::AL: // none
2541 // CPSR can be used multiple times, we should continue.
2543 case ARMCC::HS: // C
2544 case ARMCC::LO: // C
2545 case ARMCC::VS: // V
2546 case ARMCC::VC: // V
2547 case ARMCC::HI: // C Z
2548 case ARMCC::LS: // C Z
2549 case ARMCC::GE: // N V
2550 case ARMCC::LT: // N V
2551 case ARMCC::GT: // Z N V
2552 case ARMCC::LE: // Z N V
2553 // The instruction uses the V bit or C bit which is not safe.
2560 // If CPSR is not killed nor re-defined, we should check whether it is
2561 // live-out. If it is live-out, do not optimize.
2563 MachineBasicBlock *MBB = CmpInstr->getParent();
2564 for (MachineBasicBlock::succ_iterator SI = MBB->succ_begin(),
2565 SE = MBB->succ_end(); SI != SE; ++SI)
2566 if ((*SI)->isLiveIn(ARM::CPSR))
2570 // Toggle the optional operand to CPSR.
2571 MI->getOperand(5).setReg(ARM::CPSR);
2572 MI->getOperand(5).setIsDef(true);
2573 assert(!isPredicated(MI) && "Can't use flags from predicated instruction");
2574 CmpInstr->eraseFromParent();
2576 // Modify the condition code of operands in OperandsToUpdate.
2577 // Since we have SUB(r1, r2) and CMP(r2, r1), the condition code needs to
2578 // be changed from r2 > r1 to r1 < r2, from r2 < r1 to r1 > r2, etc.
2579 for (unsigned i = 0, e = OperandsToUpdate.size(); i < e; i++)
2580 OperandsToUpdate[i].first->setImm(OperandsToUpdate[i].second);
2588 bool ARMBaseInstrInfo::FoldImmediate(MachineInstr *UseMI,
2589 MachineInstr *DefMI, unsigned Reg,
2590 MachineRegisterInfo *MRI) const {
2591 // Fold large immediates into add, sub, or, xor.
2592 unsigned DefOpc = DefMI->getOpcode();
2593 if (DefOpc != ARM::t2MOVi32imm && DefOpc != ARM::MOVi32imm)
2595 if (!DefMI->getOperand(1).isImm())
2596 // Could be t2MOVi32imm <ga:xx>
2599 if (!MRI->hasOneNonDBGUse(Reg))
2602 const MCInstrDesc &DefMCID = DefMI->getDesc();
2603 if (DefMCID.hasOptionalDef()) {
2604 unsigned NumOps = DefMCID.getNumOperands();
2605 const MachineOperand &MO = DefMI->getOperand(NumOps-1);
2606 if (MO.getReg() == ARM::CPSR && !MO.isDead())
2607 // If DefMI defines CPSR and it is not dead, it's obviously not safe
2612 const MCInstrDesc &UseMCID = UseMI->getDesc();
2613 if (UseMCID.hasOptionalDef()) {
2614 unsigned NumOps = UseMCID.getNumOperands();
2615 if (UseMI->getOperand(NumOps-1).getReg() == ARM::CPSR)
2616 // If the instruction sets the flag, do not attempt this optimization
2617 // since it may change the semantics of the code.
2621 unsigned UseOpc = UseMI->getOpcode();
2622 unsigned NewUseOpc = 0;
2623 uint32_t ImmVal = (uint32_t)DefMI->getOperand(1).getImm();
2624 uint32_t SOImmValV1 = 0, SOImmValV2 = 0;
2625 bool Commute = false;
2627 default: return false;
2635 case ARM::t2EORrr: {
2636 Commute = UseMI->getOperand(2).getReg() != Reg;
2643 NewUseOpc = ARM::SUBri;
2649 if (!ARM_AM::isSOImmTwoPartVal(ImmVal))
2651 SOImmValV1 = (uint32_t)ARM_AM::getSOImmTwoPartFirst(ImmVal);
2652 SOImmValV2 = (uint32_t)ARM_AM::getSOImmTwoPartSecond(ImmVal);
2655 case ARM::ADDrr: NewUseOpc = ARM::ADDri; break;
2656 case ARM::ORRrr: NewUseOpc = ARM::ORRri; break;
2657 case ARM::EORrr: NewUseOpc = ARM::EORri; break;
2661 case ARM::t2SUBrr: {
2665 NewUseOpc = ARM::t2SUBri;
2670 case ARM::t2EORrr: {
2671 if (!ARM_AM::isT2SOImmTwoPartVal(ImmVal))
2673 SOImmValV1 = (uint32_t)ARM_AM::getT2SOImmTwoPartFirst(ImmVal);
2674 SOImmValV2 = (uint32_t)ARM_AM::getT2SOImmTwoPartSecond(ImmVal);
2677 case ARM::t2ADDrr: NewUseOpc = ARM::t2ADDri; break;
2678 case ARM::t2ORRrr: NewUseOpc = ARM::t2ORRri; break;
2679 case ARM::t2EORrr: NewUseOpc = ARM::t2EORri; break;
2687 unsigned OpIdx = Commute ? 2 : 1;
2688 unsigned Reg1 = UseMI->getOperand(OpIdx).getReg();
2689 bool isKill = UseMI->getOperand(OpIdx).isKill();
2690 unsigned NewReg = MRI->createVirtualRegister(MRI->getRegClass(Reg));
2691 AddDefaultCC(AddDefaultPred(BuildMI(*UseMI->getParent(),
2692 UseMI, UseMI->getDebugLoc(),
2693 get(NewUseOpc), NewReg)
2694 .addReg(Reg1, getKillRegState(isKill))
2695 .addImm(SOImmValV1)));
2696 UseMI->setDesc(get(NewUseOpc));
2697 UseMI->getOperand(1).setReg(NewReg);
2698 UseMI->getOperand(1).setIsKill();
2699 UseMI->getOperand(2).ChangeToImmediate(SOImmValV2);
2700 DefMI->eraseFromParent();
2704 static unsigned getNumMicroOpsSwiftLdSt(const InstrItineraryData *ItinData,
2705 const MachineInstr *MI) {
2706 switch (MI->getOpcode()) {
2708 const MCInstrDesc &Desc = MI->getDesc();
2709 int UOps = ItinData->getNumMicroOps(Desc.getSchedClass());
2710 assert(UOps >= 0 && "bad # UOps");
2718 unsigned ShOpVal = MI->getOperand(3).getImm();
2719 bool isSub = ARM_AM::getAM2Op(ShOpVal) == ARM_AM::sub;
2720 unsigned ShImm = ARM_AM::getAM2Offset(ShOpVal);
2723 ((ShImm == 1 || ShImm == 2 || ShImm == 3) &&
2724 ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl)))
2731 if (!MI->getOperand(2).getReg())
2734 unsigned ShOpVal = MI->getOperand(3).getImm();
2735 bool isSub = ARM_AM::getAM2Op(ShOpVal) == ARM_AM::sub;
2736 unsigned ShImm = ARM_AM::getAM2Offset(ShOpVal);
2739 ((ShImm == 1 || ShImm == 2 || ShImm == 3) &&
2740 ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl)))
2747 return (ARM_AM::getAM3Op(MI->getOperand(3).getImm()) == ARM_AM::sub) ? 3:2;
2749 case ARM::LDRSB_POST:
2750 case ARM::LDRSH_POST: {
2751 unsigned Rt = MI->getOperand(0).getReg();
2752 unsigned Rm = MI->getOperand(3).getReg();
2753 return (Rt == Rm) ? 4 : 3;
2756 case ARM::LDR_PRE_REG:
2757 case ARM::LDRB_PRE_REG: {
2758 unsigned Rt = MI->getOperand(0).getReg();
2759 unsigned Rm = MI->getOperand(3).getReg();
2762 unsigned ShOpVal = MI->getOperand(4).getImm();
2763 bool isSub = ARM_AM::getAM2Op(ShOpVal) == ARM_AM::sub;
2764 unsigned ShImm = ARM_AM::getAM2Offset(ShOpVal);
2767 ((ShImm == 1 || ShImm == 2 || ShImm == 3) &&
2768 ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl)))
2773 case ARM::STR_PRE_REG:
2774 case ARM::STRB_PRE_REG: {
2775 unsigned ShOpVal = MI->getOperand(4).getImm();
2776 bool isSub = ARM_AM::getAM2Op(ShOpVal) == ARM_AM::sub;
2777 unsigned ShImm = ARM_AM::getAM2Offset(ShOpVal);
2780 ((ShImm == 1 || ShImm == 2 || ShImm == 3) &&
2781 ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl)))
2787 case ARM::STRH_PRE: {
2788 unsigned Rt = MI->getOperand(0).getReg();
2789 unsigned Rm = MI->getOperand(3).getReg();
2794 return (ARM_AM::getAM3Op(MI->getOperand(4).getImm()) == ARM_AM::sub)
2798 case ARM::LDR_POST_REG:
2799 case ARM::LDRB_POST_REG:
2800 case ARM::LDRH_POST: {
2801 unsigned Rt = MI->getOperand(0).getReg();
2802 unsigned Rm = MI->getOperand(3).getReg();
2803 return (Rt == Rm) ? 3 : 2;
2806 case ARM::LDR_PRE_IMM:
2807 case ARM::LDRB_PRE_IMM:
2808 case ARM::LDR_POST_IMM:
2809 case ARM::LDRB_POST_IMM:
2810 case ARM::STRB_POST_IMM:
2811 case ARM::STRB_POST_REG:
2812 case ARM::STRB_PRE_IMM:
2813 case ARM::STRH_POST:
2814 case ARM::STR_POST_IMM:
2815 case ARM::STR_POST_REG:
2816 case ARM::STR_PRE_IMM:
2819 case ARM::LDRSB_PRE:
2820 case ARM::LDRSH_PRE: {
2821 unsigned Rm = MI->getOperand(3).getReg();
2824 unsigned Rt = MI->getOperand(0).getReg();
2827 unsigned ShOpVal = MI->getOperand(4).getImm();
2828 bool isSub = ARM_AM::getAM2Op(ShOpVal) == ARM_AM::sub;
2829 unsigned ShImm = ARM_AM::getAM2Offset(ShOpVal);
2832 ((ShImm == 1 || ShImm == 2 || ShImm == 3) &&
2833 ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl)))
2839 unsigned Rt = MI->getOperand(0).getReg();
2840 unsigned Rn = MI->getOperand(2).getReg();
2841 unsigned Rm = MI->getOperand(3).getReg();
2843 return (ARM_AM::getAM3Op(MI->getOperand(4).getImm()) == ARM_AM::sub) ?4:3;
2844 return (Rt == Rn) ? 3 : 2;
2848 unsigned Rm = MI->getOperand(3).getReg();
2850 return (ARM_AM::getAM3Op(MI->getOperand(4).getImm()) == ARM_AM::sub) ?4:3;
2854 case ARM::LDRD_POST:
2855 case ARM::t2LDRD_POST:
2858 case ARM::STRD_POST:
2859 case ARM::t2STRD_POST:
2862 case ARM::LDRD_PRE: {
2863 unsigned Rt = MI->getOperand(0).getReg();
2864 unsigned Rn = MI->getOperand(3).getReg();
2865 unsigned Rm = MI->getOperand(4).getReg();
2867 return (ARM_AM::getAM3Op(MI->getOperand(5).getImm()) == ARM_AM::sub) ?5:4;
2868 return (Rt == Rn) ? 4 : 3;
2871 case ARM::t2LDRD_PRE: {
2872 unsigned Rt = MI->getOperand(0).getReg();
2873 unsigned Rn = MI->getOperand(3).getReg();
2874 return (Rt == Rn) ? 4 : 3;
2877 case ARM::STRD_PRE: {
2878 unsigned Rm = MI->getOperand(4).getReg();
2880 return (ARM_AM::getAM3Op(MI->getOperand(5).getImm()) == ARM_AM::sub) ?5:4;
2884 case ARM::t2STRD_PRE:
2887 case ARM::t2LDR_POST:
2888 case ARM::t2LDRB_POST:
2889 case ARM::t2LDRB_PRE:
2890 case ARM::t2LDRSBi12:
2891 case ARM::t2LDRSBi8:
2892 case ARM::t2LDRSBpci:
2894 case ARM::t2LDRH_POST:
2895 case ARM::t2LDRH_PRE:
2897 case ARM::t2LDRSB_POST:
2898 case ARM::t2LDRSB_PRE:
2899 case ARM::t2LDRSH_POST:
2900 case ARM::t2LDRSH_PRE:
2901 case ARM::t2LDRSHi12:
2902 case ARM::t2LDRSHi8:
2903 case ARM::t2LDRSHpci:
2907 case ARM::t2LDRDi8: {
2908 unsigned Rt = MI->getOperand(0).getReg();
2909 unsigned Rn = MI->getOperand(2).getReg();
2910 return (Rt == Rn) ? 3 : 2;
2913 case ARM::t2STRB_POST:
2914 case ARM::t2STRB_PRE:
2917 case ARM::t2STRH_POST:
2918 case ARM::t2STRH_PRE:
2920 case ARM::t2STR_POST:
2921 case ARM::t2STR_PRE:
2927 // Return the number of 32-bit words loaded by LDM or stored by STM. If this
2928 // can't be easily determined return 0 (missing MachineMemOperand).
2930 // FIXME: The current MachineInstr design does not support relying on machine
2931 // mem operands to determine the width of a memory access. Instead, we expect
2932 // the target to provide this information based on the instruction opcode and
2933 // operands. However, using MachineMemOperand is the best solution now for
2936 // 1) getNumMicroOps tries to infer LDM memory width from the total number of MI
2937 // operands. This is much more dangerous than using the MachineMemOperand
2938 // sizes because CodeGen passes can insert/remove optional machine operands. In
2939 // fact, it's totally incorrect for preRA passes and appears to be wrong for
2940 // postRA passes as well.
2942 // 2) getNumLDMAddresses is only used by the scheduling machine model and any
2943 // machine model that calls this should handle the unknown (zero size) case.
2945 // Long term, we should require a target hook that verifies MachineMemOperand
2946 // sizes during MC lowering. That target hook should be local to MC lowering
2947 // because we can't ensure that it is aware of other MI forms. Doing this will
2948 // ensure that MachineMemOperands are correctly propagated through all passes.
2949 unsigned ARMBaseInstrInfo::getNumLDMAddresses(const MachineInstr *MI) const {
2951 for (MachineInstr::mmo_iterator I = MI->memoperands_begin(),
2952 E = MI->memoperands_end(); I != E; ++I) {
2953 Size += (*I)->getSize();
2959 ARMBaseInstrInfo::getNumMicroOps(const InstrItineraryData *ItinData,
2960 const MachineInstr *MI) const {
2961 if (!ItinData || ItinData->isEmpty())
2964 const MCInstrDesc &Desc = MI->getDesc();
2965 unsigned Class = Desc.getSchedClass();
2966 int ItinUOps = ItinData->getNumMicroOps(Class);
2967 if (ItinUOps >= 0) {
2968 if (Subtarget.isSwift() && (Desc.mayLoad() || Desc.mayStore()))
2969 return getNumMicroOpsSwiftLdSt(ItinData, MI);
2974 unsigned Opc = MI->getOpcode();
2977 llvm_unreachable("Unexpected multi-uops instruction!");
2982 // The number of uOps for load / store multiple are determined by the number
2985 // On Cortex-A8, each pair of register loads / stores can be scheduled on the
2986 // same cycle. The scheduling for the first load / store must be done
2987 // separately by assuming the address is not 64-bit aligned.
2989 // On Cortex-A9, the formula is simply (#reg / 2) + (#reg % 2). If the address
2990 // is not 64-bit aligned, then AGU would take an extra cycle. For VFP / NEON
2991 // load / store multiple, the formula is (#reg / 2) + (#reg % 2) + 1.
2993 case ARM::VLDMDIA_UPD:
2994 case ARM::VLDMDDB_UPD:
2996 case ARM::VLDMSIA_UPD:
2997 case ARM::VLDMSDB_UPD:
2999 case ARM::VSTMDIA_UPD:
3000 case ARM::VSTMDDB_UPD:
3002 case ARM::VSTMSIA_UPD:
3003 case ARM::VSTMSDB_UPD: {
3004 unsigned NumRegs = MI->getNumOperands() - Desc.getNumOperands();
3005 return (NumRegs / 2) + (NumRegs % 2) + 1;
3008 case ARM::LDMIA_RET:
3013 case ARM::LDMIA_UPD:
3014 case ARM::LDMDA_UPD:
3015 case ARM::LDMDB_UPD:
3016 case ARM::LDMIB_UPD:
3021 case ARM::STMIA_UPD:
3022 case ARM::STMDA_UPD:
3023 case ARM::STMDB_UPD:
3024 case ARM::STMIB_UPD:
3026 case ARM::tLDMIA_UPD:
3027 case ARM::tSTMIA_UPD:
3031 case ARM::t2LDMIA_RET:
3034 case ARM::t2LDMIA_UPD:
3035 case ARM::t2LDMDB_UPD:
3038 case ARM::t2STMIA_UPD:
3039 case ARM::t2STMDB_UPD: {
3040 unsigned NumRegs = MI->getNumOperands() - Desc.getNumOperands() + 1;
3041 if (Subtarget.isSwift()) {
3042 int UOps = 1 + NumRegs; // One for address computation, one for each ld / st.
3045 case ARM::VLDMDIA_UPD:
3046 case ARM::VLDMDDB_UPD:
3047 case ARM::VLDMSIA_UPD:
3048 case ARM::VLDMSDB_UPD:
3049 case ARM::VSTMDIA_UPD:
3050 case ARM::VSTMDDB_UPD:
3051 case ARM::VSTMSIA_UPD:
3052 case ARM::VSTMSDB_UPD:
3053 case ARM::LDMIA_UPD:
3054 case ARM::LDMDA_UPD:
3055 case ARM::LDMDB_UPD:
3056 case ARM::LDMIB_UPD:
3057 case ARM::STMIA_UPD:
3058 case ARM::STMDA_UPD:
3059 case ARM::STMDB_UPD:
3060 case ARM::STMIB_UPD:
3061 case ARM::tLDMIA_UPD:
3062 case ARM::tSTMIA_UPD:
3063 case ARM::t2LDMIA_UPD:
3064 case ARM::t2LDMDB_UPD:
3065 case ARM::t2STMIA_UPD:
3066 case ARM::t2STMDB_UPD:
3067 ++UOps; // One for base register writeback.
3069 case ARM::LDMIA_RET:
3071 case ARM::t2LDMIA_RET:
3072 UOps += 2; // One for base reg wb, one for write to pc.
3076 } else if (Subtarget.isCortexA8() || Subtarget.isCortexA7()) {
3079 // 4 registers would be issued: 2, 2.
3080 // 5 registers would be issued: 2, 2, 1.
3081 int A8UOps = (NumRegs / 2);
3085 } else if (Subtarget.isLikeA9() || Subtarget.isSwift()) {
3086 int A9UOps = (NumRegs / 2);
3087 // If there are odd number of registers or if it's not 64-bit aligned,
3088 // then it takes an extra AGU (Address Generation Unit) cycle.
3089 if ((NumRegs % 2) ||
3090 !MI->hasOneMemOperand() ||
3091 (*MI->memoperands_begin())->getAlignment() < 8)
3095 // Assume the worst.
3103 ARMBaseInstrInfo::getVLDMDefCycle(const InstrItineraryData *ItinData,
3104 const MCInstrDesc &DefMCID,
3106 unsigned DefIdx, unsigned DefAlign) const {
3107 int RegNo = (int)(DefIdx+1) - DefMCID.getNumOperands() + 1;
3109 // Def is the address writeback.
3110 return ItinData->getOperandCycle(DefClass, DefIdx);
3113 if (Subtarget.isCortexA8() || Subtarget.isCortexA7()) {
3114 // (regno / 2) + (regno % 2) + 1
3115 DefCycle = RegNo / 2 + 1;
3118 } else if (Subtarget.isLikeA9() || Subtarget.isSwift()) {
3120 bool isSLoad = false;
3122 switch (DefMCID.getOpcode()) {
3125 case ARM::VLDMSIA_UPD:
3126 case ARM::VLDMSDB_UPD:
3131 // If there are odd number of 'S' registers or if it's not 64-bit aligned,
3132 // then it takes an extra cycle.
3133 if ((isSLoad && (RegNo % 2)) || DefAlign < 8)
3136 // Assume the worst.
3137 DefCycle = RegNo + 2;
3144 ARMBaseInstrInfo::getLDMDefCycle(const InstrItineraryData *ItinData,
3145 const MCInstrDesc &DefMCID,
3147 unsigned DefIdx, unsigned DefAlign) const {
3148 int RegNo = (int)(DefIdx+1) - DefMCID.getNumOperands() + 1;
3150 // Def is the address writeback.
3151 return ItinData->getOperandCycle(DefClass, DefIdx);
3154 if (Subtarget.isCortexA8() || Subtarget.isCortexA7()) {
3155 // 4 registers would be issued: 1, 2, 1.
3156 // 5 registers would be issued: 1, 2, 2.
3157 DefCycle = RegNo / 2;
3160 // Result latency is issue cycle + 2: E2.
3162 } else if (Subtarget.isLikeA9() || Subtarget.isSwift()) {
3163 DefCycle = (RegNo / 2);
3164 // If there are odd number of registers or if it's not 64-bit aligned,
3165 // then it takes an extra AGU (Address Generation Unit) cycle.
3166 if ((RegNo % 2) || DefAlign < 8)
3168 // Result latency is AGU cycles + 2.
3171 // Assume the worst.
3172 DefCycle = RegNo + 2;
3179 ARMBaseInstrInfo::getVSTMUseCycle(const InstrItineraryData *ItinData,
3180 const MCInstrDesc &UseMCID,
3182 unsigned UseIdx, unsigned UseAlign) const {
3183 int RegNo = (int)(UseIdx+1) - UseMCID.getNumOperands() + 1;
3185 return ItinData->getOperandCycle(UseClass, UseIdx);
3188 if (Subtarget.isCortexA8() || Subtarget.isCortexA7()) {
3189 // (regno / 2) + (regno % 2) + 1
3190 UseCycle = RegNo / 2 + 1;
3193 } else if (Subtarget.isLikeA9() || Subtarget.isSwift()) {
3195 bool isSStore = false;
3197 switch (UseMCID.getOpcode()) {
3200 case ARM::VSTMSIA_UPD:
3201 case ARM::VSTMSDB_UPD:
3206 // If there are odd number of 'S' registers or if it's not 64-bit aligned,
3207 // then it takes an extra cycle.
3208 if ((isSStore && (RegNo % 2)) || UseAlign < 8)
3211 // Assume the worst.
3212 UseCycle = RegNo + 2;
3219 ARMBaseInstrInfo::getSTMUseCycle(const InstrItineraryData *ItinData,
3220 const MCInstrDesc &UseMCID,
3222 unsigned UseIdx, unsigned UseAlign) const {
3223 int RegNo = (int)(UseIdx+1) - UseMCID.getNumOperands() + 1;
3225 return ItinData->getOperandCycle(UseClass, UseIdx);
3228 if (Subtarget.isCortexA8() || Subtarget.isCortexA7()) {
3229 UseCycle = RegNo / 2;
3234 } else if (Subtarget.isLikeA9() || Subtarget.isSwift()) {
3235 UseCycle = (RegNo / 2);
3236 // If there are odd number of registers or if it's not 64-bit aligned,
3237 // then it takes an extra AGU (Address Generation Unit) cycle.
3238 if ((RegNo % 2) || UseAlign < 8)
3241 // Assume the worst.
3248 ARMBaseInstrInfo::getOperandLatency(const InstrItineraryData *ItinData,
3249 const MCInstrDesc &DefMCID,
3250 unsigned DefIdx, unsigned DefAlign,
3251 const MCInstrDesc &UseMCID,
3252 unsigned UseIdx, unsigned UseAlign) const {
3253 unsigned DefClass = DefMCID.getSchedClass();
3254 unsigned UseClass = UseMCID.getSchedClass();
3256 if (DefIdx < DefMCID.getNumDefs() && UseIdx < UseMCID.getNumOperands())
3257 return ItinData->getOperandLatency(DefClass, DefIdx, UseClass, UseIdx);
3259 // This may be a def / use of a variable_ops instruction, the operand
3260 // latency might be determinable dynamically. Let the target try to
3263 bool LdmBypass = false;
3264 switch (DefMCID.getOpcode()) {
3266 DefCycle = ItinData->getOperandCycle(DefClass, DefIdx);
3270 case ARM::VLDMDIA_UPD:
3271 case ARM::VLDMDDB_UPD:
3273 case ARM::VLDMSIA_UPD:
3274 case ARM::VLDMSDB_UPD:
3275 DefCycle = getVLDMDefCycle(ItinData, DefMCID, DefClass, DefIdx, DefAlign);
3278 case ARM::LDMIA_RET:
3283 case ARM::LDMIA_UPD:
3284 case ARM::LDMDA_UPD:
3285 case ARM::LDMDB_UPD:
3286 case ARM::LDMIB_UPD:
3288 case ARM::tLDMIA_UPD:
3290 case ARM::t2LDMIA_RET:
3293 case ARM::t2LDMIA_UPD:
3294 case ARM::t2LDMDB_UPD:
3296 DefCycle = getLDMDefCycle(ItinData, DefMCID, DefClass, DefIdx, DefAlign);
3301 // We can't seem to determine the result latency of the def, assume it's 2.
3305 switch (UseMCID.getOpcode()) {
3307 UseCycle = ItinData->getOperandCycle(UseClass, UseIdx);
3311 case ARM::VSTMDIA_UPD:
3312 case ARM::VSTMDDB_UPD:
3314 case ARM::VSTMSIA_UPD:
3315 case ARM::VSTMSDB_UPD:
3316 UseCycle = getVSTMUseCycle(ItinData, UseMCID, UseClass, UseIdx, UseAlign);
3323 case ARM::STMIA_UPD:
3324 case ARM::STMDA_UPD:
3325 case ARM::STMDB_UPD:
3326 case ARM::STMIB_UPD:
3327 case ARM::tSTMIA_UPD:
3332 case ARM::t2STMIA_UPD:
3333 case ARM::t2STMDB_UPD:
3334 UseCycle = getSTMUseCycle(ItinData, UseMCID, UseClass, UseIdx, UseAlign);
3339 // Assume it's read in the first stage.
3342 UseCycle = DefCycle - UseCycle + 1;
3345 // It's a variable_ops instruction so we can't use DefIdx here. Just use
3346 // first def operand.
3347 if (ItinData->hasPipelineForwarding(DefClass, DefMCID.getNumOperands()-1,
3350 } else if (ItinData->hasPipelineForwarding(DefClass, DefIdx,
3351 UseClass, UseIdx)) {
3359 static const MachineInstr *getBundledDefMI(const TargetRegisterInfo *TRI,
3360 const MachineInstr *MI, unsigned Reg,
3361 unsigned &DefIdx, unsigned &Dist) {
3364 MachineBasicBlock::const_iterator I = MI; ++I;
3365 MachineBasicBlock::const_instr_iterator II = std::prev(I.getInstrIterator());
3366 assert(II->isInsideBundle() && "Empty bundle?");
3369 while (II->isInsideBundle()) {
3370 Idx = II->findRegisterDefOperandIdx(Reg, false, true, TRI);
3377 assert(Idx != -1 && "Cannot find bundled definition!");
3382 static const MachineInstr *getBundledUseMI(const TargetRegisterInfo *TRI,
3383 const MachineInstr *MI, unsigned Reg,
3384 unsigned &UseIdx, unsigned &Dist) {
3387 MachineBasicBlock::const_instr_iterator II = MI; ++II;
3388 assert(II->isInsideBundle() && "Empty bundle?");
3389 MachineBasicBlock::const_instr_iterator E = MI->getParent()->instr_end();
3391 // FIXME: This doesn't properly handle multiple uses.
3393 while (II != E && II->isInsideBundle()) {
3394 Idx = II->findRegisterUseOperandIdx(Reg, false, TRI);
3397 if (II->getOpcode() != ARM::t2IT)
3411 /// Return the number of cycles to add to (or subtract from) the static
3412 /// itinerary based on the def opcode and alignment. The caller will ensure that
3413 /// adjusted latency is at least one cycle.
3414 static int adjustDefLatency(const ARMSubtarget &Subtarget,
3415 const MachineInstr *DefMI,
3416 const MCInstrDesc *DefMCID, unsigned DefAlign) {
3418 if (Subtarget.isCortexA8() || Subtarget.isLikeA9() || Subtarget.isCortexA7()) {
3419 // FIXME: Shifter op hack: no shift (i.e. [r +/- r]) or [r + r << 2]
3420 // variants are one cycle cheaper.
3421 switch (DefMCID->getOpcode()) {
3425 unsigned ShOpVal = DefMI->getOperand(3).getImm();
3426 unsigned ShImm = ARM_AM::getAM2Offset(ShOpVal);
3428 (ShImm == 2 && ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl))
3435 case ARM::t2LDRSHs: {
3436 // Thumb2 mode: lsl only.
3437 unsigned ShAmt = DefMI->getOperand(3).getImm();
3438 if (ShAmt == 0 || ShAmt == 2)
3443 } else if (Subtarget.isSwift()) {
3444 // FIXME: Properly handle all of the latency adjustments for address
3446 switch (DefMCID->getOpcode()) {
3450 unsigned ShOpVal = DefMI->getOperand(3).getImm();
3451 bool isSub = ARM_AM::getAM2Op(ShOpVal) == ARM_AM::sub;
3452 unsigned ShImm = ARM_AM::getAM2Offset(ShOpVal);
3455 ((ShImm == 1 || ShImm == 2 || ShImm == 3) &&
3456 ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl)))
3459 ShImm == 1 && ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsr)
3466 case ARM::t2LDRSHs: {
3467 // Thumb2 mode: lsl only.
3468 unsigned ShAmt = DefMI->getOperand(3).getImm();
3469 if (ShAmt == 0 || ShAmt == 1 || ShAmt == 2 || ShAmt == 3)
3476 if (DefAlign < 8 && Subtarget.isLikeA9()) {
3477 switch (DefMCID->getOpcode()) {
3483 case ARM::VLD1q8wb_fixed:
3484 case ARM::VLD1q16wb_fixed:
3485 case ARM::VLD1q32wb_fixed:
3486 case ARM::VLD1q64wb_fixed:
3487 case ARM::VLD1q8wb_register:
3488 case ARM::VLD1q16wb_register:
3489 case ARM::VLD1q32wb_register:
3490 case ARM::VLD1q64wb_register:
3497 case ARM::VLD2d8wb_fixed:
3498 case ARM::VLD2d16wb_fixed:
3499 case ARM::VLD2d32wb_fixed:
3500 case ARM::VLD2q8wb_fixed:
3501 case ARM::VLD2q16wb_fixed:
3502 case ARM::VLD2q32wb_fixed:
3503 case ARM::VLD2d8wb_register:
3504 case ARM::VLD2d16wb_register:
3505 case ARM::VLD2d32wb_register:
3506 case ARM::VLD2q8wb_register:
3507 case ARM::VLD2q16wb_register:
3508 case ARM::VLD2q32wb_register:
3513 case ARM::VLD3d8_UPD:
3514 case ARM::VLD3d16_UPD:
3515 case ARM::VLD3d32_UPD:
3516 case ARM::VLD1d64Twb_fixed:
3517 case ARM::VLD1d64Twb_register:
3518 case ARM::VLD3q8_UPD:
3519 case ARM::VLD3q16_UPD:
3520 case ARM::VLD3q32_UPD:
3525 case ARM::VLD4d8_UPD:
3526 case ARM::VLD4d16_UPD:
3527 case ARM::VLD4d32_UPD:
3528 case ARM::VLD1d64Qwb_fixed:
3529 case ARM::VLD1d64Qwb_register:
3530 case ARM::VLD4q8_UPD:
3531 case ARM::VLD4q16_UPD:
3532 case ARM::VLD4q32_UPD:
3533 case ARM::VLD1DUPq8:
3534 case ARM::VLD1DUPq16:
3535 case ARM::VLD1DUPq32:
3536 case ARM::VLD1DUPq8wb_fixed:
3537 case ARM::VLD1DUPq16wb_fixed:
3538 case ARM::VLD1DUPq32wb_fixed:
3539 case ARM::VLD1DUPq8wb_register:
3540 case ARM::VLD1DUPq16wb_register:
3541 case ARM::VLD1DUPq32wb_register:
3542 case ARM::VLD2DUPd8:
3543 case ARM::VLD2DUPd16:
3544 case ARM::VLD2DUPd32:
3545 case ARM::VLD2DUPd8wb_fixed:
3546 case ARM::VLD2DUPd16wb_fixed:
3547 case ARM::VLD2DUPd32wb_fixed:
3548 case ARM::VLD2DUPd8wb_register:
3549 case ARM::VLD2DUPd16wb_register:
3550 case ARM::VLD2DUPd32wb_register:
3551 case ARM::VLD4DUPd8:
3552 case ARM::VLD4DUPd16:
3553 case ARM::VLD4DUPd32:
3554 case ARM::VLD4DUPd8_UPD:
3555 case ARM::VLD4DUPd16_UPD:
3556 case ARM::VLD4DUPd32_UPD:
3558 case ARM::VLD1LNd16:
3559 case ARM::VLD1LNd32:
3560 case ARM::VLD1LNd8_UPD:
3561 case ARM::VLD1LNd16_UPD:
3562 case ARM::VLD1LNd32_UPD:
3564 case ARM::VLD2LNd16:
3565 case ARM::VLD2LNd32:
3566 case ARM::VLD2LNq16:
3567 case ARM::VLD2LNq32:
3568 case ARM::VLD2LNd8_UPD:
3569 case ARM::VLD2LNd16_UPD:
3570 case ARM::VLD2LNd32_UPD:
3571 case ARM::VLD2LNq16_UPD:
3572 case ARM::VLD2LNq32_UPD:
3574 case ARM::VLD4LNd16:
3575 case ARM::VLD4LNd32:
3576 case ARM::VLD4LNq16:
3577 case ARM::VLD4LNq32:
3578 case ARM::VLD4LNd8_UPD:
3579 case ARM::VLD4LNd16_UPD:
3580 case ARM::VLD4LNd32_UPD:
3581 case ARM::VLD4LNq16_UPD:
3582 case ARM::VLD4LNq32_UPD:
3583 // If the address is not 64-bit aligned, the latencies of these
3584 // instructions increases by one.
3595 ARMBaseInstrInfo::getOperandLatency(const InstrItineraryData *ItinData,
3596 const MachineInstr *DefMI, unsigned DefIdx,
3597 const MachineInstr *UseMI,
3598 unsigned UseIdx) const {
3599 // No operand latency. The caller may fall back to getInstrLatency.
3600 if (!ItinData || ItinData->isEmpty())
3603 const MachineOperand &DefMO = DefMI->getOperand(DefIdx);
3604 unsigned Reg = DefMO.getReg();
3605 const MCInstrDesc *DefMCID = &DefMI->getDesc();
3606 const MCInstrDesc *UseMCID = &UseMI->getDesc();
3608 unsigned DefAdj = 0;
3609 if (DefMI->isBundle()) {
3610 DefMI = getBundledDefMI(&getRegisterInfo(), DefMI, Reg, DefIdx, DefAdj);
3611 DefMCID = &DefMI->getDesc();
3613 if (DefMI->isCopyLike() || DefMI->isInsertSubreg() ||
3614 DefMI->isRegSequence() || DefMI->isImplicitDef()) {
3618 unsigned UseAdj = 0;
3619 if (UseMI->isBundle()) {
3621 const MachineInstr *NewUseMI = getBundledUseMI(&getRegisterInfo(), UseMI,
3622 Reg, NewUseIdx, UseAdj);
3628 UseMCID = &UseMI->getDesc();
3631 if (Reg == ARM::CPSR) {
3632 if (DefMI->getOpcode() == ARM::FMSTAT) {
3633 // fpscr -> cpsr stalls over 20 cycles on A8 (and earlier?)
3634 return Subtarget.isLikeA9() ? 1 : 20;
3637 // CPSR set and branch can be paired in the same cycle.
3638 if (UseMI->isBranch())
3641 // Otherwise it takes the instruction latency (generally one).
3642 unsigned Latency = getInstrLatency(ItinData, DefMI);
3644 // For Thumb2 and -Os, prefer scheduling CPSR setting instruction close to
3645 // its uses. Instructions which are otherwise scheduled between them may
3646 // incur a code size penalty (not able to use the CPSR setting 16-bit
3648 if (Latency > 0 && Subtarget.isThumb2()) {
3649 const MachineFunction *MF = DefMI->getParent()->getParent();
3650 // FIXME: Use Function::optForSize().
3651 if (MF->getFunction()->hasFnAttribute(Attribute::OptimizeForSize))
3657 if (DefMO.isImplicit() || UseMI->getOperand(UseIdx).isImplicit())
3660 unsigned DefAlign = DefMI->hasOneMemOperand()
3661 ? (*DefMI->memoperands_begin())->getAlignment() : 0;
3662 unsigned UseAlign = UseMI->hasOneMemOperand()
3663 ? (*UseMI->memoperands_begin())->getAlignment() : 0;
3665 // Get the itinerary's latency if possible, and handle variable_ops.
3666 int Latency = getOperandLatency(ItinData, *DefMCID, DefIdx, DefAlign,
3667 *UseMCID, UseIdx, UseAlign);
3668 // Unable to find operand latency. The caller may resort to getInstrLatency.
3672 // Adjust for IT block position.
3673 int Adj = DefAdj + UseAdj;
3675 // Adjust for dynamic def-side opcode variants not captured by the itinerary.
3676 Adj += adjustDefLatency(Subtarget, DefMI, DefMCID, DefAlign);
3677 if (Adj >= 0 || (int)Latency > -Adj) {
3678 return Latency + Adj;
3680 // Return the itinerary latency, which may be zero but not less than zero.
3685 ARMBaseInstrInfo::getOperandLatency(const InstrItineraryData *ItinData,
3686 SDNode *DefNode, unsigned DefIdx,
3687 SDNode *UseNode, unsigned UseIdx) const {
3688 if (!DefNode->isMachineOpcode())
3691 const MCInstrDesc &DefMCID = get(DefNode->getMachineOpcode());
3693 if (isZeroCost(DefMCID.Opcode))
3696 if (!ItinData || ItinData->isEmpty())
3697 return DefMCID.mayLoad() ? 3 : 1;
3699 if (!UseNode->isMachineOpcode()) {
3700 int Latency = ItinData->getOperandCycle(DefMCID.getSchedClass(), DefIdx);
3701 if (Subtarget.isLikeA9() || Subtarget.isSwift())
3702 return Latency <= 2 ? 1 : Latency - 1;
3704 return Latency <= 3 ? 1 : Latency - 2;
3707 const MCInstrDesc &UseMCID = get(UseNode->getMachineOpcode());
3708 const MachineSDNode *DefMN = dyn_cast<MachineSDNode>(DefNode);
3709 unsigned DefAlign = !DefMN->memoperands_empty()
3710 ? (*DefMN->memoperands_begin())->getAlignment() : 0;
3711 const MachineSDNode *UseMN = dyn_cast<MachineSDNode>(UseNode);
3712 unsigned UseAlign = !UseMN->memoperands_empty()
3713 ? (*UseMN->memoperands_begin())->getAlignment() : 0;
3714 int Latency = getOperandLatency(ItinData, DefMCID, DefIdx, DefAlign,
3715 UseMCID, UseIdx, UseAlign);
3718 (Subtarget.isCortexA8() || Subtarget.isLikeA9() ||
3719 Subtarget.isCortexA7())) {
3720 // FIXME: Shifter op hack: no shift (i.e. [r +/- r]) or [r + r << 2]
3721 // variants are one cycle cheaper.
3722 switch (DefMCID.getOpcode()) {
3727 cast<ConstantSDNode>(DefNode->getOperand(2))->getZExtValue();
3728 unsigned ShImm = ARM_AM::getAM2Offset(ShOpVal);
3730 (ShImm == 2 && ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl))
3737 case ARM::t2LDRSHs: {
3738 // Thumb2 mode: lsl only.
3740 cast<ConstantSDNode>(DefNode->getOperand(2))->getZExtValue();
3741 if (ShAmt == 0 || ShAmt == 2)
3746 } else if (DefIdx == 0 && Latency > 2 && Subtarget.isSwift()) {
3747 // FIXME: Properly handle all of the latency adjustments for address
3749 switch (DefMCID.getOpcode()) {
3754 cast<ConstantSDNode>(DefNode->getOperand(2))->getZExtValue();
3755 unsigned ShImm = ARM_AM::getAM2Offset(ShOpVal);
3757 ((ShImm == 1 || ShImm == 2 || ShImm == 3) &&
3758 ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl))
3760 else if (ShImm == 1 && ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsr)
3767 case ARM::t2LDRSHs: {
3768 // Thumb2 mode: lsl 0-3 only.
3775 if (DefAlign < 8 && Subtarget.isLikeA9())
3776 switch (DefMCID.getOpcode()) {
3782 case ARM::VLD1q8wb_register:
3783 case ARM::VLD1q16wb_register:
3784 case ARM::VLD1q32wb_register:
3785 case ARM::VLD1q64wb_register:
3786 case ARM::VLD1q8wb_fixed:
3787 case ARM::VLD1q16wb_fixed:
3788 case ARM::VLD1q32wb_fixed:
3789 case ARM::VLD1q64wb_fixed:
3793 case ARM::VLD2q8Pseudo:
3794 case ARM::VLD2q16Pseudo:
3795 case ARM::VLD2q32Pseudo:
3796 case ARM::VLD2d8wb_fixed:
3797 case ARM::VLD2d16wb_fixed:
3798 case ARM::VLD2d32wb_fixed:
3799 case ARM::VLD2q8PseudoWB_fixed:
3800 case ARM::VLD2q16PseudoWB_fixed:
3801 case ARM::VLD2q32PseudoWB_fixed:
3802 case ARM::VLD2d8wb_register:
3803 case ARM::VLD2d16wb_register:
3804 case ARM::VLD2d32wb_register:
3805 case ARM::VLD2q8PseudoWB_register:
3806 case ARM::VLD2q16PseudoWB_register:
3807 case ARM::VLD2q32PseudoWB_register:
3808 case ARM::VLD3d8Pseudo:
3809 case ARM::VLD3d16Pseudo:
3810 case ARM::VLD3d32Pseudo:
3811 case ARM::VLD1d64TPseudo:
3812 case ARM::VLD1d64TPseudoWB_fixed:
3813 case ARM::VLD3d8Pseudo_UPD:
3814 case ARM::VLD3d16Pseudo_UPD:
3815 case ARM::VLD3d32Pseudo_UPD:
3816 case ARM::VLD3q8Pseudo_UPD:
3817 case ARM::VLD3q16Pseudo_UPD:
3818 case ARM::VLD3q32Pseudo_UPD:
3819 case ARM::VLD3q8oddPseudo:
3820 case ARM::VLD3q16oddPseudo:
3821 case ARM::VLD3q32oddPseudo:
3822 case ARM::VLD3q8oddPseudo_UPD:
3823 case ARM::VLD3q16oddPseudo_UPD:
3824 case ARM::VLD3q32oddPseudo_UPD:
3825 case ARM::VLD4d8Pseudo:
3826 case ARM::VLD4d16Pseudo:
3827 case ARM::VLD4d32Pseudo:
3828 case ARM::VLD1d64QPseudo:
3829 case ARM::VLD1d64QPseudoWB_fixed:
3830 case ARM::VLD4d8Pseudo_UPD:
3831 case ARM::VLD4d16Pseudo_UPD:
3832 case ARM::VLD4d32Pseudo_UPD:
3833 case ARM::VLD4q8Pseudo_UPD:
3834 case ARM::VLD4q16Pseudo_UPD:
3835 case ARM::VLD4q32Pseudo_UPD:
3836 case ARM::VLD4q8oddPseudo:
3837 case ARM::VLD4q16oddPseudo:
3838 case ARM::VLD4q32oddPseudo:
3839 case ARM::VLD4q8oddPseudo_UPD:
3840 case ARM::VLD4q16oddPseudo_UPD:
3841 case ARM::VLD4q32oddPseudo_UPD:
3842 case ARM::VLD1DUPq8:
3843 case ARM::VLD1DUPq16:
3844 case ARM::VLD1DUPq32:
3845 case ARM::VLD1DUPq8wb_fixed:
3846 case ARM::VLD1DUPq16wb_fixed:
3847 case ARM::VLD1DUPq32wb_fixed:
3848 case ARM::VLD1DUPq8wb_register:
3849 case ARM::VLD1DUPq16wb_register:
3850 case ARM::VLD1DUPq32wb_register:
3851 case ARM::VLD2DUPd8:
3852 case ARM::VLD2DUPd16:
3853 case ARM::VLD2DUPd32:
3854 case ARM::VLD2DUPd8wb_fixed:
3855 case ARM::VLD2DUPd16wb_fixed:
3856 case ARM::VLD2DUPd32wb_fixed:
3857 case ARM::VLD2DUPd8wb_register:
3858 case ARM::VLD2DUPd16wb_register:
3859 case ARM::VLD2DUPd32wb_register:
3860 case ARM::VLD4DUPd8Pseudo:
3861 case ARM::VLD4DUPd16Pseudo:
3862 case ARM::VLD4DUPd32Pseudo:
3863 case ARM::VLD4DUPd8Pseudo_UPD:
3864 case ARM::VLD4DUPd16Pseudo_UPD:
3865 case ARM::VLD4DUPd32Pseudo_UPD:
3866 case ARM::VLD1LNq8Pseudo:
3867 case ARM::VLD1LNq16Pseudo:
3868 case ARM::VLD1LNq32Pseudo:
3869 case ARM::VLD1LNq8Pseudo_UPD:
3870 case ARM::VLD1LNq16Pseudo_UPD:
3871 case ARM::VLD1LNq32Pseudo_UPD:
3872 case ARM::VLD2LNd8Pseudo:
3873 case ARM::VLD2LNd16Pseudo:
3874 case ARM::VLD2LNd32Pseudo:
3875 case ARM::VLD2LNq16Pseudo:
3876 case ARM::VLD2LNq32Pseudo:
3877 case ARM::VLD2LNd8Pseudo_UPD:
3878 case ARM::VLD2LNd16Pseudo_UPD:
3879 case ARM::VLD2LNd32Pseudo_UPD:
3880 case ARM::VLD2LNq16Pseudo_UPD:
3881 case ARM::VLD2LNq32Pseudo_UPD:
3882 case ARM::VLD4LNd8Pseudo:
3883 case ARM::VLD4LNd16Pseudo:
3884 case ARM::VLD4LNd32Pseudo:
3885 case ARM::VLD4LNq16Pseudo:
3886 case ARM::VLD4LNq32Pseudo:
3887 case ARM::VLD4LNd8Pseudo_UPD:
3888 case ARM::VLD4LNd16Pseudo_UPD:
3889 case ARM::VLD4LNd32Pseudo_UPD:
3890 case ARM::VLD4LNq16Pseudo_UPD:
3891 case ARM::VLD4LNq32Pseudo_UPD:
3892 // If the address is not 64-bit aligned, the latencies of these
3893 // instructions increases by one.
3901 unsigned ARMBaseInstrInfo::getPredicationCost(const MachineInstr *MI) const {
3902 if (MI->isCopyLike() || MI->isInsertSubreg() ||
3903 MI->isRegSequence() || MI->isImplicitDef())
3909 const MCInstrDesc &MCID = MI->getDesc();
3911 if (MCID.isCall() || MCID.hasImplicitDefOfPhysReg(ARM::CPSR)) {
3912 // When predicated, CPSR is an additional source operand for CPSR updating
3913 // instructions, this apparently increases their latencies.
3919 unsigned ARMBaseInstrInfo::getInstrLatency(const InstrItineraryData *ItinData,
3920 const MachineInstr *MI,
3921 unsigned *PredCost) const {
3922 if (MI->isCopyLike() || MI->isInsertSubreg() ||
3923 MI->isRegSequence() || MI->isImplicitDef())
3926 // An instruction scheduler typically runs on unbundled instructions, however
3927 // other passes may query the latency of a bundled instruction.
3928 if (MI->isBundle()) {
3929 unsigned Latency = 0;
3930 MachineBasicBlock::const_instr_iterator I = MI;
3931 MachineBasicBlock::const_instr_iterator E = MI->getParent()->instr_end();
3932 while (++I != E && I->isInsideBundle()) {
3933 if (I->getOpcode() != ARM::t2IT)
3934 Latency += getInstrLatency(ItinData, I, PredCost);
3939 const MCInstrDesc &MCID = MI->getDesc();
3940 if (PredCost && (MCID.isCall() || MCID.hasImplicitDefOfPhysReg(ARM::CPSR))) {
3941 // When predicated, CPSR is an additional source operand for CPSR updating
3942 // instructions, this apparently increases their latencies.
3945 // Be sure to call getStageLatency for an empty itinerary in case it has a
3946 // valid MinLatency property.
3948 return MI->mayLoad() ? 3 : 1;
3950 unsigned Class = MCID.getSchedClass();
3952 // For instructions with variable uops, use uops as latency.
3953 if (!ItinData->isEmpty() && ItinData->getNumMicroOps(Class) < 0)
3954 return getNumMicroOps(ItinData, MI);
3956 // For the common case, fall back on the itinerary's latency.
3957 unsigned Latency = ItinData->getStageLatency(Class);
3959 // Adjust for dynamic def-side opcode variants not captured by the itinerary.
3960 unsigned DefAlign = MI->hasOneMemOperand()
3961 ? (*MI->memoperands_begin())->getAlignment() : 0;
3962 int Adj = adjustDefLatency(Subtarget, MI, &MCID, DefAlign);
3963 if (Adj >= 0 || (int)Latency > -Adj) {
3964 return Latency + Adj;
3969 int ARMBaseInstrInfo::getInstrLatency(const InstrItineraryData *ItinData,
3970 SDNode *Node) const {
3971 if (!Node->isMachineOpcode())
3974 if (!ItinData || ItinData->isEmpty())
3977 unsigned Opcode = Node->getMachineOpcode();
3980 return ItinData->getStageLatency(get(Opcode).getSchedClass());
3987 bool ARMBaseInstrInfo::
3988 hasHighOperandLatency(const TargetSchedModel &SchedModel,
3989 const MachineRegisterInfo *MRI,
3990 const MachineInstr *DefMI, unsigned DefIdx,
3991 const MachineInstr *UseMI, unsigned UseIdx) const {
3992 unsigned DDomain = DefMI->getDesc().TSFlags & ARMII::DomainMask;
3993 unsigned UDomain = UseMI->getDesc().TSFlags & ARMII::DomainMask;
3994 if (Subtarget.isCortexA8() &&
3995 (DDomain == ARMII::DomainVFP || UDomain == ARMII::DomainVFP))
3996 // CortexA8 VFP instructions are not pipelined.
3999 // Hoist VFP / NEON instructions with 4 or higher latency.
4001 = SchedModel.computeOperandLatency(DefMI, DefIdx, UseMI, UseIdx);
4004 return DDomain == ARMII::DomainVFP || DDomain == ARMII::DomainNEON ||
4005 UDomain == ARMII::DomainVFP || UDomain == ARMII::DomainNEON;
4008 bool ARMBaseInstrInfo::
4009 hasLowDefLatency(const TargetSchedModel &SchedModel,
4010 const MachineInstr *DefMI, unsigned DefIdx) const {
4011 const InstrItineraryData *ItinData = SchedModel.getInstrItineraries();
4012 if (!ItinData || ItinData->isEmpty())
4015 unsigned DDomain = DefMI->getDesc().TSFlags & ARMII::DomainMask;
4016 if (DDomain == ARMII::DomainGeneral) {
4017 unsigned DefClass = DefMI->getDesc().getSchedClass();
4018 int DefCycle = ItinData->getOperandCycle(DefClass, DefIdx);
4019 return (DefCycle != -1 && DefCycle <= 2);
4024 bool ARMBaseInstrInfo::verifyInstruction(const MachineInstr *MI,
4025 StringRef &ErrInfo) const {
4026 if (convertAddSubFlagsOpcode(MI->getOpcode())) {
4027 ErrInfo = "Pseudo flag setting opcodes only exist in Selection DAG";
4033 // LoadStackGuard has so far only been implemented for MachO. Different code
4034 // sequence is needed for other targets.
4035 void ARMBaseInstrInfo::expandLoadStackGuardBase(MachineBasicBlock::iterator MI,
4036 unsigned LoadImmOpc,
4038 Reloc::Model RM) const {
4039 MachineBasicBlock &MBB = *MI->getParent();
4040 DebugLoc DL = MI->getDebugLoc();
4041 unsigned Reg = MI->getOperand(0).getReg();
4042 const GlobalValue *GV =
4043 cast<GlobalValue>((*MI->memoperands_begin())->getValue());
4044 MachineInstrBuilder MIB;
4046 BuildMI(MBB, MI, DL, get(LoadImmOpc), Reg)
4047 .addGlobalAddress(GV, 0, ARMII::MO_NONLAZY);
4049 if (Subtarget.GVIsIndirectSymbol(GV, RM)) {
4050 MIB = BuildMI(MBB, MI, DL, get(LoadOpc), Reg);
4051 MIB.addReg(Reg, RegState::Kill).addImm(0);
4052 unsigned Flag = MachineMemOperand::MOLoad | MachineMemOperand::MOInvariant;
4053 MachineMemOperand *MMO = MBB.getParent()->getMachineMemOperand(
4054 MachinePointerInfo::getGOT(*MBB.getParent()), Flag, 4, 4);
4055 MIB.addMemOperand(MMO);
4056 AddDefaultPred(MIB);
4059 MIB = BuildMI(MBB, MI, DL, get(LoadOpc), Reg);
4060 MIB.addReg(Reg, RegState::Kill).addImm(0);
4061 MIB.setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
4062 AddDefaultPred(MIB);
4066 ARMBaseInstrInfo::isFpMLxInstruction(unsigned Opcode, unsigned &MulOpc,
4067 unsigned &AddSubOpc,
4068 bool &NegAcc, bool &HasLane) const {
4069 DenseMap<unsigned, unsigned>::const_iterator I = MLxEntryMap.find(Opcode);
4070 if (I == MLxEntryMap.end())
4073 const ARM_MLxEntry &Entry = ARM_MLxTable[I->second];
4074 MulOpc = Entry.MulOpc;
4075 AddSubOpc = Entry.AddSubOpc;
4076 NegAcc = Entry.NegAcc;
4077 HasLane = Entry.HasLane;
4081 //===----------------------------------------------------------------------===//
4082 // Execution domains.
4083 //===----------------------------------------------------------------------===//
4085 // Some instructions go down the NEON pipeline, some go down the VFP pipeline,
4086 // and some can go down both. The vmov instructions go down the VFP pipeline,
4087 // but they can be changed to vorr equivalents that are executed by the NEON
4090 // We use the following execution domain numbering:
4098 // Also see ARMInstrFormats.td and Domain* enums in ARMBaseInfo.h
4100 std::pair<uint16_t, uint16_t>
4101 ARMBaseInstrInfo::getExecutionDomain(const MachineInstr *MI) const {
4102 // If we don't have access to NEON instructions then we won't be able
4103 // to swizzle anything to the NEON domain. Check to make sure.
4104 if (Subtarget.hasNEON()) {
4105 // VMOVD, VMOVRS and VMOVSR are VFP instructions, but can be changed to NEON
4106 // if they are not predicated.
4107 if (MI->getOpcode() == ARM::VMOVD && !isPredicated(MI))
4108 return std::make_pair(ExeVFP, (1 << ExeVFP) | (1 << ExeNEON));
4110 // CortexA9 is particularly picky about mixing the two and wants these
4112 if (Subtarget.isCortexA9() && !isPredicated(MI) &&
4113 (MI->getOpcode() == ARM::VMOVRS || MI->getOpcode() == ARM::VMOVSR ||
4114 MI->getOpcode() == ARM::VMOVS))
4115 return std::make_pair(ExeVFP, (1 << ExeVFP) | (1 << ExeNEON));
4117 // No other instructions can be swizzled, so just determine their domain.
4118 unsigned Domain = MI->getDesc().TSFlags & ARMII::DomainMask;
4120 if (Domain & ARMII::DomainNEON)
4121 return std::make_pair(ExeNEON, 0);
4123 // Certain instructions can go either way on Cortex-A8.
4124 // Treat them as NEON instructions.
4125 if ((Domain & ARMII::DomainNEONA8) && Subtarget.isCortexA8())
4126 return std::make_pair(ExeNEON, 0);
4128 if (Domain & ARMII::DomainVFP)
4129 return std::make_pair(ExeVFP, 0);
4131 return std::make_pair(ExeGeneric, 0);
4134 static unsigned getCorrespondingDRegAndLane(const TargetRegisterInfo *TRI,
4135 unsigned SReg, unsigned &Lane) {
4136 unsigned DReg = TRI->getMatchingSuperReg(SReg, ARM::ssub_0, &ARM::DPRRegClass);
4139 if (DReg != ARM::NoRegister)
4143 DReg = TRI->getMatchingSuperReg(SReg, ARM::ssub_1, &ARM::DPRRegClass);
4145 assert(DReg && "S-register with no D super-register?");
4149 /// getImplicitSPRUseForDPRUse - Given a use of a DPR register and lane,
4150 /// set ImplicitSReg to a register number that must be marked as implicit-use or
4151 /// zero if no register needs to be defined as implicit-use.
4153 /// If the function cannot determine if an SPR should be marked implicit use or
4154 /// not, it returns false.
4156 /// This function handles cases where an instruction is being modified from taking
4157 /// an SPR to a DPR[Lane]. A use of the DPR is being added, which may conflict
4158 /// with an earlier def of an SPR corresponding to DPR[Lane^1] (i.e. the other
4159 /// lane of the DPR).
4161 /// If the other SPR is defined, an implicit-use of it should be added. Else,
4162 /// (including the case where the DPR itself is defined), it should not.
4164 static bool getImplicitSPRUseForDPRUse(const TargetRegisterInfo *TRI,
4166 unsigned DReg, unsigned Lane,
4167 unsigned &ImplicitSReg) {
4168 // If the DPR is defined or used already, the other SPR lane will be chained
4169 // correctly, so there is nothing to be done.
4170 if (MI->definesRegister(DReg, TRI) || MI->readsRegister(DReg, TRI)) {
4175 // Otherwise we need to go searching to see if the SPR is set explicitly.
4176 ImplicitSReg = TRI->getSubReg(DReg,
4177 (Lane & 1) ? ARM::ssub_0 : ARM::ssub_1);
4178 MachineBasicBlock::LivenessQueryResult LQR =
4179 MI->getParent()->computeRegisterLiveness(TRI, ImplicitSReg, MI);
4181 if (LQR == MachineBasicBlock::LQR_Live)
4183 else if (LQR == MachineBasicBlock::LQR_Unknown)
4186 // If the register is known not to be live, there is no need to add an
4193 ARMBaseInstrInfo::setExecutionDomain(MachineInstr *MI, unsigned Domain) const {
4194 unsigned DstReg, SrcReg, DReg;
4196 MachineInstrBuilder MIB(*MI->getParent()->getParent(), MI);
4197 const TargetRegisterInfo *TRI = &getRegisterInfo();
4198 switch (MI->getOpcode()) {
4200 llvm_unreachable("cannot handle opcode!");
4203 if (Domain != ExeNEON)
4206 // Zap the predicate operands.
4207 assert(!isPredicated(MI) && "Cannot predicate a VORRd");
4209 // Make sure we've got NEON instructions.
4210 assert(Subtarget.hasNEON() && "VORRd requires NEON");
4212 // Source instruction is %DDst = VMOVD %DSrc, 14, %noreg (; implicits)
4213 DstReg = MI->getOperand(0).getReg();
4214 SrcReg = MI->getOperand(1).getReg();
4216 for (unsigned i = MI->getDesc().getNumOperands(); i; --i)
4217 MI->RemoveOperand(i-1);
4219 // Change to a %DDst = VORRd %DSrc, %DSrc, 14, %noreg (; implicits)
4220 MI->setDesc(get(ARM::VORRd));
4221 AddDefaultPred(MIB.addReg(DstReg, RegState::Define)
4226 if (Domain != ExeNEON)
4228 assert(!isPredicated(MI) && "Cannot predicate a VGETLN");
4230 // Source instruction is %RDst = VMOVRS %SSrc, 14, %noreg (; implicits)
4231 DstReg = MI->getOperand(0).getReg();
4232 SrcReg = MI->getOperand(1).getReg();
4234 for (unsigned i = MI->getDesc().getNumOperands(); i; --i)
4235 MI->RemoveOperand(i-1);
4237 DReg = getCorrespondingDRegAndLane(TRI, SrcReg, Lane);
4239 // Convert to %RDst = VGETLNi32 %DSrc, Lane, 14, %noreg (; imps)
4240 // Note that DSrc has been widened and the other lane may be undef, which
4241 // contaminates the entire register.
4242 MI->setDesc(get(ARM::VGETLNi32));
4243 AddDefaultPred(MIB.addReg(DstReg, RegState::Define)
4244 .addReg(DReg, RegState::Undef)
4247 // The old source should be an implicit use, otherwise we might think it
4248 // was dead before here.
4249 MIB.addReg(SrcReg, RegState::Implicit);
4252 if (Domain != ExeNEON)
4254 assert(!isPredicated(MI) && "Cannot predicate a VSETLN");
4256 // Source instruction is %SDst = VMOVSR %RSrc, 14, %noreg (; implicits)
4257 DstReg = MI->getOperand(0).getReg();
4258 SrcReg = MI->getOperand(1).getReg();
4260 DReg = getCorrespondingDRegAndLane(TRI, DstReg, Lane);
4262 unsigned ImplicitSReg;
4263 if (!getImplicitSPRUseForDPRUse(TRI, MI, DReg, Lane, ImplicitSReg))
4266 for (unsigned i = MI->getDesc().getNumOperands(); i; --i)
4267 MI->RemoveOperand(i-1);
4269 // Convert to %DDst = VSETLNi32 %DDst, %RSrc, Lane, 14, %noreg (; imps)
4270 // Again DDst may be undefined at the beginning of this instruction.
4271 MI->setDesc(get(ARM::VSETLNi32));
4272 MIB.addReg(DReg, RegState::Define)
4273 .addReg(DReg, getUndefRegState(!MI->readsRegister(DReg, TRI)))
4276 AddDefaultPred(MIB);
4278 // The narrower destination must be marked as set to keep previous chains
4280 MIB.addReg(DstReg, RegState::Define | RegState::Implicit);
4281 if (ImplicitSReg != 0)
4282 MIB.addReg(ImplicitSReg, RegState::Implicit);
4286 if (Domain != ExeNEON)
4289 // Source instruction is %SDst = VMOVS %SSrc, 14, %noreg (; implicits)
4290 DstReg = MI->getOperand(0).getReg();
4291 SrcReg = MI->getOperand(1).getReg();
4293 unsigned DstLane = 0, SrcLane = 0, DDst, DSrc;
4294 DDst = getCorrespondingDRegAndLane(TRI, DstReg, DstLane);
4295 DSrc = getCorrespondingDRegAndLane(TRI, SrcReg, SrcLane);
4297 unsigned ImplicitSReg;
4298 if (!getImplicitSPRUseForDPRUse(TRI, MI, DSrc, SrcLane, ImplicitSReg))
4301 for (unsigned i = MI->getDesc().getNumOperands(); i; --i)
4302 MI->RemoveOperand(i-1);
4305 // Destination can be:
4306 // %DDst = VDUPLN32d %DDst, Lane, 14, %noreg (; implicits)
4307 MI->setDesc(get(ARM::VDUPLN32d));
4308 MIB.addReg(DDst, RegState::Define)
4309 .addReg(DDst, getUndefRegState(!MI->readsRegister(DDst, TRI)))
4311 AddDefaultPred(MIB);
4313 // Neither the source or the destination are naturally represented any
4314 // more, so add them in manually.
4315 MIB.addReg(DstReg, RegState::Implicit | RegState::Define);
4316 MIB.addReg(SrcReg, RegState::Implicit);
4317 if (ImplicitSReg != 0)
4318 MIB.addReg(ImplicitSReg, RegState::Implicit);
4322 // In general there's no single instruction that can perform an S <-> S
4323 // move in NEON space, but a pair of VEXT instructions *can* do the
4324 // job. It turns out that the VEXTs needed will only use DSrc once, with
4325 // the position based purely on the combination of lane-0 and lane-1
4326 // involved. For example
4327 // vmov s0, s2 -> vext.32 d0, d0, d1, #1 vext.32 d0, d0, d0, #1
4328 // vmov s1, s3 -> vext.32 d0, d1, d0, #1 vext.32 d0, d0, d0, #1
4329 // vmov s0, s3 -> vext.32 d0, d0, d0, #1 vext.32 d0, d1, d0, #1
4330 // vmov s1, s2 -> vext.32 d0, d0, d0, #1 vext.32 d0, d0, d1, #1
4332 // Pattern of the MachineInstrs is:
4333 // %DDst = VEXTd32 %DSrc1, %DSrc2, Lane, 14, %noreg (;implicits)
4334 MachineInstrBuilder NewMIB;
4335 NewMIB = BuildMI(*MI->getParent(), MI, MI->getDebugLoc(),
4336 get(ARM::VEXTd32), DDst);
4338 // On the first instruction, both DSrc and DDst may be <undef> if present.
4339 // Specifically when the original instruction didn't have them as an
4341 unsigned CurReg = SrcLane == 1 && DstLane == 1 ? DSrc : DDst;
4342 bool CurUndef = !MI->readsRegister(CurReg, TRI);
4343 NewMIB.addReg(CurReg, getUndefRegState(CurUndef));
4345 CurReg = SrcLane == 0 && DstLane == 0 ? DSrc : DDst;
4346 CurUndef = !MI->readsRegister(CurReg, TRI);
4347 NewMIB.addReg(CurReg, getUndefRegState(CurUndef));
4350 AddDefaultPred(NewMIB);
4352 if (SrcLane == DstLane)
4353 NewMIB.addReg(SrcReg, RegState::Implicit);
4355 MI->setDesc(get(ARM::VEXTd32));
4356 MIB.addReg(DDst, RegState::Define);
4358 // On the second instruction, DDst has definitely been defined above, so
4359 // it is not <undef>. DSrc, if present, can be <undef> as above.
4360 CurReg = SrcLane == 1 && DstLane == 0 ? DSrc : DDst;
4361 CurUndef = CurReg == DSrc && !MI->readsRegister(CurReg, TRI);
4362 MIB.addReg(CurReg, getUndefRegState(CurUndef));
4364 CurReg = SrcLane == 0 && DstLane == 1 ? DSrc : DDst;
4365 CurUndef = CurReg == DSrc && !MI->readsRegister(CurReg, TRI);
4366 MIB.addReg(CurReg, getUndefRegState(CurUndef));
4369 AddDefaultPred(MIB);
4371 if (SrcLane != DstLane)
4372 MIB.addReg(SrcReg, RegState::Implicit);
4374 // As before, the original destination is no longer represented, add it
4376 MIB.addReg(DstReg, RegState::Define | RegState::Implicit);
4377 if (ImplicitSReg != 0)
4378 MIB.addReg(ImplicitSReg, RegState::Implicit);
4385 //===----------------------------------------------------------------------===//
4386 // Partial register updates
4387 //===----------------------------------------------------------------------===//
4389 // Swift renames NEON registers with 64-bit granularity. That means any
4390 // instruction writing an S-reg implicitly reads the containing D-reg. The
4391 // problem is mostly avoided by translating f32 operations to v2f32 operations
4392 // on D-registers, but f32 loads are still a problem.
4394 // These instructions can load an f32 into a NEON register:
4396 // VLDRS - Only writes S, partial D update.
4397 // VLD1LNd32 - Writes all D-regs, explicit partial D update, 2 uops.
4398 // VLD1DUPd32 - Writes all D-regs, no partial reg update, 2 uops.
4400 // FCONSTD can be used as a dependency-breaking instruction.
4401 unsigned ARMBaseInstrInfo::
4402 getPartialRegUpdateClearance(const MachineInstr *MI,
4404 const TargetRegisterInfo *TRI) const {
4405 if (!SwiftPartialUpdateClearance ||
4406 !(Subtarget.isSwift() || Subtarget.isCortexA15()))
4409 assert(TRI && "Need TRI instance");
4411 const MachineOperand &MO = MI->getOperand(OpNum);
4414 unsigned Reg = MO.getReg();
4417 switch(MI->getOpcode()) {
4418 // Normal instructions writing only an S-register.
4423 case ARM::VMOVv4i16:
4424 case ARM::VMOVv2i32:
4425 case ARM::VMOVv2f32:
4426 case ARM::VMOVv1i64:
4427 UseOp = MI->findRegisterUseOperandIdx(Reg, false, TRI);
4430 // Explicitly reads the dependency.
4431 case ARM::VLD1LNd32:
4438 // If this instruction actually reads a value from Reg, there is no unwanted
4440 if (UseOp != -1 && MI->getOperand(UseOp).readsReg())
4443 // We must be able to clobber the whole D-reg.
4444 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
4445 // Virtual register must be a foo:ssub_0<def,undef> operand.
4446 if (!MO.getSubReg() || MI->readsVirtualRegister(Reg))
4448 } else if (ARM::SPRRegClass.contains(Reg)) {
4449 // Physical register: MI must define the full D-reg.
4450 unsigned DReg = TRI->getMatchingSuperReg(Reg, ARM::ssub_0,
4452 if (!DReg || !MI->definesRegister(DReg, TRI))
4456 // MI has an unwanted D-register dependency.
4457 // Avoid defs in the previous N instructrions.
4458 return SwiftPartialUpdateClearance;
4461 // Break a partial register dependency after getPartialRegUpdateClearance
4462 // returned non-zero.
4463 void ARMBaseInstrInfo::
4464 breakPartialRegDependency(MachineBasicBlock::iterator MI,
4466 const TargetRegisterInfo *TRI) const {
4467 assert(MI && OpNum < MI->getDesc().getNumDefs() && "OpNum is not a def");
4468 assert(TRI && "Need TRI instance");
4470 const MachineOperand &MO = MI->getOperand(OpNum);
4471 unsigned Reg = MO.getReg();
4472 assert(TargetRegisterInfo::isPhysicalRegister(Reg) &&
4473 "Can't break virtual register dependencies.");
4474 unsigned DReg = Reg;
4476 // If MI defines an S-reg, find the corresponding D super-register.
4477 if (ARM::SPRRegClass.contains(Reg)) {
4478 DReg = ARM::D0 + (Reg - ARM::S0) / 2;
4479 assert(TRI->isSuperRegister(Reg, DReg) && "Register enums broken");
4482 assert(ARM::DPRRegClass.contains(DReg) && "Can only break D-reg deps");
4483 assert(MI->definesRegister(DReg, TRI) && "MI doesn't clobber full D-reg");
4485 // FIXME: In some cases, VLDRS can be changed to a VLD1DUPd32 which defines
4486 // the full D-register by loading the same value to both lanes. The
4487 // instruction is micro-coded with 2 uops, so don't do this until we can
4488 // properly schedule micro-coded instructions. The dispatcher stalls cause
4489 // too big regressions.
4491 // Insert the dependency-breaking FCONSTD before MI.
4492 // 96 is the encoding of 0.5, but the actual value doesn't matter here.
4493 AddDefaultPred(BuildMI(*MI->getParent(), MI, MI->getDebugLoc(),
4494 get(ARM::FCONSTD), DReg).addImm(96));
4495 MI->addRegisterKilled(DReg, TRI, true);
4498 bool ARMBaseInstrInfo::hasNOP() const {
4499 return Subtarget.getFeatureBits()[ARM::HasV6KOps];
4502 bool ARMBaseInstrInfo::isSwiftFastImmShift(const MachineInstr *MI) const {
4503 if (MI->getNumOperands() < 4)
4505 unsigned ShOpVal = MI->getOperand(3).getImm();
4506 unsigned ShImm = ARM_AM::getSORegOffset(ShOpVal);
4507 // Swift supports faster shifts for: lsl 2, lsl 1, and lsr 1.
4508 if ((ShImm == 1 && ARM_AM::getSORegShOp(ShOpVal) == ARM_AM::lsr) ||
4509 ((ShImm == 1 || ShImm == 2) &&
4510 ARM_AM::getSORegShOp(ShOpVal) == ARM_AM::lsl))
4516 bool ARMBaseInstrInfo::getRegSequenceLikeInputs(
4517 const MachineInstr &MI, unsigned DefIdx,
4518 SmallVectorImpl<RegSubRegPairAndIdx> &InputRegs) const {
4519 assert(DefIdx < MI.getDesc().getNumDefs() && "Invalid definition index");
4520 assert(MI.isRegSequenceLike() && "Invalid kind of instruction");
4522 switch (MI.getOpcode()) {
4524 // dX = VMOVDRR rY, rZ
4526 // dX = REG_SEQUENCE rY, ssub_0, rZ, ssub_1
4527 // Populate the InputRegs accordingly.
4529 const MachineOperand *MOReg = &MI.getOperand(1);
4530 InputRegs.push_back(
4531 RegSubRegPairAndIdx(MOReg->getReg(), MOReg->getSubReg(), ARM::ssub_0));
4533 MOReg = &MI.getOperand(2);
4534 InputRegs.push_back(
4535 RegSubRegPairAndIdx(MOReg->getReg(), MOReg->getSubReg(), ARM::ssub_1));
4538 llvm_unreachable("Target dependent opcode missing");
4541 bool ARMBaseInstrInfo::getExtractSubregLikeInputs(
4542 const MachineInstr &MI, unsigned DefIdx,
4543 RegSubRegPairAndIdx &InputReg) const {
4544 assert(DefIdx < MI.getDesc().getNumDefs() && "Invalid definition index");
4545 assert(MI.isExtractSubregLike() && "Invalid kind of instruction");
4547 switch (MI.getOpcode()) {
4549 // rX, rY = VMOVRRD dZ
4551 // rX = EXTRACT_SUBREG dZ, ssub_0
4552 // rY = EXTRACT_SUBREG dZ, ssub_1
4553 const MachineOperand &MOReg = MI.getOperand(2);
4554 InputReg.Reg = MOReg.getReg();
4555 InputReg.SubReg = MOReg.getSubReg();
4556 InputReg.SubIdx = DefIdx == 0 ? ARM::ssub_0 : ARM::ssub_1;
4559 llvm_unreachable("Target dependent opcode missing");
4562 bool ARMBaseInstrInfo::getInsertSubregLikeInputs(
4563 const MachineInstr &MI, unsigned DefIdx, RegSubRegPair &BaseReg,
4564 RegSubRegPairAndIdx &InsertedReg) const {
4565 assert(DefIdx < MI.getDesc().getNumDefs() && "Invalid definition index");
4566 assert(MI.isInsertSubregLike() && "Invalid kind of instruction");
4568 switch (MI.getOpcode()) {
4569 case ARM::VSETLNi32:
4570 // dX = VSETLNi32 dY, rZ, imm
4571 const MachineOperand &MOBaseReg = MI.getOperand(1);
4572 const MachineOperand &MOInsertedReg = MI.getOperand(2);
4573 const MachineOperand &MOIndex = MI.getOperand(3);
4574 BaseReg.Reg = MOBaseReg.getReg();
4575 BaseReg.SubReg = MOBaseReg.getSubReg();
4577 InsertedReg.Reg = MOInsertedReg.getReg();
4578 InsertedReg.SubReg = MOInsertedReg.getSubReg();
4579 InsertedReg.SubIdx = MOIndex.getImm() == 0 ? ARM::ssub_0 : ARM::ssub_1;
4582 llvm_unreachable("Target dependent opcode missing");