1 //===-- ARMBaseInstrInfo.cpp - ARM Instruction Information ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Base ARM implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
15 #include "ARMBaseInstrInfo.h"
16 #include "ARMBaseRegisterInfo.h"
17 #include "ARMConstantPoolValue.h"
18 #include "ARMFeatures.h"
19 #include "ARMHazardRecognizer.h"
20 #include "ARMMachineFunctionInfo.h"
21 #include "MCTargetDesc/ARMAddressingModes.h"
22 #include "llvm/ADT/STLExtras.h"
23 #include "llvm/CodeGen/LiveVariables.h"
24 #include "llvm/CodeGen/MachineConstantPool.h"
25 #include "llvm/CodeGen/MachineFrameInfo.h"
26 #include "llvm/CodeGen/MachineInstrBuilder.h"
27 #include "llvm/CodeGen/MachineJumpTableInfo.h"
28 #include "llvm/CodeGen/MachineMemOperand.h"
29 #include "llvm/CodeGen/MachineRegisterInfo.h"
30 #include "llvm/CodeGen/SelectionDAGNodes.h"
31 #include "llvm/IR/Constants.h"
32 #include "llvm/IR/Function.h"
33 #include "llvm/IR/GlobalValue.h"
34 #include "llvm/MC/MCAsmInfo.h"
35 #include "llvm/MC/MCExpr.h"
36 #include "llvm/Support/BranchProbability.h"
37 #include "llvm/Support/CommandLine.h"
38 #include "llvm/Support/Debug.h"
39 #include "llvm/Support/ErrorHandling.h"
40 #include "llvm/Support/raw_ostream.h"
44 #define DEBUG_TYPE "arm-instrinfo"
46 #define GET_INSTRINFO_CTOR_DTOR
47 #include "ARMGenInstrInfo.inc"
50 EnableARM3Addr("enable-arm-3-addr-conv", cl::Hidden,
51 cl::desc("Enable ARM 2-addr to 3-addr conv"));
54 WidenVMOVS("widen-vmovs", cl::Hidden, cl::init(true),
55 cl::desc("Widen ARM vmovs to vmovd when possible"));
57 static cl::opt<unsigned>
58 SwiftPartialUpdateClearance("swift-partial-update-clearance",
59 cl::Hidden, cl::init(12),
60 cl::desc("Clearance before partial register updates"));
62 /// ARM_MLxEntry - Record information about MLA / MLS instructions.
64 uint16_t MLxOpc; // MLA / MLS opcode
65 uint16_t MulOpc; // Expanded multiplication opcode
66 uint16_t AddSubOpc; // Expanded add / sub opcode
67 bool NegAcc; // True if the acc is negated before the add / sub.
68 bool HasLane; // True if instruction has an extra "lane" operand.
71 static const ARM_MLxEntry ARM_MLxTable[] = {
72 // MLxOpc, MulOpc, AddSubOpc, NegAcc, HasLane
74 { ARM::VMLAS, ARM::VMULS, ARM::VADDS, false, false },
75 { ARM::VMLSS, ARM::VMULS, ARM::VSUBS, false, false },
76 { ARM::VMLAD, ARM::VMULD, ARM::VADDD, false, false },
77 { ARM::VMLSD, ARM::VMULD, ARM::VSUBD, false, false },
78 { ARM::VNMLAS, ARM::VNMULS, ARM::VSUBS, true, false },
79 { ARM::VNMLSS, ARM::VMULS, ARM::VSUBS, true, false },
80 { ARM::VNMLAD, ARM::VNMULD, ARM::VSUBD, true, false },
81 { ARM::VNMLSD, ARM::VMULD, ARM::VSUBD, true, false },
84 { ARM::VMLAfd, ARM::VMULfd, ARM::VADDfd, false, false },
85 { ARM::VMLSfd, ARM::VMULfd, ARM::VSUBfd, false, false },
86 { ARM::VMLAfq, ARM::VMULfq, ARM::VADDfq, false, false },
87 { ARM::VMLSfq, ARM::VMULfq, ARM::VSUBfq, false, false },
88 { ARM::VMLAslfd, ARM::VMULslfd, ARM::VADDfd, false, true },
89 { ARM::VMLSslfd, ARM::VMULslfd, ARM::VSUBfd, false, true },
90 { ARM::VMLAslfq, ARM::VMULslfq, ARM::VADDfq, false, true },
91 { ARM::VMLSslfq, ARM::VMULslfq, ARM::VSUBfq, false, true },
94 ARMBaseInstrInfo::ARMBaseInstrInfo(const ARMSubtarget& STI)
95 : ARMGenInstrInfo(ARM::ADJCALLSTACKDOWN, ARM::ADJCALLSTACKUP),
97 for (unsigned i = 0, e = array_lengthof(ARM_MLxTable); i != e; ++i) {
98 if (!MLxEntryMap.insert(std::make_pair(ARM_MLxTable[i].MLxOpc, i)).second)
99 assert(false && "Duplicated entries?");
100 MLxHazardOpcodes.insert(ARM_MLxTable[i].AddSubOpc);
101 MLxHazardOpcodes.insert(ARM_MLxTable[i].MulOpc);
105 // Use a ScoreboardHazardRecognizer for prepass ARM scheduling. TargetInstrImpl
106 // currently defaults to no prepass hazard recognizer.
107 ScheduleHazardRecognizer *
108 ARMBaseInstrInfo::CreateTargetHazardRecognizer(const TargetSubtargetInfo *STI,
109 const ScheduleDAG *DAG) const {
110 if (usePreRAHazardRecognizer()) {
111 const InstrItineraryData *II =
112 static_cast<const ARMSubtarget *>(STI)->getInstrItineraryData();
113 return new ScoreboardHazardRecognizer(II, DAG, "pre-RA-sched");
115 return TargetInstrInfo::CreateTargetHazardRecognizer(STI, DAG);
118 ScheduleHazardRecognizer *ARMBaseInstrInfo::
119 CreateTargetPostRAHazardRecognizer(const InstrItineraryData *II,
120 const ScheduleDAG *DAG) const {
121 if (Subtarget.isThumb2() || Subtarget.hasVFP2())
122 return (ScheduleHazardRecognizer *)new ARMHazardRecognizer(II, DAG);
123 return TargetInstrInfo::CreateTargetPostRAHazardRecognizer(II, DAG);
127 ARMBaseInstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
128 MachineBasicBlock::iterator &MBBI,
129 LiveVariables *LV) const {
130 // FIXME: Thumb2 support.
135 MachineInstr *MI = MBBI;
136 MachineFunction &MF = *MI->getParent()->getParent();
137 uint64_t TSFlags = MI->getDesc().TSFlags;
139 switch ((TSFlags & ARMII::IndexModeMask) >> ARMII::IndexModeShift) {
140 default: return nullptr;
141 case ARMII::IndexModePre:
144 case ARMII::IndexModePost:
148 // Try splitting an indexed load/store to an un-indexed one plus an add/sub
150 unsigned MemOpc = getUnindexedOpcode(MI->getOpcode());
154 MachineInstr *UpdateMI = nullptr;
155 MachineInstr *MemMI = nullptr;
156 unsigned AddrMode = (TSFlags & ARMII::AddrModeMask);
157 const MCInstrDesc &MCID = MI->getDesc();
158 unsigned NumOps = MCID.getNumOperands();
159 bool isLoad = !MI->mayStore();
160 const MachineOperand &WB = isLoad ? MI->getOperand(1) : MI->getOperand(0);
161 const MachineOperand &Base = MI->getOperand(2);
162 const MachineOperand &Offset = MI->getOperand(NumOps-3);
163 unsigned WBReg = WB.getReg();
164 unsigned BaseReg = Base.getReg();
165 unsigned OffReg = Offset.getReg();
166 unsigned OffImm = MI->getOperand(NumOps-2).getImm();
167 ARMCC::CondCodes Pred = (ARMCC::CondCodes)MI->getOperand(NumOps-1).getImm();
169 default: llvm_unreachable("Unknown indexed op!");
170 case ARMII::AddrMode2: {
171 bool isSub = ARM_AM::getAM2Op(OffImm) == ARM_AM::sub;
172 unsigned Amt = ARM_AM::getAM2Offset(OffImm);
174 if (ARM_AM::getSOImmVal(Amt) == -1)
175 // Can't encode it in a so_imm operand. This transformation will
176 // add more than 1 instruction. Abandon!
178 UpdateMI = BuildMI(MF, MI->getDebugLoc(),
179 get(isSub ? ARM::SUBri : ARM::ADDri), WBReg)
180 .addReg(BaseReg).addImm(Amt)
181 .addImm(Pred).addReg(0).addReg(0);
182 } else if (Amt != 0) {
183 ARM_AM::ShiftOpc ShOpc = ARM_AM::getAM2ShiftOpc(OffImm);
184 unsigned SOOpc = ARM_AM::getSORegOpc(ShOpc, Amt);
185 UpdateMI = BuildMI(MF, MI->getDebugLoc(),
186 get(isSub ? ARM::SUBrsi : ARM::ADDrsi), WBReg)
187 .addReg(BaseReg).addReg(OffReg).addReg(0).addImm(SOOpc)
188 .addImm(Pred).addReg(0).addReg(0);
190 UpdateMI = BuildMI(MF, MI->getDebugLoc(),
191 get(isSub ? ARM::SUBrr : ARM::ADDrr), WBReg)
192 .addReg(BaseReg).addReg(OffReg)
193 .addImm(Pred).addReg(0).addReg(0);
196 case ARMII::AddrMode3 : {
197 bool isSub = ARM_AM::getAM3Op(OffImm) == ARM_AM::sub;
198 unsigned Amt = ARM_AM::getAM3Offset(OffImm);
200 // Immediate is 8-bits. It's guaranteed to fit in a so_imm operand.
201 UpdateMI = BuildMI(MF, MI->getDebugLoc(),
202 get(isSub ? ARM::SUBri : ARM::ADDri), WBReg)
203 .addReg(BaseReg).addImm(Amt)
204 .addImm(Pred).addReg(0).addReg(0);
206 UpdateMI = BuildMI(MF, MI->getDebugLoc(),
207 get(isSub ? ARM::SUBrr : ARM::ADDrr), WBReg)
208 .addReg(BaseReg).addReg(OffReg)
209 .addImm(Pred).addReg(0).addReg(0);
214 std::vector<MachineInstr*> NewMIs;
217 MemMI = BuildMI(MF, MI->getDebugLoc(),
218 get(MemOpc), MI->getOperand(0).getReg())
219 .addReg(WBReg).addImm(0).addImm(Pred);
221 MemMI = BuildMI(MF, MI->getDebugLoc(),
222 get(MemOpc)).addReg(MI->getOperand(1).getReg())
223 .addReg(WBReg).addReg(0).addImm(0).addImm(Pred);
224 NewMIs.push_back(MemMI);
225 NewMIs.push_back(UpdateMI);
228 MemMI = BuildMI(MF, MI->getDebugLoc(),
229 get(MemOpc), MI->getOperand(0).getReg())
230 .addReg(BaseReg).addImm(0).addImm(Pred);
232 MemMI = BuildMI(MF, MI->getDebugLoc(),
233 get(MemOpc)).addReg(MI->getOperand(1).getReg())
234 .addReg(BaseReg).addReg(0).addImm(0).addImm(Pred);
236 UpdateMI->getOperand(0).setIsDead();
237 NewMIs.push_back(UpdateMI);
238 NewMIs.push_back(MemMI);
241 // Transfer LiveVariables states, kill / dead info.
243 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
244 MachineOperand &MO = MI->getOperand(i);
245 if (MO.isReg() && TargetRegisterInfo::isVirtualRegister(MO.getReg())) {
246 unsigned Reg = MO.getReg();
248 LiveVariables::VarInfo &VI = LV->getVarInfo(Reg);
250 MachineInstr *NewMI = (Reg == WBReg) ? UpdateMI : MemMI;
252 LV->addVirtualRegisterDead(Reg, NewMI);
254 if (MO.isUse() && MO.isKill()) {
255 for (unsigned j = 0; j < 2; ++j) {
256 // Look at the two new MI's in reverse order.
257 MachineInstr *NewMI = NewMIs[j];
258 if (!NewMI->readsRegister(Reg))
260 LV->addVirtualRegisterKilled(Reg, NewMI);
261 if (VI.removeKill(MI))
262 VI.Kills.push_back(NewMI);
270 MFI->insert(MBBI, NewMIs[1]);
271 MFI->insert(MBBI, NewMIs[0]);
277 ARMBaseInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB,
278 MachineBasicBlock *&FBB,
279 SmallVectorImpl<MachineOperand> &Cond,
280 bool AllowModify) const {
284 MachineBasicBlock::iterator I = MBB.end();
285 if (I == MBB.begin())
286 return false; // Empty blocks are easy.
289 // Walk backwards from the end of the basic block until the branch is
290 // analyzed or we give up.
291 while (isPredicated(I) || I->isTerminator() || I->isDebugValue()) {
293 // Flag to be raised on unanalyzeable instructions. This is useful in cases
294 // where we want to clean up on the end of the basic block before we bail
296 bool CantAnalyze = false;
298 // Skip over DEBUG values and predicated nonterminators.
299 while (I->isDebugValue() || !I->isTerminator()) {
300 if (I == MBB.begin())
305 if (isIndirectBranchOpcode(I->getOpcode()) ||
306 isJumpTableBranchOpcode(I->getOpcode())) {
307 // Indirect branches and jump tables can't be analyzed, but we still want
308 // to clean up any instructions at the tail of the basic block.
310 } else if (isUncondBranchOpcode(I->getOpcode())) {
311 TBB = I->getOperand(0).getMBB();
312 } else if (isCondBranchOpcode(I->getOpcode())) {
313 // Bail out if we encounter multiple conditional branches.
317 assert(!FBB && "FBB should have been null.");
319 TBB = I->getOperand(0).getMBB();
320 Cond.push_back(I->getOperand(1));
321 Cond.push_back(I->getOperand(2));
322 } else if (I->isReturn()) {
323 // Returns can't be analyzed, but we should run cleanup.
324 CantAnalyze = !isPredicated(I);
326 // We encountered other unrecognized terminator. Bail out immediately.
330 // Cleanup code - to be run for unpredicated unconditional branches and
332 if (!isPredicated(I) &&
333 (isUncondBranchOpcode(I->getOpcode()) ||
334 isIndirectBranchOpcode(I->getOpcode()) ||
335 isJumpTableBranchOpcode(I->getOpcode()) ||
337 // Forget any previous condition branch information - it no longer applies.
341 // If we can modify the function, delete everything below this
342 // unconditional branch.
344 MachineBasicBlock::iterator DI = std::next(I);
345 while (DI != MBB.end()) {
346 MachineInstr *InstToDelete = DI;
348 InstToDelete->eraseFromParent();
356 if (I == MBB.begin())
362 // We made it past the terminators without bailing out - we must have
363 // analyzed this branch successfully.
368 unsigned ARMBaseInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
369 MachineBasicBlock::iterator I = MBB.end();
370 if (I == MBB.begin()) return 0;
372 while (I->isDebugValue()) {
373 if (I == MBB.begin())
377 if (!isUncondBranchOpcode(I->getOpcode()) &&
378 !isCondBranchOpcode(I->getOpcode()))
381 // Remove the branch.
382 I->eraseFromParent();
386 if (I == MBB.begin()) return 1;
388 if (!isCondBranchOpcode(I->getOpcode()))
391 // Remove the branch.
392 I->eraseFromParent();
397 ARMBaseInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
398 MachineBasicBlock *FBB,
399 const SmallVectorImpl<MachineOperand> &Cond,
401 ARMFunctionInfo *AFI = MBB.getParent()->getInfo<ARMFunctionInfo>();
402 int BOpc = !AFI->isThumbFunction()
403 ? ARM::B : (AFI->isThumb2Function() ? ARM::t2B : ARM::tB);
404 int BccOpc = !AFI->isThumbFunction()
405 ? ARM::Bcc : (AFI->isThumb2Function() ? ARM::t2Bcc : ARM::tBcc);
406 bool isThumb = AFI->isThumbFunction() || AFI->isThumb2Function();
408 // Shouldn't be a fall through.
409 assert(TBB && "InsertBranch must not be told to insert a fallthrough");
410 assert((Cond.size() == 2 || Cond.size() == 0) &&
411 "ARM branch conditions have two components!");
413 // For conditional branches, we use addOperand to preserve CPSR flags.
416 if (Cond.empty()) { // Unconditional branch?
418 BuildMI(&MBB, DL, get(BOpc)).addMBB(TBB).addImm(ARMCC::AL).addReg(0);
420 BuildMI(&MBB, DL, get(BOpc)).addMBB(TBB);
422 BuildMI(&MBB, DL, get(BccOpc)).addMBB(TBB)
423 .addImm(Cond[0].getImm()).addOperand(Cond[1]);
427 // Two-way conditional branch.
428 BuildMI(&MBB, DL, get(BccOpc)).addMBB(TBB)
429 .addImm(Cond[0].getImm()).addOperand(Cond[1]);
431 BuildMI(&MBB, DL, get(BOpc)).addMBB(FBB).addImm(ARMCC::AL).addReg(0);
433 BuildMI(&MBB, DL, get(BOpc)).addMBB(FBB);
437 bool ARMBaseInstrInfo::
438 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
439 ARMCC::CondCodes CC = (ARMCC::CondCodes)(int)Cond[0].getImm();
440 Cond[0].setImm(ARMCC::getOppositeCondition(CC));
444 bool ARMBaseInstrInfo::isPredicated(const MachineInstr *MI) const {
445 if (MI->isBundle()) {
446 MachineBasicBlock::const_instr_iterator I = MI;
447 MachineBasicBlock::const_instr_iterator E = MI->getParent()->instr_end();
448 while (++I != E && I->isInsideBundle()) {
449 int PIdx = I->findFirstPredOperandIdx();
450 if (PIdx != -1 && I->getOperand(PIdx).getImm() != ARMCC::AL)
456 int PIdx = MI->findFirstPredOperandIdx();
457 return PIdx != -1 && MI->getOperand(PIdx).getImm() != ARMCC::AL;
460 bool ARMBaseInstrInfo::
461 PredicateInstruction(MachineInstr *MI,
462 const SmallVectorImpl<MachineOperand> &Pred) const {
463 unsigned Opc = MI->getOpcode();
464 if (isUncondBranchOpcode(Opc)) {
465 MI->setDesc(get(getMatchingCondBranchOpcode(Opc)));
466 MachineInstrBuilder(*MI->getParent()->getParent(), MI)
467 .addImm(Pred[0].getImm())
468 .addReg(Pred[1].getReg());
472 int PIdx = MI->findFirstPredOperandIdx();
474 MachineOperand &PMO = MI->getOperand(PIdx);
475 PMO.setImm(Pred[0].getImm());
476 MI->getOperand(PIdx+1).setReg(Pred[1].getReg());
482 bool ARMBaseInstrInfo::
483 SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1,
484 const SmallVectorImpl<MachineOperand> &Pred2) const {
485 if (Pred1.size() > 2 || Pred2.size() > 2)
488 ARMCC::CondCodes CC1 = (ARMCC::CondCodes)Pred1[0].getImm();
489 ARMCC::CondCodes CC2 = (ARMCC::CondCodes)Pred2[0].getImm();
499 return CC2 == ARMCC::HI;
501 return CC2 == ARMCC::LO || CC2 == ARMCC::EQ;
503 return CC2 == ARMCC::GT;
505 return CC2 == ARMCC::LT;
509 bool ARMBaseInstrInfo::DefinesPredicate(MachineInstr *MI,
510 std::vector<MachineOperand> &Pred) const {
512 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
513 const MachineOperand &MO = MI->getOperand(i);
514 if ((MO.isRegMask() && MO.clobbersPhysReg(ARM::CPSR)) ||
515 (MO.isReg() && MO.isDef() && MO.getReg() == ARM::CPSR)) {
524 static bool isCPSRDefined(const MachineInstr *MI) {
525 for (const auto &MO : MI->operands())
526 if (MO.isReg() && MO.getReg() == ARM::CPSR && MO.isDef())
531 static bool isEligibleForITBlock(const MachineInstr *MI) {
532 switch (MI->getOpcode()) {
533 default: return true;
534 case ARM::tADC: // ADC (register) T1
535 case ARM::tADDi3: // ADD (immediate) T1
536 case ARM::tADDi8: // ADD (immediate) T2
537 case ARM::tADDrr: // ADD (register) T1
538 case ARM::tAND: // AND (register) T1
539 case ARM::tASRri: // ASR (immediate) T1
540 case ARM::tASRrr: // ASR (register) T1
541 case ARM::tBIC: // BIC (register) T1
542 case ARM::tEOR: // EOR (register) T1
543 case ARM::tLSLri: // LSL (immediate) T1
544 case ARM::tLSLrr: // LSL (register) T1
545 case ARM::tLSRri: // LSR (immediate) T1
546 case ARM::tLSRrr: // LSR (register) T1
547 case ARM::tMUL: // MUL T1
548 case ARM::tMVN: // MVN (register) T1
549 case ARM::tORR: // ORR (register) T1
550 case ARM::tROR: // ROR (register) T1
551 case ARM::tRSB: // RSB (immediate) T1
552 case ARM::tSBC: // SBC (register) T1
553 case ARM::tSUBi3: // SUB (immediate) T1
554 case ARM::tSUBi8: // SUB (immediate) T2
555 case ARM::tSUBrr: // SUB (register) T1
556 return !isCPSRDefined(MI);
560 /// isPredicable - Return true if the specified instruction can be predicated.
561 /// By default, this returns true for every instruction with a
562 /// PredicateOperand.
563 bool ARMBaseInstrInfo::isPredicable(MachineInstr *MI) const {
564 if (!MI->isPredicable())
567 if (!isEligibleForITBlock(MI))
570 ARMFunctionInfo *AFI =
571 MI->getParent()->getParent()->getInfo<ARMFunctionInfo>();
573 if (AFI->isThumb2Function()) {
574 if (getSubtarget().restrictIT())
575 return isV8EligibleForIT(MI);
576 } else { // non-Thumb
577 if ((MI->getDesc().TSFlags & ARMII::DomainMask) == ARMII::DomainNEON)
585 template <> bool IsCPSRDead<MachineInstr>(MachineInstr *MI) {
586 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
587 const MachineOperand &MO = MI->getOperand(i);
588 if (!MO.isReg() || MO.isUndef() || MO.isUse())
590 if (MO.getReg() != ARM::CPSR)
595 // all definitions of CPSR are dead
600 /// GetInstSize - Return the size of the specified MachineInstr.
602 unsigned ARMBaseInstrInfo::GetInstSizeInBytes(const MachineInstr *MI) const {
603 const MachineBasicBlock &MBB = *MI->getParent();
604 const MachineFunction *MF = MBB.getParent();
605 const MCAsmInfo *MAI = MF->getTarget().getMCAsmInfo();
607 const MCInstrDesc &MCID = MI->getDesc();
609 return MCID.getSize();
611 // If this machine instr is an inline asm, measure it.
612 if (MI->getOpcode() == ARM::INLINEASM)
613 return getInlineAsmLength(MI->getOperand(0).getSymbolName(), *MAI);
614 unsigned Opc = MI->getOpcode();
617 // pseudo-instruction sizes are zero.
619 case TargetOpcode::BUNDLE:
620 return getInstBundleLength(MI);
621 case ARM::MOVi16_ga_pcrel:
622 case ARM::MOVTi16_ga_pcrel:
623 case ARM::t2MOVi16_ga_pcrel:
624 case ARM::t2MOVTi16_ga_pcrel:
627 case ARM::t2MOVi32imm:
629 case ARM::CONSTPOOL_ENTRY:
630 case ARM::JUMPTABLE_INSTS:
631 case ARM::JUMPTABLE_ADDRS:
632 case ARM::JUMPTABLE_TBB:
633 case ARM::JUMPTABLE_TBH:
634 // If this machine instr is a constant pool entry, its size is recorded as
636 return MI->getOperand(2).getImm();
637 case ARM::Int_eh_sjlj_longjmp:
639 case ARM::tInt_eh_sjlj_longjmp:
641 case ARM::Int_eh_sjlj_setjmp:
642 case ARM::Int_eh_sjlj_setjmp_nofp:
644 case ARM::tInt_eh_sjlj_setjmp:
645 case ARM::t2Int_eh_sjlj_setjmp:
646 case ARM::t2Int_eh_sjlj_setjmp_nofp:
649 return MI->getOperand(1).getImm();
653 unsigned ARMBaseInstrInfo::getInstBundleLength(const MachineInstr *MI) const {
655 MachineBasicBlock::const_instr_iterator I = MI;
656 MachineBasicBlock::const_instr_iterator E = MI->getParent()->instr_end();
657 while (++I != E && I->isInsideBundle()) {
658 assert(!I->isBundle() && "No nested bundle!");
659 Size += GetInstSizeInBytes(&*I);
664 void ARMBaseInstrInfo::copyFromCPSR(MachineBasicBlock &MBB,
665 MachineBasicBlock::iterator I,
666 unsigned DestReg, bool KillSrc,
667 const ARMSubtarget &Subtarget) const {
668 unsigned Opc = Subtarget.isThumb()
669 ? (Subtarget.isMClass() ? ARM::t2MRS_M : ARM::t2MRS_AR)
672 MachineInstrBuilder MIB =
673 BuildMI(MBB, I, I->getDebugLoc(), get(Opc), DestReg);
675 // There is only 1 A/R class MRS instruction, and it always refers to
676 // APSR. However, there are lots of other possibilities on M-class cores.
677 if (Subtarget.isMClass())
682 MIB.addReg(ARM::CPSR, RegState::Implicit | getKillRegState(KillSrc));
685 void ARMBaseInstrInfo::copyToCPSR(MachineBasicBlock &MBB,
686 MachineBasicBlock::iterator I,
687 unsigned SrcReg, bool KillSrc,
688 const ARMSubtarget &Subtarget) const {
689 unsigned Opc = Subtarget.isThumb()
690 ? (Subtarget.isMClass() ? ARM::t2MSR_M : ARM::t2MSR_AR)
693 MachineInstrBuilder MIB = BuildMI(MBB, I, I->getDebugLoc(), get(Opc));
695 if (Subtarget.isMClass())
700 MIB.addReg(SrcReg, getKillRegState(KillSrc));
704 MIB.addReg(ARM::CPSR, RegState::Implicit | RegState::Define);
707 void ARMBaseInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
708 MachineBasicBlock::iterator I, DebugLoc DL,
709 unsigned DestReg, unsigned SrcReg,
710 bool KillSrc) const {
711 bool GPRDest = ARM::GPRRegClass.contains(DestReg);
712 bool GPRSrc = ARM::GPRRegClass.contains(SrcReg);
714 if (GPRDest && GPRSrc) {
715 AddDefaultCC(AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::MOVr), DestReg)
716 .addReg(SrcReg, getKillRegState(KillSrc))));
720 bool SPRDest = ARM::SPRRegClass.contains(DestReg);
721 bool SPRSrc = ARM::SPRRegClass.contains(SrcReg);
724 if (SPRDest && SPRSrc)
726 else if (GPRDest && SPRSrc)
728 else if (SPRDest && GPRSrc)
730 else if (ARM::DPRRegClass.contains(DestReg, SrcReg) && !Subtarget.isFPOnlySP())
732 else if (ARM::QPRRegClass.contains(DestReg, SrcReg))
736 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(Opc), DestReg);
737 MIB.addReg(SrcReg, getKillRegState(KillSrc));
738 if (Opc == ARM::VORRq)
739 MIB.addReg(SrcReg, getKillRegState(KillSrc));
744 // Handle register classes that require multiple instructions.
745 unsigned BeginIdx = 0;
746 unsigned SubRegs = 0;
749 // Use VORRq when possible.
750 if (ARM::QQPRRegClass.contains(DestReg, SrcReg)) {
752 BeginIdx = ARM::qsub_0;
754 } else if (ARM::QQQQPRRegClass.contains(DestReg, SrcReg)) {
756 BeginIdx = ARM::qsub_0;
758 // Fall back to VMOVD.
759 } else if (ARM::DPairRegClass.contains(DestReg, SrcReg)) {
761 BeginIdx = ARM::dsub_0;
763 } else if (ARM::DTripleRegClass.contains(DestReg, SrcReg)) {
765 BeginIdx = ARM::dsub_0;
767 } else if (ARM::DQuadRegClass.contains(DestReg, SrcReg)) {
769 BeginIdx = ARM::dsub_0;
771 } else if (ARM::GPRPairRegClass.contains(DestReg, SrcReg)) {
772 Opc = Subtarget.isThumb2() ? ARM::tMOVr : ARM::MOVr;
773 BeginIdx = ARM::gsub_0;
775 } else if (ARM::DPairSpcRegClass.contains(DestReg, SrcReg)) {
777 BeginIdx = ARM::dsub_0;
780 } else if (ARM::DTripleSpcRegClass.contains(DestReg, SrcReg)) {
782 BeginIdx = ARM::dsub_0;
785 } else if (ARM::DQuadSpcRegClass.contains(DestReg, SrcReg)) {
787 BeginIdx = ARM::dsub_0;
790 } else if (ARM::DPRRegClass.contains(DestReg, SrcReg) && Subtarget.isFPOnlySP()) {
792 BeginIdx = ARM::ssub_0;
794 } else if (SrcReg == ARM::CPSR) {
795 copyFromCPSR(MBB, I, DestReg, KillSrc, Subtarget);
797 } else if (DestReg == ARM::CPSR) {
798 copyToCPSR(MBB, I, SrcReg, KillSrc, Subtarget);
802 assert(Opc && "Impossible reg-to-reg copy");
804 const TargetRegisterInfo *TRI = &getRegisterInfo();
805 MachineInstrBuilder Mov;
807 // Copy register tuples backward when the first Dest reg overlaps with SrcReg.
808 if (TRI->regsOverlap(SrcReg, TRI->getSubReg(DestReg, BeginIdx))) {
809 BeginIdx = BeginIdx + ((SubRegs - 1) * Spacing);
813 SmallSet<unsigned, 4> DstRegs;
815 for (unsigned i = 0; i != SubRegs; ++i) {
816 unsigned Dst = TRI->getSubReg(DestReg, BeginIdx + i * Spacing);
817 unsigned Src = TRI->getSubReg(SrcReg, BeginIdx + i * Spacing);
818 assert(Dst && Src && "Bad sub-register");
820 assert(!DstRegs.count(Src) && "destructive vector copy");
823 Mov = BuildMI(MBB, I, I->getDebugLoc(), get(Opc), Dst).addReg(Src);
824 // VORR takes two source operands.
825 if (Opc == ARM::VORRq)
827 Mov = AddDefaultPred(Mov);
829 if (Opc == ARM::MOVr)
830 Mov = AddDefaultCC(Mov);
832 // Add implicit super-register defs and kills to the last instruction.
833 Mov->addRegisterDefined(DestReg, TRI);
835 Mov->addRegisterKilled(SrcReg, TRI);
838 const MachineInstrBuilder &
839 ARMBaseInstrInfo::AddDReg(MachineInstrBuilder &MIB, unsigned Reg,
840 unsigned SubIdx, unsigned State,
841 const TargetRegisterInfo *TRI) const {
843 return MIB.addReg(Reg, State);
845 if (TargetRegisterInfo::isPhysicalRegister(Reg))
846 return MIB.addReg(TRI->getSubReg(Reg, SubIdx), State);
847 return MIB.addReg(Reg, State, SubIdx);
850 void ARMBaseInstrInfo::
851 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
852 unsigned SrcReg, bool isKill, int FI,
853 const TargetRegisterClass *RC,
854 const TargetRegisterInfo *TRI) const {
856 if (I != MBB.end()) DL = I->getDebugLoc();
857 MachineFunction &MF = *MBB.getParent();
858 MachineFrameInfo &MFI = *MF.getFrameInfo();
859 unsigned Align = MFI.getObjectAlignment(FI);
861 MachineMemOperand *MMO =
862 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(FI),
863 MachineMemOperand::MOStore,
864 MFI.getObjectSize(FI),
867 switch (RC->getSize()) {
869 if (ARM::GPRRegClass.hasSubClassEq(RC)) {
870 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::STRi12))
871 .addReg(SrcReg, getKillRegState(isKill))
872 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
873 } else if (ARM::SPRRegClass.hasSubClassEq(RC)) {
874 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTRS))
875 .addReg(SrcReg, getKillRegState(isKill))
876 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
878 llvm_unreachable("Unknown reg class!");
881 if (ARM::DPRRegClass.hasSubClassEq(RC)) {
882 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTRD))
883 .addReg(SrcReg, getKillRegState(isKill))
884 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
885 } else if (ARM::GPRPairRegClass.hasSubClassEq(RC)) {
886 if (Subtarget.hasV5TEOps()) {
887 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(ARM::STRD));
888 AddDReg(MIB, SrcReg, ARM::gsub_0, getKillRegState(isKill), TRI);
889 AddDReg(MIB, SrcReg, ARM::gsub_1, 0, TRI);
890 MIB.addFrameIndex(FI).addReg(0).addImm(0).addMemOperand(MMO);
894 // Fallback to STM instruction, which has existed since the dawn of
896 MachineInstrBuilder MIB =
897 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::STMIA))
898 .addFrameIndex(FI).addMemOperand(MMO));
899 AddDReg(MIB, SrcReg, ARM::gsub_0, getKillRegState(isKill), TRI);
900 AddDReg(MIB, SrcReg, ARM::gsub_1, 0, TRI);
903 llvm_unreachable("Unknown reg class!");
906 if (ARM::DPairRegClass.hasSubClassEq(RC)) {
907 // Use aligned spills if the stack can be realigned.
908 if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) {
909 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VST1q64))
910 .addFrameIndex(FI).addImm(16)
911 .addReg(SrcReg, getKillRegState(isKill))
912 .addMemOperand(MMO));
914 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTMQIA))
915 .addReg(SrcReg, getKillRegState(isKill))
917 .addMemOperand(MMO));
920 llvm_unreachable("Unknown reg class!");
923 if (ARM::DTripleRegClass.hasSubClassEq(RC)) {
924 // Use aligned spills if the stack can be realigned.
925 if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) {
926 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VST1d64TPseudo))
927 .addFrameIndex(FI).addImm(16)
928 .addReg(SrcReg, getKillRegState(isKill))
929 .addMemOperand(MMO));
931 MachineInstrBuilder MIB =
932 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTMDIA))
935 MIB = AddDReg(MIB, SrcReg, ARM::dsub_0, getKillRegState(isKill), TRI);
936 MIB = AddDReg(MIB, SrcReg, ARM::dsub_1, 0, TRI);
937 AddDReg(MIB, SrcReg, ARM::dsub_2, 0, TRI);
940 llvm_unreachable("Unknown reg class!");
943 if (ARM::QQPRRegClass.hasSubClassEq(RC) || ARM::DQuadRegClass.hasSubClassEq(RC)) {
944 if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) {
945 // FIXME: It's possible to only store part of the QQ register if the
946 // spilled def has a sub-register index.
947 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VST1d64QPseudo))
948 .addFrameIndex(FI).addImm(16)
949 .addReg(SrcReg, getKillRegState(isKill))
950 .addMemOperand(MMO));
952 MachineInstrBuilder MIB =
953 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTMDIA))
956 MIB = AddDReg(MIB, SrcReg, ARM::dsub_0, getKillRegState(isKill), TRI);
957 MIB = AddDReg(MIB, SrcReg, ARM::dsub_1, 0, TRI);
958 MIB = AddDReg(MIB, SrcReg, ARM::dsub_2, 0, TRI);
959 AddDReg(MIB, SrcReg, ARM::dsub_3, 0, TRI);
962 llvm_unreachable("Unknown reg class!");
965 if (ARM::QQQQPRRegClass.hasSubClassEq(RC)) {
966 MachineInstrBuilder MIB =
967 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTMDIA))
970 MIB = AddDReg(MIB, SrcReg, ARM::dsub_0, getKillRegState(isKill), TRI);
971 MIB = AddDReg(MIB, SrcReg, ARM::dsub_1, 0, TRI);
972 MIB = AddDReg(MIB, SrcReg, ARM::dsub_2, 0, TRI);
973 MIB = AddDReg(MIB, SrcReg, ARM::dsub_3, 0, TRI);
974 MIB = AddDReg(MIB, SrcReg, ARM::dsub_4, 0, TRI);
975 MIB = AddDReg(MIB, SrcReg, ARM::dsub_5, 0, TRI);
976 MIB = AddDReg(MIB, SrcReg, ARM::dsub_6, 0, TRI);
977 AddDReg(MIB, SrcReg, ARM::dsub_7, 0, TRI);
979 llvm_unreachable("Unknown reg class!");
982 llvm_unreachable("Unknown reg class!");
987 ARMBaseInstrInfo::isStoreToStackSlot(const MachineInstr *MI,
988 int &FrameIndex) const {
989 switch (MI->getOpcode()) {
992 case ARM::t2STRs: // FIXME: don't use t2STRs to access frame.
993 if (MI->getOperand(1).isFI() &&
994 MI->getOperand(2).isReg() &&
995 MI->getOperand(3).isImm() &&
996 MI->getOperand(2).getReg() == 0 &&
997 MI->getOperand(3).getImm() == 0) {
998 FrameIndex = MI->getOperand(1).getIndex();
999 return MI->getOperand(0).getReg();
1007 if (MI->getOperand(1).isFI() &&
1008 MI->getOperand(2).isImm() &&
1009 MI->getOperand(2).getImm() == 0) {
1010 FrameIndex = MI->getOperand(1).getIndex();
1011 return MI->getOperand(0).getReg();
1015 case ARM::VST1d64TPseudo:
1016 case ARM::VST1d64QPseudo:
1017 if (MI->getOperand(0).isFI() &&
1018 MI->getOperand(2).getSubReg() == 0) {
1019 FrameIndex = MI->getOperand(0).getIndex();
1020 return MI->getOperand(2).getReg();
1024 if (MI->getOperand(1).isFI() &&
1025 MI->getOperand(0).getSubReg() == 0) {
1026 FrameIndex = MI->getOperand(1).getIndex();
1027 return MI->getOperand(0).getReg();
1035 unsigned ARMBaseInstrInfo::isStoreToStackSlotPostFE(const MachineInstr *MI,
1036 int &FrameIndex) const {
1037 const MachineMemOperand *Dummy;
1038 return MI->mayStore() && hasStoreToStackSlot(MI, Dummy, FrameIndex);
1041 void ARMBaseInstrInfo::
1042 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
1043 unsigned DestReg, int FI,
1044 const TargetRegisterClass *RC,
1045 const TargetRegisterInfo *TRI) const {
1047 if (I != MBB.end()) DL = I->getDebugLoc();
1048 MachineFunction &MF = *MBB.getParent();
1049 MachineFrameInfo &MFI = *MF.getFrameInfo();
1050 unsigned Align = MFI.getObjectAlignment(FI);
1051 MachineMemOperand *MMO =
1052 MF.getMachineMemOperand(
1053 MachinePointerInfo::getFixedStack(FI),
1054 MachineMemOperand::MOLoad,
1055 MFI.getObjectSize(FI),
1058 switch (RC->getSize()) {
1060 if (ARM::GPRRegClass.hasSubClassEq(RC)) {
1061 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::LDRi12), DestReg)
1062 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
1064 } else if (ARM::SPRRegClass.hasSubClassEq(RC)) {
1065 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDRS), DestReg)
1066 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
1068 llvm_unreachable("Unknown reg class!");
1071 if (ARM::DPRRegClass.hasSubClassEq(RC)) {
1072 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDRD), DestReg)
1073 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
1074 } else if (ARM::GPRPairRegClass.hasSubClassEq(RC)) {
1075 MachineInstrBuilder MIB;
1077 if (Subtarget.hasV5TEOps()) {
1078 MIB = BuildMI(MBB, I, DL, get(ARM::LDRD));
1079 AddDReg(MIB, DestReg, ARM::gsub_0, RegState::DefineNoRead, TRI);
1080 AddDReg(MIB, DestReg, ARM::gsub_1, RegState::DefineNoRead, TRI);
1081 MIB.addFrameIndex(FI).addReg(0).addImm(0).addMemOperand(MMO);
1083 AddDefaultPred(MIB);
1085 // Fallback to LDM instruction, which has existed since the dawn of
1087 MIB = AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::LDMIA))
1088 .addFrameIndex(FI).addMemOperand(MMO));
1089 MIB = AddDReg(MIB, DestReg, ARM::gsub_0, RegState::DefineNoRead, TRI);
1090 MIB = AddDReg(MIB, DestReg, ARM::gsub_1, RegState::DefineNoRead, TRI);
1093 if (TargetRegisterInfo::isPhysicalRegister(DestReg))
1094 MIB.addReg(DestReg, RegState::ImplicitDefine);
1096 llvm_unreachable("Unknown reg class!");
1099 if (ARM::DPairRegClass.hasSubClassEq(RC)) {
1100 if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) {
1101 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLD1q64), DestReg)
1102 .addFrameIndex(FI).addImm(16)
1103 .addMemOperand(MMO));
1105 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDMQIA), DestReg)
1107 .addMemOperand(MMO));
1110 llvm_unreachable("Unknown reg class!");
1113 if (ARM::DTripleRegClass.hasSubClassEq(RC)) {
1114 if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) {
1115 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLD1d64TPseudo), DestReg)
1116 .addFrameIndex(FI).addImm(16)
1117 .addMemOperand(MMO));
1119 MachineInstrBuilder MIB =
1120 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDMDIA))
1122 .addMemOperand(MMO));
1123 MIB = AddDReg(MIB, DestReg, ARM::dsub_0, RegState::DefineNoRead, TRI);
1124 MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::DefineNoRead, TRI);
1125 MIB = AddDReg(MIB, DestReg, ARM::dsub_2, RegState::DefineNoRead, TRI);
1126 if (TargetRegisterInfo::isPhysicalRegister(DestReg))
1127 MIB.addReg(DestReg, RegState::ImplicitDefine);
1130 llvm_unreachable("Unknown reg class!");
1133 if (ARM::QQPRRegClass.hasSubClassEq(RC) || ARM::DQuadRegClass.hasSubClassEq(RC)) {
1134 if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) {
1135 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLD1d64QPseudo), DestReg)
1136 .addFrameIndex(FI).addImm(16)
1137 .addMemOperand(MMO));
1139 MachineInstrBuilder MIB =
1140 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDMDIA))
1142 .addMemOperand(MMO);
1143 MIB = AddDReg(MIB, DestReg, ARM::dsub_0, RegState::DefineNoRead, TRI);
1144 MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::DefineNoRead, TRI);
1145 MIB = AddDReg(MIB, DestReg, ARM::dsub_2, RegState::DefineNoRead, TRI);
1146 MIB = AddDReg(MIB, DestReg, ARM::dsub_3, RegState::DefineNoRead, TRI);
1147 if (TargetRegisterInfo::isPhysicalRegister(DestReg))
1148 MIB.addReg(DestReg, RegState::ImplicitDefine);
1151 llvm_unreachable("Unknown reg class!");
1154 if (ARM::QQQQPRRegClass.hasSubClassEq(RC)) {
1155 MachineInstrBuilder MIB =
1156 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDMDIA))
1158 .addMemOperand(MMO);
1159 MIB = AddDReg(MIB, DestReg, ARM::dsub_0, RegState::DefineNoRead, TRI);
1160 MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::DefineNoRead, TRI);
1161 MIB = AddDReg(MIB, DestReg, ARM::dsub_2, RegState::DefineNoRead, TRI);
1162 MIB = AddDReg(MIB, DestReg, ARM::dsub_3, RegState::DefineNoRead, TRI);
1163 MIB = AddDReg(MIB, DestReg, ARM::dsub_4, RegState::DefineNoRead, TRI);
1164 MIB = AddDReg(MIB, DestReg, ARM::dsub_5, RegState::DefineNoRead, TRI);
1165 MIB = AddDReg(MIB, DestReg, ARM::dsub_6, RegState::DefineNoRead, TRI);
1166 MIB = AddDReg(MIB, DestReg, ARM::dsub_7, RegState::DefineNoRead, TRI);
1167 if (TargetRegisterInfo::isPhysicalRegister(DestReg))
1168 MIB.addReg(DestReg, RegState::ImplicitDefine);
1170 llvm_unreachable("Unknown reg class!");
1173 llvm_unreachable("Unknown regclass!");
1178 ARMBaseInstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
1179 int &FrameIndex) const {
1180 switch (MI->getOpcode()) {
1183 case ARM::t2LDRs: // FIXME: don't use t2LDRs to access frame.
1184 if (MI->getOperand(1).isFI() &&
1185 MI->getOperand(2).isReg() &&
1186 MI->getOperand(3).isImm() &&
1187 MI->getOperand(2).getReg() == 0 &&
1188 MI->getOperand(3).getImm() == 0) {
1189 FrameIndex = MI->getOperand(1).getIndex();
1190 return MI->getOperand(0).getReg();
1198 if (MI->getOperand(1).isFI() &&
1199 MI->getOperand(2).isImm() &&
1200 MI->getOperand(2).getImm() == 0) {
1201 FrameIndex = MI->getOperand(1).getIndex();
1202 return MI->getOperand(0).getReg();
1206 case ARM::VLD1d64TPseudo:
1207 case ARM::VLD1d64QPseudo:
1208 if (MI->getOperand(1).isFI() &&
1209 MI->getOperand(0).getSubReg() == 0) {
1210 FrameIndex = MI->getOperand(1).getIndex();
1211 return MI->getOperand(0).getReg();
1215 if (MI->getOperand(1).isFI() &&
1216 MI->getOperand(0).getSubReg() == 0) {
1217 FrameIndex = MI->getOperand(1).getIndex();
1218 return MI->getOperand(0).getReg();
1226 unsigned ARMBaseInstrInfo::isLoadFromStackSlotPostFE(const MachineInstr *MI,
1227 int &FrameIndex) const {
1228 const MachineMemOperand *Dummy;
1229 return MI->mayLoad() && hasLoadFromStackSlot(MI, Dummy, FrameIndex);
1233 ARMBaseInstrInfo::expandPostRAPseudo(MachineBasicBlock::iterator MI) const {
1234 MachineFunction &MF = *MI->getParent()->getParent();
1235 Reloc::Model RM = MF.getTarget().getRelocationModel();
1237 if (MI->getOpcode() == TargetOpcode::LOAD_STACK_GUARD) {
1238 assert(getSubtarget().getTargetTriple().getObjectFormat() ==
1240 "LOAD_STACK_GUARD currently supported only for MachO.");
1241 expandLoadStackGuard(MI, RM);
1242 MI->getParent()->erase(MI);
1246 // This hook gets to expand COPY instructions before they become
1247 // copyPhysReg() calls. Look for VMOVS instructions that can legally be
1248 // widened to VMOVD. We prefer the VMOVD when possible because it may be
1249 // changed into a VORR that can go down the NEON pipeline.
1250 if (!WidenVMOVS || !MI->isCopy() || Subtarget.isCortexA15() ||
1251 Subtarget.isFPOnlySP())
1254 // Look for a copy between even S-registers. That is where we keep floats
1255 // when using NEON v2f32 instructions for f32 arithmetic.
1256 unsigned DstRegS = MI->getOperand(0).getReg();
1257 unsigned SrcRegS = MI->getOperand(1).getReg();
1258 if (!ARM::SPRRegClass.contains(DstRegS, SrcRegS))
1261 const TargetRegisterInfo *TRI = &getRegisterInfo();
1262 unsigned DstRegD = TRI->getMatchingSuperReg(DstRegS, ARM::ssub_0,
1264 unsigned SrcRegD = TRI->getMatchingSuperReg(SrcRegS, ARM::ssub_0,
1266 if (!DstRegD || !SrcRegD)
1269 // We want to widen this into a DstRegD = VMOVD SrcRegD copy. This is only
1270 // legal if the COPY already defines the full DstRegD, and it isn't a
1271 // sub-register insertion.
1272 if (!MI->definesRegister(DstRegD, TRI) || MI->readsRegister(DstRegD, TRI))
1275 // A dead copy shouldn't show up here, but reject it just in case.
1276 if (MI->getOperand(0).isDead())
1279 // All clear, widen the COPY.
1280 DEBUG(dbgs() << "widening: " << *MI);
1281 MachineInstrBuilder MIB(*MI->getParent()->getParent(), MI);
1283 // Get rid of the old <imp-def> of DstRegD. Leave it if it defines a Q-reg
1284 // or some other super-register.
1285 int ImpDefIdx = MI->findRegisterDefOperandIdx(DstRegD);
1286 if (ImpDefIdx != -1)
1287 MI->RemoveOperand(ImpDefIdx);
1289 // Change the opcode and operands.
1290 MI->setDesc(get(ARM::VMOVD));
1291 MI->getOperand(0).setReg(DstRegD);
1292 MI->getOperand(1).setReg(SrcRegD);
1293 AddDefaultPred(MIB);
1295 // We are now reading SrcRegD instead of SrcRegS. This may upset the
1296 // register scavenger and machine verifier, so we need to indicate that we
1297 // are reading an undefined value from SrcRegD, but a proper value from
1299 MI->getOperand(1).setIsUndef();
1300 MIB.addReg(SrcRegS, RegState::Implicit);
1302 // SrcRegD may actually contain an unrelated value in the ssub_1
1303 // sub-register. Don't kill it. Only kill the ssub_0 sub-register.
1304 if (MI->getOperand(1).isKill()) {
1305 MI->getOperand(1).setIsKill(false);
1306 MI->addRegisterKilled(SrcRegS, TRI, true);
1309 DEBUG(dbgs() << "replaced by: " << *MI);
1313 /// Create a copy of a const pool value. Update CPI to the new index and return
1315 static unsigned duplicateCPV(MachineFunction &MF, unsigned &CPI) {
1316 MachineConstantPool *MCP = MF.getConstantPool();
1317 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1319 const MachineConstantPoolEntry &MCPE = MCP->getConstants()[CPI];
1320 assert(MCPE.isMachineConstantPoolEntry() &&
1321 "Expecting a machine constantpool entry!");
1322 ARMConstantPoolValue *ACPV =
1323 static_cast<ARMConstantPoolValue*>(MCPE.Val.MachineCPVal);
1325 unsigned PCLabelId = AFI->createPICLabelUId();
1326 ARMConstantPoolValue *NewCPV = nullptr;
1328 // FIXME: The below assumes PIC relocation model and that the function
1329 // is Thumb mode (t1 or t2). PCAdjustment would be 8 for ARM mode PIC, and
1330 // zero for non-PIC in ARM or Thumb. The callers are all of thumb LDR
1331 // instructions, so that's probably OK, but is PIC always correct when
1333 if (ACPV->isGlobalValue())
1334 NewCPV = ARMConstantPoolConstant::
1335 Create(cast<ARMConstantPoolConstant>(ACPV)->getGV(), PCLabelId,
1337 else if (ACPV->isExtSymbol())
1338 NewCPV = ARMConstantPoolSymbol::
1339 Create(MF.getFunction()->getContext(),
1340 cast<ARMConstantPoolSymbol>(ACPV)->getSymbol(), PCLabelId, 4);
1341 else if (ACPV->isBlockAddress())
1342 NewCPV = ARMConstantPoolConstant::
1343 Create(cast<ARMConstantPoolConstant>(ACPV)->getBlockAddress(), PCLabelId,
1344 ARMCP::CPBlockAddress, 4);
1345 else if (ACPV->isLSDA())
1346 NewCPV = ARMConstantPoolConstant::Create(MF.getFunction(), PCLabelId,
1348 else if (ACPV->isMachineBasicBlock())
1349 NewCPV = ARMConstantPoolMBB::
1350 Create(MF.getFunction()->getContext(),
1351 cast<ARMConstantPoolMBB>(ACPV)->getMBB(), PCLabelId, 4);
1353 llvm_unreachable("Unexpected ARM constantpool value type!!");
1354 CPI = MCP->getConstantPoolIndex(NewCPV, MCPE.getAlignment());
1358 void ARMBaseInstrInfo::
1359 reMaterialize(MachineBasicBlock &MBB,
1360 MachineBasicBlock::iterator I,
1361 unsigned DestReg, unsigned SubIdx,
1362 const MachineInstr *Orig,
1363 const TargetRegisterInfo &TRI) const {
1364 unsigned Opcode = Orig->getOpcode();
1367 MachineInstr *MI = MBB.getParent()->CloneMachineInstr(Orig);
1368 MI->substituteRegister(Orig->getOperand(0).getReg(), DestReg, SubIdx, TRI);
1372 case ARM::tLDRpci_pic:
1373 case ARM::t2LDRpci_pic: {
1374 MachineFunction &MF = *MBB.getParent();
1375 unsigned CPI = Orig->getOperand(1).getIndex();
1376 unsigned PCLabelId = duplicateCPV(MF, CPI);
1377 MachineInstrBuilder MIB = BuildMI(MBB, I, Orig->getDebugLoc(), get(Opcode),
1379 .addConstantPoolIndex(CPI).addImm(PCLabelId);
1380 MIB->setMemRefs(Orig->memoperands_begin(), Orig->memoperands_end());
1387 ARMBaseInstrInfo::duplicate(MachineInstr *Orig, MachineFunction &MF) const {
1388 MachineInstr *MI = TargetInstrInfo::duplicate(Orig, MF);
1389 switch(Orig->getOpcode()) {
1390 case ARM::tLDRpci_pic:
1391 case ARM::t2LDRpci_pic: {
1392 unsigned CPI = Orig->getOperand(1).getIndex();
1393 unsigned PCLabelId = duplicateCPV(MF, CPI);
1394 Orig->getOperand(1).setIndex(CPI);
1395 Orig->getOperand(2).setImm(PCLabelId);
1402 bool ARMBaseInstrInfo::produceSameValue(const MachineInstr *MI0,
1403 const MachineInstr *MI1,
1404 const MachineRegisterInfo *MRI) const {
1405 int Opcode = MI0->getOpcode();
1406 if (Opcode == ARM::t2LDRpci ||
1407 Opcode == ARM::t2LDRpci_pic ||
1408 Opcode == ARM::tLDRpci ||
1409 Opcode == ARM::tLDRpci_pic ||
1410 Opcode == ARM::LDRLIT_ga_pcrel ||
1411 Opcode == ARM::LDRLIT_ga_pcrel_ldr ||
1412 Opcode == ARM::tLDRLIT_ga_pcrel ||
1413 Opcode == ARM::MOV_ga_pcrel ||
1414 Opcode == ARM::MOV_ga_pcrel_ldr ||
1415 Opcode == ARM::t2MOV_ga_pcrel) {
1416 if (MI1->getOpcode() != Opcode)
1418 if (MI0->getNumOperands() != MI1->getNumOperands())
1421 const MachineOperand &MO0 = MI0->getOperand(1);
1422 const MachineOperand &MO1 = MI1->getOperand(1);
1423 if (MO0.getOffset() != MO1.getOffset())
1426 if (Opcode == ARM::LDRLIT_ga_pcrel ||
1427 Opcode == ARM::LDRLIT_ga_pcrel_ldr ||
1428 Opcode == ARM::tLDRLIT_ga_pcrel ||
1429 Opcode == ARM::MOV_ga_pcrel ||
1430 Opcode == ARM::MOV_ga_pcrel_ldr ||
1431 Opcode == ARM::t2MOV_ga_pcrel)
1432 // Ignore the PC labels.
1433 return MO0.getGlobal() == MO1.getGlobal();
1435 const MachineFunction *MF = MI0->getParent()->getParent();
1436 const MachineConstantPool *MCP = MF->getConstantPool();
1437 int CPI0 = MO0.getIndex();
1438 int CPI1 = MO1.getIndex();
1439 const MachineConstantPoolEntry &MCPE0 = MCP->getConstants()[CPI0];
1440 const MachineConstantPoolEntry &MCPE1 = MCP->getConstants()[CPI1];
1441 bool isARMCP0 = MCPE0.isMachineConstantPoolEntry();
1442 bool isARMCP1 = MCPE1.isMachineConstantPoolEntry();
1443 if (isARMCP0 && isARMCP1) {
1444 ARMConstantPoolValue *ACPV0 =
1445 static_cast<ARMConstantPoolValue*>(MCPE0.Val.MachineCPVal);
1446 ARMConstantPoolValue *ACPV1 =
1447 static_cast<ARMConstantPoolValue*>(MCPE1.Val.MachineCPVal);
1448 return ACPV0->hasSameValue(ACPV1);
1449 } else if (!isARMCP0 && !isARMCP1) {
1450 return MCPE0.Val.ConstVal == MCPE1.Val.ConstVal;
1453 } else if (Opcode == ARM::PICLDR) {
1454 if (MI1->getOpcode() != Opcode)
1456 if (MI0->getNumOperands() != MI1->getNumOperands())
1459 unsigned Addr0 = MI0->getOperand(1).getReg();
1460 unsigned Addr1 = MI1->getOperand(1).getReg();
1461 if (Addr0 != Addr1) {
1463 !TargetRegisterInfo::isVirtualRegister(Addr0) ||
1464 !TargetRegisterInfo::isVirtualRegister(Addr1))
1467 // This assumes SSA form.
1468 MachineInstr *Def0 = MRI->getVRegDef(Addr0);
1469 MachineInstr *Def1 = MRI->getVRegDef(Addr1);
1470 // Check if the loaded value, e.g. a constantpool of a global address, are
1472 if (!produceSameValue(Def0, Def1, MRI))
1476 for (unsigned i = 3, e = MI0->getNumOperands(); i != e; ++i) {
1477 // %vreg12<def> = PICLDR %vreg11, 0, pred:14, pred:%noreg
1478 const MachineOperand &MO0 = MI0->getOperand(i);
1479 const MachineOperand &MO1 = MI1->getOperand(i);
1480 if (!MO0.isIdenticalTo(MO1))
1486 return MI0->isIdenticalTo(MI1, MachineInstr::IgnoreVRegDefs);
1489 /// areLoadsFromSameBasePtr - This is used by the pre-regalloc scheduler to
1490 /// determine if two loads are loading from the same base address. It should
1491 /// only return true if the base pointers are the same and the only differences
1492 /// between the two addresses is the offset. It also returns the offsets by
1495 /// FIXME: remove this in favor of the MachineInstr interface once pre-RA-sched
1496 /// is permanently disabled.
1497 bool ARMBaseInstrInfo::areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2,
1499 int64_t &Offset2) const {
1500 // Don't worry about Thumb: just ARM and Thumb2.
1501 if (Subtarget.isThumb1Only()) return false;
1503 if (!Load1->isMachineOpcode() || !Load2->isMachineOpcode())
1506 switch (Load1->getMachineOpcode()) {
1520 case ARM::t2LDRSHi8:
1522 case ARM::t2LDRBi12:
1523 case ARM::t2LDRSHi12:
1527 switch (Load2->getMachineOpcode()) {
1540 case ARM::t2LDRSHi8:
1542 case ARM::t2LDRBi12:
1543 case ARM::t2LDRSHi12:
1547 // Check if base addresses and chain operands match.
1548 if (Load1->getOperand(0) != Load2->getOperand(0) ||
1549 Load1->getOperand(4) != Load2->getOperand(4))
1552 // Index should be Reg0.
1553 if (Load1->getOperand(3) != Load2->getOperand(3))
1556 // Determine the offsets.
1557 if (isa<ConstantSDNode>(Load1->getOperand(1)) &&
1558 isa<ConstantSDNode>(Load2->getOperand(1))) {
1559 Offset1 = cast<ConstantSDNode>(Load1->getOperand(1))->getSExtValue();
1560 Offset2 = cast<ConstantSDNode>(Load2->getOperand(1))->getSExtValue();
1567 /// shouldScheduleLoadsNear - This is a used by the pre-regalloc scheduler to
1568 /// determine (in conjunction with areLoadsFromSameBasePtr) if two loads should
1569 /// be scheduled togther. On some targets if two loads are loading from
1570 /// addresses in the same cache line, it's better if they are scheduled
1571 /// together. This function takes two integers that represent the load offsets
1572 /// from the common base address. It returns true if it decides it's desirable
1573 /// to schedule the two loads together. "NumLoads" is the number of loads that
1574 /// have already been scheduled after Load1.
1576 /// FIXME: remove this in favor of the MachineInstr interface once pre-RA-sched
1577 /// is permanently disabled.
1578 bool ARMBaseInstrInfo::shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,
1579 int64_t Offset1, int64_t Offset2,
1580 unsigned NumLoads) const {
1581 // Don't worry about Thumb: just ARM and Thumb2.
1582 if (Subtarget.isThumb1Only()) return false;
1584 assert(Offset2 > Offset1);
1586 if ((Offset2 - Offset1) / 8 > 64)
1589 // Check if the machine opcodes are different. If they are different
1590 // then we consider them to not be of the same base address,
1591 // EXCEPT in the case of Thumb2 byte loads where one is LDRBi8 and the other LDRBi12.
1592 // In this case, they are considered to be the same because they are different
1593 // encoding forms of the same basic instruction.
1594 if ((Load1->getMachineOpcode() != Load2->getMachineOpcode()) &&
1595 !((Load1->getMachineOpcode() == ARM::t2LDRBi8 &&
1596 Load2->getMachineOpcode() == ARM::t2LDRBi12) ||
1597 (Load1->getMachineOpcode() == ARM::t2LDRBi12 &&
1598 Load2->getMachineOpcode() == ARM::t2LDRBi8)))
1599 return false; // FIXME: overly conservative?
1601 // Four loads in a row should be sufficient.
1608 bool ARMBaseInstrInfo::isSchedulingBoundary(const MachineInstr *MI,
1609 const MachineBasicBlock *MBB,
1610 const MachineFunction &MF) const {
1611 // Debug info is never a scheduling boundary. It's necessary to be explicit
1612 // due to the special treatment of IT instructions below, otherwise a
1613 // dbg_value followed by an IT will result in the IT instruction being
1614 // considered a scheduling hazard, which is wrong. It should be the actual
1615 // instruction preceding the dbg_value instruction(s), just like it is
1616 // when debug info is not present.
1617 if (MI->isDebugValue())
1620 // Terminators and labels can't be scheduled around.
1621 if (MI->isTerminator() || MI->isPosition())
1624 // Treat the start of the IT block as a scheduling boundary, but schedule
1625 // t2IT along with all instructions following it.
1626 // FIXME: This is a big hammer. But the alternative is to add all potential
1627 // true and anti dependencies to IT block instructions as implicit operands
1628 // to the t2IT instruction. The added compile time and complexity does not
1630 MachineBasicBlock::const_iterator I = MI;
1631 // Make sure to skip any dbg_value instructions
1632 while (++I != MBB->end() && I->isDebugValue())
1634 if (I != MBB->end() && I->getOpcode() == ARM::t2IT)
1637 // Don't attempt to schedule around any instruction that defines
1638 // a stack-oriented pointer, as it's unlikely to be profitable. This
1639 // saves compile time, because it doesn't require every single
1640 // stack slot reference to depend on the instruction that does the
1642 // Calls don't actually change the stack pointer, even if they have imp-defs.
1643 // No ARM calling conventions change the stack pointer. (X86 calling
1644 // conventions sometimes do).
1645 if (!MI->isCall() && MI->definesRegister(ARM::SP))
1651 bool ARMBaseInstrInfo::
1652 isProfitableToIfCvt(MachineBasicBlock &MBB,
1653 unsigned NumCycles, unsigned ExtraPredCycles,
1654 const BranchProbability &Probability) const {
1658 // If we are optimizing for size, see if the branch in the predecessor can be
1659 // lowered to cbn?z by the constant island lowering pass, and return false if
1660 // so. This results in a shorter instruction sequence.
1661 const Function *F = MBB.getParent()->getFunction();
1662 if (F->hasFnAttribute(Attribute::OptimizeForSize) ||
1663 F->hasFnAttribute(Attribute::MinSize)) {
1664 MachineBasicBlock *Pred = *MBB.pred_begin();
1665 if (!Pred->empty()) {
1666 MachineInstr *LastMI = &*Pred->rbegin();
1667 if (LastMI->getOpcode() == ARM::t2Bcc) {
1668 MachineBasicBlock::iterator CmpMI = LastMI;
1669 if (CmpMI != Pred->begin()) {
1671 if (CmpMI->getOpcode() == ARM::tCMPi8 ||
1672 CmpMI->getOpcode() == ARM::t2CMPri) {
1673 unsigned Reg = CmpMI->getOperand(0).getReg();
1674 unsigned PredReg = 0;
1675 ARMCC::CondCodes P = getInstrPredicate(CmpMI, PredReg);
1676 if (P == ARMCC::AL && CmpMI->getOperand(1).getImm() == 0 &&
1677 isARMLowRegister(Reg))
1685 // Attempt to estimate the relative costs of predication versus branching.
1686 unsigned UnpredCost = Probability.getNumerator() * NumCycles;
1687 UnpredCost /= Probability.getDenominator();
1688 UnpredCost += 1; // The branch itself
1689 UnpredCost += Subtarget.getMispredictionPenalty() / 10;
1691 return (NumCycles + ExtraPredCycles) <= UnpredCost;
1694 bool ARMBaseInstrInfo::
1695 isProfitableToIfCvt(MachineBasicBlock &TMBB,
1696 unsigned TCycles, unsigned TExtra,
1697 MachineBasicBlock &FMBB,
1698 unsigned FCycles, unsigned FExtra,
1699 const BranchProbability &Probability) const {
1700 if (!TCycles || !FCycles)
1703 // Attempt to estimate the relative costs of predication versus branching.
1704 unsigned TUnpredCost = Probability.getNumerator() * TCycles;
1705 TUnpredCost /= Probability.getDenominator();
1707 uint32_t Comp = Probability.getDenominator() - Probability.getNumerator();
1708 unsigned FUnpredCost = Comp * FCycles;
1709 FUnpredCost /= Probability.getDenominator();
1711 unsigned UnpredCost = TUnpredCost + FUnpredCost;
1712 UnpredCost += 1; // The branch itself
1713 UnpredCost += Subtarget.getMispredictionPenalty() / 10;
1715 return (TCycles + FCycles + TExtra + FExtra) <= UnpredCost;
1719 ARMBaseInstrInfo::isProfitableToUnpredicate(MachineBasicBlock &TMBB,
1720 MachineBasicBlock &FMBB) const {
1721 // Reduce false anti-dependencies to let Swift's out-of-order execution
1722 // engine do its thing.
1723 return Subtarget.isSwift();
1726 /// getInstrPredicate - If instruction is predicated, returns its predicate
1727 /// condition, otherwise returns AL. It also returns the condition code
1728 /// register by reference.
1730 llvm::getInstrPredicate(const MachineInstr *MI, unsigned &PredReg) {
1731 int PIdx = MI->findFirstPredOperandIdx();
1737 PredReg = MI->getOperand(PIdx+1).getReg();
1738 return (ARMCC::CondCodes)MI->getOperand(PIdx).getImm();
1742 int llvm::getMatchingCondBranchOpcode(int Opc) {
1747 if (Opc == ARM::t2B)
1750 llvm_unreachable("Unknown unconditional branch opcode!");
1753 /// commuteInstruction - Handle commutable instructions.
1755 ARMBaseInstrInfo::commuteInstruction(MachineInstr *MI, bool NewMI) const {
1756 switch (MI->getOpcode()) {
1758 case ARM::t2MOVCCr: {
1759 // MOVCC can be commuted by inverting the condition.
1760 unsigned PredReg = 0;
1761 ARMCC::CondCodes CC = getInstrPredicate(MI, PredReg);
1762 // MOVCC AL can't be inverted. Shouldn't happen.
1763 if (CC == ARMCC::AL || PredReg != ARM::CPSR)
1765 MI = TargetInstrInfo::commuteInstruction(MI, NewMI);
1768 // After swapping the MOVCC operands, also invert the condition.
1769 MI->getOperand(MI->findFirstPredOperandIdx())
1770 .setImm(ARMCC::getOppositeCondition(CC));
1774 return TargetInstrInfo::commuteInstruction(MI, NewMI);
1777 /// Identify instructions that can be folded into a MOVCC instruction, and
1778 /// return the defining instruction.
1779 static MachineInstr *canFoldIntoMOVCC(unsigned Reg,
1780 const MachineRegisterInfo &MRI,
1781 const TargetInstrInfo *TII) {
1782 if (!TargetRegisterInfo::isVirtualRegister(Reg))
1784 if (!MRI.hasOneNonDBGUse(Reg))
1786 MachineInstr *MI = MRI.getVRegDef(Reg);
1789 // MI is folded into the MOVCC by predicating it.
1790 if (!MI->isPredicable())
1792 // Check if MI has any non-dead defs or physreg uses. This also detects
1793 // predicated instructions which will be reading CPSR.
1794 for (unsigned i = 1, e = MI->getNumOperands(); i != e; ++i) {
1795 const MachineOperand &MO = MI->getOperand(i);
1796 // Reject frame index operands, PEI can't handle the predicated pseudos.
1797 if (MO.isFI() || MO.isCPI() || MO.isJTI())
1801 // MI can't have any tied operands, that would conflict with predication.
1804 if (TargetRegisterInfo::isPhysicalRegister(MO.getReg()))
1806 if (MO.isDef() && !MO.isDead())
1809 bool DontMoveAcrossStores = true;
1810 if (!MI->isSafeToMove(TII, /* AliasAnalysis = */ nullptr,
1811 DontMoveAcrossStores))
1816 bool ARMBaseInstrInfo::analyzeSelect(const MachineInstr *MI,
1817 SmallVectorImpl<MachineOperand> &Cond,
1818 unsigned &TrueOp, unsigned &FalseOp,
1819 bool &Optimizable) const {
1820 assert((MI->getOpcode() == ARM::MOVCCr || MI->getOpcode() == ARM::t2MOVCCr) &&
1821 "Unknown select instruction");
1826 // 3: Condition code.
1830 Cond.push_back(MI->getOperand(3));
1831 Cond.push_back(MI->getOperand(4));
1832 // We can always fold a def.
1838 ARMBaseInstrInfo::optimizeSelect(MachineInstr *MI,
1839 SmallPtrSetImpl<MachineInstr *> &SeenMIs,
1840 bool PreferFalse) const {
1841 assert((MI->getOpcode() == ARM::MOVCCr || MI->getOpcode() == ARM::t2MOVCCr) &&
1842 "Unknown select instruction");
1843 MachineRegisterInfo &MRI = MI->getParent()->getParent()->getRegInfo();
1844 MachineInstr *DefMI = canFoldIntoMOVCC(MI->getOperand(2).getReg(), MRI, this);
1845 bool Invert = !DefMI;
1847 DefMI = canFoldIntoMOVCC(MI->getOperand(1).getReg(), MRI, this);
1851 // Find new register class to use.
1852 MachineOperand FalseReg = MI->getOperand(Invert ? 2 : 1);
1853 unsigned DestReg = MI->getOperand(0).getReg();
1854 const TargetRegisterClass *PreviousClass = MRI.getRegClass(FalseReg.getReg());
1855 if (!MRI.constrainRegClass(DestReg, PreviousClass))
1858 // Create a new predicated version of DefMI.
1859 // Rfalse is the first use.
1860 MachineInstrBuilder NewMI = BuildMI(*MI->getParent(), MI, MI->getDebugLoc(),
1861 DefMI->getDesc(), DestReg);
1863 // Copy all the DefMI operands, excluding its (null) predicate.
1864 const MCInstrDesc &DefDesc = DefMI->getDesc();
1865 for (unsigned i = 1, e = DefDesc.getNumOperands();
1866 i != e && !DefDesc.OpInfo[i].isPredicate(); ++i)
1867 NewMI.addOperand(DefMI->getOperand(i));
1869 unsigned CondCode = MI->getOperand(3).getImm();
1871 NewMI.addImm(ARMCC::getOppositeCondition(ARMCC::CondCodes(CondCode)));
1873 NewMI.addImm(CondCode);
1874 NewMI.addOperand(MI->getOperand(4));
1876 // DefMI is not the -S version that sets CPSR, so add an optional %noreg.
1877 if (NewMI->hasOptionalDef())
1878 AddDefaultCC(NewMI);
1880 // The output register value when the predicate is false is an implicit
1881 // register operand tied to the first def.
1882 // The tie makes the register allocator ensure the FalseReg is allocated the
1883 // same register as operand 0.
1884 FalseReg.setImplicit();
1885 NewMI.addOperand(FalseReg);
1886 NewMI->tieOperands(0, NewMI->getNumOperands() - 1);
1888 // Update SeenMIs set: register newly created MI and erase removed DefMI.
1889 SeenMIs.insert(NewMI);
1890 SeenMIs.erase(DefMI);
1892 // If MI is inside a loop, and DefMI is outside the loop, then kill flags on
1893 // DefMI would be invalid when tranferred inside the loop. Checking for a
1894 // loop is expensive, but at least remove kill flags if they are in different
1896 if (DefMI->getParent() != MI->getParent())
1897 NewMI->clearKillInfo();
1899 // The caller will erase MI, but not DefMI.
1900 DefMI->eraseFromParent();
1904 /// Map pseudo instructions that imply an 'S' bit onto real opcodes. Whether the
1905 /// instruction is encoded with an 'S' bit is determined by the optional CPSR
1908 /// This will go away once we can teach tblgen how to set the optional CPSR def
1910 struct AddSubFlagsOpcodePair {
1912 uint16_t MachineOpc;
1915 static const AddSubFlagsOpcodePair AddSubFlagsOpcodeMap[] = {
1916 {ARM::ADDSri, ARM::ADDri},
1917 {ARM::ADDSrr, ARM::ADDrr},
1918 {ARM::ADDSrsi, ARM::ADDrsi},
1919 {ARM::ADDSrsr, ARM::ADDrsr},
1921 {ARM::SUBSri, ARM::SUBri},
1922 {ARM::SUBSrr, ARM::SUBrr},
1923 {ARM::SUBSrsi, ARM::SUBrsi},
1924 {ARM::SUBSrsr, ARM::SUBrsr},
1926 {ARM::RSBSri, ARM::RSBri},
1927 {ARM::RSBSrsi, ARM::RSBrsi},
1928 {ARM::RSBSrsr, ARM::RSBrsr},
1930 {ARM::t2ADDSri, ARM::t2ADDri},
1931 {ARM::t2ADDSrr, ARM::t2ADDrr},
1932 {ARM::t2ADDSrs, ARM::t2ADDrs},
1934 {ARM::t2SUBSri, ARM::t2SUBri},
1935 {ARM::t2SUBSrr, ARM::t2SUBrr},
1936 {ARM::t2SUBSrs, ARM::t2SUBrs},
1938 {ARM::t2RSBSri, ARM::t2RSBri},
1939 {ARM::t2RSBSrs, ARM::t2RSBrs},
1942 unsigned llvm::convertAddSubFlagsOpcode(unsigned OldOpc) {
1943 for (unsigned i = 0, e = array_lengthof(AddSubFlagsOpcodeMap); i != e; ++i)
1944 if (OldOpc == AddSubFlagsOpcodeMap[i].PseudoOpc)
1945 return AddSubFlagsOpcodeMap[i].MachineOpc;
1949 void llvm::emitARMRegPlusImmediate(MachineBasicBlock &MBB,
1950 MachineBasicBlock::iterator &MBBI, DebugLoc dl,
1951 unsigned DestReg, unsigned BaseReg, int NumBytes,
1952 ARMCC::CondCodes Pred, unsigned PredReg,
1953 const ARMBaseInstrInfo &TII, unsigned MIFlags) {
1954 if (NumBytes == 0 && DestReg != BaseReg) {
1955 BuildMI(MBB, MBBI, dl, TII.get(ARM::MOVr), DestReg)
1956 .addReg(BaseReg, RegState::Kill)
1957 .addImm((unsigned)Pred).addReg(PredReg).addReg(0)
1958 .setMIFlags(MIFlags);
1962 bool isSub = NumBytes < 0;
1963 if (isSub) NumBytes = -NumBytes;
1966 unsigned RotAmt = ARM_AM::getSOImmValRotate(NumBytes);
1967 unsigned ThisVal = NumBytes & ARM_AM::rotr32(0xFF, RotAmt);
1968 assert(ThisVal && "Didn't extract field correctly");
1970 // We will handle these bits from offset, clear them.
1971 NumBytes &= ~ThisVal;
1973 assert(ARM_AM::getSOImmVal(ThisVal) != -1 && "Bit extraction didn't work?");
1975 // Build the new ADD / SUB.
1976 unsigned Opc = isSub ? ARM::SUBri : ARM::ADDri;
1977 BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg)
1978 .addReg(BaseReg, RegState::Kill).addImm(ThisVal)
1979 .addImm((unsigned)Pred).addReg(PredReg).addReg(0)
1980 .setMIFlags(MIFlags);
1985 static bool isAnySubRegLive(unsigned Reg, const TargetRegisterInfo *TRI,
1987 for (MCSubRegIterator Subreg(Reg, TRI, /* IncludeSelf */ true);
1988 Subreg.isValid(); ++Subreg)
1989 if (MI->getParent()->computeRegisterLiveness(TRI, *Subreg, MI) !=
1990 MachineBasicBlock::LQR_Dead)
1994 bool llvm::tryFoldSPUpdateIntoPushPop(const ARMSubtarget &Subtarget,
1995 MachineFunction &MF, MachineInstr *MI,
1996 unsigned NumBytes) {
1997 // This optimisation potentially adds lots of load and store
1998 // micro-operations, it's only really a great benefit to code-size.
1999 if (!MF.getFunction()->hasFnAttribute(Attribute::MinSize))
2002 // If only one register is pushed/popped, LLVM can use an LDR/STR
2003 // instead. We can't modify those so make sure we're dealing with an
2004 // instruction we understand.
2005 bool IsPop = isPopOpcode(MI->getOpcode());
2006 bool IsPush = isPushOpcode(MI->getOpcode());
2007 if (!IsPush && !IsPop)
2010 bool IsVFPPushPop = MI->getOpcode() == ARM::VSTMDDB_UPD ||
2011 MI->getOpcode() == ARM::VLDMDIA_UPD;
2012 bool IsT1PushPop = MI->getOpcode() == ARM::tPUSH ||
2013 MI->getOpcode() == ARM::tPOP ||
2014 MI->getOpcode() == ARM::tPOP_RET;
2016 assert((IsT1PushPop || (MI->getOperand(0).getReg() == ARM::SP &&
2017 MI->getOperand(1).getReg() == ARM::SP)) &&
2018 "trying to fold sp update into non-sp-updating push/pop");
2020 // The VFP push & pop act on D-registers, so we can only fold an adjustment
2021 // by a multiple of 8 bytes in correctly. Similarly rN is 4-bytes. Don't try
2022 // if this is violated.
2023 if (NumBytes % (IsVFPPushPop ? 8 : 4) != 0)
2026 // ARM and Thumb2 push/pop insts have explicit "sp, sp" operands (+
2027 // pred) so the list starts at 4. Thumb1 starts after the predicate.
2028 int RegListIdx = IsT1PushPop ? 2 : 4;
2030 // Calculate the space we'll need in terms of registers.
2031 unsigned FirstReg = MI->getOperand(RegListIdx).getReg();
2032 unsigned RD0Reg, RegsNeeded;
2035 RegsNeeded = NumBytes / 8;
2038 RegsNeeded = NumBytes / 4;
2041 // We're going to have to strip all list operands off before
2042 // re-adding them since the order matters, so save the existing ones
2044 SmallVector<MachineOperand, 4> RegList;
2045 for (int i = MI->getNumOperands() - 1; i >= RegListIdx; --i)
2046 RegList.push_back(MI->getOperand(i));
2048 const TargetRegisterInfo *TRI = MF.getRegInfo().getTargetRegisterInfo();
2049 const MCPhysReg *CSRegs = TRI->getCalleeSavedRegs(&MF);
2051 // Now try to find enough space in the reglist to allocate NumBytes.
2052 for (unsigned CurReg = FirstReg - 1; CurReg >= RD0Reg && RegsNeeded;
2055 // Pushing any register is completely harmless, mark the
2056 // register involved as undef since we don't care about it in
2058 RegList.push_back(MachineOperand::CreateReg(CurReg, false, false,
2059 false, false, true));
2064 // However, we can only pop an extra register if it's not live. For
2065 // registers live within the function we might clobber a return value
2066 // register; the other way a register can be live here is if it's
2068 // TODO: Currently, computeRegisterLiveness() does not report "live" if a
2069 // sub reg is live. When computeRegisterLiveness() works for sub reg, it
2070 // can replace isAnySubRegLive().
2071 if (isCalleeSavedRegister(CurReg, CSRegs) ||
2072 isAnySubRegLive(CurReg, TRI, MI)) {
2073 // VFP pops don't allow holes in the register list, so any skip is fatal
2074 // for our transformation. GPR pops do, so we should just keep looking.
2081 // Mark the unimportant registers as <def,dead> in the POP.
2082 RegList.push_back(MachineOperand::CreateReg(CurReg, true, false, false,
2090 // Finally we know we can profitably perform the optimisation so go
2091 // ahead: strip all existing registers off and add them back again
2092 // in the right order.
2093 for (int i = MI->getNumOperands() - 1; i >= RegListIdx; --i)
2094 MI->RemoveOperand(i);
2096 // Add the complete list back in.
2097 MachineInstrBuilder MIB(MF, &*MI);
2098 for (int i = RegList.size() - 1; i >= 0; --i)
2099 MIB.addOperand(RegList[i]);
2104 bool llvm::rewriteARMFrameIndex(MachineInstr &MI, unsigned FrameRegIdx,
2105 unsigned FrameReg, int &Offset,
2106 const ARMBaseInstrInfo &TII) {
2107 unsigned Opcode = MI.getOpcode();
2108 const MCInstrDesc &Desc = MI.getDesc();
2109 unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
2112 // Memory operands in inline assembly always use AddrMode2.
2113 if (Opcode == ARM::INLINEASM)
2114 AddrMode = ARMII::AddrMode2;
2116 if (Opcode == ARM::ADDri) {
2117 Offset += MI.getOperand(FrameRegIdx+1).getImm();
2119 // Turn it into a move.
2120 MI.setDesc(TII.get(ARM::MOVr));
2121 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
2122 MI.RemoveOperand(FrameRegIdx+1);
2125 } else if (Offset < 0) {
2128 MI.setDesc(TII.get(ARM::SUBri));
2131 // Common case: small offset, fits into instruction.
2132 if (ARM_AM::getSOImmVal(Offset) != -1) {
2133 // Replace the FrameIndex with sp / fp
2134 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
2135 MI.getOperand(FrameRegIdx+1).ChangeToImmediate(Offset);
2140 // Otherwise, pull as much of the immedidate into this ADDri/SUBri
2142 unsigned RotAmt = ARM_AM::getSOImmValRotate(Offset);
2143 unsigned ThisImmVal = Offset & ARM_AM::rotr32(0xFF, RotAmt);
2145 // We will handle these bits from offset, clear them.
2146 Offset &= ~ThisImmVal;
2148 // Get the properly encoded SOImmVal field.
2149 assert(ARM_AM::getSOImmVal(ThisImmVal) != -1 &&
2150 "Bit extraction didn't work?");
2151 MI.getOperand(FrameRegIdx+1).ChangeToImmediate(ThisImmVal);
2153 unsigned ImmIdx = 0;
2155 unsigned NumBits = 0;
2158 case ARMII::AddrMode_i12: {
2159 ImmIdx = FrameRegIdx + 1;
2160 InstrOffs = MI.getOperand(ImmIdx).getImm();
2164 case ARMII::AddrMode2: {
2165 ImmIdx = FrameRegIdx+2;
2166 InstrOffs = ARM_AM::getAM2Offset(MI.getOperand(ImmIdx).getImm());
2167 if (ARM_AM::getAM2Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub)
2172 case ARMII::AddrMode3: {
2173 ImmIdx = FrameRegIdx+2;
2174 InstrOffs = ARM_AM::getAM3Offset(MI.getOperand(ImmIdx).getImm());
2175 if (ARM_AM::getAM3Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub)
2180 case ARMII::AddrMode4:
2181 case ARMII::AddrMode6:
2182 // Can't fold any offset even if it's zero.
2184 case ARMII::AddrMode5: {
2185 ImmIdx = FrameRegIdx+1;
2186 InstrOffs = ARM_AM::getAM5Offset(MI.getOperand(ImmIdx).getImm());
2187 if (ARM_AM::getAM5Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub)
2194 llvm_unreachable("Unsupported addressing mode!");
2197 Offset += InstrOffs * Scale;
2198 assert((Offset & (Scale-1)) == 0 && "Can't encode this offset!");
2204 // Attempt to fold address comp. if opcode has offset bits
2206 // Common case: small offset, fits into instruction.
2207 MachineOperand &ImmOp = MI.getOperand(ImmIdx);
2208 int ImmedOffset = Offset / Scale;
2209 unsigned Mask = (1 << NumBits) - 1;
2210 if ((unsigned)Offset <= Mask * Scale) {
2211 // Replace the FrameIndex with sp
2212 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
2213 // FIXME: When addrmode2 goes away, this will simplify (like the
2214 // T2 version), as the LDR.i12 versions don't need the encoding
2215 // tricks for the offset value.
2217 if (AddrMode == ARMII::AddrMode_i12)
2218 ImmedOffset = -ImmedOffset;
2220 ImmedOffset |= 1 << NumBits;
2222 ImmOp.ChangeToImmediate(ImmedOffset);
2227 // Otherwise, it didn't fit. Pull in what we can to simplify the immed.
2228 ImmedOffset = ImmedOffset & Mask;
2230 if (AddrMode == ARMII::AddrMode_i12)
2231 ImmedOffset = -ImmedOffset;
2233 ImmedOffset |= 1 << NumBits;
2235 ImmOp.ChangeToImmediate(ImmedOffset);
2236 Offset &= ~(Mask*Scale);
2240 Offset = (isSub) ? -Offset : Offset;
2244 /// analyzeCompare - For a comparison instruction, return the source registers
2245 /// in SrcReg and SrcReg2 if having two register operands, and the value it
2246 /// compares against in CmpValue. Return true if the comparison instruction
2247 /// can be analyzed.
2248 bool ARMBaseInstrInfo::
2249 analyzeCompare(const MachineInstr *MI, unsigned &SrcReg, unsigned &SrcReg2,
2250 int &CmpMask, int &CmpValue) const {
2251 switch (MI->getOpcode()) {
2255 SrcReg = MI->getOperand(0).getReg();
2258 CmpValue = MI->getOperand(1).getImm();
2262 SrcReg = MI->getOperand(0).getReg();
2263 SrcReg2 = MI->getOperand(1).getReg();
2269 SrcReg = MI->getOperand(0).getReg();
2271 CmpMask = MI->getOperand(1).getImm();
2279 /// isSuitableForMask - Identify a suitable 'and' instruction that
2280 /// operates on the given source register and applies the same mask
2281 /// as a 'tst' instruction. Provide a limited look-through for copies.
2282 /// When successful, MI will hold the found instruction.
2283 static bool isSuitableForMask(MachineInstr *&MI, unsigned SrcReg,
2284 int CmpMask, bool CommonUse) {
2285 switch (MI->getOpcode()) {
2288 if (CmpMask != MI->getOperand(2).getImm())
2290 if (SrcReg == MI->getOperand(CommonUse ? 1 : 0).getReg())
2298 /// getSwappedCondition - assume the flags are set by MI(a,b), return
2299 /// the condition code if we modify the instructions such that flags are
2301 inline static ARMCC::CondCodes getSwappedCondition(ARMCC::CondCodes CC) {
2303 default: return ARMCC::AL;
2304 case ARMCC::EQ: return ARMCC::EQ;
2305 case ARMCC::NE: return ARMCC::NE;
2306 case ARMCC::HS: return ARMCC::LS;
2307 case ARMCC::LO: return ARMCC::HI;
2308 case ARMCC::HI: return ARMCC::LO;
2309 case ARMCC::LS: return ARMCC::HS;
2310 case ARMCC::GE: return ARMCC::LE;
2311 case ARMCC::LT: return ARMCC::GT;
2312 case ARMCC::GT: return ARMCC::LT;
2313 case ARMCC::LE: return ARMCC::GE;
2317 /// isRedundantFlagInstr - check whether the first instruction, whose only
2318 /// purpose is to update flags, can be made redundant.
2319 /// CMPrr can be made redundant by SUBrr if the operands are the same.
2320 /// CMPri can be made redundant by SUBri if the operands are the same.
2321 /// This function can be extended later on.
2322 inline static bool isRedundantFlagInstr(MachineInstr *CmpI, unsigned SrcReg,
2323 unsigned SrcReg2, int ImmValue,
2325 if ((CmpI->getOpcode() == ARM::CMPrr ||
2326 CmpI->getOpcode() == ARM::t2CMPrr) &&
2327 (OI->getOpcode() == ARM::SUBrr ||
2328 OI->getOpcode() == ARM::t2SUBrr) &&
2329 ((OI->getOperand(1).getReg() == SrcReg &&
2330 OI->getOperand(2).getReg() == SrcReg2) ||
2331 (OI->getOperand(1).getReg() == SrcReg2 &&
2332 OI->getOperand(2).getReg() == SrcReg)))
2335 if ((CmpI->getOpcode() == ARM::CMPri ||
2336 CmpI->getOpcode() == ARM::t2CMPri) &&
2337 (OI->getOpcode() == ARM::SUBri ||
2338 OI->getOpcode() == ARM::t2SUBri) &&
2339 OI->getOperand(1).getReg() == SrcReg &&
2340 OI->getOperand(2).getImm() == ImmValue)
2345 /// optimizeCompareInstr - Convert the instruction supplying the argument to the
2346 /// comparison into one that sets the zero bit in the flags register;
2347 /// Remove a redundant Compare instruction if an earlier instruction can set the
2348 /// flags in the same way as Compare.
2349 /// E.g. SUBrr(r1,r2) and CMPrr(r1,r2). We also handle the case where two
2350 /// operands are swapped: SUBrr(r1,r2) and CMPrr(r2,r1), by updating the
2351 /// condition code of instructions which use the flags.
2352 bool ARMBaseInstrInfo::
2353 optimizeCompareInstr(MachineInstr *CmpInstr, unsigned SrcReg, unsigned SrcReg2,
2354 int CmpMask, int CmpValue,
2355 const MachineRegisterInfo *MRI) const {
2356 // Get the unique definition of SrcReg.
2357 MachineInstr *MI = MRI->getUniqueVRegDef(SrcReg);
2358 if (!MI) return false;
2360 // Masked compares sometimes use the same register as the corresponding 'and'.
2361 if (CmpMask != ~0) {
2362 if (!isSuitableForMask(MI, SrcReg, CmpMask, false) || isPredicated(MI)) {
2364 for (MachineRegisterInfo::use_instr_iterator
2365 UI = MRI->use_instr_begin(SrcReg), UE = MRI->use_instr_end();
2367 if (UI->getParent() != CmpInstr->getParent()) continue;
2368 MachineInstr *PotentialAND = &*UI;
2369 if (!isSuitableForMask(PotentialAND, SrcReg, CmpMask, true) ||
2370 isPredicated(PotentialAND))
2375 if (!MI) return false;
2379 // Get ready to iterate backward from CmpInstr.
2380 MachineBasicBlock::iterator I = CmpInstr, E = MI,
2381 B = CmpInstr->getParent()->begin();
2383 // Early exit if CmpInstr is at the beginning of the BB.
2384 if (I == B) return false;
2386 // There are two possible candidates which can be changed to set CPSR:
2387 // One is MI, the other is a SUB instruction.
2388 // For CMPrr(r1,r2), we are looking for SUB(r1,r2) or SUB(r2,r1).
2389 // For CMPri(r1, CmpValue), we are looking for SUBri(r1, CmpValue).
2390 MachineInstr *Sub = nullptr;
2392 // MI is not a candidate for CMPrr.
2394 else if (MI->getParent() != CmpInstr->getParent() || CmpValue != 0) {
2395 // Conservatively refuse to convert an instruction which isn't in the same
2396 // BB as the comparison.
2397 // For CMPri w/ CmpValue != 0, a Sub may still be a candidate.
2398 // Thus we cannot return here.
2399 if (CmpInstr->getOpcode() == ARM::CMPri ||
2400 CmpInstr->getOpcode() == ARM::t2CMPri)
2406 // Check that CPSR isn't set between the comparison instruction and the one we
2407 // want to change. At the same time, search for Sub.
2408 const TargetRegisterInfo *TRI = &getRegisterInfo();
2410 for (; I != E; --I) {
2411 const MachineInstr &Instr = *I;
2413 if (Instr.modifiesRegister(ARM::CPSR, TRI) ||
2414 Instr.readsRegister(ARM::CPSR, TRI))
2415 // This instruction modifies or uses CPSR after the one we want to
2416 // change. We can't do this transformation.
2419 // Check whether CmpInstr can be made redundant by the current instruction.
2420 if (isRedundantFlagInstr(CmpInstr, SrcReg, SrcReg2, CmpValue, &*I)) {
2426 // The 'and' is below the comparison instruction.
2430 // Return false if no candidates exist.
2434 // The single candidate is called MI.
2437 // We can't use a predicated instruction - it doesn't always write the flags.
2438 if (isPredicated(MI))
2441 switch (MI->getOpcode()) {
2475 case ARM::t2EORri: {
2476 // Scan forward for the use of CPSR
2477 // When checking against MI: if it's a conditional code that requires
2478 // checking of the V bit or C bit, then this is not safe to do.
2479 // It is safe to remove CmpInstr if CPSR is redefined or killed.
2480 // If we are done with the basic block, we need to check whether CPSR is
2482 SmallVector<std::pair<MachineOperand*, ARMCC::CondCodes>, 4>
2484 bool isSafe = false;
2486 E = CmpInstr->getParent()->end();
2487 while (!isSafe && ++I != E) {
2488 const MachineInstr &Instr = *I;
2489 for (unsigned IO = 0, EO = Instr.getNumOperands();
2490 !isSafe && IO != EO; ++IO) {
2491 const MachineOperand &MO = Instr.getOperand(IO);
2492 if (MO.isRegMask() && MO.clobbersPhysReg(ARM::CPSR)) {
2496 if (!MO.isReg() || MO.getReg() != ARM::CPSR)
2502 // Condition code is after the operand before CPSR except for VSELs.
2503 ARMCC::CondCodes CC;
2504 bool IsInstrVSel = true;
2505 switch (Instr.getOpcode()) {
2507 IsInstrVSel = false;
2508 CC = (ARMCC::CondCodes)Instr.getOperand(IO - 1).getImm();
2529 ARMCC::CondCodes NewCC = getSwappedCondition(CC);
2530 if (NewCC == ARMCC::AL)
2532 // If we have SUB(r1, r2) and CMP(r2, r1), the condition code based
2533 // on CMP needs to be updated to be based on SUB.
2534 // Push the condition code operands to OperandsToUpdate.
2535 // If it is safe to remove CmpInstr, the condition code of these
2536 // operands will be modified.
2537 if (SrcReg2 != 0 && Sub->getOperand(1).getReg() == SrcReg2 &&
2538 Sub->getOperand(2).getReg() == SrcReg) {
2539 // VSel doesn't support condition code update.
2542 OperandsToUpdate.push_back(
2543 std::make_pair(&((*I).getOperand(IO - 1)), NewCC));
2546 // No Sub, so this is x = <op> y, z; cmp x, 0.
2548 case ARMCC::EQ: // Z
2549 case ARMCC::NE: // Z
2550 case ARMCC::MI: // N
2551 case ARMCC::PL: // N
2552 case ARMCC::AL: // none
2553 // CPSR can be used multiple times, we should continue.
2555 case ARMCC::HS: // C
2556 case ARMCC::LO: // C
2557 case ARMCC::VS: // V
2558 case ARMCC::VC: // V
2559 case ARMCC::HI: // C Z
2560 case ARMCC::LS: // C Z
2561 case ARMCC::GE: // N V
2562 case ARMCC::LT: // N V
2563 case ARMCC::GT: // Z N V
2564 case ARMCC::LE: // Z N V
2565 // The instruction uses the V bit or C bit which is not safe.
2572 // If CPSR is not killed nor re-defined, we should check whether it is
2573 // live-out. If it is live-out, do not optimize.
2575 MachineBasicBlock *MBB = CmpInstr->getParent();
2576 for (MachineBasicBlock::succ_iterator SI = MBB->succ_begin(),
2577 SE = MBB->succ_end(); SI != SE; ++SI)
2578 if ((*SI)->isLiveIn(ARM::CPSR))
2582 // Toggle the optional operand to CPSR.
2583 MI->getOperand(5).setReg(ARM::CPSR);
2584 MI->getOperand(5).setIsDef(true);
2585 assert(!isPredicated(MI) && "Can't use flags from predicated instruction");
2586 CmpInstr->eraseFromParent();
2588 // Modify the condition code of operands in OperandsToUpdate.
2589 // Since we have SUB(r1, r2) and CMP(r2, r1), the condition code needs to
2590 // be changed from r2 > r1 to r1 < r2, from r2 < r1 to r1 > r2, etc.
2591 for (unsigned i = 0, e = OperandsToUpdate.size(); i < e; i++)
2592 OperandsToUpdate[i].first->setImm(OperandsToUpdate[i].second);
2600 bool ARMBaseInstrInfo::FoldImmediate(MachineInstr *UseMI,
2601 MachineInstr *DefMI, unsigned Reg,
2602 MachineRegisterInfo *MRI) const {
2603 // Fold large immediates into add, sub, or, xor.
2604 unsigned DefOpc = DefMI->getOpcode();
2605 if (DefOpc != ARM::t2MOVi32imm && DefOpc != ARM::MOVi32imm)
2607 if (!DefMI->getOperand(1).isImm())
2608 // Could be t2MOVi32imm <ga:xx>
2611 if (!MRI->hasOneNonDBGUse(Reg))
2614 const MCInstrDesc &DefMCID = DefMI->getDesc();
2615 if (DefMCID.hasOptionalDef()) {
2616 unsigned NumOps = DefMCID.getNumOperands();
2617 const MachineOperand &MO = DefMI->getOperand(NumOps-1);
2618 if (MO.getReg() == ARM::CPSR && !MO.isDead())
2619 // If DefMI defines CPSR and it is not dead, it's obviously not safe
2624 const MCInstrDesc &UseMCID = UseMI->getDesc();
2625 if (UseMCID.hasOptionalDef()) {
2626 unsigned NumOps = UseMCID.getNumOperands();
2627 if (UseMI->getOperand(NumOps-1).getReg() == ARM::CPSR)
2628 // If the instruction sets the flag, do not attempt this optimization
2629 // since it may change the semantics of the code.
2633 unsigned UseOpc = UseMI->getOpcode();
2634 unsigned NewUseOpc = 0;
2635 uint32_t ImmVal = (uint32_t)DefMI->getOperand(1).getImm();
2636 uint32_t SOImmValV1 = 0, SOImmValV2 = 0;
2637 bool Commute = false;
2639 default: return false;
2647 case ARM::t2EORrr: {
2648 Commute = UseMI->getOperand(2).getReg() != Reg;
2655 NewUseOpc = ARM::SUBri;
2661 if (!ARM_AM::isSOImmTwoPartVal(ImmVal))
2663 SOImmValV1 = (uint32_t)ARM_AM::getSOImmTwoPartFirst(ImmVal);
2664 SOImmValV2 = (uint32_t)ARM_AM::getSOImmTwoPartSecond(ImmVal);
2667 case ARM::ADDrr: NewUseOpc = ARM::ADDri; break;
2668 case ARM::ORRrr: NewUseOpc = ARM::ORRri; break;
2669 case ARM::EORrr: NewUseOpc = ARM::EORri; break;
2673 case ARM::t2SUBrr: {
2677 NewUseOpc = ARM::t2SUBri;
2682 case ARM::t2EORrr: {
2683 if (!ARM_AM::isT2SOImmTwoPartVal(ImmVal))
2685 SOImmValV1 = (uint32_t)ARM_AM::getT2SOImmTwoPartFirst(ImmVal);
2686 SOImmValV2 = (uint32_t)ARM_AM::getT2SOImmTwoPartSecond(ImmVal);
2689 case ARM::t2ADDrr: NewUseOpc = ARM::t2ADDri; break;
2690 case ARM::t2ORRrr: NewUseOpc = ARM::t2ORRri; break;
2691 case ARM::t2EORrr: NewUseOpc = ARM::t2EORri; break;
2699 unsigned OpIdx = Commute ? 2 : 1;
2700 unsigned Reg1 = UseMI->getOperand(OpIdx).getReg();
2701 bool isKill = UseMI->getOperand(OpIdx).isKill();
2702 unsigned NewReg = MRI->createVirtualRegister(MRI->getRegClass(Reg));
2703 AddDefaultCC(AddDefaultPred(BuildMI(*UseMI->getParent(),
2704 UseMI, UseMI->getDebugLoc(),
2705 get(NewUseOpc), NewReg)
2706 .addReg(Reg1, getKillRegState(isKill))
2707 .addImm(SOImmValV1)));
2708 UseMI->setDesc(get(NewUseOpc));
2709 UseMI->getOperand(1).setReg(NewReg);
2710 UseMI->getOperand(1).setIsKill();
2711 UseMI->getOperand(2).ChangeToImmediate(SOImmValV2);
2712 DefMI->eraseFromParent();
2716 static unsigned getNumMicroOpsSwiftLdSt(const InstrItineraryData *ItinData,
2717 const MachineInstr *MI) {
2718 switch (MI->getOpcode()) {
2720 const MCInstrDesc &Desc = MI->getDesc();
2721 int UOps = ItinData->getNumMicroOps(Desc.getSchedClass());
2722 assert(UOps >= 0 && "bad # UOps");
2730 unsigned ShOpVal = MI->getOperand(3).getImm();
2731 bool isSub = ARM_AM::getAM2Op(ShOpVal) == ARM_AM::sub;
2732 unsigned ShImm = ARM_AM::getAM2Offset(ShOpVal);
2735 ((ShImm == 1 || ShImm == 2 || ShImm == 3) &&
2736 ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl)))
2743 if (!MI->getOperand(2).getReg())
2746 unsigned ShOpVal = MI->getOperand(3).getImm();
2747 bool isSub = ARM_AM::getAM2Op(ShOpVal) == ARM_AM::sub;
2748 unsigned ShImm = ARM_AM::getAM2Offset(ShOpVal);
2751 ((ShImm == 1 || ShImm == 2 || ShImm == 3) &&
2752 ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl)))
2759 return (ARM_AM::getAM3Op(MI->getOperand(3).getImm()) == ARM_AM::sub) ? 3:2;
2761 case ARM::LDRSB_POST:
2762 case ARM::LDRSH_POST: {
2763 unsigned Rt = MI->getOperand(0).getReg();
2764 unsigned Rm = MI->getOperand(3).getReg();
2765 return (Rt == Rm) ? 4 : 3;
2768 case ARM::LDR_PRE_REG:
2769 case ARM::LDRB_PRE_REG: {
2770 unsigned Rt = MI->getOperand(0).getReg();
2771 unsigned Rm = MI->getOperand(3).getReg();
2774 unsigned ShOpVal = MI->getOperand(4).getImm();
2775 bool isSub = ARM_AM::getAM2Op(ShOpVal) == ARM_AM::sub;
2776 unsigned ShImm = ARM_AM::getAM2Offset(ShOpVal);
2779 ((ShImm == 1 || ShImm == 2 || ShImm == 3) &&
2780 ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl)))
2785 case ARM::STR_PRE_REG:
2786 case ARM::STRB_PRE_REG: {
2787 unsigned ShOpVal = MI->getOperand(4).getImm();
2788 bool isSub = ARM_AM::getAM2Op(ShOpVal) == ARM_AM::sub;
2789 unsigned ShImm = ARM_AM::getAM2Offset(ShOpVal);
2792 ((ShImm == 1 || ShImm == 2 || ShImm == 3) &&
2793 ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl)))
2799 case ARM::STRH_PRE: {
2800 unsigned Rt = MI->getOperand(0).getReg();
2801 unsigned Rm = MI->getOperand(3).getReg();
2806 return (ARM_AM::getAM3Op(MI->getOperand(4).getImm()) == ARM_AM::sub)
2810 case ARM::LDR_POST_REG:
2811 case ARM::LDRB_POST_REG:
2812 case ARM::LDRH_POST: {
2813 unsigned Rt = MI->getOperand(0).getReg();
2814 unsigned Rm = MI->getOperand(3).getReg();
2815 return (Rt == Rm) ? 3 : 2;
2818 case ARM::LDR_PRE_IMM:
2819 case ARM::LDRB_PRE_IMM:
2820 case ARM::LDR_POST_IMM:
2821 case ARM::LDRB_POST_IMM:
2822 case ARM::STRB_POST_IMM:
2823 case ARM::STRB_POST_REG:
2824 case ARM::STRB_PRE_IMM:
2825 case ARM::STRH_POST:
2826 case ARM::STR_POST_IMM:
2827 case ARM::STR_POST_REG:
2828 case ARM::STR_PRE_IMM:
2831 case ARM::LDRSB_PRE:
2832 case ARM::LDRSH_PRE: {
2833 unsigned Rm = MI->getOperand(3).getReg();
2836 unsigned Rt = MI->getOperand(0).getReg();
2839 unsigned ShOpVal = MI->getOperand(4).getImm();
2840 bool isSub = ARM_AM::getAM2Op(ShOpVal) == ARM_AM::sub;
2841 unsigned ShImm = ARM_AM::getAM2Offset(ShOpVal);
2844 ((ShImm == 1 || ShImm == 2 || ShImm == 3) &&
2845 ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl)))
2851 unsigned Rt = MI->getOperand(0).getReg();
2852 unsigned Rn = MI->getOperand(2).getReg();
2853 unsigned Rm = MI->getOperand(3).getReg();
2855 return (ARM_AM::getAM3Op(MI->getOperand(4).getImm()) == ARM_AM::sub) ?4:3;
2856 return (Rt == Rn) ? 3 : 2;
2860 unsigned Rm = MI->getOperand(3).getReg();
2862 return (ARM_AM::getAM3Op(MI->getOperand(4).getImm()) == ARM_AM::sub) ?4:3;
2866 case ARM::LDRD_POST:
2867 case ARM::t2LDRD_POST:
2870 case ARM::STRD_POST:
2871 case ARM::t2STRD_POST:
2874 case ARM::LDRD_PRE: {
2875 unsigned Rt = MI->getOperand(0).getReg();
2876 unsigned Rn = MI->getOperand(3).getReg();
2877 unsigned Rm = MI->getOperand(4).getReg();
2879 return (ARM_AM::getAM3Op(MI->getOperand(5).getImm()) == ARM_AM::sub) ?5:4;
2880 return (Rt == Rn) ? 4 : 3;
2883 case ARM::t2LDRD_PRE: {
2884 unsigned Rt = MI->getOperand(0).getReg();
2885 unsigned Rn = MI->getOperand(3).getReg();
2886 return (Rt == Rn) ? 4 : 3;
2889 case ARM::STRD_PRE: {
2890 unsigned Rm = MI->getOperand(4).getReg();
2892 return (ARM_AM::getAM3Op(MI->getOperand(5).getImm()) == ARM_AM::sub) ?5:4;
2896 case ARM::t2STRD_PRE:
2899 case ARM::t2LDR_POST:
2900 case ARM::t2LDRB_POST:
2901 case ARM::t2LDRB_PRE:
2902 case ARM::t2LDRSBi12:
2903 case ARM::t2LDRSBi8:
2904 case ARM::t2LDRSBpci:
2906 case ARM::t2LDRH_POST:
2907 case ARM::t2LDRH_PRE:
2909 case ARM::t2LDRSB_POST:
2910 case ARM::t2LDRSB_PRE:
2911 case ARM::t2LDRSH_POST:
2912 case ARM::t2LDRSH_PRE:
2913 case ARM::t2LDRSHi12:
2914 case ARM::t2LDRSHi8:
2915 case ARM::t2LDRSHpci:
2919 case ARM::t2LDRDi8: {
2920 unsigned Rt = MI->getOperand(0).getReg();
2921 unsigned Rn = MI->getOperand(2).getReg();
2922 return (Rt == Rn) ? 3 : 2;
2925 case ARM::t2STRB_POST:
2926 case ARM::t2STRB_PRE:
2929 case ARM::t2STRH_POST:
2930 case ARM::t2STRH_PRE:
2932 case ARM::t2STR_POST:
2933 case ARM::t2STR_PRE:
2939 // Return the number of 32-bit words loaded by LDM or stored by STM. If this
2940 // can't be easily determined return 0 (missing MachineMemOperand).
2942 // FIXME: The current MachineInstr design does not support relying on machine
2943 // mem operands to determine the width of a memory access. Instead, we expect
2944 // the target to provide this information based on the instruction opcode and
2945 // operands. However, using MachineMemOperand is the best solution now for
2948 // 1) getNumMicroOps tries to infer LDM memory width from the total number of MI
2949 // operands. This is much more dangerous than using the MachineMemOperand
2950 // sizes because CodeGen passes can insert/remove optional machine operands. In
2951 // fact, it's totally incorrect for preRA passes and appears to be wrong for
2952 // postRA passes as well.
2954 // 2) getNumLDMAddresses is only used by the scheduling machine model and any
2955 // machine model that calls this should handle the unknown (zero size) case.
2957 // Long term, we should require a target hook that verifies MachineMemOperand
2958 // sizes during MC lowering. That target hook should be local to MC lowering
2959 // because we can't ensure that it is aware of other MI forms. Doing this will
2960 // ensure that MachineMemOperands are correctly propagated through all passes.
2961 unsigned ARMBaseInstrInfo::getNumLDMAddresses(const MachineInstr *MI) const {
2963 for (MachineInstr::mmo_iterator I = MI->memoperands_begin(),
2964 E = MI->memoperands_end(); I != E; ++I) {
2965 Size += (*I)->getSize();
2971 ARMBaseInstrInfo::getNumMicroOps(const InstrItineraryData *ItinData,
2972 const MachineInstr *MI) const {
2973 if (!ItinData || ItinData->isEmpty())
2976 const MCInstrDesc &Desc = MI->getDesc();
2977 unsigned Class = Desc.getSchedClass();
2978 int ItinUOps = ItinData->getNumMicroOps(Class);
2979 if (ItinUOps >= 0) {
2980 if (Subtarget.isSwift() && (Desc.mayLoad() || Desc.mayStore()))
2981 return getNumMicroOpsSwiftLdSt(ItinData, MI);
2986 unsigned Opc = MI->getOpcode();
2989 llvm_unreachable("Unexpected multi-uops instruction!");
2994 // The number of uOps for load / store multiple are determined by the number
2997 // On Cortex-A8, each pair of register loads / stores can be scheduled on the
2998 // same cycle. The scheduling for the first load / store must be done
2999 // separately by assuming the address is not 64-bit aligned.
3001 // On Cortex-A9, the formula is simply (#reg / 2) + (#reg % 2). If the address
3002 // is not 64-bit aligned, then AGU would take an extra cycle. For VFP / NEON
3003 // load / store multiple, the formula is (#reg / 2) + (#reg % 2) + 1.
3005 case ARM::VLDMDIA_UPD:
3006 case ARM::VLDMDDB_UPD:
3008 case ARM::VLDMSIA_UPD:
3009 case ARM::VLDMSDB_UPD:
3011 case ARM::VSTMDIA_UPD:
3012 case ARM::VSTMDDB_UPD:
3014 case ARM::VSTMSIA_UPD:
3015 case ARM::VSTMSDB_UPD: {
3016 unsigned NumRegs = MI->getNumOperands() - Desc.getNumOperands();
3017 return (NumRegs / 2) + (NumRegs % 2) + 1;
3020 case ARM::LDMIA_RET:
3025 case ARM::LDMIA_UPD:
3026 case ARM::LDMDA_UPD:
3027 case ARM::LDMDB_UPD:
3028 case ARM::LDMIB_UPD:
3033 case ARM::STMIA_UPD:
3034 case ARM::STMDA_UPD:
3035 case ARM::STMDB_UPD:
3036 case ARM::STMIB_UPD:
3038 case ARM::tLDMIA_UPD:
3039 case ARM::tSTMIA_UPD:
3043 case ARM::t2LDMIA_RET:
3046 case ARM::t2LDMIA_UPD:
3047 case ARM::t2LDMDB_UPD:
3050 case ARM::t2STMIA_UPD:
3051 case ARM::t2STMDB_UPD: {
3052 unsigned NumRegs = MI->getNumOperands() - Desc.getNumOperands() + 1;
3053 if (Subtarget.isSwift()) {
3054 int UOps = 1 + NumRegs; // One for address computation, one for each ld / st.
3057 case ARM::VLDMDIA_UPD:
3058 case ARM::VLDMDDB_UPD:
3059 case ARM::VLDMSIA_UPD:
3060 case ARM::VLDMSDB_UPD:
3061 case ARM::VSTMDIA_UPD:
3062 case ARM::VSTMDDB_UPD:
3063 case ARM::VSTMSIA_UPD:
3064 case ARM::VSTMSDB_UPD:
3065 case ARM::LDMIA_UPD:
3066 case ARM::LDMDA_UPD:
3067 case ARM::LDMDB_UPD:
3068 case ARM::LDMIB_UPD:
3069 case ARM::STMIA_UPD:
3070 case ARM::STMDA_UPD:
3071 case ARM::STMDB_UPD:
3072 case ARM::STMIB_UPD:
3073 case ARM::tLDMIA_UPD:
3074 case ARM::tSTMIA_UPD:
3075 case ARM::t2LDMIA_UPD:
3076 case ARM::t2LDMDB_UPD:
3077 case ARM::t2STMIA_UPD:
3078 case ARM::t2STMDB_UPD:
3079 ++UOps; // One for base register writeback.
3081 case ARM::LDMIA_RET:
3083 case ARM::t2LDMIA_RET:
3084 UOps += 2; // One for base reg wb, one for write to pc.
3088 } else if (Subtarget.isCortexA8() || Subtarget.isCortexA7()) {
3091 // 4 registers would be issued: 2, 2.
3092 // 5 registers would be issued: 2, 2, 1.
3093 int A8UOps = (NumRegs / 2);
3097 } else if (Subtarget.isLikeA9() || Subtarget.isSwift()) {
3098 int A9UOps = (NumRegs / 2);
3099 // If there are odd number of registers or if it's not 64-bit aligned,
3100 // then it takes an extra AGU (Address Generation Unit) cycle.
3101 if ((NumRegs % 2) ||
3102 !MI->hasOneMemOperand() ||
3103 (*MI->memoperands_begin())->getAlignment() < 8)
3107 // Assume the worst.
3115 ARMBaseInstrInfo::getVLDMDefCycle(const InstrItineraryData *ItinData,
3116 const MCInstrDesc &DefMCID,
3118 unsigned DefIdx, unsigned DefAlign) const {
3119 int RegNo = (int)(DefIdx+1) - DefMCID.getNumOperands() + 1;
3121 // Def is the address writeback.
3122 return ItinData->getOperandCycle(DefClass, DefIdx);
3125 if (Subtarget.isCortexA8() || Subtarget.isCortexA7()) {
3126 // (regno / 2) + (regno % 2) + 1
3127 DefCycle = RegNo / 2 + 1;
3130 } else if (Subtarget.isLikeA9() || Subtarget.isSwift()) {
3132 bool isSLoad = false;
3134 switch (DefMCID.getOpcode()) {
3137 case ARM::VLDMSIA_UPD:
3138 case ARM::VLDMSDB_UPD:
3143 // If there are odd number of 'S' registers or if it's not 64-bit aligned,
3144 // then it takes an extra cycle.
3145 if ((isSLoad && (RegNo % 2)) || DefAlign < 8)
3148 // Assume the worst.
3149 DefCycle = RegNo + 2;
3156 ARMBaseInstrInfo::getLDMDefCycle(const InstrItineraryData *ItinData,
3157 const MCInstrDesc &DefMCID,
3159 unsigned DefIdx, unsigned DefAlign) const {
3160 int RegNo = (int)(DefIdx+1) - DefMCID.getNumOperands() + 1;
3162 // Def is the address writeback.
3163 return ItinData->getOperandCycle(DefClass, DefIdx);
3166 if (Subtarget.isCortexA8() || Subtarget.isCortexA7()) {
3167 // 4 registers would be issued: 1, 2, 1.
3168 // 5 registers would be issued: 1, 2, 2.
3169 DefCycle = RegNo / 2;
3172 // Result latency is issue cycle + 2: E2.
3174 } else if (Subtarget.isLikeA9() || Subtarget.isSwift()) {
3175 DefCycle = (RegNo / 2);
3176 // If there are odd number of registers or if it's not 64-bit aligned,
3177 // then it takes an extra AGU (Address Generation Unit) cycle.
3178 if ((RegNo % 2) || DefAlign < 8)
3180 // Result latency is AGU cycles + 2.
3183 // Assume the worst.
3184 DefCycle = RegNo + 2;
3191 ARMBaseInstrInfo::getVSTMUseCycle(const InstrItineraryData *ItinData,
3192 const MCInstrDesc &UseMCID,
3194 unsigned UseIdx, unsigned UseAlign) const {
3195 int RegNo = (int)(UseIdx+1) - UseMCID.getNumOperands() + 1;
3197 return ItinData->getOperandCycle(UseClass, UseIdx);
3200 if (Subtarget.isCortexA8() || Subtarget.isCortexA7()) {
3201 // (regno / 2) + (regno % 2) + 1
3202 UseCycle = RegNo / 2 + 1;
3205 } else if (Subtarget.isLikeA9() || Subtarget.isSwift()) {
3207 bool isSStore = false;
3209 switch (UseMCID.getOpcode()) {
3212 case ARM::VSTMSIA_UPD:
3213 case ARM::VSTMSDB_UPD:
3218 // If there are odd number of 'S' registers or if it's not 64-bit aligned,
3219 // then it takes an extra cycle.
3220 if ((isSStore && (RegNo % 2)) || UseAlign < 8)
3223 // Assume the worst.
3224 UseCycle = RegNo + 2;
3231 ARMBaseInstrInfo::getSTMUseCycle(const InstrItineraryData *ItinData,
3232 const MCInstrDesc &UseMCID,
3234 unsigned UseIdx, unsigned UseAlign) const {
3235 int RegNo = (int)(UseIdx+1) - UseMCID.getNumOperands() + 1;
3237 return ItinData->getOperandCycle(UseClass, UseIdx);
3240 if (Subtarget.isCortexA8() || Subtarget.isCortexA7()) {
3241 UseCycle = RegNo / 2;
3246 } else if (Subtarget.isLikeA9() || Subtarget.isSwift()) {
3247 UseCycle = (RegNo / 2);
3248 // If there are odd number of registers or if it's not 64-bit aligned,
3249 // then it takes an extra AGU (Address Generation Unit) cycle.
3250 if ((RegNo % 2) || UseAlign < 8)
3253 // Assume the worst.
3260 ARMBaseInstrInfo::getOperandLatency(const InstrItineraryData *ItinData,
3261 const MCInstrDesc &DefMCID,
3262 unsigned DefIdx, unsigned DefAlign,
3263 const MCInstrDesc &UseMCID,
3264 unsigned UseIdx, unsigned UseAlign) const {
3265 unsigned DefClass = DefMCID.getSchedClass();
3266 unsigned UseClass = UseMCID.getSchedClass();
3268 if (DefIdx < DefMCID.getNumDefs() && UseIdx < UseMCID.getNumOperands())
3269 return ItinData->getOperandLatency(DefClass, DefIdx, UseClass, UseIdx);
3271 // This may be a def / use of a variable_ops instruction, the operand
3272 // latency might be determinable dynamically. Let the target try to
3275 bool LdmBypass = false;
3276 switch (DefMCID.getOpcode()) {
3278 DefCycle = ItinData->getOperandCycle(DefClass, DefIdx);
3282 case ARM::VLDMDIA_UPD:
3283 case ARM::VLDMDDB_UPD:
3285 case ARM::VLDMSIA_UPD:
3286 case ARM::VLDMSDB_UPD:
3287 DefCycle = getVLDMDefCycle(ItinData, DefMCID, DefClass, DefIdx, DefAlign);
3290 case ARM::LDMIA_RET:
3295 case ARM::LDMIA_UPD:
3296 case ARM::LDMDA_UPD:
3297 case ARM::LDMDB_UPD:
3298 case ARM::LDMIB_UPD:
3300 case ARM::tLDMIA_UPD:
3302 case ARM::t2LDMIA_RET:
3305 case ARM::t2LDMIA_UPD:
3306 case ARM::t2LDMDB_UPD:
3308 DefCycle = getLDMDefCycle(ItinData, DefMCID, DefClass, DefIdx, DefAlign);
3313 // We can't seem to determine the result latency of the def, assume it's 2.
3317 switch (UseMCID.getOpcode()) {
3319 UseCycle = ItinData->getOperandCycle(UseClass, UseIdx);
3323 case ARM::VSTMDIA_UPD:
3324 case ARM::VSTMDDB_UPD:
3326 case ARM::VSTMSIA_UPD:
3327 case ARM::VSTMSDB_UPD:
3328 UseCycle = getVSTMUseCycle(ItinData, UseMCID, UseClass, UseIdx, UseAlign);
3335 case ARM::STMIA_UPD:
3336 case ARM::STMDA_UPD:
3337 case ARM::STMDB_UPD:
3338 case ARM::STMIB_UPD:
3339 case ARM::tSTMIA_UPD:
3344 case ARM::t2STMIA_UPD:
3345 case ARM::t2STMDB_UPD:
3346 UseCycle = getSTMUseCycle(ItinData, UseMCID, UseClass, UseIdx, UseAlign);
3351 // Assume it's read in the first stage.
3354 UseCycle = DefCycle - UseCycle + 1;
3357 // It's a variable_ops instruction so we can't use DefIdx here. Just use
3358 // first def operand.
3359 if (ItinData->hasPipelineForwarding(DefClass, DefMCID.getNumOperands()-1,
3362 } else if (ItinData->hasPipelineForwarding(DefClass, DefIdx,
3363 UseClass, UseIdx)) {
3371 static const MachineInstr *getBundledDefMI(const TargetRegisterInfo *TRI,
3372 const MachineInstr *MI, unsigned Reg,
3373 unsigned &DefIdx, unsigned &Dist) {
3376 MachineBasicBlock::const_iterator I = MI; ++I;
3377 MachineBasicBlock::const_instr_iterator II = std::prev(I.getInstrIterator());
3378 assert(II->isInsideBundle() && "Empty bundle?");
3381 while (II->isInsideBundle()) {
3382 Idx = II->findRegisterDefOperandIdx(Reg, false, true, TRI);
3389 assert(Idx != -1 && "Cannot find bundled definition!");
3394 static const MachineInstr *getBundledUseMI(const TargetRegisterInfo *TRI,
3395 const MachineInstr *MI, unsigned Reg,
3396 unsigned &UseIdx, unsigned &Dist) {
3399 MachineBasicBlock::const_instr_iterator II = MI; ++II;
3400 assert(II->isInsideBundle() && "Empty bundle?");
3401 MachineBasicBlock::const_instr_iterator E = MI->getParent()->instr_end();
3403 // FIXME: This doesn't properly handle multiple uses.
3405 while (II != E && II->isInsideBundle()) {
3406 Idx = II->findRegisterUseOperandIdx(Reg, false, TRI);
3409 if (II->getOpcode() != ARM::t2IT)
3423 /// Return the number of cycles to add to (or subtract from) the static
3424 /// itinerary based on the def opcode and alignment. The caller will ensure that
3425 /// adjusted latency is at least one cycle.
3426 static int adjustDefLatency(const ARMSubtarget &Subtarget,
3427 const MachineInstr *DefMI,
3428 const MCInstrDesc *DefMCID, unsigned DefAlign) {
3430 if (Subtarget.isCortexA8() || Subtarget.isLikeA9() || Subtarget.isCortexA7()) {
3431 // FIXME: Shifter op hack: no shift (i.e. [r +/- r]) or [r + r << 2]
3432 // variants are one cycle cheaper.
3433 switch (DefMCID->getOpcode()) {
3437 unsigned ShOpVal = DefMI->getOperand(3).getImm();
3438 unsigned ShImm = ARM_AM::getAM2Offset(ShOpVal);
3440 (ShImm == 2 && ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl))
3447 case ARM::t2LDRSHs: {
3448 // Thumb2 mode: lsl only.
3449 unsigned ShAmt = DefMI->getOperand(3).getImm();
3450 if (ShAmt == 0 || ShAmt == 2)
3455 } else if (Subtarget.isSwift()) {
3456 // FIXME: Properly handle all of the latency adjustments for address
3458 switch (DefMCID->getOpcode()) {
3462 unsigned ShOpVal = DefMI->getOperand(3).getImm();
3463 bool isSub = ARM_AM::getAM2Op(ShOpVal) == ARM_AM::sub;
3464 unsigned ShImm = ARM_AM::getAM2Offset(ShOpVal);
3467 ((ShImm == 1 || ShImm == 2 || ShImm == 3) &&
3468 ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl)))
3471 ShImm == 1 && ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsr)
3478 case ARM::t2LDRSHs: {
3479 // Thumb2 mode: lsl only.
3480 unsigned ShAmt = DefMI->getOperand(3).getImm();
3481 if (ShAmt == 0 || ShAmt == 1 || ShAmt == 2 || ShAmt == 3)
3488 if (DefAlign < 8 && Subtarget.isLikeA9()) {
3489 switch (DefMCID->getOpcode()) {
3495 case ARM::VLD1q8wb_fixed:
3496 case ARM::VLD1q16wb_fixed:
3497 case ARM::VLD1q32wb_fixed:
3498 case ARM::VLD1q64wb_fixed:
3499 case ARM::VLD1q8wb_register:
3500 case ARM::VLD1q16wb_register:
3501 case ARM::VLD1q32wb_register:
3502 case ARM::VLD1q64wb_register:
3509 case ARM::VLD2d8wb_fixed:
3510 case ARM::VLD2d16wb_fixed:
3511 case ARM::VLD2d32wb_fixed:
3512 case ARM::VLD2q8wb_fixed:
3513 case ARM::VLD2q16wb_fixed:
3514 case ARM::VLD2q32wb_fixed:
3515 case ARM::VLD2d8wb_register:
3516 case ARM::VLD2d16wb_register:
3517 case ARM::VLD2d32wb_register:
3518 case ARM::VLD2q8wb_register:
3519 case ARM::VLD2q16wb_register:
3520 case ARM::VLD2q32wb_register:
3525 case ARM::VLD3d8_UPD:
3526 case ARM::VLD3d16_UPD:
3527 case ARM::VLD3d32_UPD:
3528 case ARM::VLD1d64Twb_fixed:
3529 case ARM::VLD1d64Twb_register:
3530 case ARM::VLD3q8_UPD:
3531 case ARM::VLD3q16_UPD:
3532 case ARM::VLD3q32_UPD:
3537 case ARM::VLD4d8_UPD:
3538 case ARM::VLD4d16_UPD:
3539 case ARM::VLD4d32_UPD:
3540 case ARM::VLD1d64Qwb_fixed:
3541 case ARM::VLD1d64Qwb_register:
3542 case ARM::VLD4q8_UPD:
3543 case ARM::VLD4q16_UPD:
3544 case ARM::VLD4q32_UPD:
3545 case ARM::VLD1DUPq8:
3546 case ARM::VLD1DUPq16:
3547 case ARM::VLD1DUPq32:
3548 case ARM::VLD1DUPq8wb_fixed:
3549 case ARM::VLD1DUPq16wb_fixed:
3550 case ARM::VLD1DUPq32wb_fixed:
3551 case ARM::VLD1DUPq8wb_register:
3552 case ARM::VLD1DUPq16wb_register:
3553 case ARM::VLD1DUPq32wb_register:
3554 case ARM::VLD2DUPd8:
3555 case ARM::VLD2DUPd16:
3556 case ARM::VLD2DUPd32:
3557 case ARM::VLD2DUPd8wb_fixed:
3558 case ARM::VLD2DUPd16wb_fixed:
3559 case ARM::VLD2DUPd32wb_fixed:
3560 case ARM::VLD2DUPd8wb_register:
3561 case ARM::VLD2DUPd16wb_register:
3562 case ARM::VLD2DUPd32wb_register:
3563 case ARM::VLD4DUPd8:
3564 case ARM::VLD4DUPd16:
3565 case ARM::VLD4DUPd32:
3566 case ARM::VLD4DUPd8_UPD:
3567 case ARM::VLD4DUPd16_UPD:
3568 case ARM::VLD4DUPd32_UPD:
3570 case ARM::VLD1LNd16:
3571 case ARM::VLD1LNd32:
3572 case ARM::VLD1LNd8_UPD:
3573 case ARM::VLD1LNd16_UPD:
3574 case ARM::VLD1LNd32_UPD:
3576 case ARM::VLD2LNd16:
3577 case ARM::VLD2LNd32:
3578 case ARM::VLD2LNq16:
3579 case ARM::VLD2LNq32:
3580 case ARM::VLD2LNd8_UPD:
3581 case ARM::VLD2LNd16_UPD:
3582 case ARM::VLD2LNd32_UPD:
3583 case ARM::VLD2LNq16_UPD:
3584 case ARM::VLD2LNq32_UPD:
3586 case ARM::VLD4LNd16:
3587 case ARM::VLD4LNd32:
3588 case ARM::VLD4LNq16:
3589 case ARM::VLD4LNq32:
3590 case ARM::VLD4LNd8_UPD:
3591 case ARM::VLD4LNd16_UPD:
3592 case ARM::VLD4LNd32_UPD:
3593 case ARM::VLD4LNq16_UPD:
3594 case ARM::VLD4LNq32_UPD:
3595 // If the address is not 64-bit aligned, the latencies of these
3596 // instructions increases by one.
3607 ARMBaseInstrInfo::getOperandLatency(const InstrItineraryData *ItinData,
3608 const MachineInstr *DefMI, unsigned DefIdx,
3609 const MachineInstr *UseMI,
3610 unsigned UseIdx) const {
3611 // No operand latency. The caller may fall back to getInstrLatency.
3612 if (!ItinData || ItinData->isEmpty())
3615 const MachineOperand &DefMO = DefMI->getOperand(DefIdx);
3616 unsigned Reg = DefMO.getReg();
3617 const MCInstrDesc *DefMCID = &DefMI->getDesc();
3618 const MCInstrDesc *UseMCID = &UseMI->getDesc();
3620 unsigned DefAdj = 0;
3621 if (DefMI->isBundle()) {
3622 DefMI = getBundledDefMI(&getRegisterInfo(), DefMI, Reg, DefIdx, DefAdj);
3623 DefMCID = &DefMI->getDesc();
3625 if (DefMI->isCopyLike() || DefMI->isInsertSubreg() ||
3626 DefMI->isRegSequence() || DefMI->isImplicitDef()) {
3630 unsigned UseAdj = 0;
3631 if (UseMI->isBundle()) {
3633 const MachineInstr *NewUseMI = getBundledUseMI(&getRegisterInfo(), UseMI,
3634 Reg, NewUseIdx, UseAdj);
3640 UseMCID = &UseMI->getDesc();
3643 if (Reg == ARM::CPSR) {
3644 if (DefMI->getOpcode() == ARM::FMSTAT) {
3645 // fpscr -> cpsr stalls over 20 cycles on A8 (and earlier?)
3646 return Subtarget.isLikeA9() ? 1 : 20;
3649 // CPSR set and branch can be paired in the same cycle.
3650 if (UseMI->isBranch())
3653 // Otherwise it takes the instruction latency (generally one).
3654 unsigned Latency = getInstrLatency(ItinData, DefMI);
3656 // For Thumb2 and -Os, prefer scheduling CPSR setting instruction close to
3657 // its uses. Instructions which are otherwise scheduled between them may
3658 // incur a code size penalty (not able to use the CPSR setting 16-bit
3660 if (Latency > 0 && Subtarget.isThumb2()) {
3661 const MachineFunction *MF = DefMI->getParent()->getParent();
3662 if (MF->getFunction()->hasFnAttribute(Attribute::OptimizeForSize))
3668 if (DefMO.isImplicit() || UseMI->getOperand(UseIdx).isImplicit())
3671 unsigned DefAlign = DefMI->hasOneMemOperand()
3672 ? (*DefMI->memoperands_begin())->getAlignment() : 0;
3673 unsigned UseAlign = UseMI->hasOneMemOperand()
3674 ? (*UseMI->memoperands_begin())->getAlignment() : 0;
3676 // Get the itinerary's latency if possible, and handle variable_ops.
3677 int Latency = getOperandLatency(ItinData, *DefMCID, DefIdx, DefAlign,
3678 *UseMCID, UseIdx, UseAlign);
3679 // Unable to find operand latency. The caller may resort to getInstrLatency.
3683 // Adjust for IT block position.
3684 int Adj = DefAdj + UseAdj;
3686 // Adjust for dynamic def-side opcode variants not captured by the itinerary.
3687 Adj += adjustDefLatency(Subtarget, DefMI, DefMCID, DefAlign);
3688 if (Adj >= 0 || (int)Latency > -Adj) {
3689 return Latency + Adj;
3691 // Return the itinerary latency, which may be zero but not less than zero.
3696 ARMBaseInstrInfo::getOperandLatency(const InstrItineraryData *ItinData,
3697 SDNode *DefNode, unsigned DefIdx,
3698 SDNode *UseNode, unsigned UseIdx) const {
3699 if (!DefNode->isMachineOpcode())
3702 const MCInstrDesc &DefMCID = get(DefNode->getMachineOpcode());
3704 if (isZeroCost(DefMCID.Opcode))
3707 if (!ItinData || ItinData->isEmpty())
3708 return DefMCID.mayLoad() ? 3 : 1;
3710 if (!UseNode->isMachineOpcode()) {
3711 int Latency = ItinData->getOperandCycle(DefMCID.getSchedClass(), DefIdx);
3712 if (Subtarget.isLikeA9() || Subtarget.isSwift())
3713 return Latency <= 2 ? 1 : Latency - 1;
3715 return Latency <= 3 ? 1 : Latency - 2;
3718 const MCInstrDesc &UseMCID = get(UseNode->getMachineOpcode());
3719 const MachineSDNode *DefMN = dyn_cast<MachineSDNode>(DefNode);
3720 unsigned DefAlign = !DefMN->memoperands_empty()
3721 ? (*DefMN->memoperands_begin())->getAlignment() : 0;
3722 const MachineSDNode *UseMN = dyn_cast<MachineSDNode>(UseNode);
3723 unsigned UseAlign = !UseMN->memoperands_empty()
3724 ? (*UseMN->memoperands_begin())->getAlignment() : 0;
3725 int Latency = getOperandLatency(ItinData, DefMCID, DefIdx, DefAlign,
3726 UseMCID, UseIdx, UseAlign);
3729 (Subtarget.isCortexA8() || Subtarget.isLikeA9() ||
3730 Subtarget.isCortexA7())) {
3731 // FIXME: Shifter op hack: no shift (i.e. [r +/- r]) or [r + r << 2]
3732 // variants are one cycle cheaper.
3733 switch (DefMCID.getOpcode()) {
3738 cast<ConstantSDNode>(DefNode->getOperand(2))->getZExtValue();
3739 unsigned ShImm = ARM_AM::getAM2Offset(ShOpVal);
3741 (ShImm == 2 && ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl))
3748 case ARM::t2LDRSHs: {
3749 // Thumb2 mode: lsl only.
3751 cast<ConstantSDNode>(DefNode->getOperand(2))->getZExtValue();
3752 if (ShAmt == 0 || ShAmt == 2)
3757 } else if (DefIdx == 0 && Latency > 2 && Subtarget.isSwift()) {
3758 // FIXME: Properly handle all of the latency adjustments for address
3760 switch (DefMCID.getOpcode()) {
3765 cast<ConstantSDNode>(DefNode->getOperand(2))->getZExtValue();
3766 unsigned ShImm = ARM_AM::getAM2Offset(ShOpVal);
3768 ((ShImm == 1 || ShImm == 2 || ShImm == 3) &&
3769 ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl))
3771 else if (ShImm == 1 && ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsr)
3778 case ARM::t2LDRSHs: {
3779 // Thumb2 mode: lsl 0-3 only.
3786 if (DefAlign < 8 && Subtarget.isLikeA9())
3787 switch (DefMCID.getOpcode()) {
3793 case ARM::VLD1q8wb_register:
3794 case ARM::VLD1q16wb_register:
3795 case ARM::VLD1q32wb_register:
3796 case ARM::VLD1q64wb_register:
3797 case ARM::VLD1q8wb_fixed:
3798 case ARM::VLD1q16wb_fixed:
3799 case ARM::VLD1q32wb_fixed:
3800 case ARM::VLD1q64wb_fixed:
3804 case ARM::VLD2q8Pseudo:
3805 case ARM::VLD2q16Pseudo:
3806 case ARM::VLD2q32Pseudo:
3807 case ARM::VLD2d8wb_fixed:
3808 case ARM::VLD2d16wb_fixed:
3809 case ARM::VLD2d32wb_fixed:
3810 case ARM::VLD2q8PseudoWB_fixed:
3811 case ARM::VLD2q16PseudoWB_fixed:
3812 case ARM::VLD2q32PseudoWB_fixed:
3813 case ARM::VLD2d8wb_register:
3814 case ARM::VLD2d16wb_register:
3815 case ARM::VLD2d32wb_register:
3816 case ARM::VLD2q8PseudoWB_register:
3817 case ARM::VLD2q16PseudoWB_register:
3818 case ARM::VLD2q32PseudoWB_register:
3819 case ARM::VLD3d8Pseudo:
3820 case ARM::VLD3d16Pseudo:
3821 case ARM::VLD3d32Pseudo:
3822 case ARM::VLD1d64TPseudo:
3823 case ARM::VLD1d64TPseudoWB_fixed:
3824 case ARM::VLD3d8Pseudo_UPD:
3825 case ARM::VLD3d16Pseudo_UPD:
3826 case ARM::VLD3d32Pseudo_UPD:
3827 case ARM::VLD3q8Pseudo_UPD:
3828 case ARM::VLD3q16Pseudo_UPD:
3829 case ARM::VLD3q32Pseudo_UPD:
3830 case ARM::VLD3q8oddPseudo:
3831 case ARM::VLD3q16oddPseudo:
3832 case ARM::VLD3q32oddPseudo:
3833 case ARM::VLD3q8oddPseudo_UPD:
3834 case ARM::VLD3q16oddPseudo_UPD:
3835 case ARM::VLD3q32oddPseudo_UPD:
3836 case ARM::VLD4d8Pseudo:
3837 case ARM::VLD4d16Pseudo:
3838 case ARM::VLD4d32Pseudo:
3839 case ARM::VLD1d64QPseudo:
3840 case ARM::VLD1d64QPseudoWB_fixed:
3841 case ARM::VLD4d8Pseudo_UPD:
3842 case ARM::VLD4d16Pseudo_UPD:
3843 case ARM::VLD4d32Pseudo_UPD:
3844 case ARM::VLD4q8Pseudo_UPD:
3845 case ARM::VLD4q16Pseudo_UPD:
3846 case ARM::VLD4q32Pseudo_UPD:
3847 case ARM::VLD4q8oddPseudo:
3848 case ARM::VLD4q16oddPseudo:
3849 case ARM::VLD4q32oddPseudo:
3850 case ARM::VLD4q8oddPseudo_UPD:
3851 case ARM::VLD4q16oddPseudo_UPD:
3852 case ARM::VLD4q32oddPseudo_UPD:
3853 case ARM::VLD1DUPq8:
3854 case ARM::VLD1DUPq16:
3855 case ARM::VLD1DUPq32:
3856 case ARM::VLD1DUPq8wb_fixed:
3857 case ARM::VLD1DUPq16wb_fixed:
3858 case ARM::VLD1DUPq32wb_fixed:
3859 case ARM::VLD1DUPq8wb_register:
3860 case ARM::VLD1DUPq16wb_register:
3861 case ARM::VLD1DUPq32wb_register:
3862 case ARM::VLD2DUPd8:
3863 case ARM::VLD2DUPd16:
3864 case ARM::VLD2DUPd32:
3865 case ARM::VLD2DUPd8wb_fixed:
3866 case ARM::VLD2DUPd16wb_fixed:
3867 case ARM::VLD2DUPd32wb_fixed:
3868 case ARM::VLD2DUPd8wb_register:
3869 case ARM::VLD2DUPd16wb_register:
3870 case ARM::VLD2DUPd32wb_register:
3871 case ARM::VLD4DUPd8Pseudo:
3872 case ARM::VLD4DUPd16Pseudo:
3873 case ARM::VLD4DUPd32Pseudo:
3874 case ARM::VLD4DUPd8Pseudo_UPD:
3875 case ARM::VLD4DUPd16Pseudo_UPD:
3876 case ARM::VLD4DUPd32Pseudo_UPD:
3877 case ARM::VLD1LNq8Pseudo:
3878 case ARM::VLD1LNq16Pseudo:
3879 case ARM::VLD1LNq32Pseudo:
3880 case ARM::VLD1LNq8Pseudo_UPD:
3881 case ARM::VLD1LNq16Pseudo_UPD:
3882 case ARM::VLD1LNq32Pseudo_UPD:
3883 case ARM::VLD2LNd8Pseudo:
3884 case ARM::VLD2LNd16Pseudo:
3885 case ARM::VLD2LNd32Pseudo:
3886 case ARM::VLD2LNq16Pseudo:
3887 case ARM::VLD2LNq32Pseudo:
3888 case ARM::VLD2LNd8Pseudo_UPD:
3889 case ARM::VLD2LNd16Pseudo_UPD:
3890 case ARM::VLD2LNd32Pseudo_UPD:
3891 case ARM::VLD2LNq16Pseudo_UPD:
3892 case ARM::VLD2LNq32Pseudo_UPD:
3893 case ARM::VLD4LNd8Pseudo:
3894 case ARM::VLD4LNd16Pseudo:
3895 case ARM::VLD4LNd32Pseudo:
3896 case ARM::VLD4LNq16Pseudo:
3897 case ARM::VLD4LNq32Pseudo:
3898 case ARM::VLD4LNd8Pseudo_UPD:
3899 case ARM::VLD4LNd16Pseudo_UPD:
3900 case ARM::VLD4LNd32Pseudo_UPD:
3901 case ARM::VLD4LNq16Pseudo_UPD:
3902 case ARM::VLD4LNq32Pseudo_UPD:
3903 // If the address is not 64-bit aligned, the latencies of these
3904 // instructions increases by one.
3912 unsigned ARMBaseInstrInfo::getPredicationCost(const MachineInstr *MI) const {
3913 if (MI->isCopyLike() || MI->isInsertSubreg() ||
3914 MI->isRegSequence() || MI->isImplicitDef())
3920 const MCInstrDesc &MCID = MI->getDesc();
3922 if (MCID.isCall() || MCID.hasImplicitDefOfPhysReg(ARM::CPSR)) {
3923 // When predicated, CPSR is an additional source operand for CPSR updating
3924 // instructions, this apparently increases their latencies.
3930 unsigned ARMBaseInstrInfo::getInstrLatency(const InstrItineraryData *ItinData,
3931 const MachineInstr *MI,
3932 unsigned *PredCost) const {
3933 if (MI->isCopyLike() || MI->isInsertSubreg() ||
3934 MI->isRegSequence() || MI->isImplicitDef())
3937 // An instruction scheduler typically runs on unbundled instructions, however
3938 // other passes may query the latency of a bundled instruction.
3939 if (MI->isBundle()) {
3940 unsigned Latency = 0;
3941 MachineBasicBlock::const_instr_iterator I = MI;
3942 MachineBasicBlock::const_instr_iterator E = MI->getParent()->instr_end();
3943 while (++I != E && I->isInsideBundle()) {
3944 if (I->getOpcode() != ARM::t2IT)
3945 Latency += getInstrLatency(ItinData, I, PredCost);
3950 const MCInstrDesc &MCID = MI->getDesc();
3951 if (PredCost && (MCID.isCall() || MCID.hasImplicitDefOfPhysReg(ARM::CPSR))) {
3952 // When predicated, CPSR is an additional source operand for CPSR updating
3953 // instructions, this apparently increases their latencies.
3956 // Be sure to call getStageLatency for an empty itinerary in case it has a
3957 // valid MinLatency property.
3959 return MI->mayLoad() ? 3 : 1;
3961 unsigned Class = MCID.getSchedClass();
3963 // For instructions with variable uops, use uops as latency.
3964 if (!ItinData->isEmpty() && ItinData->getNumMicroOps(Class) < 0)
3965 return getNumMicroOps(ItinData, MI);
3967 // For the common case, fall back on the itinerary's latency.
3968 unsigned Latency = ItinData->getStageLatency(Class);
3970 // Adjust for dynamic def-side opcode variants not captured by the itinerary.
3971 unsigned DefAlign = MI->hasOneMemOperand()
3972 ? (*MI->memoperands_begin())->getAlignment() : 0;
3973 int Adj = adjustDefLatency(Subtarget, MI, &MCID, DefAlign);
3974 if (Adj >= 0 || (int)Latency > -Adj) {
3975 return Latency + Adj;
3980 int ARMBaseInstrInfo::getInstrLatency(const InstrItineraryData *ItinData,
3981 SDNode *Node) const {
3982 if (!Node->isMachineOpcode())
3985 if (!ItinData || ItinData->isEmpty())
3988 unsigned Opcode = Node->getMachineOpcode();
3991 return ItinData->getStageLatency(get(Opcode).getSchedClass());
3998 bool ARMBaseInstrInfo::
3999 hasHighOperandLatency(const InstrItineraryData *ItinData,
4000 const MachineRegisterInfo *MRI,
4001 const MachineInstr *DefMI, unsigned DefIdx,
4002 const MachineInstr *UseMI, unsigned UseIdx) const {
4003 unsigned DDomain = DefMI->getDesc().TSFlags & ARMII::DomainMask;
4004 unsigned UDomain = UseMI->getDesc().TSFlags & ARMII::DomainMask;
4005 if (Subtarget.isCortexA8() &&
4006 (DDomain == ARMII::DomainVFP || UDomain == ARMII::DomainVFP))
4007 // CortexA8 VFP instructions are not pipelined.
4010 // Hoist VFP / NEON instructions with 4 or higher latency.
4011 int Latency = computeOperandLatency(ItinData, DefMI, DefIdx, UseMI, UseIdx);
4013 Latency = getInstrLatency(ItinData, DefMI);
4016 return DDomain == ARMII::DomainVFP || DDomain == ARMII::DomainNEON ||
4017 UDomain == ARMII::DomainVFP || UDomain == ARMII::DomainNEON;
4020 bool ARMBaseInstrInfo::
4021 hasLowDefLatency(const InstrItineraryData *ItinData,
4022 const MachineInstr *DefMI, unsigned DefIdx) const {
4023 if (!ItinData || ItinData->isEmpty())
4026 unsigned DDomain = DefMI->getDesc().TSFlags & ARMII::DomainMask;
4027 if (DDomain == ARMII::DomainGeneral) {
4028 unsigned DefClass = DefMI->getDesc().getSchedClass();
4029 int DefCycle = ItinData->getOperandCycle(DefClass, DefIdx);
4030 return (DefCycle != -1 && DefCycle <= 2);
4035 bool ARMBaseInstrInfo::verifyInstruction(const MachineInstr *MI,
4036 StringRef &ErrInfo) const {
4037 if (convertAddSubFlagsOpcode(MI->getOpcode())) {
4038 ErrInfo = "Pseudo flag setting opcodes only exist in Selection DAG";
4044 // LoadStackGuard has so far only been implemented for MachO. Different code
4045 // sequence is needed for other targets.
4046 void ARMBaseInstrInfo::expandLoadStackGuardBase(MachineBasicBlock::iterator MI,
4047 unsigned LoadImmOpc,
4049 Reloc::Model RM) const {
4050 MachineBasicBlock &MBB = *MI->getParent();
4051 DebugLoc DL = MI->getDebugLoc();
4052 unsigned Reg = MI->getOperand(0).getReg();
4053 const GlobalValue *GV =
4054 cast<GlobalValue>((*MI->memoperands_begin())->getValue());
4055 MachineInstrBuilder MIB;
4057 BuildMI(MBB, MI, DL, get(LoadImmOpc), Reg)
4058 .addGlobalAddress(GV, 0, ARMII::MO_NONLAZY);
4060 if (Subtarget.GVIsIndirectSymbol(GV, RM)) {
4061 MIB = BuildMI(MBB, MI, DL, get(LoadOpc), Reg);
4062 MIB.addReg(Reg, RegState::Kill).addImm(0);
4063 unsigned Flag = MachineMemOperand::MOLoad | MachineMemOperand::MOInvariant;
4064 MachineMemOperand *MMO = MBB.getParent()->
4065 getMachineMemOperand(MachinePointerInfo::getGOT(), Flag, 4, 4);
4066 MIB.addMemOperand(MMO);
4067 AddDefaultPred(MIB);
4070 MIB = BuildMI(MBB, MI, DL, get(LoadOpc), Reg);
4071 MIB.addReg(Reg, RegState::Kill).addImm(0);
4072 MIB.setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
4073 AddDefaultPred(MIB);
4077 ARMBaseInstrInfo::isFpMLxInstruction(unsigned Opcode, unsigned &MulOpc,
4078 unsigned &AddSubOpc,
4079 bool &NegAcc, bool &HasLane) const {
4080 DenseMap<unsigned, unsigned>::const_iterator I = MLxEntryMap.find(Opcode);
4081 if (I == MLxEntryMap.end())
4084 const ARM_MLxEntry &Entry = ARM_MLxTable[I->second];
4085 MulOpc = Entry.MulOpc;
4086 AddSubOpc = Entry.AddSubOpc;
4087 NegAcc = Entry.NegAcc;
4088 HasLane = Entry.HasLane;
4092 //===----------------------------------------------------------------------===//
4093 // Execution domains.
4094 //===----------------------------------------------------------------------===//
4096 // Some instructions go down the NEON pipeline, some go down the VFP pipeline,
4097 // and some can go down both. The vmov instructions go down the VFP pipeline,
4098 // but they can be changed to vorr equivalents that are executed by the NEON
4101 // We use the following execution domain numbering:
4109 // Also see ARMInstrFormats.td and Domain* enums in ARMBaseInfo.h
4111 std::pair<uint16_t, uint16_t>
4112 ARMBaseInstrInfo::getExecutionDomain(const MachineInstr *MI) const {
4113 // If we don't have access to NEON instructions then we won't be able
4114 // to swizzle anything to the NEON domain. Check to make sure.
4115 if (Subtarget.hasNEON()) {
4116 // VMOVD, VMOVRS and VMOVSR are VFP instructions, but can be changed to NEON
4117 // if they are not predicated.
4118 if (MI->getOpcode() == ARM::VMOVD && !isPredicated(MI))
4119 return std::make_pair(ExeVFP, (1 << ExeVFP) | (1 << ExeNEON));
4121 // CortexA9 is particularly picky about mixing the two and wants these
4123 if (Subtarget.isCortexA9() && !isPredicated(MI) &&
4124 (MI->getOpcode() == ARM::VMOVRS || MI->getOpcode() == ARM::VMOVSR ||
4125 MI->getOpcode() == ARM::VMOVS))
4126 return std::make_pair(ExeVFP, (1 << ExeVFP) | (1 << ExeNEON));
4128 // No other instructions can be swizzled, so just determine their domain.
4129 unsigned Domain = MI->getDesc().TSFlags & ARMII::DomainMask;
4131 if (Domain & ARMII::DomainNEON)
4132 return std::make_pair(ExeNEON, 0);
4134 // Certain instructions can go either way on Cortex-A8.
4135 // Treat them as NEON instructions.
4136 if ((Domain & ARMII::DomainNEONA8) && Subtarget.isCortexA8())
4137 return std::make_pair(ExeNEON, 0);
4139 if (Domain & ARMII::DomainVFP)
4140 return std::make_pair(ExeVFP, 0);
4142 return std::make_pair(ExeGeneric, 0);
4145 static unsigned getCorrespondingDRegAndLane(const TargetRegisterInfo *TRI,
4146 unsigned SReg, unsigned &Lane) {
4147 unsigned DReg = TRI->getMatchingSuperReg(SReg, ARM::ssub_0, &ARM::DPRRegClass);
4150 if (DReg != ARM::NoRegister)
4154 DReg = TRI->getMatchingSuperReg(SReg, ARM::ssub_1, &ARM::DPRRegClass);
4156 assert(DReg && "S-register with no D super-register?");
4160 /// getImplicitSPRUseForDPRUse - Given a use of a DPR register and lane,
4161 /// set ImplicitSReg to a register number that must be marked as implicit-use or
4162 /// zero if no register needs to be defined as implicit-use.
4164 /// If the function cannot determine if an SPR should be marked implicit use or
4165 /// not, it returns false.
4167 /// This function handles cases where an instruction is being modified from taking
4168 /// an SPR to a DPR[Lane]. A use of the DPR is being added, which may conflict
4169 /// with an earlier def of an SPR corresponding to DPR[Lane^1] (i.e. the other
4170 /// lane of the DPR).
4172 /// If the other SPR is defined, an implicit-use of it should be added. Else,
4173 /// (including the case where the DPR itself is defined), it should not.
4175 static bool getImplicitSPRUseForDPRUse(const TargetRegisterInfo *TRI,
4177 unsigned DReg, unsigned Lane,
4178 unsigned &ImplicitSReg) {
4179 // If the DPR is defined or used already, the other SPR lane will be chained
4180 // correctly, so there is nothing to be done.
4181 if (MI->definesRegister(DReg, TRI) || MI->readsRegister(DReg, TRI)) {
4186 // Otherwise we need to go searching to see if the SPR is set explicitly.
4187 ImplicitSReg = TRI->getSubReg(DReg,
4188 (Lane & 1) ? ARM::ssub_0 : ARM::ssub_1);
4189 MachineBasicBlock::LivenessQueryResult LQR =
4190 MI->getParent()->computeRegisterLiveness(TRI, ImplicitSReg, MI);
4192 if (LQR == MachineBasicBlock::LQR_Live)
4194 else if (LQR == MachineBasicBlock::LQR_Unknown)
4197 // If the register is known not to be live, there is no need to add an
4204 ARMBaseInstrInfo::setExecutionDomain(MachineInstr *MI, unsigned Domain) const {
4205 unsigned DstReg, SrcReg, DReg;
4207 MachineInstrBuilder MIB(*MI->getParent()->getParent(), MI);
4208 const TargetRegisterInfo *TRI = &getRegisterInfo();
4209 switch (MI->getOpcode()) {
4211 llvm_unreachable("cannot handle opcode!");
4214 if (Domain != ExeNEON)
4217 // Zap the predicate operands.
4218 assert(!isPredicated(MI) && "Cannot predicate a VORRd");
4220 // Make sure we've got NEON instructions.
4221 assert(Subtarget.hasNEON() && "VORRd requires NEON");
4223 // Source instruction is %DDst = VMOVD %DSrc, 14, %noreg (; implicits)
4224 DstReg = MI->getOperand(0).getReg();
4225 SrcReg = MI->getOperand(1).getReg();
4227 for (unsigned i = MI->getDesc().getNumOperands(); i; --i)
4228 MI->RemoveOperand(i-1);
4230 // Change to a %DDst = VORRd %DSrc, %DSrc, 14, %noreg (; implicits)
4231 MI->setDesc(get(ARM::VORRd));
4232 AddDefaultPred(MIB.addReg(DstReg, RegState::Define)
4237 if (Domain != ExeNEON)
4239 assert(!isPredicated(MI) && "Cannot predicate a VGETLN");
4241 // Source instruction is %RDst = VMOVRS %SSrc, 14, %noreg (; implicits)
4242 DstReg = MI->getOperand(0).getReg();
4243 SrcReg = MI->getOperand(1).getReg();
4245 for (unsigned i = MI->getDesc().getNumOperands(); i; --i)
4246 MI->RemoveOperand(i-1);
4248 DReg = getCorrespondingDRegAndLane(TRI, SrcReg, Lane);
4250 // Convert to %RDst = VGETLNi32 %DSrc, Lane, 14, %noreg (; imps)
4251 // Note that DSrc has been widened and the other lane may be undef, which
4252 // contaminates the entire register.
4253 MI->setDesc(get(ARM::VGETLNi32));
4254 AddDefaultPred(MIB.addReg(DstReg, RegState::Define)
4255 .addReg(DReg, RegState::Undef)
4258 // The old source should be an implicit use, otherwise we might think it
4259 // was dead before here.
4260 MIB.addReg(SrcReg, RegState::Implicit);
4263 if (Domain != ExeNEON)
4265 assert(!isPredicated(MI) && "Cannot predicate a VSETLN");
4267 // Source instruction is %SDst = VMOVSR %RSrc, 14, %noreg (; implicits)
4268 DstReg = MI->getOperand(0).getReg();
4269 SrcReg = MI->getOperand(1).getReg();
4271 DReg = getCorrespondingDRegAndLane(TRI, DstReg, Lane);
4273 unsigned ImplicitSReg;
4274 if (!getImplicitSPRUseForDPRUse(TRI, MI, DReg, Lane, ImplicitSReg))
4277 for (unsigned i = MI->getDesc().getNumOperands(); i; --i)
4278 MI->RemoveOperand(i-1);
4280 // Convert to %DDst = VSETLNi32 %DDst, %RSrc, Lane, 14, %noreg (; imps)
4281 // Again DDst may be undefined at the beginning of this instruction.
4282 MI->setDesc(get(ARM::VSETLNi32));
4283 MIB.addReg(DReg, RegState::Define)
4284 .addReg(DReg, getUndefRegState(!MI->readsRegister(DReg, TRI)))
4287 AddDefaultPred(MIB);
4289 // The narrower destination must be marked as set to keep previous chains
4291 MIB.addReg(DstReg, RegState::Define | RegState::Implicit);
4292 if (ImplicitSReg != 0)
4293 MIB.addReg(ImplicitSReg, RegState::Implicit);
4297 if (Domain != ExeNEON)
4300 // Source instruction is %SDst = VMOVS %SSrc, 14, %noreg (; implicits)
4301 DstReg = MI->getOperand(0).getReg();
4302 SrcReg = MI->getOperand(1).getReg();
4304 unsigned DstLane = 0, SrcLane = 0, DDst, DSrc;
4305 DDst = getCorrespondingDRegAndLane(TRI, DstReg, DstLane);
4306 DSrc = getCorrespondingDRegAndLane(TRI, SrcReg, SrcLane);
4308 unsigned ImplicitSReg;
4309 if (!getImplicitSPRUseForDPRUse(TRI, MI, DSrc, SrcLane, ImplicitSReg))
4312 for (unsigned i = MI->getDesc().getNumOperands(); i; --i)
4313 MI->RemoveOperand(i-1);
4316 // Destination can be:
4317 // %DDst = VDUPLN32d %DDst, Lane, 14, %noreg (; implicits)
4318 MI->setDesc(get(ARM::VDUPLN32d));
4319 MIB.addReg(DDst, RegState::Define)
4320 .addReg(DDst, getUndefRegState(!MI->readsRegister(DDst, TRI)))
4322 AddDefaultPred(MIB);
4324 // Neither the source or the destination are naturally represented any
4325 // more, so add them in manually.
4326 MIB.addReg(DstReg, RegState::Implicit | RegState::Define);
4327 MIB.addReg(SrcReg, RegState::Implicit);
4328 if (ImplicitSReg != 0)
4329 MIB.addReg(ImplicitSReg, RegState::Implicit);
4333 // In general there's no single instruction that can perform an S <-> S
4334 // move in NEON space, but a pair of VEXT instructions *can* do the
4335 // job. It turns out that the VEXTs needed will only use DSrc once, with
4336 // the position based purely on the combination of lane-0 and lane-1
4337 // involved. For example
4338 // vmov s0, s2 -> vext.32 d0, d0, d1, #1 vext.32 d0, d0, d0, #1
4339 // vmov s1, s3 -> vext.32 d0, d1, d0, #1 vext.32 d0, d0, d0, #1
4340 // vmov s0, s3 -> vext.32 d0, d0, d0, #1 vext.32 d0, d1, d0, #1
4341 // vmov s1, s2 -> vext.32 d0, d0, d0, #1 vext.32 d0, d0, d1, #1
4343 // Pattern of the MachineInstrs is:
4344 // %DDst = VEXTd32 %DSrc1, %DSrc2, Lane, 14, %noreg (;implicits)
4345 MachineInstrBuilder NewMIB;
4346 NewMIB = BuildMI(*MI->getParent(), MI, MI->getDebugLoc(),
4347 get(ARM::VEXTd32), DDst);
4349 // On the first instruction, both DSrc and DDst may be <undef> if present.
4350 // Specifically when the original instruction didn't have them as an
4352 unsigned CurReg = SrcLane == 1 && DstLane == 1 ? DSrc : DDst;
4353 bool CurUndef = !MI->readsRegister(CurReg, TRI);
4354 NewMIB.addReg(CurReg, getUndefRegState(CurUndef));
4356 CurReg = SrcLane == 0 && DstLane == 0 ? DSrc : DDst;
4357 CurUndef = !MI->readsRegister(CurReg, TRI);
4358 NewMIB.addReg(CurReg, getUndefRegState(CurUndef));
4361 AddDefaultPred(NewMIB);
4363 if (SrcLane == DstLane)
4364 NewMIB.addReg(SrcReg, RegState::Implicit);
4366 MI->setDesc(get(ARM::VEXTd32));
4367 MIB.addReg(DDst, RegState::Define);
4369 // On the second instruction, DDst has definitely been defined above, so
4370 // it is not <undef>. DSrc, if present, can be <undef> as above.
4371 CurReg = SrcLane == 1 && DstLane == 0 ? DSrc : DDst;
4372 CurUndef = CurReg == DSrc && !MI->readsRegister(CurReg, TRI);
4373 MIB.addReg(CurReg, getUndefRegState(CurUndef));
4375 CurReg = SrcLane == 0 && DstLane == 1 ? DSrc : DDst;
4376 CurUndef = CurReg == DSrc && !MI->readsRegister(CurReg, TRI);
4377 MIB.addReg(CurReg, getUndefRegState(CurUndef));
4380 AddDefaultPred(MIB);
4382 if (SrcLane != DstLane)
4383 MIB.addReg(SrcReg, RegState::Implicit);
4385 // As before, the original destination is no longer represented, add it
4387 MIB.addReg(DstReg, RegState::Define | RegState::Implicit);
4388 if (ImplicitSReg != 0)
4389 MIB.addReg(ImplicitSReg, RegState::Implicit);
4396 //===----------------------------------------------------------------------===//
4397 // Partial register updates
4398 //===----------------------------------------------------------------------===//
4400 // Swift renames NEON registers with 64-bit granularity. That means any
4401 // instruction writing an S-reg implicitly reads the containing D-reg. The
4402 // problem is mostly avoided by translating f32 operations to v2f32 operations
4403 // on D-registers, but f32 loads are still a problem.
4405 // These instructions can load an f32 into a NEON register:
4407 // VLDRS - Only writes S, partial D update.
4408 // VLD1LNd32 - Writes all D-regs, explicit partial D update, 2 uops.
4409 // VLD1DUPd32 - Writes all D-regs, no partial reg update, 2 uops.
4411 // FCONSTD can be used as a dependency-breaking instruction.
4412 unsigned ARMBaseInstrInfo::
4413 getPartialRegUpdateClearance(const MachineInstr *MI,
4415 const TargetRegisterInfo *TRI) const {
4416 if (!SwiftPartialUpdateClearance ||
4417 !(Subtarget.isSwift() || Subtarget.isCortexA15()))
4420 assert(TRI && "Need TRI instance");
4422 const MachineOperand &MO = MI->getOperand(OpNum);
4425 unsigned Reg = MO.getReg();
4428 switch(MI->getOpcode()) {
4429 // Normal instructions writing only an S-register.
4434 case ARM::VMOVv4i16:
4435 case ARM::VMOVv2i32:
4436 case ARM::VMOVv2f32:
4437 case ARM::VMOVv1i64:
4438 UseOp = MI->findRegisterUseOperandIdx(Reg, false, TRI);
4441 // Explicitly reads the dependency.
4442 case ARM::VLD1LNd32:
4449 // If this instruction actually reads a value from Reg, there is no unwanted
4451 if (UseOp != -1 && MI->getOperand(UseOp).readsReg())
4454 // We must be able to clobber the whole D-reg.
4455 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
4456 // Virtual register must be a foo:ssub_0<def,undef> operand.
4457 if (!MO.getSubReg() || MI->readsVirtualRegister(Reg))
4459 } else if (ARM::SPRRegClass.contains(Reg)) {
4460 // Physical register: MI must define the full D-reg.
4461 unsigned DReg = TRI->getMatchingSuperReg(Reg, ARM::ssub_0,
4463 if (!DReg || !MI->definesRegister(DReg, TRI))
4467 // MI has an unwanted D-register dependency.
4468 // Avoid defs in the previous N instructrions.
4469 return SwiftPartialUpdateClearance;
4472 // Break a partial register dependency after getPartialRegUpdateClearance
4473 // returned non-zero.
4474 void ARMBaseInstrInfo::
4475 breakPartialRegDependency(MachineBasicBlock::iterator MI,
4477 const TargetRegisterInfo *TRI) const {
4478 assert(MI && OpNum < MI->getDesc().getNumDefs() && "OpNum is not a def");
4479 assert(TRI && "Need TRI instance");
4481 const MachineOperand &MO = MI->getOperand(OpNum);
4482 unsigned Reg = MO.getReg();
4483 assert(TargetRegisterInfo::isPhysicalRegister(Reg) &&
4484 "Can't break virtual register dependencies.");
4485 unsigned DReg = Reg;
4487 // If MI defines an S-reg, find the corresponding D super-register.
4488 if (ARM::SPRRegClass.contains(Reg)) {
4489 DReg = ARM::D0 + (Reg - ARM::S0) / 2;
4490 assert(TRI->isSuperRegister(Reg, DReg) && "Register enums broken");
4493 assert(ARM::DPRRegClass.contains(DReg) && "Can only break D-reg deps");
4494 assert(MI->definesRegister(DReg, TRI) && "MI doesn't clobber full D-reg");
4496 // FIXME: In some cases, VLDRS can be changed to a VLD1DUPd32 which defines
4497 // the full D-register by loading the same value to both lanes. The
4498 // instruction is micro-coded with 2 uops, so don't do this until we can
4499 // properly schedule micro-coded instructions. The dispatcher stalls cause
4500 // too big regressions.
4502 // Insert the dependency-breaking FCONSTD before MI.
4503 // 96 is the encoding of 0.5, but the actual value doesn't matter here.
4504 AddDefaultPred(BuildMI(*MI->getParent(), MI, MI->getDebugLoc(),
4505 get(ARM::FCONSTD), DReg).addImm(96));
4506 MI->addRegisterKilled(DReg, TRI, true);
4509 bool ARMBaseInstrInfo::hasNOP() const {
4510 return (Subtarget.getFeatureBits() & ARM::HasV6KOps) != 0;
4513 bool ARMBaseInstrInfo::isSwiftFastImmShift(const MachineInstr *MI) const {
4514 if (MI->getNumOperands() < 4)
4516 unsigned ShOpVal = MI->getOperand(3).getImm();
4517 unsigned ShImm = ARM_AM::getSORegOffset(ShOpVal);
4518 // Swift supports faster shifts for: lsl 2, lsl 1, and lsr 1.
4519 if ((ShImm == 1 && ARM_AM::getSORegShOp(ShOpVal) == ARM_AM::lsr) ||
4520 ((ShImm == 1 || ShImm == 2) &&
4521 ARM_AM::getSORegShOp(ShOpVal) == ARM_AM::lsl))
4527 bool ARMBaseInstrInfo::getRegSequenceLikeInputs(
4528 const MachineInstr &MI, unsigned DefIdx,
4529 SmallVectorImpl<RegSubRegPairAndIdx> &InputRegs) const {
4530 assert(DefIdx < MI.getDesc().getNumDefs() && "Invalid definition index");
4531 assert(MI.isRegSequenceLike() && "Invalid kind of instruction");
4533 switch (MI.getOpcode()) {
4535 // dX = VMOVDRR rY, rZ
4537 // dX = REG_SEQUENCE rY, ssub_0, rZ, ssub_1
4538 // Populate the InputRegs accordingly.
4540 const MachineOperand *MOReg = &MI.getOperand(1);
4541 InputRegs.push_back(
4542 RegSubRegPairAndIdx(MOReg->getReg(), MOReg->getSubReg(), ARM::ssub_0));
4544 MOReg = &MI.getOperand(2);
4545 InputRegs.push_back(
4546 RegSubRegPairAndIdx(MOReg->getReg(), MOReg->getSubReg(), ARM::ssub_1));
4549 llvm_unreachable("Target dependent opcode missing");
4552 bool ARMBaseInstrInfo::getExtractSubregLikeInputs(
4553 const MachineInstr &MI, unsigned DefIdx,
4554 RegSubRegPairAndIdx &InputReg) const {
4555 assert(DefIdx < MI.getDesc().getNumDefs() && "Invalid definition index");
4556 assert(MI.isExtractSubregLike() && "Invalid kind of instruction");
4558 switch (MI.getOpcode()) {
4560 // rX, rY = VMOVRRD dZ
4562 // rX = EXTRACT_SUBREG dZ, ssub_0
4563 // rY = EXTRACT_SUBREG dZ, ssub_1
4564 const MachineOperand &MOReg = MI.getOperand(2);
4565 InputReg.Reg = MOReg.getReg();
4566 InputReg.SubReg = MOReg.getSubReg();
4567 InputReg.SubIdx = DefIdx == 0 ? ARM::ssub_0 : ARM::ssub_1;
4570 llvm_unreachable("Target dependent opcode missing");
4573 bool ARMBaseInstrInfo::getInsertSubregLikeInputs(
4574 const MachineInstr &MI, unsigned DefIdx, RegSubRegPair &BaseReg,
4575 RegSubRegPairAndIdx &InsertedReg) const {
4576 assert(DefIdx < MI.getDesc().getNumDefs() && "Invalid definition index");
4577 assert(MI.isInsertSubregLike() && "Invalid kind of instruction");
4579 switch (MI.getOpcode()) {
4580 case ARM::VSETLNi32:
4581 // dX = VSETLNi32 dY, rZ, imm
4582 const MachineOperand &MOBaseReg = MI.getOperand(1);
4583 const MachineOperand &MOInsertedReg = MI.getOperand(2);
4584 const MachineOperand &MOIndex = MI.getOperand(3);
4585 BaseReg.Reg = MOBaseReg.getReg();
4586 BaseReg.SubReg = MOBaseReg.getSubReg();
4588 InsertedReg.Reg = MOInsertedReg.getReg();
4589 InsertedReg.SubReg = MOInsertedReg.getSubReg();
4590 InsertedReg.SubIdx = MOIndex.getImm() == 0 ? ARM::ssub_0 : ARM::ssub_1;
4593 llvm_unreachable("Target dependent opcode missing");