1 //===- ARMBaseInstrInfo.cpp - ARM Instruction Information -----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Base ARM implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "ARMBaseInstrInfo.h"
16 #include "ARMAddressingModes.h"
17 #include "ARMGenInstrInfo.inc"
18 #include "ARMMachineFunctionInfo.h"
19 #include "ARMRegisterInfo.h"
20 #include "llvm/ADT/STLExtras.h"
21 #include "llvm/CodeGen/LiveVariables.h"
22 #include "llvm/CodeGen/MachineFrameInfo.h"
23 #include "llvm/CodeGen/MachineInstrBuilder.h"
24 #include "llvm/CodeGen/MachineJumpTableInfo.h"
25 #include "llvm/CodeGen/MachineMemOperand.h"
26 #include "llvm/CodeGen/MachineRegisterInfo.h"
27 #include "llvm/CodeGen/PseudoSourceValue.h"
28 #include "llvm/MC/MCAsmInfo.h"
29 #include "llvm/Support/CommandLine.h"
30 #include "llvm/Support/Debug.h"
31 #include "llvm/Support/ErrorHandling.h"
35 EnableARM3Addr("enable-arm-3-addr-conv", cl::Hidden,
36 cl::desc("Enable ARM 2-addr to 3-addr conv"));
38 ARMBaseInstrInfo::ARMBaseInstrInfo(const ARMSubtarget& STI)
39 : TargetInstrInfoImpl(ARMInsts, array_lengthof(ARMInsts)),
44 ARMBaseInstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
45 MachineBasicBlock::iterator &MBBI,
46 LiveVariables *LV) const {
47 // FIXME: Thumb2 support.
52 MachineInstr *MI = MBBI;
53 MachineFunction &MF = *MI->getParent()->getParent();
54 unsigned TSFlags = MI->getDesc().TSFlags;
56 switch ((TSFlags & ARMII::IndexModeMask) >> ARMII::IndexModeShift) {
58 case ARMII::IndexModePre:
61 case ARMII::IndexModePost:
65 // Try splitting an indexed load/store to an un-indexed one plus an add/sub
67 unsigned MemOpc = getUnindexedOpcode(MI->getOpcode());
71 MachineInstr *UpdateMI = NULL;
72 MachineInstr *MemMI = NULL;
73 unsigned AddrMode = (TSFlags & ARMII::AddrModeMask);
74 const TargetInstrDesc &TID = MI->getDesc();
75 unsigned NumOps = TID.getNumOperands();
76 bool isLoad = !TID.mayStore();
77 const MachineOperand &WB = isLoad ? MI->getOperand(1) : MI->getOperand(0);
78 const MachineOperand &Base = MI->getOperand(2);
79 const MachineOperand &Offset = MI->getOperand(NumOps-3);
80 unsigned WBReg = WB.getReg();
81 unsigned BaseReg = Base.getReg();
82 unsigned OffReg = Offset.getReg();
83 unsigned OffImm = MI->getOperand(NumOps-2).getImm();
84 ARMCC::CondCodes Pred = (ARMCC::CondCodes)MI->getOperand(NumOps-1).getImm();
87 assert(false && "Unknown indexed op!");
89 case ARMII::AddrMode2: {
90 bool isSub = ARM_AM::getAM2Op(OffImm) == ARM_AM::sub;
91 unsigned Amt = ARM_AM::getAM2Offset(OffImm);
93 if (ARM_AM::getSOImmVal(Amt) == -1)
94 // Can't encode it in a so_imm operand. This transformation will
95 // add more than 1 instruction. Abandon!
97 UpdateMI = BuildMI(MF, MI->getDebugLoc(),
98 get(isSub ? ARM::SUBri : ARM::ADDri), WBReg)
99 .addReg(BaseReg).addImm(Amt)
100 .addImm(Pred).addReg(0).addReg(0);
101 } else if (Amt != 0) {
102 ARM_AM::ShiftOpc ShOpc = ARM_AM::getAM2ShiftOpc(OffImm);
103 unsigned SOOpc = ARM_AM::getSORegOpc(ShOpc, Amt);
104 UpdateMI = BuildMI(MF, MI->getDebugLoc(),
105 get(isSub ? ARM::SUBrs : ARM::ADDrs), WBReg)
106 .addReg(BaseReg).addReg(OffReg).addReg(0).addImm(SOOpc)
107 .addImm(Pred).addReg(0).addReg(0);
109 UpdateMI = BuildMI(MF, MI->getDebugLoc(),
110 get(isSub ? ARM::SUBrr : ARM::ADDrr), WBReg)
111 .addReg(BaseReg).addReg(OffReg)
112 .addImm(Pred).addReg(0).addReg(0);
115 case ARMII::AddrMode3 : {
116 bool isSub = ARM_AM::getAM3Op(OffImm) == ARM_AM::sub;
117 unsigned Amt = ARM_AM::getAM3Offset(OffImm);
119 // Immediate is 8-bits. It's guaranteed to fit in a so_imm operand.
120 UpdateMI = BuildMI(MF, MI->getDebugLoc(),
121 get(isSub ? ARM::SUBri : ARM::ADDri), WBReg)
122 .addReg(BaseReg).addImm(Amt)
123 .addImm(Pred).addReg(0).addReg(0);
125 UpdateMI = BuildMI(MF, MI->getDebugLoc(),
126 get(isSub ? ARM::SUBrr : ARM::ADDrr), WBReg)
127 .addReg(BaseReg).addReg(OffReg)
128 .addImm(Pred).addReg(0).addReg(0);
133 std::vector<MachineInstr*> NewMIs;
136 MemMI = BuildMI(MF, MI->getDebugLoc(),
137 get(MemOpc), MI->getOperand(0).getReg())
138 .addReg(WBReg).addReg(0).addImm(0).addImm(Pred);
140 MemMI = BuildMI(MF, MI->getDebugLoc(),
141 get(MemOpc)).addReg(MI->getOperand(1).getReg())
142 .addReg(WBReg).addReg(0).addImm(0).addImm(Pred);
143 NewMIs.push_back(MemMI);
144 NewMIs.push_back(UpdateMI);
147 MemMI = BuildMI(MF, MI->getDebugLoc(),
148 get(MemOpc), MI->getOperand(0).getReg())
149 .addReg(BaseReg).addReg(0).addImm(0).addImm(Pred);
151 MemMI = BuildMI(MF, MI->getDebugLoc(),
152 get(MemOpc)).addReg(MI->getOperand(1).getReg())
153 .addReg(BaseReg).addReg(0).addImm(0).addImm(Pred);
155 UpdateMI->getOperand(0).setIsDead();
156 NewMIs.push_back(UpdateMI);
157 NewMIs.push_back(MemMI);
160 // Transfer LiveVariables states, kill / dead info.
162 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
163 MachineOperand &MO = MI->getOperand(i);
164 if (MO.isReg() && MO.getReg() &&
165 TargetRegisterInfo::isVirtualRegister(MO.getReg())) {
166 unsigned Reg = MO.getReg();
168 LiveVariables::VarInfo &VI = LV->getVarInfo(Reg);
170 MachineInstr *NewMI = (Reg == WBReg) ? UpdateMI : MemMI;
172 LV->addVirtualRegisterDead(Reg, NewMI);
174 if (MO.isUse() && MO.isKill()) {
175 for (unsigned j = 0; j < 2; ++j) {
176 // Look at the two new MI's in reverse order.
177 MachineInstr *NewMI = NewMIs[j];
178 if (!NewMI->readsRegister(Reg))
180 LV->addVirtualRegisterKilled(Reg, NewMI);
181 if (VI.removeKill(MI))
182 VI.Kills.push_back(NewMI);
190 MFI->insert(MBBI, NewMIs[1]);
191 MFI->insert(MBBI, NewMIs[0]);
197 ARMBaseInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB,
198 MachineBasicBlock *&FBB,
199 SmallVectorImpl<MachineOperand> &Cond,
200 bool AllowModify) const {
201 // If the block has no terminators, it just falls into the block after it.
202 MachineBasicBlock::iterator I = MBB.end();
203 if (I == MBB.begin() || !isUnpredicatedTerminator(--I))
206 // Get the last instruction in the block.
207 MachineInstr *LastInst = I;
209 // If there is only one terminator instruction, process it.
210 unsigned LastOpc = LastInst->getOpcode();
211 if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) {
212 if (isUncondBranchOpcode(LastOpc)) {
213 TBB = LastInst->getOperand(0).getMBB();
216 if (isCondBranchOpcode(LastOpc)) {
217 // Block ends with fall-through condbranch.
218 TBB = LastInst->getOperand(0).getMBB();
219 Cond.push_back(LastInst->getOperand(1));
220 Cond.push_back(LastInst->getOperand(2));
223 return true; // Can't handle indirect branch.
226 // Get the instruction before it if it is a terminator.
227 MachineInstr *SecondLastInst = I;
229 // If there are three terminators, we don't know what sort of block this is.
230 if (SecondLastInst && I != MBB.begin() && isUnpredicatedTerminator(--I))
233 // If the block ends with a B and a Bcc, handle it.
234 unsigned SecondLastOpc = SecondLastInst->getOpcode();
235 if (isCondBranchOpcode(SecondLastOpc) && isUncondBranchOpcode(LastOpc)) {
236 TBB = SecondLastInst->getOperand(0).getMBB();
237 Cond.push_back(SecondLastInst->getOperand(1));
238 Cond.push_back(SecondLastInst->getOperand(2));
239 FBB = LastInst->getOperand(0).getMBB();
243 // If the block ends with two unconditional branches, handle it. The second
244 // one is not executed, so remove it.
245 if (isUncondBranchOpcode(SecondLastOpc) && isUncondBranchOpcode(LastOpc)) {
246 TBB = SecondLastInst->getOperand(0).getMBB();
249 I->eraseFromParent();
253 // ...likewise if it ends with a branch table followed by an unconditional
254 // branch. The branch folder can create these, and we must get rid of them for
255 // correctness of Thumb constant islands.
256 if ((isJumpTableBranchOpcode(SecondLastOpc) ||
257 isIndirectBranchOpcode(SecondLastOpc)) &&
258 isUncondBranchOpcode(LastOpc)) {
261 I->eraseFromParent();
265 // Otherwise, can't handle this.
270 unsigned ARMBaseInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
271 MachineBasicBlock::iterator I = MBB.end();
272 if (I == MBB.begin()) return 0;
274 if (!isUncondBranchOpcode(I->getOpcode()) &&
275 !isCondBranchOpcode(I->getOpcode()))
278 // Remove the branch.
279 I->eraseFromParent();
283 if (I == MBB.begin()) return 1;
285 if (!isCondBranchOpcode(I->getOpcode()))
288 // Remove the branch.
289 I->eraseFromParent();
294 ARMBaseInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
295 MachineBasicBlock *FBB,
296 const SmallVectorImpl<MachineOperand> &Cond) const {
297 // FIXME this should probably have a DebugLoc argument
298 DebugLoc dl = DebugLoc::getUnknownLoc();
300 ARMFunctionInfo *AFI = MBB.getParent()->getInfo<ARMFunctionInfo>();
301 int BOpc = !AFI->isThumbFunction()
302 ? ARM::B : (AFI->isThumb2Function() ? ARM::t2B : ARM::tB);
303 int BccOpc = !AFI->isThumbFunction()
304 ? ARM::Bcc : (AFI->isThumb2Function() ? ARM::t2Bcc : ARM::tBcc);
306 // Shouldn't be a fall through.
307 assert(TBB && "InsertBranch must not be told to insert a fallthrough");
308 assert((Cond.size() == 2 || Cond.size() == 0) &&
309 "ARM branch conditions have two components!");
312 if (Cond.empty()) // Unconditional branch?
313 BuildMI(&MBB, dl, get(BOpc)).addMBB(TBB);
315 BuildMI(&MBB, dl, get(BccOpc)).addMBB(TBB)
316 .addImm(Cond[0].getImm()).addReg(Cond[1].getReg());
320 // Two-way conditional branch.
321 BuildMI(&MBB, dl, get(BccOpc)).addMBB(TBB)
322 .addImm(Cond[0].getImm()).addReg(Cond[1].getReg());
323 BuildMI(&MBB, dl, get(BOpc)).addMBB(FBB);
327 bool ARMBaseInstrInfo::
328 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
329 ARMCC::CondCodes CC = (ARMCC::CondCodes)(int)Cond[0].getImm();
330 Cond[0].setImm(ARMCC::getOppositeCondition(CC));
334 bool ARMBaseInstrInfo::
335 PredicateInstruction(MachineInstr *MI,
336 const SmallVectorImpl<MachineOperand> &Pred) const {
337 unsigned Opc = MI->getOpcode();
338 if (isUncondBranchOpcode(Opc)) {
339 MI->setDesc(get(getMatchingCondBranchOpcode(Opc)));
340 MI->addOperand(MachineOperand::CreateImm(Pred[0].getImm()));
341 MI->addOperand(MachineOperand::CreateReg(Pred[1].getReg(), false));
345 int PIdx = MI->findFirstPredOperandIdx();
347 MachineOperand &PMO = MI->getOperand(PIdx);
348 PMO.setImm(Pred[0].getImm());
349 MI->getOperand(PIdx+1).setReg(Pred[1].getReg());
355 bool ARMBaseInstrInfo::
356 SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1,
357 const SmallVectorImpl<MachineOperand> &Pred2) const {
358 if (Pred1.size() > 2 || Pred2.size() > 2)
361 ARMCC::CondCodes CC1 = (ARMCC::CondCodes)Pred1[0].getImm();
362 ARMCC::CondCodes CC2 = (ARMCC::CondCodes)Pred2[0].getImm();
372 return CC2 == ARMCC::HI;
374 return CC2 == ARMCC::LO || CC2 == ARMCC::EQ;
376 return CC2 == ARMCC::GT;
378 return CC2 == ARMCC::LT;
382 bool ARMBaseInstrInfo::DefinesPredicate(MachineInstr *MI,
383 std::vector<MachineOperand> &Pred) const {
384 // FIXME: This confuses implicit_def with optional CPSR def.
385 const TargetInstrDesc &TID = MI->getDesc();
386 if (!TID.getImplicitDefs() && !TID.hasOptionalDef())
390 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
391 const MachineOperand &MO = MI->getOperand(i);
392 if (MO.isReg() && MO.getReg() == ARM::CPSR) {
402 /// FIXME: Works around a gcc miscompilation with -fstrict-aliasing
403 static unsigned getNumJTEntries(const std::vector<MachineJumpTableEntry> &JT,
404 unsigned JTI) DISABLE_INLINE;
405 static unsigned getNumJTEntries(const std::vector<MachineJumpTableEntry> &JT,
407 return JT[JTI].MBBs.size();
410 /// GetInstSize - Return the size of the specified MachineInstr.
412 unsigned ARMBaseInstrInfo::GetInstSizeInBytes(const MachineInstr *MI) const {
413 const MachineBasicBlock &MBB = *MI->getParent();
414 const MachineFunction *MF = MBB.getParent();
415 const MCAsmInfo *MAI = MF->getTarget().getMCAsmInfo();
417 // Basic size info comes from the TSFlags field.
418 const TargetInstrDesc &TID = MI->getDesc();
419 unsigned TSFlags = TID.TSFlags;
421 unsigned Opc = MI->getOpcode();
422 switch ((TSFlags & ARMII::SizeMask) >> ARMII::SizeShift) {
424 // If this machine instr is an inline asm, measure it.
425 if (MI->getOpcode() == ARM::INLINEASM)
426 return getInlineAsmLength(MI->getOperand(0).getSymbolName(), *MAI);
431 llvm_unreachable("Unknown or unset size field for instr!");
432 case TargetInstrInfo::IMPLICIT_DEF:
433 case TargetInstrInfo::KILL:
434 case TargetInstrInfo::DBG_LABEL:
435 case TargetInstrInfo::EH_LABEL:
440 case ARMII::Size8Bytes: return 8; // ARM instruction x 2.
441 case ARMII::Size4Bytes: return 4; // ARM / Thumb2 instruction.
442 case ARMII::Size2Bytes: return 2; // Thumb1 instruction.
443 case ARMII::SizeSpecial: {
445 case ARM::CONSTPOOL_ENTRY:
446 // If this machine instr is a constant pool entry, its size is recorded as
448 return MI->getOperand(2).getImm();
449 case ARM::Int_eh_sjlj_setjmp:
451 case ARM::t2Int_eh_sjlj_setjmp:
460 // These are jumptable branches, i.e. a branch followed by an inlined
461 // jumptable. The size is 4 + 4 * number of entries. For TBB, each
462 // entry is one byte; TBH two byte each.
463 unsigned EntrySize = (Opc == ARM::t2TBB)
464 ? 1 : ((Opc == ARM::t2TBH) ? 2 : 4);
465 unsigned NumOps = TID.getNumOperands();
466 MachineOperand JTOP =
467 MI->getOperand(NumOps - (TID.isPredicable() ? 3 : 2));
468 unsigned JTI = JTOP.getIndex();
469 const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
470 const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
471 assert(JTI < JT.size());
472 // Thumb instructions are 2 byte aligned, but JT entries are 4 byte
473 // 4 aligned. The assembler / linker may add 2 byte padding just before
474 // the JT entries. The size does not include this padding; the
475 // constant islands pass does separate bookkeeping for it.
476 // FIXME: If we know the size of the function is less than (1 << 16) *2
477 // bytes, we can use 16-bit entries instead. Then there won't be an
479 unsigned InstSize = (Opc == ARM::tBR_JTr || Opc == ARM::t2BR_JT) ? 2 : 4;
480 unsigned NumEntries = getNumJTEntries(JT, JTI);
481 if (Opc == ARM::t2TBB && (NumEntries & 1))
482 // Make sure the instruction that follows TBB is 2-byte aligned.
483 // FIXME: Constant island pass should insert an "ALIGN" instruction
486 return NumEntries * EntrySize + InstSize;
489 // Otherwise, pseudo-instruction sizes are zero.
494 return 0; // Not reached
497 /// Return true if the instruction is a register to register move and
498 /// leave the source and dest operands in the passed parameters.
501 ARMBaseInstrInfo::isMoveInstr(const MachineInstr &MI,
502 unsigned &SrcReg, unsigned &DstReg,
503 unsigned& SrcSubIdx, unsigned& DstSubIdx) const {
504 SrcSubIdx = DstSubIdx = 0; // No sub-registers.
506 switch (MI.getOpcode()) {
512 SrcReg = MI.getOperand(1).getReg();
513 DstReg = MI.getOperand(0).getReg();
518 case ARM::tMOVgpr2tgpr:
519 case ARM::tMOVtgpr2gpr:
520 case ARM::tMOVgpr2gpr:
522 assert(MI.getDesc().getNumOperands() >= 2 &&
523 MI.getOperand(0).isReg() &&
524 MI.getOperand(1).isReg() &&
525 "Invalid ARM MOV instruction");
526 SrcReg = MI.getOperand(1).getReg();
527 DstReg = MI.getOperand(0).getReg();
536 ARMBaseInstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
537 int &FrameIndex) const {
538 switch (MI->getOpcode()) {
541 case ARM::t2LDRs: // FIXME: don't use t2LDRs to access frame.
542 if (MI->getOperand(1).isFI() &&
543 MI->getOperand(2).isReg() &&
544 MI->getOperand(3).isImm() &&
545 MI->getOperand(2).getReg() == 0 &&
546 MI->getOperand(3).getImm() == 0) {
547 FrameIndex = MI->getOperand(1).getIndex();
548 return MI->getOperand(0).getReg();
553 if (MI->getOperand(1).isFI() &&
554 MI->getOperand(2).isImm() &&
555 MI->getOperand(2).getImm() == 0) {
556 FrameIndex = MI->getOperand(1).getIndex();
557 return MI->getOperand(0).getReg();
562 if (MI->getOperand(1).isFI() &&
563 MI->getOperand(2).isImm() &&
564 MI->getOperand(2).getImm() == 0) {
565 FrameIndex = MI->getOperand(1).getIndex();
566 return MI->getOperand(0).getReg();
575 ARMBaseInstrInfo::isStoreToStackSlot(const MachineInstr *MI,
576 int &FrameIndex) const {
577 switch (MI->getOpcode()) {
580 case ARM::t2STRs: // FIXME: don't use t2STRs to access frame.
581 if (MI->getOperand(1).isFI() &&
582 MI->getOperand(2).isReg() &&
583 MI->getOperand(3).isImm() &&
584 MI->getOperand(2).getReg() == 0 &&
585 MI->getOperand(3).getImm() == 0) {
586 FrameIndex = MI->getOperand(1).getIndex();
587 return MI->getOperand(0).getReg();
592 if (MI->getOperand(1).isFI() &&
593 MI->getOperand(2).isImm() &&
594 MI->getOperand(2).getImm() == 0) {
595 FrameIndex = MI->getOperand(1).getIndex();
596 return MI->getOperand(0).getReg();
601 if (MI->getOperand(1).isFI() &&
602 MI->getOperand(2).isImm() &&
603 MI->getOperand(2).getImm() == 0) {
604 FrameIndex = MI->getOperand(1).getIndex();
605 return MI->getOperand(0).getReg();
614 ARMBaseInstrInfo::copyRegToReg(MachineBasicBlock &MBB,
615 MachineBasicBlock::iterator I,
616 unsigned DestReg, unsigned SrcReg,
617 const TargetRegisterClass *DestRC,
618 const TargetRegisterClass *SrcRC) const {
619 DebugLoc DL = DebugLoc::getUnknownLoc();
620 if (I != MBB.end()) DL = I->getDebugLoc();
622 if (DestRC != SrcRC) {
623 // Allow DPR / DPR_VFP2 / DPR_8 cross-class copies
624 // Allow QPR / QPR_VFP2 cross-class copies
625 if (DestRC == ARM::DPRRegisterClass) {
626 if (SrcRC == ARM::DPR_VFP2RegisterClass ||
627 SrcRC == ARM::DPR_8RegisterClass) {
630 } else if (DestRC == ARM::DPR_VFP2RegisterClass) {
631 if (SrcRC == ARM::DPRRegisterClass ||
632 SrcRC == ARM::DPR_8RegisterClass) {
635 } else if (DestRC == ARM::DPR_8RegisterClass) {
636 if (SrcRC == ARM::DPRRegisterClass ||
637 SrcRC == ARM::DPR_VFP2RegisterClass) {
640 } else if ((DestRC == ARM::QPRRegisterClass &&
641 SrcRC == ARM::QPR_VFP2RegisterClass) ||
642 (DestRC == ARM::QPR_VFP2RegisterClass &&
643 SrcRC == ARM::QPRRegisterClass)) {
648 if (DestRC == ARM::GPRRegisterClass) {
649 AddDefaultCC(AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::MOVr),
650 DestReg).addReg(SrcReg)));
651 } else if (DestRC == ARM::SPRRegisterClass) {
652 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::FCPYS), DestReg)
654 } else if (DestRC == ARM::DPR_VFP2RegisterClass ||
655 DestRC == ARM::DPR_8RegisterClass ||
656 SrcRC == ARM::DPR_VFP2RegisterClass ||
657 SrcRC == ARM::DPR_8RegisterClass) {
658 // Always use neon reg-reg move if source or dest is NEON-only regclass.
659 BuildMI(MBB, I, DL, get(ARM::VMOVD), DestReg).addReg(SrcReg);
660 } else if (DestRC == ARM::DPRRegisterClass) {
661 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::FCPYD), DestReg)
663 } else if (DestRC == ARM::QPRRegisterClass ||
664 DestRC == ARM::QPR_VFP2RegisterClass) {
665 BuildMI(MBB, I, DL, get(ARM::VMOVQ), DestReg).addReg(SrcReg);
673 void ARMBaseInstrInfo::
674 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
675 unsigned SrcReg, bool isKill, int FI,
676 const TargetRegisterClass *RC) const {
677 DebugLoc DL = DebugLoc::getUnknownLoc();
678 if (I != MBB.end()) DL = I->getDebugLoc();
679 MachineFunction &MF = *MBB.getParent();
680 MachineFrameInfo &MFI = *MF.getFrameInfo();
682 MachineMemOperand *MMO =
683 MF.getMachineMemOperand(PseudoSourceValue::getFixedStack(FI),
684 MachineMemOperand::MOStore, 0,
685 MFI.getObjectSize(FI),
686 MFI.getObjectAlignment(FI));
688 if (RC == ARM::GPRRegisterClass) {
689 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::STR))
690 .addReg(SrcReg, getKillRegState(isKill))
691 .addFrameIndex(FI).addReg(0).addImm(0).addMemOperand(MMO));
692 } else if (RC == ARM::DPRRegisterClass ||
693 RC == ARM::DPR_VFP2RegisterClass ||
694 RC == ARM::DPR_8RegisterClass) {
695 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::FSTD))
696 .addReg(SrcReg, getKillRegState(isKill))
697 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
698 } else if (RC == ARM::SPRRegisterClass) {
699 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::FSTS))
700 .addReg(SrcReg, getKillRegState(isKill))
701 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
703 assert((RC == ARM::QPRRegisterClass ||
704 RC == ARM::QPR_VFP2RegisterClass) && "Unknown regclass!");
705 // FIXME: Neon instructions should support predicates
706 BuildMI(MBB, I, DL, get(ARM::VSTRQ)).addReg(SrcReg, getKillRegState(isKill))
707 .addFrameIndex(FI).addImm(0).addMemOperand(MMO);
711 void ARMBaseInstrInfo::
712 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
713 unsigned DestReg, int FI,
714 const TargetRegisterClass *RC) const {
715 DebugLoc DL = DebugLoc::getUnknownLoc();
716 if (I != MBB.end()) DL = I->getDebugLoc();
717 MachineFunction &MF = *MBB.getParent();
718 MachineFrameInfo &MFI = *MF.getFrameInfo();
720 MachineMemOperand *MMO =
721 MF.getMachineMemOperand(PseudoSourceValue::getFixedStack(FI),
722 MachineMemOperand::MOLoad, 0,
723 MFI.getObjectSize(FI),
724 MFI.getObjectAlignment(FI));
726 if (RC == ARM::GPRRegisterClass) {
727 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::LDR), DestReg)
728 .addFrameIndex(FI).addReg(0).addImm(0).addMemOperand(MMO));
729 } else if (RC == ARM::DPRRegisterClass ||
730 RC == ARM::DPR_VFP2RegisterClass ||
731 RC == ARM::DPR_8RegisterClass) {
732 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::FLDD), DestReg)
733 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
734 } else if (RC == ARM::SPRRegisterClass) {
735 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::FLDS), DestReg)
736 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
738 assert((RC == ARM::QPRRegisterClass ||
739 RC == ARM::QPR_VFP2RegisterClass) && "Unknown regclass!");
740 // FIXME: Neon instructions should support predicates
741 BuildMI(MBB, I, DL, get(ARM::VLDRQ), DestReg).addFrameIndex(FI).addImm(0).
746 MachineInstr *ARMBaseInstrInfo::
747 foldMemoryOperandImpl(MachineFunction &MF, MachineInstr *MI,
748 const SmallVectorImpl<unsigned> &Ops, int FI) const {
749 if (Ops.size() != 1) return NULL;
751 unsigned OpNum = Ops[0];
752 unsigned Opc = MI->getOpcode();
753 MachineInstr *NewMI = NULL;
754 if (Opc == ARM::MOVr || Opc == ARM::t2MOVr) {
755 // If it is updating CPSR, then it cannot be folded.
756 if (MI->getOperand(4).getReg() == ARM::CPSR && !MI->getOperand(4).isDead())
758 unsigned Pred = MI->getOperand(2).getImm();
759 unsigned PredReg = MI->getOperand(3).getReg();
760 if (OpNum == 0) { // move -> store
761 unsigned SrcReg = MI->getOperand(1).getReg();
762 unsigned SrcSubReg = MI->getOperand(1).getSubReg();
763 bool isKill = MI->getOperand(1).isKill();
764 bool isUndef = MI->getOperand(1).isUndef();
765 if (Opc == ARM::MOVr)
766 NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::STR))
768 getKillRegState(isKill) | getUndefRegState(isUndef),
770 .addFrameIndex(FI).addReg(0).addImm(0).addImm(Pred).addReg(PredReg);
772 NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::t2STRi12))
774 getKillRegState(isKill) | getUndefRegState(isUndef),
776 .addFrameIndex(FI).addImm(0).addImm(Pred).addReg(PredReg);
777 } else { // move -> load
778 unsigned DstReg = MI->getOperand(0).getReg();
779 unsigned DstSubReg = MI->getOperand(0).getSubReg();
780 bool isDead = MI->getOperand(0).isDead();
781 bool isUndef = MI->getOperand(0).isUndef();
782 if (Opc == ARM::MOVr)
783 NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::LDR))
786 getDeadRegState(isDead) |
787 getUndefRegState(isUndef), DstSubReg)
788 .addFrameIndex(FI).addReg(0).addImm(0).addImm(Pred).addReg(PredReg);
790 NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::t2LDRi12))
793 getDeadRegState(isDead) |
794 getUndefRegState(isUndef), DstSubReg)
795 .addFrameIndex(FI).addImm(0).addImm(Pred).addReg(PredReg);
797 } else if (Opc == ARM::tMOVgpr2gpr ||
798 Opc == ARM::tMOVtgpr2gpr ||
799 Opc == ARM::tMOVgpr2tgpr) {
800 if (OpNum == 0) { // move -> store
801 unsigned SrcReg = MI->getOperand(1).getReg();
802 unsigned SrcSubReg = MI->getOperand(1).getSubReg();
803 bool isKill = MI->getOperand(1).isKill();
804 bool isUndef = MI->getOperand(1).isUndef();
805 NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::t2STRi12))
807 getKillRegState(isKill) | getUndefRegState(isUndef),
809 .addFrameIndex(FI).addImm(0).addImm(ARMCC::AL).addReg(0);
810 } else { // move -> load
811 unsigned DstReg = MI->getOperand(0).getReg();
812 unsigned DstSubReg = MI->getOperand(0).getSubReg();
813 bool isDead = MI->getOperand(0).isDead();
814 bool isUndef = MI->getOperand(0).isUndef();
815 NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::t2LDRi12))
818 getDeadRegState(isDead) |
819 getUndefRegState(isUndef),
821 .addFrameIndex(FI).addImm(0).addImm(ARMCC::AL).addReg(0);
823 } else if (Opc == ARM::FCPYS) {
824 unsigned Pred = MI->getOperand(2).getImm();
825 unsigned PredReg = MI->getOperand(3).getReg();
826 if (OpNum == 0) { // move -> store
827 unsigned SrcReg = MI->getOperand(1).getReg();
828 unsigned SrcSubReg = MI->getOperand(1).getSubReg();
829 bool isKill = MI->getOperand(1).isKill();
830 bool isUndef = MI->getOperand(1).isUndef();
831 NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::FSTS))
832 .addReg(SrcReg, getKillRegState(isKill) | getUndefRegState(isUndef),
835 .addImm(0).addImm(Pred).addReg(PredReg);
836 } else { // move -> load
837 unsigned DstReg = MI->getOperand(0).getReg();
838 unsigned DstSubReg = MI->getOperand(0).getSubReg();
839 bool isDead = MI->getOperand(0).isDead();
840 bool isUndef = MI->getOperand(0).isUndef();
841 NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::FLDS))
844 getDeadRegState(isDead) |
845 getUndefRegState(isUndef),
847 .addFrameIndex(FI).addImm(0).addImm(Pred).addReg(PredReg);
850 else if (Opc == ARM::FCPYD) {
851 unsigned Pred = MI->getOperand(2).getImm();
852 unsigned PredReg = MI->getOperand(3).getReg();
853 if (OpNum == 0) { // move -> store
854 unsigned SrcReg = MI->getOperand(1).getReg();
855 unsigned SrcSubReg = MI->getOperand(1).getSubReg();
856 bool isKill = MI->getOperand(1).isKill();
857 bool isUndef = MI->getOperand(1).isUndef();
858 NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::FSTD))
860 getKillRegState(isKill) | getUndefRegState(isUndef),
862 .addFrameIndex(FI).addImm(0).addImm(Pred).addReg(PredReg);
863 } else { // move -> load
864 unsigned DstReg = MI->getOperand(0).getReg();
865 unsigned DstSubReg = MI->getOperand(0).getSubReg();
866 bool isDead = MI->getOperand(0).isDead();
867 bool isUndef = MI->getOperand(0).isUndef();
868 NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::FLDD))
871 getDeadRegState(isDead) |
872 getUndefRegState(isUndef),
874 .addFrameIndex(FI).addImm(0).addImm(Pred).addReg(PredReg);
882 ARMBaseInstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
884 const SmallVectorImpl<unsigned> &Ops,
885 MachineInstr* LoadMI) const {
891 ARMBaseInstrInfo::canFoldMemoryOperand(const MachineInstr *MI,
892 const SmallVectorImpl<unsigned> &Ops) const {
893 if (Ops.size() != 1) return false;
895 unsigned Opc = MI->getOpcode();
896 if (Opc == ARM::MOVr || Opc == ARM::t2MOVr) {
897 // If it is updating CPSR, then it cannot be folded.
898 return MI->getOperand(4).getReg() != ARM::CPSR ||
899 MI->getOperand(4).isDead();
900 } else if (Opc == ARM::tMOVgpr2gpr ||
901 Opc == ARM::tMOVtgpr2gpr ||
902 Opc == ARM::tMOVgpr2tgpr) {
904 } else if (Opc == ARM::FCPYS || Opc == ARM::FCPYD) {
906 } else if (Opc == ARM::VMOVD || Opc == ARM::VMOVQ) {
907 return false; // FIXME
913 /// getInstrPredicate - If instruction is predicated, returns its predicate
914 /// condition, otherwise returns AL. It also returns the condition code
915 /// register by reference.
917 llvm::getInstrPredicate(const MachineInstr *MI, unsigned &PredReg) {
918 int PIdx = MI->findFirstPredOperandIdx();
924 PredReg = MI->getOperand(PIdx+1).getReg();
925 return (ARMCC::CondCodes)MI->getOperand(PIdx).getImm();
929 int llvm::getMatchingCondBranchOpcode(int Opc) {
932 else if (Opc == ARM::tB)
934 else if (Opc == ARM::t2B)
937 llvm_unreachable("Unknown unconditional branch opcode!");
942 void llvm::emitARMRegPlusImmediate(MachineBasicBlock &MBB,
943 MachineBasicBlock::iterator &MBBI, DebugLoc dl,
944 unsigned DestReg, unsigned BaseReg, int NumBytes,
945 ARMCC::CondCodes Pred, unsigned PredReg,
946 const ARMBaseInstrInfo &TII) {
947 bool isSub = NumBytes < 0;
948 if (isSub) NumBytes = -NumBytes;
951 unsigned RotAmt = ARM_AM::getSOImmValRotate(NumBytes);
952 unsigned ThisVal = NumBytes & ARM_AM::rotr32(0xFF, RotAmt);
953 assert(ThisVal && "Didn't extract field correctly");
955 // We will handle these bits from offset, clear them.
956 NumBytes &= ~ThisVal;
958 assert(ARM_AM::getSOImmVal(ThisVal) != -1 && "Bit extraction didn't work?");
960 // Build the new ADD / SUB.
961 unsigned Opc = isSub ? ARM::SUBri : ARM::ADDri;
962 BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg)
963 .addReg(BaseReg, RegState::Kill).addImm(ThisVal)
964 .addImm((unsigned)Pred).addReg(PredReg).addReg(0);
969 bool llvm::rewriteARMFrameIndex(MachineInstr &MI, unsigned FrameRegIdx,
970 unsigned FrameReg, int &Offset,
971 const ARMBaseInstrInfo &TII) {
972 unsigned Opcode = MI.getOpcode();
973 const TargetInstrDesc &Desc = MI.getDesc();
974 unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
977 // Memory operands in inline assembly always use AddrMode2.
978 if (Opcode == ARM::INLINEASM)
979 AddrMode = ARMII::AddrMode2;
981 if (Opcode == ARM::ADDri) {
982 Offset += MI.getOperand(FrameRegIdx+1).getImm();
984 // Turn it into a move.
985 MI.setDesc(TII.get(ARM::MOVr));
986 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
987 MI.RemoveOperand(FrameRegIdx+1);
990 } else if (Offset < 0) {
993 MI.setDesc(TII.get(ARM::SUBri));
996 // Common case: small offset, fits into instruction.
997 if (ARM_AM::getSOImmVal(Offset) != -1) {
998 // Replace the FrameIndex with sp / fp
999 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
1000 MI.getOperand(FrameRegIdx+1).ChangeToImmediate(Offset);
1005 // Otherwise, pull as much of the immedidate into this ADDri/SUBri
1007 unsigned RotAmt = ARM_AM::getSOImmValRotate(Offset);
1008 unsigned ThisImmVal = Offset & ARM_AM::rotr32(0xFF, RotAmt);
1010 // We will handle these bits from offset, clear them.
1011 Offset &= ~ThisImmVal;
1013 // Get the properly encoded SOImmVal field.
1014 assert(ARM_AM::getSOImmVal(ThisImmVal) != -1 &&
1015 "Bit extraction didn't work?");
1016 MI.getOperand(FrameRegIdx+1).ChangeToImmediate(ThisImmVal);
1018 unsigned ImmIdx = 0;
1020 unsigned NumBits = 0;
1023 case ARMII::AddrMode2: {
1024 ImmIdx = FrameRegIdx+2;
1025 InstrOffs = ARM_AM::getAM2Offset(MI.getOperand(ImmIdx).getImm());
1026 if (ARM_AM::getAM2Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub)
1031 case ARMII::AddrMode3: {
1032 ImmIdx = FrameRegIdx+2;
1033 InstrOffs = ARM_AM::getAM3Offset(MI.getOperand(ImmIdx).getImm());
1034 if (ARM_AM::getAM3Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub)
1039 case ARMII::AddrMode4:
1040 // Can't fold any offset even if it's zero.
1042 case ARMII::AddrMode5: {
1043 ImmIdx = FrameRegIdx+1;
1044 InstrOffs = ARM_AM::getAM5Offset(MI.getOperand(ImmIdx).getImm());
1045 if (ARM_AM::getAM5Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub)
1052 llvm_unreachable("Unsupported addressing mode!");
1056 Offset += InstrOffs * Scale;
1057 assert((Offset & (Scale-1)) == 0 && "Can't encode this offset!");
1063 // Attempt to fold address comp. if opcode has offset bits
1065 // Common case: small offset, fits into instruction.
1066 MachineOperand &ImmOp = MI.getOperand(ImmIdx);
1067 int ImmedOffset = Offset / Scale;
1068 unsigned Mask = (1 << NumBits) - 1;
1069 if ((unsigned)Offset <= Mask * Scale) {
1070 // Replace the FrameIndex with sp
1071 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
1073 ImmedOffset |= 1 << NumBits;
1074 ImmOp.ChangeToImmediate(ImmedOffset);
1079 // Otherwise, it didn't fit. Pull in what we can to simplify the immed.
1080 ImmedOffset = ImmedOffset & Mask;
1082 ImmedOffset |= 1 << NumBits;
1083 ImmOp.ChangeToImmediate(ImmedOffset);
1084 Offset &= ~(Mask*Scale);
1088 Offset = (isSub) ? -Offset : Offset;