1 //===- ARMBaseInstrInfo.cpp - ARM Instruction Information -------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Base ARM implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "ARMBaseInstrInfo.h"
16 #include "ARMAddressingModes.h"
17 #include "ARMConstantPoolValue.h"
18 #include "ARMGenInstrInfo.inc"
19 #include "ARMMachineFunctionInfo.h"
20 #include "ARMRegisterInfo.h"
21 #include "llvm/Constants.h"
22 #include "llvm/Function.h"
23 #include "llvm/GlobalValue.h"
24 #include "llvm/ADT/STLExtras.h"
25 #include "llvm/CodeGen/LiveVariables.h"
26 #include "llvm/CodeGen/MachineConstantPool.h"
27 #include "llvm/CodeGen/MachineFrameInfo.h"
28 #include "llvm/CodeGen/MachineInstrBuilder.h"
29 #include "llvm/CodeGen/MachineJumpTableInfo.h"
30 #include "llvm/CodeGen/MachineMemOperand.h"
31 #include "llvm/CodeGen/PseudoSourceValue.h"
32 #include "llvm/MC/MCAsmInfo.h"
33 #include "llvm/Support/CommandLine.h"
34 #include "llvm/Support/Debug.h"
35 #include "llvm/Support/ErrorHandling.h"
39 EnableARM3Addr("enable-arm-3-addr-conv", cl::Hidden,
40 cl::desc("Enable ARM 2-addr to 3-addr conv"));
42 ARMBaseInstrInfo::ARMBaseInstrInfo(const ARMSubtarget& STI)
43 : TargetInstrInfoImpl(ARMInsts, array_lengthof(ARMInsts)),
48 ARMBaseInstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
49 MachineBasicBlock::iterator &MBBI,
50 LiveVariables *LV) const {
51 // FIXME: Thumb2 support.
56 MachineInstr *MI = MBBI;
57 MachineFunction &MF = *MI->getParent()->getParent();
58 unsigned TSFlags = MI->getDesc().TSFlags;
60 switch ((TSFlags & ARMII::IndexModeMask) >> ARMII::IndexModeShift) {
62 case ARMII::IndexModePre:
65 case ARMII::IndexModePost:
69 // Try splitting an indexed load/store to an un-indexed one plus an add/sub
71 unsigned MemOpc = getUnindexedOpcode(MI->getOpcode());
75 MachineInstr *UpdateMI = NULL;
76 MachineInstr *MemMI = NULL;
77 unsigned AddrMode = (TSFlags & ARMII::AddrModeMask);
78 const TargetInstrDesc &TID = MI->getDesc();
79 unsigned NumOps = TID.getNumOperands();
80 bool isLoad = !TID.mayStore();
81 const MachineOperand &WB = isLoad ? MI->getOperand(1) : MI->getOperand(0);
82 const MachineOperand &Base = MI->getOperand(2);
83 const MachineOperand &Offset = MI->getOperand(NumOps-3);
84 unsigned WBReg = WB.getReg();
85 unsigned BaseReg = Base.getReg();
86 unsigned OffReg = Offset.getReg();
87 unsigned OffImm = MI->getOperand(NumOps-2).getImm();
88 ARMCC::CondCodes Pred = (ARMCC::CondCodes)MI->getOperand(NumOps-1).getImm();
91 assert(false && "Unknown indexed op!");
93 case ARMII::AddrMode2: {
94 bool isSub = ARM_AM::getAM2Op(OffImm) == ARM_AM::sub;
95 unsigned Amt = ARM_AM::getAM2Offset(OffImm);
97 if (ARM_AM::getSOImmVal(Amt) == -1)
98 // Can't encode it in a so_imm operand. This transformation will
99 // add more than 1 instruction. Abandon!
101 UpdateMI = BuildMI(MF, MI->getDebugLoc(),
102 get(isSub ? ARM::SUBri : ARM::ADDri), WBReg)
103 .addReg(BaseReg).addImm(Amt)
104 .addImm(Pred).addReg(0).addReg(0);
105 } else if (Amt != 0) {
106 ARM_AM::ShiftOpc ShOpc = ARM_AM::getAM2ShiftOpc(OffImm);
107 unsigned SOOpc = ARM_AM::getSORegOpc(ShOpc, Amt);
108 UpdateMI = BuildMI(MF, MI->getDebugLoc(),
109 get(isSub ? ARM::SUBrs : ARM::ADDrs), WBReg)
110 .addReg(BaseReg).addReg(OffReg).addReg(0).addImm(SOOpc)
111 .addImm(Pred).addReg(0).addReg(0);
113 UpdateMI = BuildMI(MF, MI->getDebugLoc(),
114 get(isSub ? ARM::SUBrr : ARM::ADDrr), WBReg)
115 .addReg(BaseReg).addReg(OffReg)
116 .addImm(Pred).addReg(0).addReg(0);
119 case ARMII::AddrMode3 : {
120 bool isSub = ARM_AM::getAM3Op(OffImm) == ARM_AM::sub;
121 unsigned Amt = ARM_AM::getAM3Offset(OffImm);
123 // Immediate is 8-bits. It's guaranteed to fit in a so_imm operand.
124 UpdateMI = BuildMI(MF, MI->getDebugLoc(),
125 get(isSub ? ARM::SUBri : ARM::ADDri), WBReg)
126 .addReg(BaseReg).addImm(Amt)
127 .addImm(Pred).addReg(0).addReg(0);
129 UpdateMI = BuildMI(MF, MI->getDebugLoc(),
130 get(isSub ? ARM::SUBrr : ARM::ADDrr), WBReg)
131 .addReg(BaseReg).addReg(OffReg)
132 .addImm(Pred).addReg(0).addReg(0);
137 std::vector<MachineInstr*> NewMIs;
140 MemMI = BuildMI(MF, MI->getDebugLoc(),
141 get(MemOpc), MI->getOperand(0).getReg())
142 .addReg(WBReg).addReg(0).addImm(0).addImm(Pred);
144 MemMI = BuildMI(MF, MI->getDebugLoc(),
145 get(MemOpc)).addReg(MI->getOperand(1).getReg())
146 .addReg(WBReg).addReg(0).addImm(0).addImm(Pred);
147 NewMIs.push_back(MemMI);
148 NewMIs.push_back(UpdateMI);
151 MemMI = BuildMI(MF, MI->getDebugLoc(),
152 get(MemOpc), MI->getOperand(0).getReg())
153 .addReg(BaseReg).addReg(0).addImm(0).addImm(Pred);
155 MemMI = BuildMI(MF, MI->getDebugLoc(),
156 get(MemOpc)).addReg(MI->getOperand(1).getReg())
157 .addReg(BaseReg).addReg(0).addImm(0).addImm(Pred);
159 UpdateMI->getOperand(0).setIsDead();
160 NewMIs.push_back(UpdateMI);
161 NewMIs.push_back(MemMI);
164 // Transfer LiveVariables states, kill / dead info.
166 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
167 MachineOperand &MO = MI->getOperand(i);
168 if (MO.isReg() && MO.getReg() &&
169 TargetRegisterInfo::isVirtualRegister(MO.getReg())) {
170 unsigned Reg = MO.getReg();
172 LiveVariables::VarInfo &VI = LV->getVarInfo(Reg);
174 MachineInstr *NewMI = (Reg == WBReg) ? UpdateMI : MemMI;
176 LV->addVirtualRegisterDead(Reg, NewMI);
178 if (MO.isUse() && MO.isKill()) {
179 for (unsigned j = 0; j < 2; ++j) {
180 // Look at the two new MI's in reverse order.
181 MachineInstr *NewMI = NewMIs[j];
182 if (!NewMI->readsRegister(Reg))
184 LV->addVirtualRegisterKilled(Reg, NewMI);
185 if (VI.removeKill(MI))
186 VI.Kills.push_back(NewMI);
194 MFI->insert(MBBI, NewMIs[1]);
195 MFI->insert(MBBI, NewMIs[0]);
201 ARMBaseInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB,
202 MachineBasicBlock *&FBB,
203 SmallVectorImpl<MachineOperand> &Cond,
204 bool AllowModify) const {
205 // If the block has no terminators, it just falls into the block after it.
206 MachineBasicBlock::iterator I = MBB.end();
207 if (I == MBB.begin())
210 while (I->isDebugValue()) {
211 if (I == MBB.begin())
215 if (!isUnpredicatedTerminator(I))
218 // Get the last instruction in the block.
219 MachineInstr *LastInst = I;
221 // If there is only one terminator instruction, process it.
222 unsigned LastOpc = LastInst->getOpcode();
223 if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) {
224 if (isUncondBranchOpcode(LastOpc)) {
225 TBB = LastInst->getOperand(0).getMBB();
228 if (isCondBranchOpcode(LastOpc)) {
229 // Block ends with fall-through condbranch.
230 TBB = LastInst->getOperand(0).getMBB();
231 Cond.push_back(LastInst->getOperand(1));
232 Cond.push_back(LastInst->getOperand(2));
235 return true; // Can't handle indirect branch.
238 // Get the instruction before it if it is a terminator.
239 MachineInstr *SecondLastInst = I;
241 // If there are three terminators, we don't know what sort of block this is.
242 if (SecondLastInst && I != MBB.begin() && isUnpredicatedTerminator(--I))
245 // If the block ends with a B and a Bcc, handle it.
246 unsigned SecondLastOpc = SecondLastInst->getOpcode();
247 if (isCondBranchOpcode(SecondLastOpc) && isUncondBranchOpcode(LastOpc)) {
248 TBB = SecondLastInst->getOperand(0).getMBB();
249 Cond.push_back(SecondLastInst->getOperand(1));
250 Cond.push_back(SecondLastInst->getOperand(2));
251 FBB = LastInst->getOperand(0).getMBB();
255 // If the block ends with two unconditional branches, handle it. The second
256 // one is not executed, so remove it.
257 if (isUncondBranchOpcode(SecondLastOpc) && isUncondBranchOpcode(LastOpc)) {
258 TBB = SecondLastInst->getOperand(0).getMBB();
261 I->eraseFromParent();
265 // ...likewise if it ends with a branch table followed by an unconditional
266 // branch. The branch folder can create these, and we must get rid of them for
267 // correctness of Thumb constant islands.
268 if ((isJumpTableBranchOpcode(SecondLastOpc) ||
269 isIndirectBranchOpcode(SecondLastOpc)) &&
270 isUncondBranchOpcode(LastOpc)) {
273 I->eraseFromParent();
277 // Otherwise, can't handle this.
282 unsigned ARMBaseInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
283 MachineBasicBlock::iterator I = MBB.end();
284 if (I == MBB.begin()) return 0;
286 while (I->isDebugValue()) {
287 if (I == MBB.begin())
291 if (!isUncondBranchOpcode(I->getOpcode()) &&
292 !isCondBranchOpcode(I->getOpcode()))
295 // Remove the branch.
296 I->eraseFromParent();
300 if (I == MBB.begin()) return 1;
302 if (!isCondBranchOpcode(I->getOpcode()))
305 // Remove the branch.
306 I->eraseFromParent();
311 ARMBaseInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
312 MachineBasicBlock *FBB,
313 const SmallVectorImpl<MachineOperand> &Cond) const {
314 // FIXME this should probably have a DebugLoc argument
317 ARMFunctionInfo *AFI = MBB.getParent()->getInfo<ARMFunctionInfo>();
318 int BOpc = !AFI->isThumbFunction()
319 ? ARM::B : (AFI->isThumb2Function() ? ARM::t2B : ARM::tB);
320 int BccOpc = !AFI->isThumbFunction()
321 ? ARM::Bcc : (AFI->isThumb2Function() ? ARM::t2Bcc : ARM::tBcc);
323 // Shouldn't be a fall through.
324 assert(TBB && "InsertBranch must not be told to insert a fallthrough");
325 assert((Cond.size() == 2 || Cond.size() == 0) &&
326 "ARM branch conditions have two components!");
329 if (Cond.empty()) // Unconditional branch?
330 BuildMI(&MBB, dl, get(BOpc)).addMBB(TBB);
332 BuildMI(&MBB, dl, get(BccOpc)).addMBB(TBB)
333 .addImm(Cond[0].getImm()).addReg(Cond[1].getReg());
337 // Two-way conditional branch.
338 BuildMI(&MBB, dl, get(BccOpc)).addMBB(TBB)
339 .addImm(Cond[0].getImm()).addReg(Cond[1].getReg());
340 BuildMI(&MBB, dl, get(BOpc)).addMBB(FBB);
344 bool ARMBaseInstrInfo::
345 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
346 ARMCC::CondCodes CC = (ARMCC::CondCodes)(int)Cond[0].getImm();
347 Cond[0].setImm(ARMCC::getOppositeCondition(CC));
351 bool ARMBaseInstrInfo::
352 PredicateInstruction(MachineInstr *MI,
353 const SmallVectorImpl<MachineOperand> &Pred) const {
354 unsigned Opc = MI->getOpcode();
355 if (isUncondBranchOpcode(Opc)) {
356 MI->setDesc(get(getMatchingCondBranchOpcode(Opc)));
357 MI->addOperand(MachineOperand::CreateImm(Pred[0].getImm()));
358 MI->addOperand(MachineOperand::CreateReg(Pred[1].getReg(), false));
362 int PIdx = MI->findFirstPredOperandIdx();
364 MachineOperand &PMO = MI->getOperand(PIdx);
365 PMO.setImm(Pred[0].getImm());
366 MI->getOperand(PIdx+1).setReg(Pred[1].getReg());
372 bool ARMBaseInstrInfo::
373 SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1,
374 const SmallVectorImpl<MachineOperand> &Pred2) const {
375 if (Pred1.size() > 2 || Pred2.size() > 2)
378 ARMCC::CondCodes CC1 = (ARMCC::CondCodes)Pred1[0].getImm();
379 ARMCC::CondCodes CC2 = (ARMCC::CondCodes)Pred2[0].getImm();
389 return CC2 == ARMCC::HI;
391 return CC2 == ARMCC::LO || CC2 == ARMCC::EQ;
393 return CC2 == ARMCC::GT;
395 return CC2 == ARMCC::LT;
399 bool ARMBaseInstrInfo::DefinesPredicate(MachineInstr *MI,
400 std::vector<MachineOperand> &Pred) const {
401 // FIXME: This confuses implicit_def with optional CPSR def.
402 const TargetInstrDesc &TID = MI->getDesc();
403 if (!TID.getImplicitDefs() && !TID.hasOptionalDef())
407 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
408 const MachineOperand &MO = MI->getOperand(i);
409 if (MO.isReg() && MO.getReg() == ARM::CPSR) {
418 /// isPredicable - Return true if the specified instruction can be predicated.
419 /// By default, this returns true for every instruction with a
420 /// PredicateOperand.
421 bool ARMBaseInstrInfo::isPredicable(MachineInstr *MI) const {
422 const TargetInstrDesc &TID = MI->getDesc();
423 if (!TID.isPredicable())
426 if ((TID.TSFlags & ARMII::DomainMask) == ARMII::DomainNEON) {
427 ARMFunctionInfo *AFI =
428 MI->getParent()->getParent()->getInfo<ARMFunctionInfo>();
429 return AFI->isThumb2Function();
434 /// FIXME: Works around a gcc miscompilation with -fstrict-aliasing.
436 static unsigned getNumJTEntries(const std::vector<MachineJumpTableEntry> &JT,
438 static unsigned getNumJTEntries(const std::vector<MachineJumpTableEntry> &JT,
440 assert(JTI < JT.size());
441 return JT[JTI].MBBs.size();
444 /// GetInstSize - Return the size of the specified MachineInstr.
446 unsigned ARMBaseInstrInfo::GetInstSizeInBytes(const MachineInstr *MI) const {
447 const MachineBasicBlock &MBB = *MI->getParent();
448 const MachineFunction *MF = MBB.getParent();
449 const MCAsmInfo *MAI = MF->getTarget().getMCAsmInfo();
451 // Basic size info comes from the TSFlags field.
452 const TargetInstrDesc &TID = MI->getDesc();
453 unsigned TSFlags = TID.TSFlags;
455 unsigned Opc = MI->getOpcode();
456 switch ((TSFlags & ARMII::SizeMask) >> ARMII::SizeShift) {
458 // If this machine instr is an inline asm, measure it.
459 if (MI->getOpcode() == ARM::INLINEASM)
460 return getInlineAsmLength(MI->getOperand(0).getSymbolName(), *MAI);
465 llvm_unreachable("Unknown or unset size field for instr!");
466 case TargetOpcode::IMPLICIT_DEF:
467 case TargetOpcode::KILL:
468 case TargetOpcode::DBG_LABEL:
469 case TargetOpcode::EH_LABEL:
470 case TargetOpcode::DBG_VALUE:
475 case ARMII::Size8Bytes: return 8; // ARM instruction x 2.
476 case ARMII::Size4Bytes: return 4; // ARM / Thumb2 instruction.
477 case ARMII::Size2Bytes: return 2; // Thumb1 instruction.
478 case ARMII::SizeSpecial: {
480 case ARM::CONSTPOOL_ENTRY:
481 // If this machine instr is a constant pool entry, its size is recorded as
483 return MI->getOperand(2).getImm();
484 case ARM::Int_eh_sjlj_setjmp:
485 case ARM::Int_eh_sjlj_setjmp_nofp:
487 case ARM::tInt_eh_sjlj_setjmp:
488 case ARM::t2Int_eh_sjlj_setjmp:
489 case ARM::t2Int_eh_sjlj_setjmp_nofp:
498 // These are jumptable branches, i.e. a branch followed by an inlined
499 // jumptable. The size is 4 + 4 * number of entries. For TBB, each
500 // entry is one byte; TBH two byte each.
501 unsigned EntrySize = (Opc == ARM::t2TBB)
502 ? 1 : ((Opc == ARM::t2TBH) ? 2 : 4);
503 unsigned NumOps = TID.getNumOperands();
504 MachineOperand JTOP =
505 MI->getOperand(NumOps - (TID.isPredicable() ? 3 : 2));
506 unsigned JTI = JTOP.getIndex();
507 const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
509 const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
510 assert(JTI < JT.size());
511 // Thumb instructions are 2 byte aligned, but JT entries are 4 byte
512 // 4 aligned. The assembler / linker may add 2 byte padding just before
513 // the JT entries. The size does not include this padding; the
514 // constant islands pass does separate bookkeeping for it.
515 // FIXME: If we know the size of the function is less than (1 << 16) *2
516 // bytes, we can use 16-bit entries instead. Then there won't be an
518 unsigned InstSize = (Opc == ARM::tBR_JTr || Opc == ARM::t2BR_JT) ? 2 : 4;
519 unsigned NumEntries = getNumJTEntries(JT, JTI);
520 if (Opc == ARM::t2TBB && (NumEntries & 1))
521 // Make sure the instruction that follows TBB is 2-byte aligned.
522 // FIXME: Constant island pass should insert an "ALIGN" instruction
525 return NumEntries * EntrySize + InstSize;
528 // Otherwise, pseudo-instruction sizes are zero.
533 return 0; // Not reached
536 /// Return true if the instruction is a register to register move and
537 /// leave the source and dest operands in the passed parameters.
540 ARMBaseInstrInfo::isMoveInstr(const MachineInstr &MI,
541 unsigned &SrcReg, unsigned &DstReg,
542 unsigned& SrcSubIdx, unsigned& DstSubIdx) const {
543 switch (MI.getOpcode()) {
550 SrcReg = MI.getOperand(1).getReg();
551 DstReg = MI.getOperand(0).getReg();
552 SrcSubIdx = MI.getOperand(1).getSubReg();
553 DstSubIdx = MI.getOperand(0).getSubReg();
558 case ARM::tMOVgpr2tgpr:
559 case ARM::tMOVtgpr2gpr:
560 case ARM::tMOVgpr2gpr:
562 assert(MI.getDesc().getNumOperands() >= 2 &&
563 MI.getOperand(0).isReg() &&
564 MI.getOperand(1).isReg() &&
565 "Invalid ARM MOV instruction");
566 SrcReg = MI.getOperand(1).getReg();
567 DstReg = MI.getOperand(0).getReg();
568 SrcSubIdx = MI.getOperand(1).getSubReg();
569 DstSubIdx = MI.getOperand(0).getSubReg();
578 ARMBaseInstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
579 int &FrameIndex) const {
580 switch (MI->getOpcode()) {
583 case ARM::t2LDRs: // FIXME: don't use t2LDRs to access frame.
584 if (MI->getOperand(1).isFI() &&
585 MI->getOperand(2).isReg() &&
586 MI->getOperand(3).isImm() &&
587 MI->getOperand(2).getReg() == 0 &&
588 MI->getOperand(3).getImm() == 0) {
589 FrameIndex = MI->getOperand(1).getIndex();
590 return MI->getOperand(0).getReg();
595 if (MI->getOperand(1).isFI() &&
596 MI->getOperand(2).isImm() &&
597 MI->getOperand(2).getImm() == 0) {
598 FrameIndex = MI->getOperand(1).getIndex();
599 return MI->getOperand(0).getReg();
604 if (MI->getOperand(1).isFI() &&
605 MI->getOperand(2).isImm() &&
606 MI->getOperand(2).getImm() == 0) {
607 FrameIndex = MI->getOperand(1).getIndex();
608 return MI->getOperand(0).getReg();
617 ARMBaseInstrInfo::isStoreToStackSlot(const MachineInstr *MI,
618 int &FrameIndex) const {
619 switch (MI->getOpcode()) {
622 case ARM::t2STRs: // FIXME: don't use t2STRs to access frame.
623 if (MI->getOperand(1).isFI() &&
624 MI->getOperand(2).isReg() &&
625 MI->getOperand(3).isImm() &&
626 MI->getOperand(2).getReg() == 0 &&
627 MI->getOperand(3).getImm() == 0) {
628 FrameIndex = MI->getOperand(1).getIndex();
629 return MI->getOperand(0).getReg();
634 if (MI->getOperand(1).isFI() &&
635 MI->getOperand(2).isImm() &&
636 MI->getOperand(2).getImm() == 0) {
637 FrameIndex = MI->getOperand(1).getIndex();
638 return MI->getOperand(0).getReg();
643 if (MI->getOperand(1).isFI() &&
644 MI->getOperand(2).isImm() &&
645 MI->getOperand(2).getImm() == 0) {
646 FrameIndex = MI->getOperand(1).getIndex();
647 return MI->getOperand(0).getReg();
656 ARMBaseInstrInfo::copyRegToReg(MachineBasicBlock &MBB,
657 MachineBasicBlock::iterator I,
658 unsigned DestReg, unsigned SrcReg,
659 const TargetRegisterClass *DestRC,
660 const TargetRegisterClass *SrcRC,
662 // tGPR is used sometimes in ARM instructions that need to avoid using
663 // certain registers. Just treat it as GPR here.
664 if (DestRC == ARM::tGPRRegisterClass)
665 DestRC = ARM::GPRRegisterClass;
666 if (SrcRC == ARM::tGPRRegisterClass)
667 SrcRC = ARM::GPRRegisterClass;
669 // Allow DPR / DPR_VFP2 / DPR_8 cross-class copies.
670 if (DestRC == ARM::DPR_8RegisterClass)
671 DestRC = ARM::DPR_VFP2RegisterClass;
672 if (SrcRC == ARM::DPR_8RegisterClass)
673 SrcRC = ARM::DPR_VFP2RegisterClass;
675 // Allow QPR / QPR_VFP2 / QPR_8 cross-class copies.
676 if (DestRC == ARM::QPR_VFP2RegisterClass ||
677 DestRC == ARM::QPR_8RegisterClass)
678 DestRC = ARM::QPRRegisterClass;
679 if (SrcRC == ARM::QPR_VFP2RegisterClass ||
680 SrcRC == ARM::QPR_8RegisterClass)
681 SrcRC = ARM::QPRRegisterClass;
683 // Allow QQPR / QQPR_VFP2 / QQPR_8 cross-class copies.
684 if (DestRC == ARM::QQPR_VFP2RegisterClass ||
685 DestRC == ARM::QQPR_8RegisterClass)
686 DestRC = ARM::QQPRRegisterClass;
687 if (SrcRC == ARM::QQPR_VFP2RegisterClass ||
688 SrcRC == ARM::QQPR_8RegisterClass)
689 SrcRC = ARM::QQPRRegisterClass;
691 // Disallow copies of unequal sizes.
692 if (DestRC != SrcRC && DestRC->getSize() != SrcRC->getSize())
695 if (DestRC == ARM::GPRRegisterClass) {
696 if (SrcRC == ARM::SPRRegisterClass)
697 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VMOVRS), DestReg)
700 AddDefaultCC(AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::MOVr),
701 DestReg).addReg(SrcReg)));
705 if (DestRC == ARM::SPRRegisterClass)
706 Opc = (SrcRC == ARM::GPRRegisterClass ? ARM::VMOVSR : ARM::VMOVS);
707 else if (DestRC == ARM::DPRRegisterClass)
709 else if (DestRC == ARM::DPR_VFP2RegisterClass ||
710 SrcRC == ARM::DPR_VFP2RegisterClass)
711 // Always use neon reg-reg move if source or dest is NEON-only regclass.
712 Opc = ARM::VMOVDneon;
713 else if (DestRC == ARM::QPRRegisterClass)
715 else if (DestRC == ARM::QQPRRegisterClass)
720 AddDefaultPred(BuildMI(MBB, I, DL, get(Opc), DestReg).addReg(SrcReg));
727 MachineInstrBuilder &AddDReg(MachineInstrBuilder &MIB,
728 unsigned Reg, unsigned SubIdx, unsigned State,
729 const TargetRegisterInfo *TRI) {
731 return MIB.addReg(Reg, State);
733 if (TargetRegisterInfo::isPhysicalRegister(Reg))
734 return MIB.addReg(TRI->getSubReg(Reg, SubIdx), State);
735 return MIB.addReg(Reg, State, SubIdx);
738 void ARMBaseInstrInfo::
739 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
740 unsigned SrcReg, bool isKill, int FI,
741 const TargetRegisterClass *RC,
742 const TargetRegisterInfo *TRI) const {
744 if (I != MBB.end()) DL = I->getDebugLoc();
745 MachineFunction &MF = *MBB.getParent();
746 MachineFrameInfo &MFI = *MF.getFrameInfo();
747 unsigned Align = MFI.getObjectAlignment(FI);
749 MachineMemOperand *MMO =
750 MF.getMachineMemOperand(PseudoSourceValue::getFixedStack(FI),
751 MachineMemOperand::MOStore, 0,
752 MFI.getObjectSize(FI),
755 // tGPR is used sometimes in ARM instructions that need to avoid using
756 // certain registers. Just treat it as GPR here.
757 if (RC == ARM::tGPRRegisterClass)
758 RC = ARM::GPRRegisterClass;
760 if (RC == ARM::GPRRegisterClass) {
761 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::STR))
762 .addReg(SrcReg, getKillRegState(isKill))
763 .addFrameIndex(FI).addReg(0).addImm(0).addMemOperand(MMO));
764 } else if (RC == ARM::SPRRegisterClass) {
765 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTRS))
766 .addReg(SrcReg, getKillRegState(isKill))
767 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
768 } else if (RC == ARM::DPRRegisterClass ||
769 RC == ARM::DPR_VFP2RegisterClass ||
770 RC == ARM::DPR_8RegisterClass) {
771 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTRD))
772 .addReg(SrcReg, getKillRegState(isKill))
773 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
774 } else if (RC == ARM::QPRRegisterClass ||
775 RC == ARM::QPR_VFP2RegisterClass ||
776 RC == ARM::QPR_8RegisterClass) {
777 // FIXME: Neon instructions should support predicates
778 if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) {
779 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VST1q))
780 .addFrameIndex(FI).addImm(128)
781 .addReg(SrcReg, getKillRegState(isKill))
782 .addMemOperand(MMO));
784 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTMQ))
785 .addReg(SrcReg, getKillRegState(isKill))
787 .addImm(ARM_AM::getAM5Opc(ARM_AM::ia, 4))
788 .addMemOperand(MMO));
791 assert((RC == ARM::QQPRRegisterClass ||
792 RC == ARM::QQPR_VFP2RegisterClass ||
793 RC == ARM::QQPR_8RegisterClass) && "Unknown regclass!");
794 if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) {
795 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(ARM::VST2q32))
796 .addFrameIndex(FI).addImm(128);
797 MIB = AddDReg(MIB, SrcReg, ARM::DSUBREG_0, getKillRegState(isKill), TRI);
798 MIB = AddDReg(MIB, SrcReg, ARM::DSUBREG_1, 0, TRI);
799 MIB = AddDReg(MIB, SrcReg, ARM::DSUBREG_2, 0, TRI);
800 MIB = AddDReg(MIB, SrcReg, ARM::DSUBREG_3, 0, TRI);
801 AddDefaultPred(MIB.addMemOperand(MMO));
803 MachineInstrBuilder MIB =
804 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTMD))
806 .addImm(ARM_AM::getAM5Opc(ARM_AM::ia, 4)))
808 MIB = AddDReg(MIB, SrcReg, ARM::DSUBREG_0, getKillRegState(isKill), TRI);
809 MIB = AddDReg(MIB, SrcReg, ARM::DSUBREG_1, 0, TRI);
810 MIB = AddDReg(MIB, SrcReg, ARM::DSUBREG_2, 0, TRI);
811 AddDReg(MIB, SrcReg, ARM::DSUBREG_3, 0, TRI);
816 void ARMBaseInstrInfo::
817 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
818 unsigned DestReg, int FI,
819 const TargetRegisterClass *RC,
820 const TargetRegisterInfo *TRI) const {
822 if (I != MBB.end()) DL = I->getDebugLoc();
823 MachineFunction &MF = *MBB.getParent();
824 MachineFrameInfo &MFI = *MF.getFrameInfo();
825 unsigned Align = MFI.getObjectAlignment(FI);
826 MachineMemOperand *MMO =
827 MF.getMachineMemOperand(PseudoSourceValue::getFixedStack(FI),
828 MachineMemOperand::MOLoad, 0,
829 MFI.getObjectSize(FI),
832 // tGPR is used sometimes in ARM instructions that need to avoid using
833 // certain registers. Just treat it as GPR here.
834 if (RC == ARM::tGPRRegisterClass)
835 RC = ARM::GPRRegisterClass;
837 if (RC == ARM::GPRRegisterClass) {
838 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::LDR), DestReg)
839 .addFrameIndex(FI).addReg(0).addImm(0).addMemOperand(MMO));
840 } else if (RC == ARM::SPRRegisterClass) {
841 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDRS), DestReg)
842 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
843 } else if (RC == ARM::DPRRegisterClass ||
844 RC == ARM::DPR_VFP2RegisterClass ||
845 RC == ARM::DPR_8RegisterClass) {
846 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDRD), DestReg)
847 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
848 } else if (RC == ARM::QPRRegisterClass ||
849 RC == ARM::QPR_VFP2RegisterClass ||
850 RC == ARM::QPR_8RegisterClass) {
851 if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) {
852 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLD1q), DestReg)
853 .addFrameIndex(FI).addImm(128)
854 .addMemOperand(MMO));
856 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDMQ), DestReg)
858 .addImm(ARM_AM::getAM5Opc(ARM_AM::ia, 4))
859 .addMemOperand(MMO));
862 assert((RC == ARM::QQPRRegisterClass ||
863 RC == ARM::QQPR_VFP2RegisterClass ||
864 RC == ARM::QQPR_8RegisterClass) && "Unknown regclass!");
865 if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) {
866 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(ARM::VLD2q32));
867 MIB = AddDReg(MIB, DestReg, ARM::DSUBREG_0, RegState::Define, TRI);
868 MIB = AddDReg(MIB, DestReg, ARM::DSUBREG_1, RegState::Define, TRI);
869 MIB = AddDReg(MIB, DestReg, ARM::DSUBREG_2, RegState::Define, TRI);
870 MIB = AddDReg(MIB, DestReg, ARM::DSUBREG_3, RegState::Define, TRI);
871 AddDefaultPred(MIB.addFrameIndex(FI).addImm(128).addMemOperand(MMO));
873 MachineInstrBuilder MIB =
874 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDMD))
876 .addImm(ARM_AM::getAM5Opc(ARM_AM::ia, 4)))
878 MIB = AddDReg(MIB, DestReg, ARM::DSUBREG_0, RegState::Define, TRI);
879 MIB = AddDReg(MIB, DestReg, ARM::DSUBREG_1, RegState::Define, TRI);
880 MIB = AddDReg(MIB, DestReg, ARM::DSUBREG_2, RegState::Define, TRI);
881 AddDReg(MIB, DestReg, ARM::DSUBREG_3, RegState::Define, TRI);
887 ARMBaseInstrInfo::emitFrameIndexDebugValue(MachineFunction &MF,
888 int FrameIx, uint64_t Offset,
891 MachineInstrBuilder MIB = BuildMI(MF, DL, get(ARM::DBG_VALUE))
892 .addFrameIndex(FrameIx).addImm(0).addImm(Offset).addMetadata(MDPtr);
896 MachineInstr *ARMBaseInstrInfo::
897 foldMemoryOperandImpl(MachineFunction &MF, MachineInstr *MI,
898 const SmallVectorImpl<unsigned> &Ops, int FI) const {
899 if (Ops.size() != 1) return NULL;
901 unsigned OpNum = Ops[0];
902 unsigned Opc = MI->getOpcode();
903 MachineInstr *NewMI = NULL;
904 if (Opc == ARM::MOVr || Opc == ARM::t2MOVr) {
905 // If it is updating CPSR, then it cannot be folded.
906 if (MI->getOperand(4).getReg() == ARM::CPSR && !MI->getOperand(4).isDead())
908 unsigned Pred = MI->getOperand(2).getImm();
909 unsigned PredReg = MI->getOperand(3).getReg();
910 if (OpNum == 0) { // move -> store
911 unsigned SrcReg = MI->getOperand(1).getReg();
912 unsigned SrcSubReg = MI->getOperand(1).getSubReg();
913 bool isKill = MI->getOperand(1).isKill();
914 bool isUndef = MI->getOperand(1).isUndef();
915 if (Opc == ARM::MOVr)
916 NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::STR))
918 getKillRegState(isKill) | getUndefRegState(isUndef),
920 .addFrameIndex(FI).addReg(0).addImm(0).addImm(Pred).addReg(PredReg);
922 NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::t2STRi12))
924 getKillRegState(isKill) | getUndefRegState(isUndef),
926 .addFrameIndex(FI).addImm(0).addImm(Pred).addReg(PredReg);
927 } else { // move -> load
928 unsigned DstReg = MI->getOperand(0).getReg();
929 unsigned DstSubReg = MI->getOperand(0).getSubReg();
930 bool isDead = MI->getOperand(0).isDead();
931 bool isUndef = MI->getOperand(0).isUndef();
932 if (Opc == ARM::MOVr)
933 NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::LDR))
936 getDeadRegState(isDead) |
937 getUndefRegState(isUndef), DstSubReg)
938 .addFrameIndex(FI).addReg(0).addImm(0).addImm(Pred).addReg(PredReg);
940 NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::t2LDRi12))
943 getDeadRegState(isDead) |
944 getUndefRegState(isUndef), DstSubReg)
945 .addFrameIndex(FI).addImm(0).addImm(Pred).addReg(PredReg);
947 } else if (Opc == ARM::tMOVgpr2gpr ||
948 Opc == ARM::tMOVtgpr2gpr ||
949 Opc == ARM::tMOVgpr2tgpr) {
950 if (OpNum == 0) { // move -> store
951 unsigned SrcReg = MI->getOperand(1).getReg();
952 unsigned SrcSubReg = MI->getOperand(1).getSubReg();
953 bool isKill = MI->getOperand(1).isKill();
954 bool isUndef = MI->getOperand(1).isUndef();
955 NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::t2STRi12))
957 getKillRegState(isKill) | getUndefRegState(isUndef),
959 .addFrameIndex(FI).addImm(0).addImm(ARMCC::AL).addReg(0);
960 } else { // move -> load
961 unsigned DstReg = MI->getOperand(0).getReg();
962 unsigned DstSubReg = MI->getOperand(0).getSubReg();
963 bool isDead = MI->getOperand(0).isDead();
964 bool isUndef = MI->getOperand(0).isUndef();
965 NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::t2LDRi12))
968 getDeadRegState(isDead) |
969 getUndefRegState(isUndef),
971 .addFrameIndex(FI).addImm(0).addImm(ARMCC::AL).addReg(0);
973 } else if (Opc == ARM::VMOVS) {
974 unsigned Pred = MI->getOperand(2).getImm();
975 unsigned PredReg = MI->getOperand(3).getReg();
976 if (OpNum == 0) { // move -> store
977 unsigned SrcReg = MI->getOperand(1).getReg();
978 unsigned SrcSubReg = MI->getOperand(1).getSubReg();
979 bool isKill = MI->getOperand(1).isKill();
980 bool isUndef = MI->getOperand(1).isUndef();
981 NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::VSTRS))
982 .addReg(SrcReg, getKillRegState(isKill) | getUndefRegState(isUndef),
985 .addImm(0).addImm(Pred).addReg(PredReg);
986 } else { // move -> load
987 unsigned DstReg = MI->getOperand(0).getReg();
988 unsigned DstSubReg = MI->getOperand(0).getSubReg();
989 bool isDead = MI->getOperand(0).isDead();
990 bool isUndef = MI->getOperand(0).isUndef();
991 NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::VLDRS))
994 getDeadRegState(isDead) |
995 getUndefRegState(isUndef),
997 .addFrameIndex(FI).addImm(0).addImm(Pred).addReg(PredReg);
999 } else if (Opc == ARM::VMOVD || Opc == ARM::VMOVDneon) {
1000 unsigned Pred = MI->getOperand(2).getImm();
1001 unsigned PredReg = MI->getOperand(3).getReg();
1002 if (OpNum == 0) { // move -> store
1003 unsigned SrcReg = MI->getOperand(1).getReg();
1004 unsigned SrcSubReg = MI->getOperand(1).getSubReg();
1005 bool isKill = MI->getOperand(1).isKill();
1006 bool isUndef = MI->getOperand(1).isUndef();
1007 NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::VSTRD))
1009 getKillRegState(isKill) | getUndefRegState(isUndef),
1011 .addFrameIndex(FI).addImm(0).addImm(Pred).addReg(PredReg);
1012 } else { // move -> load
1013 unsigned DstReg = MI->getOperand(0).getReg();
1014 unsigned DstSubReg = MI->getOperand(0).getSubReg();
1015 bool isDead = MI->getOperand(0).isDead();
1016 bool isUndef = MI->getOperand(0).isUndef();
1017 NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::VLDRD))
1020 getDeadRegState(isDead) |
1021 getUndefRegState(isUndef),
1023 .addFrameIndex(FI).addImm(0).addImm(Pred).addReg(PredReg);
1025 } else if (Opc == ARM::VMOVQ) {
1026 MachineFrameInfo &MFI = *MF.getFrameInfo();
1027 unsigned Pred = MI->getOperand(2).getImm();
1028 unsigned PredReg = MI->getOperand(3).getReg();
1029 if (OpNum == 0) { // move -> store
1030 unsigned SrcReg = MI->getOperand(1).getReg();
1031 unsigned SrcSubReg = MI->getOperand(1).getSubReg();
1032 bool isKill = MI->getOperand(1).isKill();
1033 bool isUndef = MI->getOperand(1).isUndef();
1034 if (MFI.getObjectAlignment(FI) >= 16 &&
1035 getRegisterInfo().canRealignStack(MF)) {
1036 NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::VST1q))
1037 .addFrameIndex(FI).addImm(128)
1039 getKillRegState(isKill) | getUndefRegState(isUndef),
1041 .addImm(Pred).addReg(PredReg);
1043 NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::VSTMQ))
1045 getKillRegState(isKill) | getUndefRegState(isUndef),
1047 .addFrameIndex(FI).addImm(ARM_AM::getAM5Opc(ARM_AM::ia, 4))
1048 .addImm(Pred).addReg(PredReg);
1050 } else { // move -> load
1051 unsigned DstReg = MI->getOperand(0).getReg();
1052 unsigned DstSubReg = MI->getOperand(0).getSubReg();
1053 bool isDead = MI->getOperand(0).isDead();
1054 bool isUndef = MI->getOperand(0).isUndef();
1055 if (MFI.getObjectAlignment(FI) >= 16 &&
1056 getRegisterInfo().canRealignStack(MF)) {
1057 NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::VLD1q))
1060 getDeadRegState(isDead) |
1061 getUndefRegState(isUndef),
1063 .addFrameIndex(FI).addImm(128).addImm(Pred).addReg(PredReg);
1065 NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::VLDMQ))
1068 getDeadRegState(isDead) |
1069 getUndefRegState(isUndef),
1071 .addFrameIndex(FI).addImm(ARM_AM::getAM5Opc(ARM_AM::ia, 4))
1072 .addImm(Pred).addReg(PredReg);
1081 ARMBaseInstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
1083 const SmallVectorImpl<unsigned> &Ops,
1084 MachineInstr* LoadMI) const {
1090 ARMBaseInstrInfo::canFoldMemoryOperand(const MachineInstr *MI,
1091 const SmallVectorImpl<unsigned> &Ops) const {
1092 if (Ops.size() != 1) return false;
1094 unsigned Opc = MI->getOpcode();
1095 if (Opc == ARM::MOVr || Opc == ARM::t2MOVr) {
1096 // If it is updating CPSR, then it cannot be folded.
1097 return MI->getOperand(4).getReg() != ARM::CPSR ||
1098 MI->getOperand(4).isDead();
1099 } else if (Opc == ARM::tMOVgpr2gpr ||
1100 Opc == ARM::tMOVtgpr2gpr ||
1101 Opc == ARM::tMOVgpr2tgpr) {
1103 } else if (Opc == ARM::VMOVS || Opc == ARM::VMOVD ||
1104 Opc == ARM::VMOVDneon || Opc == ARM::VMOVQ) {
1111 /// Create a copy of a const pool value. Update CPI to the new index and return
1113 static unsigned duplicateCPV(MachineFunction &MF, unsigned &CPI) {
1114 MachineConstantPool *MCP = MF.getConstantPool();
1115 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1117 const MachineConstantPoolEntry &MCPE = MCP->getConstants()[CPI];
1118 assert(MCPE.isMachineConstantPoolEntry() &&
1119 "Expecting a machine constantpool entry!");
1120 ARMConstantPoolValue *ACPV =
1121 static_cast<ARMConstantPoolValue*>(MCPE.Val.MachineCPVal);
1123 unsigned PCLabelId = AFI->createConstPoolEntryUId();
1124 ARMConstantPoolValue *NewCPV = 0;
1125 if (ACPV->isGlobalValue())
1126 NewCPV = new ARMConstantPoolValue(ACPV->getGV(), PCLabelId,
1128 else if (ACPV->isExtSymbol())
1129 NewCPV = new ARMConstantPoolValue(MF.getFunction()->getContext(),
1130 ACPV->getSymbol(), PCLabelId, 4);
1131 else if (ACPV->isBlockAddress())
1132 NewCPV = new ARMConstantPoolValue(ACPV->getBlockAddress(), PCLabelId,
1133 ARMCP::CPBlockAddress, 4);
1135 llvm_unreachable("Unexpected ARM constantpool value type!!");
1136 CPI = MCP->getConstantPoolIndex(NewCPV, MCPE.getAlignment());
1140 void ARMBaseInstrInfo::
1141 reMaterialize(MachineBasicBlock &MBB,
1142 MachineBasicBlock::iterator I,
1143 unsigned DestReg, unsigned SubIdx,
1144 const MachineInstr *Orig,
1145 const TargetRegisterInfo *TRI) const {
1146 if (SubIdx && TargetRegisterInfo::isPhysicalRegister(DestReg)) {
1147 DestReg = TRI->getSubReg(DestReg, SubIdx);
1151 unsigned Opcode = Orig->getOpcode();
1154 MachineInstr *MI = MBB.getParent()->CloneMachineInstr(Orig);
1155 MI->getOperand(0).setReg(DestReg);
1159 case ARM::tLDRpci_pic:
1160 case ARM::t2LDRpci_pic: {
1161 MachineFunction &MF = *MBB.getParent();
1162 unsigned CPI = Orig->getOperand(1).getIndex();
1163 unsigned PCLabelId = duplicateCPV(MF, CPI);
1164 MachineInstrBuilder MIB = BuildMI(MBB, I, Orig->getDebugLoc(), get(Opcode),
1166 .addConstantPoolIndex(CPI).addImm(PCLabelId);
1167 (*MIB).setMemRefs(Orig->memoperands_begin(), Orig->memoperands_end());
1172 MachineInstr *NewMI = prior(I);
1173 NewMI->getOperand(0).setSubReg(SubIdx);
1177 ARMBaseInstrInfo::duplicate(MachineInstr *Orig, MachineFunction &MF) const {
1178 MachineInstr *MI = TargetInstrInfoImpl::duplicate(Orig, MF);
1179 switch(Orig->getOpcode()) {
1180 case ARM::tLDRpci_pic:
1181 case ARM::t2LDRpci_pic: {
1182 unsigned CPI = Orig->getOperand(1).getIndex();
1183 unsigned PCLabelId = duplicateCPV(MF, CPI);
1184 Orig->getOperand(1).setIndex(CPI);
1185 Orig->getOperand(2).setImm(PCLabelId);
1192 bool ARMBaseInstrInfo::produceSameValue(const MachineInstr *MI0,
1193 const MachineInstr *MI1) const {
1194 int Opcode = MI0->getOpcode();
1195 if (Opcode == ARM::t2LDRpci ||
1196 Opcode == ARM::t2LDRpci_pic ||
1197 Opcode == ARM::tLDRpci ||
1198 Opcode == ARM::tLDRpci_pic) {
1199 if (MI1->getOpcode() != Opcode)
1201 if (MI0->getNumOperands() != MI1->getNumOperands())
1204 const MachineOperand &MO0 = MI0->getOperand(1);
1205 const MachineOperand &MO1 = MI1->getOperand(1);
1206 if (MO0.getOffset() != MO1.getOffset())
1209 const MachineFunction *MF = MI0->getParent()->getParent();
1210 const MachineConstantPool *MCP = MF->getConstantPool();
1211 int CPI0 = MO0.getIndex();
1212 int CPI1 = MO1.getIndex();
1213 const MachineConstantPoolEntry &MCPE0 = MCP->getConstants()[CPI0];
1214 const MachineConstantPoolEntry &MCPE1 = MCP->getConstants()[CPI1];
1215 ARMConstantPoolValue *ACPV0 =
1216 static_cast<ARMConstantPoolValue*>(MCPE0.Val.MachineCPVal);
1217 ARMConstantPoolValue *ACPV1 =
1218 static_cast<ARMConstantPoolValue*>(MCPE1.Val.MachineCPVal);
1219 return ACPV0->hasSameValue(ACPV1);
1222 return MI0->isIdenticalTo(MI1, MachineInstr::IgnoreVRegDefs);
1225 /// getInstrPredicate - If instruction is predicated, returns its predicate
1226 /// condition, otherwise returns AL. It also returns the condition code
1227 /// register by reference.
1229 llvm::getInstrPredicate(const MachineInstr *MI, unsigned &PredReg) {
1230 int PIdx = MI->findFirstPredOperandIdx();
1236 PredReg = MI->getOperand(PIdx+1).getReg();
1237 return (ARMCC::CondCodes)MI->getOperand(PIdx).getImm();
1241 int llvm::getMatchingCondBranchOpcode(int Opc) {
1244 else if (Opc == ARM::tB)
1246 else if (Opc == ARM::t2B)
1249 llvm_unreachable("Unknown unconditional branch opcode!");
1254 void llvm::emitARMRegPlusImmediate(MachineBasicBlock &MBB,
1255 MachineBasicBlock::iterator &MBBI, DebugLoc dl,
1256 unsigned DestReg, unsigned BaseReg, int NumBytes,
1257 ARMCC::CondCodes Pred, unsigned PredReg,
1258 const ARMBaseInstrInfo &TII) {
1259 bool isSub = NumBytes < 0;
1260 if (isSub) NumBytes = -NumBytes;
1263 unsigned RotAmt = ARM_AM::getSOImmValRotate(NumBytes);
1264 unsigned ThisVal = NumBytes & ARM_AM::rotr32(0xFF, RotAmt);
1265 assert(ThisVal && "Didn't extract field correctly");
1267 // We will handle these bits from offset, clear them.
1268 NumBytes &= ~ThisVal;
1270 assert(ARM_AM::getSOImmVal(ThisVal) != -1 && "Bit extraction didn't work?");
1272 // Build the new ADD / SUB.
1273 unsigned Opc = isSub ? ARM::SUBri : ARM::ADDri;
1274 BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg)
1275 .addReg(BaseReg, RegState::Kill).addImm(ThisVal)
1276 .addImm((unsigned)Pred).addReg(PredReg).addReg(0);
1281 bool llvm::rewriteARMFrameIndex(MachineInstr &MI, unsigned FrameRegIdx,
1282 unsigned FrameReg, int &Offset,
1283 const ARMBaseInstrInfo &TII) {
1284 unsigned Opcode = MI.getOpcode();
1285 const TargetInstrDesc &Desc = MI.getDesc();
1286 unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
1289 // Memory operands in inline assembly always use AddrMode2.
1290 if (Opcode == ARM::INLINEASM)
1291 AddrMode = ARMII::AddrMode2;
1293 if (Opcode == ARM::ADDri) {
1294 Offset += MI.getOperand(FrameRegIdx+1).getImm();
1296 // Turn it into a move.
1297 MI.setDesc(TII.get(ARM::MOVr));
1298 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
1299 MI.RemoveOperand(FrameRegIdx+1);
1302 } else if (Offset < 0) {
1305 MI.setDesc(TII.get(ARM::SUBri));
1308 // Common case: small offset, fits into instruction.
1309 if (ARM_AM::getSOImmVal(Offset) != -1) {
1310 // Replace the FrameIndex with sp / fp
1311 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
1312 MI.getOperand(FrameRegIdx+1).ChangeToImmediate(Offset);
1317 // Otherwise, pull as much of the immedidate into this ADDri/SUBri
1319 unsigned RotAmt = ARM_AM::getSOImmValRotate(Offset);
1320 unsigned ThisImmVal = Offset & ARM_AM::rotr32(0xFF, RotAmt);
1322 // We will handle these bits from offset, clear them.
1323 Offset &= ~ThisImmVal;
1325 // Get the properly encoded SOImmVal field.
1326 assert(ARM_AM::getSOImmVal(ThisImmVal) != -1 &&
1327 "Bit extraction didn't work?");
1328 MI.getOperand(FrameRegIdx+1).ChangeToImmediate(ThisImmVal);
1330 unsigned ImmIdx = 0;
1332 unsigned NumBits = 0;
1335 case ARMII::AddrMode2: {
1336 ImmIdx = FrameRegIdx+2;
1337 InstrOffs = ARM_AM::getAM2Offset(MI.getOperand(ImmIdx).getImm());
1338 if (ARM_AM::getAM2Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub)
1343 case ARMII::AddrMode3: {
1344 ImmIdx = FrameRegIdx+2;
1345 InstrOffs = ARM_AM::getAM3Offset(MI.getOperand(ImmIdx).getImm());
1346 if (ARM_AM::getAM3Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub)
1351 case ARMII::AddrMode4:
1352 case ARMII::AddrMode6:
1353 // Can't fold any offset even if it's zero.
1355 case ARMII::AddrMode5: {
1356 ImmIdx = FrameRegIdx+1;
1357 InstrOffs = ARM_AM::getAM5Offset(MI.getOperand(ImmIdx).getImm());
1358 if (ARM_AM::getAM5Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub)
1365 llvm_unreachable("Unsupported addressing mode!");
1369 Offset += InstrOffs * Scale;
1370 assert((Offset & (Scale-1)) == 0 && "Can't encode this offset!");
1376 // Attempt to fold address comp. if opcode has offset bits
1378 // Common case: small offset, fits into instruction.
1379 MachineOperand &ImmOp = MI.getOperand(ImmIdx);
1380 int ImmedOffset = Offset / Scale;
1381 unsigned Mask = (1 << NumBits) - 1;
1382 if ((unsigned)Offset <= Mask * Scale) {
1383 // Replace the FrameIndex with sp
1384 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
1386 ImmedOffset |= 1 << NumBits;
1387 ImmOp.ChangeToImmediate(ImmedOffset);
1392 // Otherwise, it didn't fit. Pull in what we can to simplify the immed.
1393 ImmedOffset = ImmedOffset & Mask;
1395 ImmedOffset |= 1 << NumBits;
1396 ImmOp.ChangeToImmediate(ImmedOffset);
1397 Offset &= ~(Mask*Scale);
1401 Offset = (isSub) ? -Offset : Offset;