1 //===- ARMBaseInstrInfo.cpp - ARM Instruction Information -------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Base ARM implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "ARMBaseInstrInfo.h"
16 #include "ARMAddressingModes.h"
17 #include "ARMConstantPoolValue.h"
18 #include "ARMGenInstrInfo.inc"
19 #include "ARMMachineFunctionInfo.h"
20 #include "ARMRegisterInfo.h"
21 #include "llvm/Constants.h"
22 #include "llvm/Function.h"
23 #include "llvm/GlobalValue.h"
24 #include "llvm/ADT/STLExtras.h"
25 #include "llvm/CodeGen/LiveVariables.h"
26 #include "llvm/CodeGen/MachineConstantPool.h"
27 #include "llvm/CodeGen/MachineFrameInfo.h"
28 #include "llvm/CodeGen/MachineInstrBuilder.h"
29 #include "llvm/CodeGen/MachineJumpTableInfo.h"
30 #include "llvm/CodeGen/MachineMemOperand.h"
31 #include "llvm/CodeGen/PseudoSourceValue.h"
32 #include "llvm/MC/MCAsmInfo.h"
33 #include "llvm/Support/CommandLine.h"
34 #include "llvm/Support/Debug.h"
35 #include "llvm/Support/ErrorHandling.h"
39 EnableARM3Addr("enable-arm-3-addr-conv", cl::Hidden,
40 cl::desc("Enable ARM 2-addr to 3-addr conv"));
42 ARMBaseInstrInfo::ARMBaseInstrInfo(const ARMSubtarget& STI)
43 : TargetInstrInfoImpl(ARMInsts, array_lengthof(ARMInsts)),
48 ARMBaseInstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
49 MachineBasicBlock::iterator &MBBI,
50 LiveVariables *LV) const {
51 // FIXME: Thumb2 support.
56 MachineInstr *MI = MBBI;
57 MachineFunction &MF = *MI->getParent()->getParent();
58 unsigned TSFlags = MI->getDesc().TSFlags;
60 switch ((TSFlags & ARMII::IndexModeMask) >> ARMII::IndexModeShift) {
62 case ARMII::IndexModePre:
65 case ARMII::IndexModePost:
69 // Try splitting an indexed load/store to an un-indexed one plus an add/sub
71 unsigned MemOpc = getUnindexedOpcode(MI->getOpcode());
75 MachineInstr *UpdateMI = NULL;
76 MachineInstr *MemMI = NULL;
77 unsigned AddrMode = (TSFlags & ARMII::AddrModeMask);
78 const TargetInstrDesc &TID = MI->getDesc();
79 unsigned NumOps = TID.getNumOperands();
80 bool isLoad = !TID.mayStore();
81 const MachineOperand &WB = isLoad ? MI->getOperand(1) : MI->getOperand(0);
82 const MachineOperand &Base = MI->getOperand(2);
83 const MachineOperand &Offset = MI->getOperand(NumOps-3);
84 unsigned WBReg = WB.getReg();
85 unsigned BaseReg = Base.getReg();
86 unsigned OffReg = Offset.getReg();
87 unsigned OffImm = MI->getOperand(NumOps-2).getImm();
88 ARMCC::CondCodes Pred = (ARMCC::CondCodes)MI->getOperand(NumOps-1).getImm();
91 assert(false && "Unknown indexed op!");
93 case ARMII::AddrMode2: {
94 bool isSub = ARM_AM::getAM2Op(OffImm) == ARM_AM::sub;
95 unsigned Amt = ARM_AM::getAM2Offset(OffImm);
97 if (ARM_AM::getSOImmVal(Amt) == -1)
98 // Can't encode it in a so_imm operand. This transformation will
99 // add more than 1 instruction. Abandon!
101 UpdateMI = BuildMI(MF, MI->getDebugLoc(),
102 get(isSub ? ARM::SUBri : ARM::ADDri), WBReg)
103 .addReg(BaseReg).addImm(Amt)
104 .addImm(Pred).addReg(0).addReg(0);
105 } else if (Amt != 0) {
106 ARM_AM::ShiftOpc ShOpc = ARM_AM::getAM2ShiftOpc(OffImm);
107 unsigned SOOpc = ARM_AM::getSORegOpc(ShOpc, Amt);
108 UpdateMI = BuildMI(MF, MI->getDebugLoc(),
109 get(isSub ? ARM::SUBrs : ARM::ADDrs), WBReg)
110 .addReg(BaseReg).addReg(OffReg).addReg(0).addImm(SOOpc)
111 .addImm(Pred).addReg(0).addReg(0);
113 UpdateMI = BuildMI(MF, MI->getDebugLoc(),
114 get(isSub ? ARM::SUBrr : ARM::ADDrr), WBReg)
115 .addReg(BaseReg).addReg(OffReg)
116 .addImm(Pred).addReg(0).addReg(0);
119 case ARMII::AddrMode3 : {
120 bool isSub = ARM_AM::getAM3Op(OffImm) == ARM_AM::sub;
121 unsigned Amt = ARM_AM::getAM3Offset(OffImm);
123 // Immediate is 8-bits. It's guaranteed to fit in a so_imm operand.
124 UpdateMI = BuildMI(MF, MI->getDebugLoc(),
125 get(isSub ? ARM::SUBri : ARM::ADDri), WBReg)
126 .addReg(BaseReg).addImm(Amt)
127 .addImm(Pred).addReg(0).addReg(0);
129 UpdateMI = BuildMI(MF, MI->getDebugLoc(),
130 get(isSub ? ARM::SUBrr : ARM::ADDrr), WBReg)
131 .addReg(BaseReg).addReg(OffReg)
132 .addImm(Pred).addReg(0).addReg(0);
137 std::vector<MachineInstr*> NewMIs;
140 MemMI = BuildMI(MF, MI->getDebugLoc(),
141 get(MemOpc), MI->getOperand(0).getReg())
142 .addReg(WBReg).addReg(0).addImm(0).addImm(Pred);
144 MemMI = BuildMI(MF, MI->getDebugLoc(),
145 get(MemOpc)).addReg(MI->getOperand(1).getReg())
146 .addReg(WBReg).addReg(0).addImm(0).addImm(Pred);
147 NewMIs.push_back(MemMI);
148 NewMIs.push_back(UpdateMI);
151 MemMI = BuildMI(MF, MI->getDebugLoc(),
152 get(MemOpc), MI->getOperand(0).getReg())
153 .addReg(BaseReg).addReg(0).addImm(0).addImm(Pred);
155 MemMI = BuildMI(MF, MI->getDebugLoc(),
156 get(MemOpc)).addReg(MI->getOperand(1).getReg())
157 .addReg(BaseReg).addReg(0).addImm(0).addImm(Pred);
159 UpdateMI->getOperand(0).setIsDead();
160 NewMIs.push_back(UpdateMI);
161 NewMIs.push_back(MemMI);
164 // Transfer LiveVariables states, kill / dead info.
166 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
167 MachineOperand &MO = MI->getOperand(i);
168 if (MO.isReg() && MO.getReg() &&
169 TargetRegisterInfo::isVirtualRegister(MO.getReg())) {
170 unsigned Reg = MO.getReg();
172 LiveVariables::VarInfo &VI = LV->getVarInfo(Reg);
174 MachineInstr *NewMI = (Reg == WBReg) ? UpdateMI : MemMI;
176 LV->addVirtualRegisterDead(Reg, NewMI);
178 if (MO.isUse() && MO.isKill()) {
179 for (unsigned j = 0; j < 2; ++j) {
180 // Look at the two new MI's in reverse order.
181 MachineInstr *NewMI = NewMIs[j];
182 if (!NewMI->readsRegister(Reg))
184 LV->addVirtualRegisterKilled(Reg, NewMI);
185 if (VI.removeKill(MI))
186 VI.Kills.push_back(NewMI);
194 MFI->insert(MBBI, NewMIs[1]);
195 MFI->insert(MBBI, NewMIs[0]);
201 ARMBaseInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB,
202 MachineBasicBlock *&FBB,
203 SmallVectorImpl<MachineOperand> &Cond,
204 bool AllowModify) const {
205 // If the block has no terminators, it just falls into the block after it.
206 MachineBasicBlock::iterator I = MBB.end();
207 if (I == MBB.begin())
210 while (I->isDebugValue()) {
211 if (I == MBB.begin())
215 if (!isUnpredicatedTerminator(I))
218 // Get the last instruction in the block.
219 MachineInstr *LastInst = I;
221 // If there is only one terminator instruction, process it.
222 unsigned LastOpc = LastInst->getOpcode();
223 if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) {
224 if (isUncondBranchOpcode(LastOpc)) {
225 TBB = LastInst->getOperand(0).getMBB();
228 if (isCondBranchOpcode(LastOpc)) {
229 // Block ends with fall-through condbranch.
230 TBB = LastInst->getOperand(0).getMBB();
231 Cond.push_back(LastInst->getOperand(1));
232 Cond.push_back(LastInst->getOperand(2));
235 return true; // Can't handle indirect branch.
238 // Get the instruction before it if it is a terminator.
239 MachineInstr *SecondLastInst = I;
241 // If there are three terminators, we don't know what sort of block this is.
242 if (SecondLastInst && I != MBB.begin() && isUnpredicatedTerminator(--I))
245 // If the block ends with a B and a Bcc, handle it.
246 unsigned SecondLastOpc = SecondLastInst->getOpcode();
247 if (isCondBranchOpcode(SecondLastOpc) && isUncondBranchOpcode(LastOpc)) {
248 TBB = SecondLastInst->getOperand(0).getMBB();
249 Cond.push_back(SecondLastInst->getOperand(1));
250 Cond.push_back(SecondLastInst->getOperand(2));
251 FBB = LastInst->getOperand(0).getMBB();
255 // If the block ends with two unconditional branches, handle it. The second
256 // one is not executed, so remove it.
257 if (isUncondBranchOpcode(SecondLastOpc) && isUncondBranchOpcode(LastOpc)) {
258 TBB = SecondLastInst->getOperand(0).getMBB();
261 I->eraseFromParent();
265 // ...likewise if it ends with a branch table followed by an unconditional
266 // branch. The branch folder can create these, and we must get rid of them for
267 // correctness of Thumb constant islands.
268 if ((isJumpTableBranchOpcode(SecondLastOpc) ||
269 isIndirectBranchOpcode(SecondLastOpc)) &&
270 isUncondBranchOpcode(LastOpc)) {
273 I->eraseFromParent();
277 // Otherwise, can't handle this.
282 unsigned ARMBaseInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
283 MachineBasicBlock::iterator I = MBB.end();
284 if (I == MBB.begin()) return 0;
286 while (I->isDebugValue()) {
287 if (I == MBB.begin())
291 if (!isUncondBranchOpcode(I->getOpcode()) &&
292 !isCondBranchOpcode(I->getOpcode()))
295 // Remove the branch.
296 I->eraseFromParent();
300 if (I == MBB.begin()) return 1;
302 if (!isCondBranchOpcode(I->getOpcode()))
305 // Remove the branch.
306 I->eraseFromParent();
311 ARMBaseInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
312 MachineBasicBlock *FBB,
313 const SmallVectorImpl<MachineOperand> &Cond) const {
314 // FIXME this should probably have a DebugLoc argument
317 ARMFunctionInfo *AFI = MBB.getParent()->getInfo<ARMFunctionInfo>();
318 int BOpc = !AFI->isThumbFunction()
319 ? ARM::B : (AFI->isThumb2Function() ? ARM::t2B : ARM::tB);
320 int BccOpc = !AFI->isThumbFunction()
321 ? ARM::Bcc : (AFI->isThumb2Function() ? ARM::t2Bcc : ARM::tBcc);
323 // Shouldn't be a fall through.
324 assert(TBB && "InsertBranch must not be told to insert a fallthrough");
325 assert((Cond.size() == 2 || Cond.size() == 0) &&
326 "ARM branch conditions have two components!");
329 if (Cond.empty()) // Unconditional branch?
330 BuildMI(&MBB, dl, get(BOpc)).addMBB(TBB);
332 BuildMI(&MBB, dl, get(BccOpc)).addMBB(TBB)
333 .addImm(Cond[0].getImm()).addReg(Cond[1].getReg());
337 // Two-way conditional branch.
338 BuildMI(&MBB, dl, get(BccOpc)).addMBB(TBB)
339 .addImm(Cond[0].getImm()).addReg(Cond[1].getReg());
340 BuildMI(&MBB, dl, get(BOpc)).addMBB(FBB);
344 bool ARMBaseInstrInfo::
345 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
346 ARMCC::CondCodes CC = (ARMCC::CondCodes)(int)Cond[0].getImm();
347 Cond[0].setImm(ARMCC::getOppositeCondition(CC));
351 bool ARMBaseInstrInfo::
352 PredicateInstruction(MachineInstr *MI,
353 const SmallVectorImpl<MachineOperand> &Pred) const {
354 unsigned Opc = MI->getOpcode();
355 if (isUncondBranchOpcode(Opc)) {
356 MI->setDesc(get(getMatchingCondBranchOpcode(Opc)));
357 MI->addOperand(MachineOperand::CreateImm(Pred[0].getImm()));
358 MI->addOperand(MachineOperand::CreateReg(Pred[1].getReg(), false));
362 int PIdx = MI->findFirstPredOperandIdx();
364 MachineOperand &PMO = MI->getOperand(PIdx);
365 PMO.setImm(Pred[0].getImm());
366 MI->getOperand(PIdx+1).setReg(Pred[1].getReg());
372 bool ARMBaseInstrInfo::
373 SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1,
374 const SmallVectorImpl<MachineOperand> &Pred2) const {
375 if (Pred1.size() > 2 || Pred2.size() > 2)
378 ARMCC::CondCodes CC1 = (ARMCC::CondCodes)Pred1[0].getImm();
379 ARMCC::CondCodes CC2 = (ARMCC::CondCodes)Pred2[0].getImm();
389 return CC2 == ARMCC::HI;
391 return CC2 == ARMCC::LO || CC2 == ARMCC::EQ;
393 return CC2 == ARMCC::GT;
395 return CC2 == ARMCC::LT;
399 bool ARMBaseInstrInfo::DefinesPredicate(MachineInstr *MI,
400 std::vector<MachineOperand> &Pred) const {
401 // FIXME: This confuses implicit_def with optional CPSR def.
402 const TargetInstrDesc &TID = MI->getDesc();
403 if (!TID.getImplicitDefs() && !TID.hasOptionalDef())
407 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
408 const MachineOperand &MO = MI->getOperand(i);
409 if (MO.isReg() && MO.getReg() == ARM::CPSR) {
418 /// isPredicable - Return true if the specified instruction can be predicated.
419 /// By default, this returns true for every instruction with a
420 /// PredicateOperand.
421 bool ARMBaseInstrInfo::isPredicable(MachineInstr *MI) const {
422 const TargetInstrDesc &TID = MI->getDesc();
423 if (!TID.isPredicable())
426 if ((TID.TSFlags & ARMII::DomainMask) == ARMII::DomainNEON) {
427 ARMFunctionInfo *AFI =
428 MI->getParent()->getParent()->getInfo<ARMFunctionInfo>();
429 return AFI->isThumb2Function();
434 /// FIXME: Works around a gcc miscompilation with -fstrict-aliasing.
436 static unsigned getNumJTEntries(const std::vector<MachineJumpTableEntry> &JT,
438 static unsigned getNumJTEntries(const std::vector<MachineJumpTableEntry> &JT,
440 assert(JTI < JT.size());
441 return JT[JTI].MBBs.size();
444 /// GetInstSize - Return the size of the specified MachineInstr.
446 unsigned ARMBaseInstrInfo::GetInstSizeInBytes(const MachineInstr *MI) const {
447 const MachineBasicBlock &MBB = *MI->getParent();
448 const MachineFunction *MF = MBB.getParent();
449 const MCAsmInfo *MAI = MF->getTarget().getMCAsmInfo();
451 // Basic size info comes from the TSFlags field.
452 const TargetInstrDesc &TID = MI->getDesc();
453 unsigned TSFlags = TID.TSFlags;
455 unsigned Opc = MI->getOpcode();
456 switch ((TSFlags & ARMII::SizeMask) >> ARMII::SizeShift) {
458 // If this machine instr is an inline asm, measure it.
459 if (MI->getOpcode() == ARM::INLINEASM)
460 return getInlineAsmLength(MI->getOperand(0).getSymbolName(), *MAI);
465 llvm_unreachable("Unknown or unset size field for instr!");
466 case TargetOpcode::IMPLICIT_DEF:
467 case TargetOpcode::KILL:
468 case TargetOpcode::DBG_LABEL:
469 case TargetOpcode::EH_LABEL:
470 case TargetOpcode::DBG_VALUE:
475 case ARMII::Size8Bytes: return 8; // ARM instruction x 2.
476 case ARMII::Size4Bytes: return 4; // ARM / Thumb2 instruction.
477 case ARMII::Size2Bytes: return 2; // Thumb1 instruction.
478 case ARMII::SizeSpecial: {
480 case ARM::CONSTPOOL_ENTRY:
481 // If this machine instr is a constant pool entry, its size is recorded as
483 return MI->getOperand(2).getImm();
484 case ARM::Int_eh_sjlj_setjmp:
485 case ARM::Int_eh_sjlj_setjmp_nofp:
487 case ARM::tInt_eh_sjlj_setjmp:
488 case ARM::t2Int_eh_sjlj_setjmp:
489 case ARM::t2Int_eh_sjlj_setjmp_nofp:
498 // These are jumptable branches, i.e. a branch followed by an inlined
499 // jumptable. The size is 4 + 4 * number of entries. For TBB, each
500 // entry is one byte; TBH two byte each.
501 unsigned EntrySize = (Opc == ARM::t2TBB)
502 ? 1 : ((Opc == ARM::t2TBH) ? 2 : 4);
503 unsigned NumOps = TID.getNumOperands();
504 MachineOperand JTOP =
505 MI->getOperand(NumOps - (TID.isPredicable() ? 3 : 2));
506 unsigned JTI = JTOP.getIndex();
507 const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
509 const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
510 assert(JTI < JT.size());
511 // Thumb instructions are 2 byte aligned, but JT entries are 4 byte
512 // 4 aligned. The assembler / linker may add 2 byte padding just before
513 // the JT entries. The size does not include this padding; the
514 // constant islands pass does separate bookkeeping for it.
515 // FIXME: If we know the size of the function is less than (1 << 16) *2
516 // bytes, we can use 16-bit entries instead. Then there won't be an
518 unsigned InstSize = (Opc == ARM::tBR_JTr || Opc == ARM::t2BR_JT) ? 2 : 4;
519 unsigned NumEntries = getNumJTEntries(JT, JTI);
520 if (Opc == ARM::t2TBB && (NumEntries & 1))
521 // Make sure the instruction that follows TBB is 2-byte aligned.
522 // FIXME: Constant island pass should insert an "ALIGN" instruction
525 return NumEntries * EntrySize + InstSize;
528 // Otherwise, pseudo-instruction sizes are zero.
533 return 0; // Not reached
536 /// Return true if the instruction is a register to register move and
537 /// leave the source and dest operands in the passed parameters.
540 ARMBaseInstrInfo::isMoveInstr(const MachineInstr &MI,
541 unsigned &SrcReg, unsigned &DstReg,
542 unsigned& SrcSubIdx, unsigned& DstSubIdx) const {
543 SrcSubIdx = DstSubIdx = 0; // No sub-registers.
545 switch (MI.getOpcode()) {
552 SrcReg = MI.getOperand(1).getReg();
553 DstReg = MI.getOperand(0).getReg();
558 case ARM::tMOVgpr2tgpr:
559 case ARM::tMOVtgpr2gpr:
560 case ARM::tMOVgpr2gpr:
562 assert(MI.getDesc().getNumOperands() >= 2 &&
563 MI.getOperand(0).isReg() &&
564 MI.getOperand(1).isReg() &&
565 "Invalid ARM MOV instruction");
566 SrcReg = MI.getOperand(1).getReg();
567 DstReg = MI.getOperand(0).getReg();
576 ARMBaseInstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
577 int &FrameIndex) const {
578 switch (MI->getOpcode()) {
581 case ARM::t2LDRs: // FIXME: don't use t2LDRs to access frame.
582 if (MI->getOperand(1).isFI() &&
583 MI->getOperand(2).isReg() &&
584 MI->getOperand(3).isImm() &&
585 MI->getOperand(2).getReg() == 0 &&
586 MI->getOperand(3).getImm() == 0) {
587 FrameIndex = MI->getOperand(1).getIndex();
588 return MI->getOperand(0).getReg();
593 if (MI->getOperand(1).isFI() &&
594 MI->getOperand(2).isImm() &&
595 MI->getOperand(2).getImm() == 0) {
596 FrameIndex = MI->getOperand(1).getIndex();
597 return MI->getOperand(0).getReg();
602 if (MI->getOperand(1).isFI() &&
603 MI->getOperand(2).isImm() &&
604 MI->getOperand(2).getImm() == 0) {
605 FrameIndex = MI->getOperand(1).getIndex();
606 return MI->getOperand(0).getReg();
615 ARMBaseInstrInfo::isStoreToStackSlot(const MachineInstr *MI,
616 int &FrameIndex) const {
617 switch (MI->getOpcode()) {
620 case ARM::t2STRs: // FIXME: don't use t2STRs to access frame.
621 if (MI->getOperand(1).isFI() &&
622 MI->getOperand(2).isReg() &&
623 MI->getOperand(3).isImm() &&
624 MI->getOperand(2).getReg() == 0 &&
625 MI->getOperand(3).getImm() == 0) {
626 FrameIndex = MI->getOperand(1).getIndex();
627 return MI->getOperand(0).getReg();
632 if (MI->getOperand(1).isFI() &&
633 MI->getOperand(2).isImm() &&
634 MI->getOperand(2).getImm() == 0) {
635 FrameIndex = MI->getOperand(1).getIndex();
636 return MI->getOperand(0).getReg();
641 if (MI->getOperand(1).isFI() &&
642 MI->getOperand(2).isImm() &&
643 MI->getOperand(2).getImm() == 0) {
644 FrameIndex = MI->getOperand(1).getIndex();
645 return MI->getOperand(0).getReg();
654 ARMBaseInstrInfo::copyRegToReg(MachineBasicBlock &MBB,
655 MachineBasicBlock::iterator I,
656 unsigned DestReg, unsigned SrcReg,
657 const TargetRegisterClass *DestRC,
658 const TargetRegisterClass *SrcRC) const {
660 if (I != MBB.end()) DL = I->getDebugLoc();
662 // tGPR is used sometimes in ARM instructions that need to avoid using
663 // certain registers. Just treat it as GPR here.
664 if (DestRC == ARM::tGPRRegisterClass)
665 DestRC = ARM::GPRRegisterClass;
666 if (SrcRC == ARM::tGPRRegisterClass)
667 SrcRC = ARM::GPRRegisterClass;
669 // Allow DPR / DPR_VFP2 / DPR_8 cross-class copies.
670 if (DestRC == ARM::DPR_8RegisterClass)
671 DestRC = ARM::DPR_VFP2RegisterClass;
672 if (SrcRC == ARM::DPR_8RegisterClass)
673 SrcRC = ARM::DPR_VFP2RegisterClass;
675 // Allow QPR / QPR_VFP2 / QPR_8 cross-class copies.
676 if (DestRC == ARM::QPR_VFP2RegisterClass ||
677 DestRC == ARM::QPR_8RegisterClass)
678 DestRC = ARM::QPRRegisterClass;
679 if (SrcRC == ARM::QPR_VFP2RegisterClass ||
680 SrcRC == ARM::QPR_8RegisterClass)
681 SrcRC = ARM::QPRRegisterClass;
683 // Allow QQPR / QQPR_VFP2 / QQPR_8 cross-class copies.
684 if (DestRC == ARM::QQPR_VFP2RegisterClass ||
685 DestRC == ARM::QQPR_8RegisterClass)
686 DestRC = ARM::QQPRRegisterClass;
687 if (SrcRC == ARM::QQPR_VFP2RegisterClass ||
688 SrcRC == ARM::QQPR_8RegisterClass)
689 SrcRC = ARM::QQPRRegisterClass;
691 // Disallow copies of unequal sizes.
692 if (DestRC != SrcRC && DestRC->getSize() != SrcRC->getSize())
695 if (DestRC == ARM::GPRRegisterClass) {
696 if (SrcRC == ARM::SPRRegisterClass)
697 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VMOVRS), DestReg)
700 AddDefaultCC(AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::MOVr),
701 DestReg).addReg(SrcReg)));
705 if (DestRC == ARM::SPRRegisterClass)
706 Opc = (SrcRC == ARM::GPRRegisterClass ? ARM::VMOVSR : ARM::VMOVS);
707 else if (DestRC == ARM::DPRRegisterClass)
709 else if (DestRC == ARM::DPR_VFP2RegisterClass ||
710 SrcRC == ARM::DPR_VFP2RegisterClass)
711 // Always use neon reg-reg move if source or dest is NEON-only regclass.
712 Opc = ARM::VMOVDneon;
713 else if (DestRC == ARM::QPRRegisterClass)
715 else if (DestRC == ARM::QQPRRegisterClass)
720 AddDefaultPred(BuildMI(MBB, I, DL, get(Opc), DestReg).addReg(SrcReg));
726 void ARMBaseInstrInfo::
727 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
728 unsigned SrcReg, bool isKill, int FI,
729 const TargetRegisterClass *RC) const {
731 if (I != MBB.end()) DL = I->getDebugLoc();
732 MachineFunction &MF = *MBB.getParent();
733 MachineFrameInfo &MFI = *MF.getFrameInfo();
734 unsigned Align = MFI.getObjectAlignment(FI);
736 MachineMemOperand *MMO =
737 MF.getMachineMemOperand(PseudoSourceValue::getFixedStack(FI),
738 MachineMemOperand::MOStore, 0,
739 MFI.getObjectSize(FI),
742 // tGPR is used sometimes in ARM instructions that need to avoid using
743 // certain registers. Just treat it as GPR here.
744 if (RC == ARM::tGPRRegisterClass)
745 RC = ARM::GPRRegisterClass;
747 if (RC == ARM::GPRRegisterClass) {
748 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::STR))
749 .addReg(SrcReg, getKillRegState(isKill))
750 .addFrameIndex(FI).addReg(0).addImm(0).addMemOperand(MMO));
751 } else if (RC == ARM::SPRRegisterClass) {
752 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTRS))
753 .addReg(SrcReg, getKillRegState(isKill))
754 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
755 } else if (RC == ARM::DPRRegisterClass ||
756 RC == ARM::DPR_VFP2RegisterClass ||
757 RC == ARM::DPR_8RegisterClass) {
758 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTRD))
759 .addReg(SrcReg, getKillRegState(isKill))
760 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
761 } else if (RC == ARM::QPRRegisterClass ||
762 RC == ARM::QPR_VFP2RegisterClass ||
763 RC == ARM::QPR_8RegisterClass) {
764 // FIXME: Neon instructions should support predicates
765 if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) {
766 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VST1q))
767 .addFrameIndex(FI).addImm(128)
769 .addReg(SrcReg, getKillRegState(isKill)));
771 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTMQ)).
772 addReg(SrcReg, getKillRegState(isKill))
774 .addImm(ARM_AM::getAM5Opc(ARM_AM::ia, 4))
775 .addMemOperand(MMO));
778 assert((RC == ARM::QQPRRegisterClass ||
779 RC == ARM::QQPR_VFP2RegisterClass ||
780 RC == ARM::QQPR_8RegisterClass) && "Unknown regclass!");
781 llvm_unreachable("Not yet implemented!");
785 void ARMBaseInstrInfo::
786 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
787 unsigned DestReg, int FI,
788 const TargetRegisterClass *RC) const {
790 if (I != MBB.end()) DL = I->getDebugLoc();
791 MachineFunction &MF = *MBB.getParent();
792 MachineFrameInfo &MFI = *MF.getFrameInfo();
793 unsigned Align = MFI.getObjectAlignment(FI);
795 MachineMemOperand *MMO =
796 MF.getMachineMemOperand(PseudoSourceValue::getFixedStack(FI),
797 MachineMemOperand::MOLoad, 0,
798 MFI.getObjectSize(FI),
801 // tGPR is used sometimes in ARM instructions that need to avoid using
802 // certain registers. Just treat it as GPR here.
803 if (RC == ARM::tGPRRegisterClass)
804 RC = ARM::GPRRegisterClass;
806 if (RC == ARM::GPRRegisterClass) {
807 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::LDR), DestReg)
808 .addFrameIndex(FI).addReg(0).addImm(0).addMemOperand(MMO));
809 } else if (RC == ARM::SPRRegisterClass) {
810 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDRS), DestReg)
811 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
812 } else if (RC == ARM::DPRRegisterClass ||
813 RC == ARM::DPR_VFP2RegisterClass ||
814 RC == ARM::DPR_8RegisterClass) {
815 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDRD), DestReg)
816 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
817 } else if (RC == ARM::QPRRegisterClass ||
818 RC == ARM::QPR_VFP2RegisterClass ||
819 RC == ARM::QPR_8RegisterClass) {
820 if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) {
821 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLD1q), DestReg)
822 .addFrameIndex(FI).addImm(128)
823 .addMemOperand(MMO));
825 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDMQ), DestReg)
827 .addImm(ARM_AM::getAM5Opc(ARM_AM::ia, 4))
828 .addMemOperand(MMO));
831 assert((RC == ARM::QQPRRegisterClass ||
832 RC == ARM::QQPR_VFP2RegisterClass ||
833 RC == ARM::QQPR_8RegisterClass) && "Unknown regclass!");
834 llvm_unreachable("Not yet implemented!");
839 ARMBaseInstrInfo::emitFrameIndexDebugValue(MachineFunction &MF,
840 int FrameIx, uint64_t Offset,
843 MachineInstrBuilder MIB = BuildMI(MF, DL, get(ARM::DBG_VALUE))
844 .addFrameIndex(FrameIx).addImm(0).addImm(Offset).addMetadata(MDPtr);
848 MachineInstr *ARMBaseInstrInfo::
849 foldMemoryOperandImpl(MachineFunction &MF, MachineInstr *MI,
850 const SmallVectorImpl<unsigned> &Ops, int FI) const {
851 if (Ops.size() != 1) return NULL;
853 unsigned OpNum = Ops[0];
854 unsigned Opc = MI->getOpcode();
855 MachineInstr *NewMI = NULL;
856 if (Opc == ARM::MOVr || Opc == ARM::t2MOVr) {
857 // If it is updating CPSR, then it cannot be folded.
858 if (MI->getOperand(4).getReg() == ARM::CPSR && !MI->getOperand(4).isDead())
860 unsigned Pred = MI->getOperand(2).getImm();
861 unsigned PredReg = MI->getOperand(3).getReg();
862 if (OpNum == 0) { // move -> store
863 unsigned SrcReg = MI->getOperand(1).getReg();
864 unsigned SrcSubReg = MI->getOperand(1).getSubReg();
865 bool isKill = MI->getOperand(1).isKill();
866 bool isUndef = MI->getOperand(1).isUndef();
867 if (Opc == ARM::MOVr)
868 NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::STR))
870 getKillRegState(isKill) | getUndefRegState(isUndef),
872 .addFrameIndex(FI).addReg(0).addImm(0).addImm(Pred).addReg(PredReg);
874 NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::t2STRi12))
876 getKillRegState(isKill) | getUndefRegState(isUndef),
878 .addFrameIndex(FI).addImm(0).addImm(Pred).addReg(PredReg);
879 } else { // move -> load
880 unsigned DstReg = MI->getOperand(0).getReg();
881 unsigned DstSubReg = MI->getOperand(0).getSubReg();
882 bool isDead = MI->getOperand(0).isDead();
883 bool isUndef = MI->getOperand(0).isUndef();
884 if (Opc == ARM::MOVr)
885 NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::LDR))
888 getDeadRegState(isDead) |
889 getUndefRegState(isUndef), DstSubReg)
890 .addFrameIndex(FI).addReg(0).addImm(0).addImm(Pred).addReg(PredReg);
892 NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::t2LDRi12))
895 getDeadRegState(isDead) |
896 getUndefRegState(isUndef), DstSubReg)
897 .addFrameIndex(FI).addImm(0).addImm(Pred).addReg(PredReg);
899 } else if (Opc == ARM::tMOVgpr2gpr ||
900 Opc == ARM::tMOVtgpr2gpr ||
901 Opc == ARM::tMOVgpr2tgpr) {
902 if (OpNum == 0) { // move -> store
903 unsigned SrcReg = MI->getOperand(1).getReg();
904 unsigned SrcSubReg = MI->getOperand(1).getSubReg();
905 bool isKill = MI->getOperand(1).isKill();
906 bool isUndef = MI->getOperand(1).isUndef();
907 NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::t2STRi12))
909 getKillRegState(isKill) | getUndefRegState(isUndef),
911 .addFrameIndex(FI).addImm(0).addImm(ARMCC::AL).addReg(0);
912 } else { // move -> load
913 unsigned DstReg = MI->getOperand(0).getReg();
914 unsigned DstSubReg = MI->getOperand(0).getSubReg();
915 bool isDead = MI->getOperand(0).isDead();
916 bool isUndef = MI->getOperand(0).isUndef();
917 NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::t2LDRi12))
920 getDeadRegState(isDead) |
921 getUndefRegState(isUndef),
923 .addFrameIndex(FI).addImm(0).addImm(ARMCC::AL).addReg(0);
925 } else if (Opc == ARM::VMOVS) {
926 unsigned Pred = MI->getOperand(2).getImm();
927 unsigned PredReg = MI->getOperand(3).getReg();
928 if (OpNum == 0) { // move -> store
929 unsigned SrcReg = MI->getOperand(1).getReg();
930 unsigned SrcSubReg = MI->getOperand(1).getSubReg();
931 bool isKill = MI->getOperand(1).isKill();
932 bool isUndef = MI->getOperand(1).isUndef();
933 NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::VSTRS))
934 .addReg(SrcReg, getKillRegState(isKill) | getUndefRegState(isUndef),
937 .addImm(0).addImm(Pred).addReg(PredReg);
938 } else { // move -> load
939 unsigned DstReg = MI->getOperand(0).getReg();
940 unsigned DstSubReg = MI->getOperand(0).getSubReg();
941 bool isDead = MI->getOperand(0).isDead();
942 bool isUndef = MI->getOperand(0).isUndef();
943 NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::VLDRS))
946 getDeadRegState(isDead) |
947 getUndefRegState(isUndef),
949 .addFrameIndex(FI).addImm(0).addImm(Pred).addReg(PredReg);
952 else if (Opc == ARM::VMOVD) {
953 unsigned Pred = MI->getOperand(2).getImm();
954 unsigned PredReg = MI->getOperand(3).getReg();
955 if (OpNum == 0) { // move -> store
956 unsigned SrcReg = MI->getOperand(1).getReg();
957 unsigned SrcSubReg = MI->getOperand(1).getSubReg();
958 bool isKill = MI->getOperand(1).isKill();
959 bool isUndef = MI->getOperand(1).isUndef();
960 NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::VSTRD))
962 getKillRegState(isKill) | getUndefRegState(isUndef),
964 .addFrameIndex(FI).addImm(0).addImm(Pred).addReg(PredReg);
965 } else { // move -> load
966 unsigned DstReg = MI->getOperand(0).getReg();
967 unsigned DstSubReg = MI->getOperand(0).getSubReg();
968 bool isDead = MI->getOperand(0).isDead();
969 bool isUndef = MI->getOperand(0).isUndef();
970 NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::VLDRD))
973 getDeadRegState(isDead) |
974 getUndefRegState(isUndef),
976 .addFrameIndex(FI).addImm(0).addImm(Pred).addReg(PredReg);
984 ARMBaseInstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
986 const SmallVectorImpl<unsigned> &Ops,
987 MachineInstr* LoadMI) const {
993 ARMBaseInstrInfo::canFoldMemoryOperand(const MachineInstr *MI,
994 const SmallVectorImpl<unsigned> &Ops) const {
995 if (Ops.size() != 1) return false;
997 unsigned Opc = MI->getOpcode();
998 if (Opc == ARM::MOVr || Opc == ARM::t2MOVr) {
999 // If it is updating CPSR, then it cannot be folded.
1000 return MI->getOperand(4).getReg() != ARM::CPSR ||
1001 MI->getOperand(4).isDead();
1002 } else if (Opc == ARM::tMOVgpr2gpr ||
1003 Opc == ARM::tMOVtgpr2gpr ||
1004 Opc == ARM::tMOVgpr2tgpr) {
1006 } else if (Opc == ARM::VMOVS || Opc == ARM::VMOVD) {
1008 } else if (Opc == ARM::VMOVDneon || Opc == ARM::VMOVQ) {
1009 return false; // FIXME
1015 /// Create a copy of a const pool value. Update CPI to the new index and return
1017 static unsigned duplicateCPV(MachineFunction &MF, unsigned &CPI) {
1018 MachineConstantPool *MCP = MF.getConstantPool();
1019 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1021 const MachineConstantPoolEntry &MCPE = MCP->getConstants()[CPI];
1022 assert(MCPE.isMachineConstantPoolEntry() &&
1023 "Expecting a machine constantpool entry!");
1024 ARMConstantPoolValue *ACPV =
1025 static_cast<ARMConstantPoolValue*>(MCPE.Val.MachineCPVal);
1027 unsigned PCLabelId = AFI->createConstPoolEntryUId();
1028 ARMConstantPoolValue *NewCPV = 0;
1029 if (ACPV->isGlobalValue())
1030 NewCPV = new ARMConstantPoolValue(ACPV->getGV(), PCLabelId,
1032 else if (ACPV->isExtSymbol())
1033 NewCPV = new ARMConstantPoolValue(MF.getFunction()->getContext(),
1034 ACPV->getSymbol(), PCLabelId, 4);
1035 else if (ACPV->isBlockAddress())
1036 NewCPV = new ARMConstantPoolValue(ACPV->getBlockAddress(), PCLabelId,
1037 ARMCP::CPBlockAddress, 4);
1039 llvm_unreachable("Unexpected ARM constantpool value type!!");
1040 CPI = MCP->getConstantPoolIndex(NewCPV, MCPE.getAlignment());
1044 void ARMBaseInstrInfo::
1045 reMaterialize(MachineBasicBlock &MBB,
1046 MachineBasicBlock::iterator I,
1047 unsigned DestReg, unsigned SubIdx,
1048 const MachineInstr *Orig,
1049 const TargetRegisterInfo *TRI) const {
1050 if (SubIdx && TargetRegisterInfo::isPhysicalRegister(DestReg)) {
1051 DestReg = TRI->getSubReg(DestReg, SubIdx);
1055 unsigned Opcode = Orig->getOpcode();
1058 MachineInstr *MI = MBB.getParent()->CloneMachineInstr(Orig);
1059 MI->getOperand(0).setReg(DestReg);
1063 case ARM::tLDRpci_pic:
1064 case ARM::t2LDRpci_pic: {
1065 MachineFunction &MF = *MBB.getParent();
1066 unsigned CPI = Orig->getOperand(1).getIndex();
1067 unsigned PCLabelId = duplicateCPV(MF, CPI);
1068 MachineInstrBuilder MIB = BuildMI(MBB, I, Orig->getDebugLoc(), get(Opcode),
1070 .addConstantPoolIndex(CPI).addImm(PCLabelId);
1071 (*MIB).setMemRefs(Orig->memoperands_begin(), Orig->memoperands_end());
1076 MachineInstr *NewMI = prior(I);
1077 NewMI->getOperand(0).setSubReg(SubIdx);
1081 ARMBaseInstrInfo::duplicate(MachineInstr *Orig, MachineFunction &MF) const {
1082 MachineInstr *MI = TargetInstrInfoImpl::duplicate(Orig, MF);
1083 switch(Orig->getOpcode()) {
1084 case ARM::tLDRpci_pic:
1085 case ARM::t2LDRpci_pic: {
1086 unsigned CPI = Orig->getOperand(1).getIndex();
1087 unsigned PCLabelId = duplicateCPV(MF, CPI);
1088 Orig->getOperand(1).setIndex(CPI);
1089 Orig->getOperand(2).setImm(PCLabelId);
1096 bool ARMBaseInstrInfo::produceSameValue(const MachineInstr *MI0,
1097 const MachineInstr *MI1) const {
1098 int Opcode = MI0->getOpcode();
1099 if (Opcode == ARM::t2LDRpci ||
1100 Opcode == ARM::t2LDRpci_pic ||
1101 Opcode == ARM::tLDRpci ||
1102 Opcode == ARM::tLDRpci_pic) {
1103 if (MI1->getOpcode() != Opcode)
1105 if (MI0->getNumOperands() != MI1->getNumOperands())
1108 const MachineOperand &MO0 = MI0->getOperand(1);
1109 const MachineOperand &MO1 = MI1->getOperand(1);
1110 if (MO0.getOffset() != MO1.getOffset())
1113 const MachineFunction *MF = MI0->getParent()->getParent();
1114 const MachineConstantPool *MCP = MF->getConstantPool();
1115 int CPI0 = MO0.getIndex();
1116 int CPI1 = MO1.getIndex();
1117 const MachineConstantPoolEntry &MCPE0 = MCP->getConstants()[CPI0];
1118 const MachineConstantPoolEntry &MCPE1 = MCP->getConstants()[CPI1];
1119 ARMConstantPoolValue *ACPV0 =
1120 static_cast<ARMConstantPoolValue*>(MCPE0.Val.MachineCPVal);
1121 ARMConstantPoolValue *ACPV1 =
1122 static_cast<ARMConstantPoolValue*>(MCPE1.Val.MachineCPVal);
1123 return ACPV0->hasSameValue(ACPV1);
1126 return MI0->isIdenticalTo(MI1, MachineInstr::IgnoreVRegDefs);
1129 /// getInstrPredicate - If instruction is predicated, returns its predicate
1130 /// condition, otherwise returns AL. It also returns the condition code
1131 /// register by reference.
1133 llvm::getInstrPredicate(const MachineInstr *MI, unsigned &PredReg) {
1134 int PIdx = MI->findFirstPredOperandIdx();
1140 PredReg = MI->getOperand(PIdx+1).getReg();
1141 return (ARMCC::CondCodes)MI->getOperand(PIdx).getImm();
1145 int llvm::getMatchingCondBranchOpcode(int Opc) {
1148 else if (Opc == ARM::tB)
1150 else if (Opc == ARM::t2B)
1153 llvm_unreachable("Unknown unconditional branch opcode!");
1158 void llvm::emitARMRegPlusImmediate(MachineBasicBlock &MBB,
1159 MachineBasicBlock::iterator &MBBI, DebugLoc dl,
1160 unsigned DestReg, unsigned BaseReg, int NumBytes,
1161 ARMCC::CondCodes Pred, unsigned PredReg,
1162 const ARMBaseInstrInfo &TII) {
1163 bool isSub = NumBytes < 0;
1164 if (isSub) NumBytes = -NumBytes;
1167 unsigned RotAmt = ARM_AM::getSOImmValRotate(NumBytes);
1168 unsigned ThisVal = NumBytes & ARM_AM::rotr32(0xFF, RotAmt);
1169 assert(ThisVal && "Didn't extract field correctly");
1171 // We will handle these bits from offset, clear them.
1172 NumBytes &= ~ThisVal;
1174 assert(ARM_AM::getSOImmVal(ThisVal) != -1 && "Bit extraction didn't work?");
1176 // Build the new ADD / SUB.
1177 unsigned Opc = isSub ? ARM::SUBri : ARM::ADDri;
1178 BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg)
1179 .addReg(BaseReg, RegState::Kill).addImm(ThisVal)
1180 .addImm((unsigned)Pred).addReg(PredReg).addReg(0);
1185 bool llvm::rewriteARMFrameIndex(MachineInstr &MI, unsigned FrameRegIdx,
1186 unsigned FrameReg, int &Offset,
1187 const ARMBaseInstrInfo &TII) {
1188 unsigned Opcode = MI.getOpcode();
1189 const TargetInstrDesc &Desc = MI.getDesc();
1190 unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
1193 // Memory operands in inline assembly always use AddrMode2.
1194 if (Opcode == ARM::INLINEASM)
1195 AddrMode = ARMII::AddrMode2;
1197 if (Opcode == ARM::ADDri) {
1198 Offset += MI.getOperand(FrameRegIdx+1).getImm();
1200 // Turn it into a move.
1201 MI.setDesc(TII.get(ARM::MOVr));
1202 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
1203 MI.RemoveOperand(FrameRegIdx+1);
1206 } else if (Offset < 0) {
1209 MI.setDesc(TII.get(ARM::SUBri));
1212 // Common case: small offset, fits into instruction.
1213 if (ARM_AM::getSOImmVal(Offset) != -1) {
1214 // Replace the FrameIndex with sp / fp
1215 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
1216 MI.getOperand(FrameRegIdx+1).ChangeToImmediate(Offset);
1221 // Otherwise, pull as much of the immedidate into this ADDri/SUBri
1223 unsigned RotAmt = ARM_AM::getSOImmValRotate(Offset);
1224 unsigned ThisImmVal = Offset & ARM_AM::rotr32(0xFF, RotAmt);
1226 // We will handle these bits from offset, clear them.
1227 Offset &= ~ThisImmVal;
1229 // Get the properly encoded SOImmVal field.
1230 assert(ARM_AM::getSOImmVal(ThisImmVal) != -1 &&
1231 "Bit extraction didn't work?");
1232 MI.getOperand(FrameRegIdx+1).ChangeToImmediate(ThisImmVal);
1234 unsigned ImmIdx = 0;
1236 unsigned NumBits = 0;
1239 case ARMII::AddrMode2: {
1240 ImmIdx = FrameRegIdx+2;
1241 InstrOffs = ARM_AM::getAM2Offset(MI.getOperand(ImmIdx).getImm());
1242 if (ARM_AM::getAM2Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub)
1247 case ARMII::AddrMode3: {
1248 ImmIdx = FrameRegIdx+2;
1249 InstrOffs = ARM_AM::getAM3Offset(MI.getOperand(ImmIdx).getImm());
1250 if (ARM_AM::getAM3Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub)
1255 case ARMII::AddrMode4:
1256 case ARMII::AddrMode6:
1257 // Can't fold any offset even if it's zero.
1259 case ARMII::AddrMode5: {
1260 ImmIdx = FrameRegIdx+1;
1261 InstrOffs = ARM_AM::getAM5Offset(MI.getOperand(ImmIdx).getImm());
1262 if (ARM_AM::getAM5Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub)
1269 llvm_unreachable("Unsupported addressing mode!");
1273 Offset += InstrOffs * Scale;
1274 assert((Offset & (Scale-1)) == 0 && "Can't encode this offset!");
1280 // Attempt to fold address comp. if opcode has offset bits
1282 // Common case: small offset, fits into instruction.
1283 MachineOperand &ImmOp = MI.getOperand(ImmIdx);
1284 int ImmedOffset = Offset / Scale;
1285 unsigned Mask = (1 << NumBits) - 1;
1286 if ((unsigned)Offset <= Mask * Scale) {
1287 // Replace the FrameIndex with sp
1288 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
1290 ImmedOffset |= 1 << NumBits;
1291 ImmOp.ChangeToImmediate(ImmedOffset);
1296 // Otherwise, it didn't fit. Pull in what we can to simplify the immed.
1297 ImmedOffset = ImmedOffset & Mask;
1299 ImmedOffset |= 1 << NumBits;
1300 ImmOp.ChangeToImmediate(ImmedOffset);
1301 Offset &= ~(Mask*Scale);
1305 Offset = (isSub) ? -Offset : Offset;