1 //===- ARMBaseInstrInfo.cpp - ARM Instruction Information -------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Base ARM implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "ARMBaseInstrInfo.h"
16 #include "ARMConstantPoolValue.h"
17 #include "ARMHazardRecognizer.h"
18 #include "ARMMachineFunctionInfo.h"
19 #include "ARMRegisterInfo.h"
20 #include "MCTargetDesc/ARMAddressingModes.h"
21 #include "llvm/Constants.h"
22 #include "llvm/Function.h"
23 #include "llvm/GlobalValue.h"
24 #include "llvm/CodeGen/LiveVariables.h"
25 #include "llvm/CodeGen/MachineConstantPool.h"
26 #include "llvm/CodeGen/MachineFrameInfo.h"
27 #include "llvm/CodeGen/MachineInstrBuilder.h"
28 #include "llvm/CodeGen/MachineJumpTableInfo.h"
29 #include "llvm/CodeGen/MachineMemOperand.h"
30 #include "llvm/CodeGen/MachineRegisterInfo.h"
31 #include "llvm/CodeGen/SelectionDAGNodes.h"
32 #include "llvm/MC/MCAsmInfo.h"
33 #include "llvm/Support/BranchProbability.h"
34 #include "llvm/Support/CommandLine.h"
35 #include "llvm/Support/Debug.h"
36 #include "llvm/Support/ErrorHandling.h"
37 #include "llvm/ADT/STLExtras.h"
39 #define GET_INSTRINFO_CTOR
40 #include "ARMGenInstrInfo.inc"
45 EnableARM3Addr("enable-arm-3-addr-conv", cl::Hidden,
46 cl::desc("Enable ARM 2-addr to 3-addr conv"));
49 WidenVMOVS("widen-vmovs", cl::Hidden, cl::init(true),
50 cl::desc("Widen ARM vmovs to vmovd when possible"));
52 /// ARM_MLxEntry - Record information about MLA / MLS instructions.
54 unsigned MLxOpc; // MLA / MLS opcode
55 unsigned MulOpc; // Expanded multiplication opcode
56 unsigned AddSubOpc; // Expanded add / sub opcode
57 bool NegAcc; // True if the acc is negated before the add / sub.
58 bool HasLane; // True if instruction has an extra "lane" operand.
61 static const ARM_MLxEntry ARM_MLxTable[] = {
62 // MLxOpc, MulOpc, AddSubOpc, NegAcc, HasLane
64 { ARM::VMLAS, ARM::VMULS, ARM::VADDS, false, false },
65 { ARM::VMLSS, ARM::VMULS, ARM::VSUBS, false, false },
66 { ARM::VMLAD, ARM::VMULD, ARM::VADDD, false, false },
67 { ARM::VMLSD, ARM::VMULD, ARM::VSUBD, false, false },
68 { ARM::VNMLAS, ARM::VNMULS, ARM::VSUBS, true, false },
69 { ARM::VNMLSS, ARM::VMULS, ARM::VSUBS, true, false },
70 { ARM::VNMLAD, ARM::VNMULD, ARM::VSUBD, true, false },
71 { ARM::VNMLSD, ARM::VMULD, ARM::VSUBD, true, false },
74 { ARM::VMLAfd, ARM::VMULfd, ARM::VADDfd, false, false },
75 { ARM::VMLSfd, ARM::VMULfd, ARM::VSUBfd, false, false },
76 { ARM::VMLAfq, ARM::VMULfq, ARM::VADDfq, false, false },
77 { ARM::VMLSfq, ARM::VMULfq, ARM::VSUBfq, false, false },
78 { ARM::VMLAslfd, ARM::VMULslfd, ARM::VADDfd, false, true },
79 { ARM::VMLSslfd, ARM::VMULslfd, ARM::VSUBfd, false, true },
80 { ARM::VMLAslfq, ARM::VMULslfq, ARM::VADDfq, false, true },
81 { ARM::VMLSslfq, ARM::VMULslfq, ARM::VSUBfq, false, true },
84 ARMBaseInstrInfo::ARMBaseInstrInfo(const ARMSubtarget& STI)
85 : ARMGenInstrInfo(ARM::ADJCALLSTACKDOWN, ARM::ADJCALLSTACKUP),
87 for (unsigned i = 0, e = array_lengthof(ARM_MLxTable); i != e; ++i) {
88 if (!MLxEntryMap.insert(std::make_pair(ARM_MLxTable[i].MLxOpc, i)).second)
89 assert(false && "Duplicated entries?");
90 MLxHazardOpcodes.insert(ARM_MLxTable[i].AddSubOpc);
91 MLxHazardOpcodes.insert(ARM_MLxTable[i].MulOpc);
95 // Use a ScoreboardHazardRecognizer for prepass ARM scheduling. TargetInstrImpl
96 // currently defaults to no prepass hazard recognizer.
97 ScheduleHazardRecognizer *ARMBaseInstrInfo::
98 CreateTargetHazardRecognizer(const TargetMachine *TM,
99 const ScheduleDAG *DAG) const {
100 if (usePreRAHazardRecognizer()) {
101 const InstrItineraryData *II = TM->getInstrItineraryData();
102 return new ScoreboardHazardRecognizer(II, DAG, "pre-RA-sched");
104 return TargetInstrInfoImpl::CreateTargetHazardRecognizer(TM, DAG);
107 ScheduleHazardRecognizer *ARMBaseInstrInfo::
108 CreateTargetPostRAHazardRecognizer(const InstrItineraryData *II,
109 const ScheduleDAG *DAG) const {
110 if (Subtarget.isThumb2() || Subtarget.hasVFP2())
111 return (ScheduleHazardRecognizer *)
112 new ARMHazardRecognizer(II, *this, getRegisterInfo(), Subtarget, DAG);
113 return TargetInstrInfoImpl::CreateTargetPostRAHazardRecognizer(II, DAG);
117 ARMBaseInstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
118 MachineBasicBlock::iterator &MBBI,
119 LiveVariables *LV) const {
120 // FIXME: Thumb2 support.
125 MachineInstr *MI = MBBI;
126 MachineFunction &MF = *MI->getParent()->getParent();
127 uint64_t TSFlags = MI->getDesc().TSFlags;
129 switch ((TSFlags & ARMII::IndexModeMask) >> ARMII::IndexModeShift) {
130 default: return NULL;
131 case ARMII::IndexModePre:
134 case ARMII::IndexModePost:
138 // Try splitting an indexed load/store to an un-indexed one plus an add/sub
140 unsigned MemOpc = getUnindexedOpcode(MI->getOpcode());
144 MachineInstr *UpdateMI = NULL;
145 MachineInstr *MemMI = NULL;
146 unsigned AddrMode = (TSFlags & ARMII::AddrModeMask);
147 const MCInstrDesc &MCID = MI->getDesc();
148 unsigned NumOps = MCID.getNumOperands();
149 bool isLoad = !MCID.mayStore();
150 const MachineOperand &WB = isLoad ? MI->getOperand(1) : MI->getOperand(0);
151 const MachineOperand &Base = MI->getOperand(2);
152 const MachineOperand &Offset = MI->getOperand(NumOps-3);
153 unsigned WBReg = WB.getReg();
154 unsigned BaseReg = Base.getReg();
155 unsigned OffReg = Offset.getReg();
156 unsigned OffImm = MI->getOperand(NumOps-2).getImm();
157 ARMCC::CondCodes Pred = (ARMCC::CondCodes)MI->getOperand(NumOps-1).getImm();
160 assert(false && "Unknown indexed op!");
162 case ARMII::AddrMode2: {
163 bool isSub = ARM_AM::getAM2Op(OffImm) == ARM_AM::sub;
164 unsigned Amt = ARM_AM::getAM2Offset(OffImm);
166 if (ARM_AM::getSOImmVal(Amt) == -1)
167 // Can't encode it in a so_imm operand. This transformation will
168 // add more than 1 instruction. Abandon!
170 UpdateMI = BuildMI(MF, MI->getDebugLoc(),
171 get(isSub ? ARM::SUBri : ARM::ADDri), WBReg)
172 .addReg(BaseReg).addImm(Amt)
173 .addImm(Pred).addReg(0).addReg(0);
174 } else if (Amt != 0) {
175 ARM_AM::ShiftOpc ShOpc = ARM_AM::getAM2ShiftOpc(OffImm);
176 unsigned SOOpc = ARM_AM::getSORegOpc(ShOpc, Amt);
177 UpdateMI = BuildMI(MF, MI->getDebugLoc(),
178 get(isSub ? ARM::SUBrsi : ARM::ADDrsi), WBReg)
179 .addReg(BaseReg).addReg(OffReg).addReg(0).addImm(SOOpc)
180 .addImm(Pred).addReg(0).addReg(0);
182 UpdateMI = BuildMI(MF, MI->getDebugLoc(),
183 get(isSub ? ARM::SUBrr : ARM::ADDrr), WBReg)
184 .addReg(BaseReg).addReg(OffReg)
185 .addImm(Pred).addReg(0).addReg(0);
188 case ARMII::AddrMode3 : {
189 bool isSub = ARM_AM::getAM3Op(OffImm) == ARM_AM::sub;
190 unsigned Amt = ARM_AM::getAM3Offset(OffImm);
192 // Immediate is 8-bits. It's guaranteed to fit in a so_imm operand.
193 UpdateMI = BuildMI(MF, MI->getDebugLoc(),
194 get(isSub ? ARM::SUBri : ARM::ADDri), WBReg)
195 .addReg(BaseReg).addImm(Amt)
196 .addImm(Pred).addReg(0).addReg(0);
198 UpdateMI = BuildMI(MF, MI->getDebugLoc(),
199 get(isSub ? ARM::SUBrr : ARM::ADDrr), WBReg)
200 .addReg(BaseReg).addReg(OffReg)
201 .addImm(Pred).addReg(0).addReg(0);
206 std::vector<MachineInstr*> NewMIs;
209 MemMI = BuildMI(MF, MI->getDebugLoc(),
210 get(MemOpc), MI->getOperand(0).getReg())
211 .addReg(WBReg).addImm(0).addImm(Pred);
213 MemMI = BuildMI(MF, MI->getDebugLoc(),
214 get(MemOpc)).addReg(MI->getOperand(1).getReg())
215 .addReg(WBReg).addReg(0).addImm(0).addImm(Pred);
216 NewMIs.push_back(MemMI);
217 NewMIs.push_back(UpdateMI);
220 MemMI = BuildMI(MF, MI->getDebugLoc(),
221 get(MemOpc), MI->getOperand(0).getReg())
222 .addReg(BaseReg).addImm(0).addImm(Pred);
224 MemMI = BuildMI(MF, MI->getDebugLoc(),
225 get(MemOpc)).addReg(MI->getOperand(1).getReg())
226 .addReg(BaseReg).addReg(0).addImm(0).addImm(Pred);
228 UpdateMI->getOperand(0).setIsDead();
229 NewMIs.push_back(UpdateMI);
230 NewMIs.push_back(MemMI);
233 // Transfer LiveVariables states, kill / dead info.
235 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
236 MachineOperand &MO = MI->getOperand(i);
237 if (MO.isReg() && TargetRegisterInfo::isVirtualRegister(MO.getReg())) {
238 unsigned Reg = MO.getReg();
240 LiveVariables::VarInfo &VI = LV->getVarInfo(Reg);
242 MachineInstr *NewMI = (Reg == WBReg) ? UpdateMI : MemMI;
244 LV->addVirtualRegisterDead(Reg, NewMI);
246 if (MO.isUse() && MO.isKill()) {
247 for (unsigned j = 0; j < 2; ++j) {
248 // Look at the two new MI's in reverse order.
249 MachineInstr *NewMI = NewMIs[j];
250 if (!NewMI->readsRegister(Reg))
252 LV->addVirtualRegisterKilled(Reg, NewMI);
253 if (VI.removeKill(MI))
254 VI.Kills.push_back(NewMI);
262 MFI->insert(MBBI, NewMIs[1]);
263 MFI->insert(MBBI, NewMIs[0]);
269 ARMBaseInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB,
270 MachineBasicBlock *&FBB,
271 SmallVectorImpl<MachineOperand> &Cond,
272 bool AllowModify) const {
273 // If the block has no terminators, it just falls into the block after it.
274 MachineBasicBlock::iterator I = MBB.end();
275 if (I == MBB.begin())
278 while (I->isDebugValue()) {
279 if (I == MBB.begin())
283 if (!isUnpredicatedTerminator(I))
286 // Get the last instruction in the block.
287 MachineInstr *LastInst = I;
289 // If there is only one terminator instruction, process it.
290 unsigned LastOpc = LastInst->getOpcode();
291 if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) {
292 if (isUncondBranchOpcode(LastOpc)) {
293 TBB = LastInst->getOperand(0).getMBB();
296 if (isCondBranchOpcode(LastOpc)) {
297 // Block ends with fall-through condbranch.
298 TBB = LastInst->getOperand(0).getMBB();
299 Cond.push_back(LastInst->getOperand(1));
300 Cond.push_back(LastInst->getOperand(2));
303 return true; // Can't handle indirect branch.
306 // Get the instruction before it if it is a terminator.
307 MachineInstr *SecondLastInst = I;
308 unsigned SecondLastOpc = SecondLastInst->getOpcode();
310 // If AllowModify is true and the block ends with two or more unconditional
311 // branches, delete all but the first unconditional branch.
312 if (AllowModify && isUncondBranchOpcode(LastOpc)) {
313 while (isUncondBranchOpcode(SecondLastOpc)) {
314 LastInst->eraseFromParent();
315 LastInst = SecondLastInst;
316 LastOpc = LastInst->getOpcode();
317 if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) {
318 // Return now the only terminator is an unconditional branch.
319 TBB = LastInst->getOperand(0).getMBB();
323 SecondLastOpc = SecondLastInst->getOpcode();
328 // If there are three terminators, we don't know what sort of block this is.
329 if (SecondLastInst && I != MBB.begin() && isUnpredicatedTerminator(--I))
332 // If the block ends with a B and a Bcc, handle it.
333 if (isCondBranchOpcode(SecondLastOpc) && isUncondBranchOpcode(LastOpc)) {
334 TBB = SecondLastInst->getOperand(0).getMBB();
335 Cond.push_back(SecondLastInst->getOperand(1));
336 Cond.push_back(SecondLastInst->getOperand(2));
337 FBB = LastInst->getOperand(0).getMBB();
341 // If the block ends with two unconditional branches, handle it. The second
342 // one is not executed, so remove it.
343 if (isUncondBranchOpcode(SecondLastOpc) && isUncondBranchOpcode(LastOpc)) {
344 TBB = SecondLastInst->getOperand(0).getMBB();
347 I->eraseFromParent();
351 // ...likewise if it ends with a branch table followed by an unconditional
352 // branch. The branch folder can create these, and we must get rid of them for
353 // correctness of Thumb constant islands.
354 if ((isJumpTableBranchOpcode(SecondLastOpc) ||
355 isIndirectBranchOpcode(SecondLastOpc)) &&
356 isUncondBranchOpcode(LastOpc)) {
359 I->eraseFromParent();
363 // Otherwise, can't handle this.
368 unsigned ARMBaseInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
369 MachineBasicBlock::iterator I = MBB.end();
370 if (I == MBB.begin()) return 0;
372 while (I->isDebugValue()) {
373 if (I == MBB.begin())
377 if (!isUncondBranchOpcode(I->getOpcode()) &&
378 !isCondBranchOpcode(I->getOpcode()))
381 // Remove the branch.
382 I->eraseFromParent();
386 if (I == MBB.begin()) return 1;
388 if (!isCondBranchOpcode(I->getOpcode()))
391 // Remove the branch.
392 I->eraseFromParent();
397 ARMBaseInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
398 MachineBasicBlock *FBB,
399 const SmallVectorImpl<MachineOperand> &Cond,
401 ARMFunctionInfo *AFI = MBB.getParent()->getInfo<ARMFunctionInfo>();
402 int BOpc = !AFI->isThumbFunction()
403 ? ARM::B : (AFI->isThumb2Function() ? ARM::t2B : ARM::tB);
404 int BccOpc = !AFI->isThumbFunction()
405 ? ARM::Bcc : (AFI->isThumb2Function() ? ARM::t2Bcc : ARM::tBcc);
406 bool isThumb = AFI->isThumbFunction() || AFI->isThumb2Function();
408 // Shouldn't be a fall through.
409 assert(TBB && "InsertBranch must not be told to insert a fallthrough");
410 assert((Cond.size() == 2 || Cond.size() == 0) &&
411 "ARM branch conditions have two components!");
414 if (Cond.empty()) { // Unconditional branch?
416 BuildMI(&MBB, DL, get(BOpc)).addMBB(TBB).addImm(ARMCC::AL).addReg(0);
418 BuildMI(&MBB, DL, get(BOpc)).addMBB(TBB);
420 BuildMI(&MBB, DL, get(BccOpc)).addMBB(TBB)
421 .addImm(Cond[0].getImm()).addReg(Cond[1].getReg());
425 // Two-way conditional branch.
426 BuildMI(&MBB, DL, get(BccOpc)).addMBB(TBB)
427 .addImm(Cond[0].getImm()).addReg(Cond[1].getReg());
429 BuildMI(&MBB, DL, get(BOpc)).addMBB(FBB).addImm(ARMCC::AL).addReg(0);
431 BuildMI(&MBB, DL, get(BOpc)).addMBB(FBB);
435 bool ARMBaseInstrInfo::
436 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
437 ARMCC::CondCodes CC = (ARMCC::CondCodes)(int)Cond[0].getImm();
438 Cond[0].setImm(ARMCC::getOppositeCondition(CC));
442 bool ARMBaseInstrInfo::
443 PredicateInstruction(MachineInstr *MI,
444 const SmallVectorImpl<MachineOperand> &Pred) const {
445 unsigned Opc = MI->getOpcode();
446 if (isUncondBranchOpcode(Opc)) {
447 MI->setDesc(get(getMatchingCondBranchOpcode(Opc)));
448 MI->addOperand(MachineOperand::CreateImm(Pred[0].getImm()));
449 MI->addOperand(MachineOperand::CreateReg(Pred[1].getReg(), false));
453 int PIdx = MI->findFirstPredOperandIdx();
455 MachineOperand &PMO = MI->getOperand(PIdx);
456 PMO.setImm(Pred[0].getImm());
457 MI->getOperand(PIdx+1).setReg(Pred[1].getReg());
463 bool ARMBaseInstrInfo::
464 SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1,
465 const SmallVectorImpl<MachineOperand> &Pred2) const {
466 if (Pred1.size() > 2 || Pred2.size() > 2)
469 ARMCC::CondCodes CC1 = (ARMCC::CondCodes)Pred1[0].getImm();
470 ARMCC::CondCodes CC2 = (ARMCC::CondCodes)Pred2[0].getImm();
480 return CC2 == ARMCC::HI;
482 return CC2 == ARMCC::LO || CC2 == ARMCC::EQ;
484 return CC2 == ARMCC::GT;
486 return CC2 == ARMCC::LT;
490 bool ARMBaseInstrInfo::DefinesPredicate(MachineInstr *MI,
491 std::vector<MachineOperand> &Pred) const {
492 // FIXME: This confuses implicit_def with optional CPSR def.
493 const MCInstrDesc &MCID = MI->getDesc();
494 if (!MCID.getImplicitDefs() && !MCID.hasOptionalDef())
498 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
499 const MachineOperand &MO = MI->getOperand(i);
500 if (MO.isReg() && MO.getReg() == ARM::CPSR) {
509 /// isPredicable - Return true if the specified instruction can be predicated.
510 /// By default, this returns true for every instruction with a
511 /// PredicateOperand.
512 bool ARMBaseInstrInfo::isPredicable(MachineInstr *MI) const {
513 const MCInstrDesc &MCID = MI->getDesc();
514 if (!MCID.isPredicable())
517 if ((MCID.TSFlags & ARMII::DomainMask) == ARMII::DomainNEON) {
518 ARMFunctionInfo *AFI =
519 MI->getParent()->getParent()->getInfo<ARMFunctionInfo>();
520 return AFI->isThumb2Function();
525 /// FIXME: Works around a gcc miscompilation with -fstrict-aliasing.
526 LLVM_ATTRIBUTE_NOINLINE
527 static unsigned getNumJTEntries(const std::vector<MachineJumpTableEntry> &JT,
529 static unsigned getNumJTEntries(const std::vector<MachineJumpTableEntry> &JT,
531 assert(JTI < JT.size());
532 return JT[JTI].MBBs.size();
535 /// GetInstSize - Return the size of the specified MachineInstr.
537 unsigned ARMBaseInstrInfo::GetInstSizeInBytes(const MachineInstr *MI) const {
538 const MachineBasicBlock &MBB = *MI->getParent();
539 const MachineFunction *MF = MBB.getParent();
540 const MCAsmInfo *MAI = MF->getTarget().getMCAsmInfo();
542 const MCInstrDesc &MCID = MI->getDesc();
544 return MCID.getSize();
546 // If this machine instr is an inline asm, measure it.
547 if (MI->getOpcode() == ARM::INLINEASM)
548 return getInlineAsmLength(MI->getOperand(0).getSymbolName(), *MAI);
551 unsigned Opc = MI->getOpcode();
553 case TargetOpcode::IMPLICIT_DEF:
554 case TargetOpcode::KILL:
555 case TargetOpcode::PROLOG_LABEL:
556 case TargetOpcode::EH_LABEL:
557 case TargetOpcode::DBG_VALUE:
559 case ARM::MOVi16_ga_pcrel:
560 case ARM::MOVTi16_ga_pcrel:
561 case ARM::t2MOVi16_ga_pcrel:
562 case ARM::t2MOVTi16_ga_pcrel:
565 case ARM::t2MOVi32imm:
567 case ARM::CONSTPOOL_ENTRY:
568 // If this machine instr is a constant pool entry, its size is recorded as
570 return MI->getOperand(2).getImm();
571 case ARM::Int_eh_sjlj_longjmp:
573 case ARM::tInt_eh_sjlj_longjmp:
575 case ARM::Int_eh_sjlj_setjmp:
576 case ARM::Int_eh_sjlj_setjmp_nofp:
578 case ARM::tInt_eh_sjlj_setjmp:
579 case ARM::t2Int_eh_sjlj_setjmp:
580 case ARM::t2Int_eh_sjlj_setjmp_nofp:
588 case ARM::t2TBH_JT: {
589 // These are jumptable branches, i.e. a branch followed by an inlined
590 // jumptable. The size is 4 + 4 * number of entries. For TBB, each
591 // entry is one byte; TBH two byte each.
592 unsigned EntrySize = (Opc == ARM::t2TBB_JT)
593 ? 1 : ((Opc == ARM::t2TBH_JT) ? 2 : 4);
594 unsigned NumOps = MCID.getNumOperands();
595 MachineOperand JTOP =
596 MI->getOperand(NumOps - (MCID.isPredicable() ? 3 : 2));
597 unsigned JTI = JTOP.getIndex();
598 const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
600 const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
601 assert(JTI < JT.size());
602 // Thumb instructions are 2 byte aligned, but JT entries are 4 byte
603 // 4 aligned. The assembler / linker may add 2 byte padding just before
604 // the JT entries. The size does not include this padding; the
605 // constant islands pass does separate bookkeeping for it.
606 // FIXME: If we know the size of the function is less than (1 << 16) *2
607 // bytes, we can use 16-bit entries instead. Then there won't be an
609 unsigned InstSize = (Opc == ARM::tBR_JTr || Opc == ARM::t2BR_JT) ? 2 : 4;
610 unsigned NumEntries = getNumJTEntries(JT, JTI);
611 if (Opc == ARM::t2TBB_JT && (NumEntries & 1))
612 // Make sure the instruction that follows TBB is 2-byte aligned.
613 // FIXME: Constant island pass should insert an "ALIGN" instruction
616 return NumEntries * EntrySize + InstSize;
619 // Otherwise, pseudo-instruction sizes are zero.
622 return 0; // Not reached
625 void ARMBaseInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
626 MachineBasicBlock::iterator I, DebugLoc DL,
627 unsigned DestReg, unsigned SrcReg,
628 bool KillSrc) const {
629 bool GPRDest = ARM::GPRRegClass.contains(DestReg);
630 bool GPRSrc = ARM::GPRRegClass.contains(SrcReg);
632 if (GPRDest && GPRSrc) {
633 AddDefaultCC(AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::MOVr), DestReg)
634 .addReg(SrcReg, getKillRegState(KillSrc))));
638 bool SPRDest = ARM::SPRRegClass.contains(DestReg);
639 bool SPRSrc = ARM::SPRRegClass.contains(SrcReg);
642 if (SPRDest && SPRSrc)
644 else if (GPRDest && SPRSrc)
646 else if (SPRDest && GPRSrc)
648 else if (ARM::DPRRegClass.contains(DestReg, SrcReg))
650 else if (ARM::QPRRegClass.contains(DestReg, SrcReg))
654 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(Opc), DestReg);
655 MIB.addReg(SrcReg, getKillRegState(KillSrc));
656 if (Opc == ARM::VORRq)
657 MIB.addReg(SrcReg, getKillRegState(KillSrc));
662 // Generate instructions for VMOVQQ and VMOVQQQQ pseudos in place.
663 if (ARM::QQPRRegClass.contains(DestReg, SrcReg) ||
664 ARM::QQQQPRRegClass.contains(DestReg, SrcReg)) {
665 const TargetRegisterInfo *TRI = &getRegisterInfo();
666 assert(ARM::qsub_0 + 3 == ARM::qsub_3 && "Expected contiguous enum.");
667 unsigned EndSubReg = ARM::QQPRRegClass.contains(DestReg, SrcReg) ?
668 ARM::qsub_1 : ARM::qsub_3;
669 for (unsigned i = ARM::qsub_0, e = EndSubReg + 1; i != e; ++i) {
670 unsigned Dst = TRI->getSubReg(DestReg, i);
671 unsigned Src = TRI->getSubReg(SrcReg, i);
672 MachineInstrBuilder Mov =
673 AddDefaultPred(BuildMI(MBB, I, I->getDebugLoc(), get(ARM::VORRq))
674 .addReg(Dst, RegState::Define)
675 .addReg(Src, getKillRegState(KillSrc))
676 .addReg(Src, getKillRegState(KillSrc)));
677 if (i == EndSubReg) {
678 Mov->addRegisterDefined(DestReg, TRI);
680 Mov->addRegisterKilled(SrcReg, TRI);
685 llvm_unreachable("Impossible reg-to-reg copy");
689 MachineInstrBuilder &AddDReg(MachineInstrBuilder &MIB,
690 unsigned Reg, unsigned SubIdx, unsigned State,
691 const TargetRegisterInfo *TRI) {
693 return MIB.addReg(Reg, State);
695 if (TargetRegisterInfo::isPhysicalRegister(Reg))
696 return MIB.addReg(TRI->getSubReg(Reg, SubIdx), State);
697 return MIB.addReg(Reg, State, SubIdx);
700 void ARMBaseInstrInfo::
701 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
702 unsigned SrcReg, bool isKill, int FI,
703 const TargetRegisterClass *RC,
704 const TargetRegisterInfo *TRI) const {
706 if (I != MBB.end()) DL = I->getDebugLoc();
707 MachineFunction &MF = *MBB.getParent();
708 MachineFrameInfo &MFI = *MF.getFrameInfo();
709 unsigned Align = MFI.getObjectAlignment(FI);
711 MachineMemOperand *MMO =
712 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(FI),
713 MachineMemOperand::MOStore,
714 MFI.getObjectSize(FI),
717 switch (RC->getSize()) {
719 if (ARM::GPRRegClass.hasSubClassEq(RC)) {
720 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::STRi12))
721 .addReg(SrcReg, getKillRegState(isKill))
722 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
723 } else if (ARM::SPRRegClass.hasSubClassEq(RC)) {
724 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTRS))
725 .addReg(SrcReg, getKillRegState(isKill))
726 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
728 llvm_unreachable("Unknown reg class!");
731 if (ARM::DPRRegClass.hasSubClassEq(RC)) {
732 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTRD))
733 .addReg(SrcReg, getKillRegState(isKill))
734 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
736 llvm_unreachable("Unknown reg class!");
739 if (ARM::QPRRegClass.hasSubClassEq(RC)) {
740 if (Align >= 16 && getRegisterInfo().needsStackRealignment(MF)) {
741 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VST1q64Pseudo))
742 .addFrameIndex(FI).addImm(16)
743 .addReg(SrcReg, getKillRegState(isKill))
744 .addMemOperand(MMO));
746 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTMQIA))
747 .addReg(SrcReg, getKillRegState(isKill))
749 .addMemOperand(MMO));
752 llvm_unreachable("Unknown reg class!");
755 if (ARM::QQPRRegClass.hasSubClassEq(RC)) {
756 if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) {
757 // FIXME: It's possible to only store part of the QQ register if the
758 // spilled def has a sub-register index.
759 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VST1d64QPseudo))
760 .addFrameIndex(FI).addImm(16)
761 .addReg(SrcReg, getKillRegState(isKill))
762 .addMemOperand(MMO));
764 MachineInstrBuilder MIB =
765 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTMDIA))
768 MIB = AddDReg(MIB, SrcReg, ARM::dsub_0, getKillRegState(isKill), TRI);
769 MIB = AddDReg(MIB, SrcReg, ARM::dsub_1, 0, TRI);
770 MIB = AddDReg(MIB, SrcReg, ARM::dsub_2, 0, TRI);
771 AddDReg(MIB, SrcReg, ARM::dsub_3, 0, TRI);
774 llvm_unreachable("Unknown reg class!");
777 if (ARM::QQQQPRRegClass.hasSubClassEq(RC)) {
778 MachineInstrBuilder MIB =
779 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTMDIA))
782 MIB = AddDReg(MIB, SrcReg, ARM::dsub_0, getKillRegState(isKill), TRI);
783 MIB = AddDReg(MIB, SrcReg, ARM::dsub_1, 0, TRI);
784 MIB = AddDReg(MIB, SrcReg, ARM::dsub_2, 0, TRI);
785 MIB = AddDReg(MIB, SrcReg, ARM::dsub_3, 0, TRI);
786 MIB = AddDReg(MIB, SrcReg, ARM::dsub_4, 0, TRI);
787 MIB = AddDReg(MIB, SrcReg, ARM::dsub_5, 0, TRI);
788 MIB = AddDReg(MIB, SrcReg, ARM::dsub_6, 0, TRI);
789 AddDReg(MIB, SrcReg, ARM::dsub_7, 0, TRI);
791 llvm_unreachable("Unknown reg class!");
794 llvm_unreachable("Unknown reg class!");
799 ARMBaseInstrInfo::isStoreToStackSlot(const MachineInstr *MI,
800 int &FrameIndex) const {
801 switch (MI->getOpcode()) {
804 case ARM::t2STRs: // FIXME: don't use t2STRs to access frame.
805 if (MI->getOperand(1).isFI() &&
806 MI->getOperand(2).isReg() &&
807 MI->getOperand(3).isImm() &&
808 MI->getOperand(2).getReg() == 0 &&
809 MI->getOperand(3).getImm() == 0) {
810 FrameIndex = MI->getOperand(1).getIndex();
811 return MI->getOperand(0).getReg();
819 if (MI->getOperand(1).isFI() &&
820 MI->getOperand(2).isImm() &&
821 MI->getOperand(2).getImm() == 0) {
822 FrameIndex = MI->getOperand(1).getIndex();
823 return MI->getOperand(0).getReg();
826 case ARM::VST1q64Pseudo:
827 if (MI->getOperand(0).isFI() &&
828 MI->getOperand(2).getSubReg() == 0) {
829 FrameIndex = MI->getOperand(0).getIndex();
830 return MI->getOperand(2).getReg();
834 if (MI->getOperand(1).isFI() &&
835 MI->getOperand(0).getSubReg() == 0) {
836 FrameIndex = MI->getOperand(1).getIndex();
837 return MI->getOperand(0).getReg();
845 unsigned ARMBaseInstrInfo::isStoreToStackSlotPostFE(const MachineInstr *MI,
846 int &FrameIndex) const {
847 const MachineMemOperand *Dummy;
848 return MI->getDesc().mayStore() && hasStoreToStackSlot(MI, Dummy, FrameIndex);
851 void ARMBaseInstrInfo::
852 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
853 unsigned DestReg, int FI,
854 const TargetRegisterClass *RC,
855 const TargetRegisterInfo *TRI) const {
857 if (I != MBB.end()) DL = I->getDebugLoc();
858 MachineFunction &MF = *MBB.getParent();
859 MachineFrameInfo &MFI = *MF.getFrameInfo();
860 unsigned Align = MFI.getObjectAlignment(FI);
861 MachineMemOperand *MMO =
862 MF.getMachineMemOperand(
863 MachinePointerInfo::getFixedStack(FI),
864 MachineMemOperand::MOLoad,
865 MFI.getObjectSize(FI),
868 switch (RC->getSize()) {
870 if (ARM::GPRRegClass.hasSubClassEq(RC)) {
871 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::LDRi12), DestReg)
872 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
874 } else if (ARM::SPRRegClass.hasSubClassEq(RC)) {
875 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDRS), DestReg)
876 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
878 llvm_unreachable("Unknown reg class!");
881 if (ARM::DPRRegClass.hasSubClassEq(RC)) {
882 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDRD), DestReg)
883 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
885 llvm_unreachable("Unknown reg class!");
888 if (ARM::QPRRegClass.hasSubClassEq(RC)) {
889 if (Align >= 16 && getRegisterInfo().needsStackRealignment(MF)) {
890 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLD1q64Pseudo), DestReg)
891 .addFrameIndex(FI).addImm(16)
892 .addMemOperand(MMO));
894 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDMQIA), DestReg)
896 .addMemOperand(MMO));
899 llvm_unreachable("Unknown reg class!");
902 if (ARM::QQPRRegClass.hasSubClassEq(RC)) {
903 if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) {
904 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLD1d64QPseudo), DestReg)
905 .addFrameIndex(FI).addImm(16)
906 .addMemOperand(MMO));
908 MachineInstrBuilder MIB =
909 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDMDIA))
912 MIB = AddDReg(MIB, DestReg, ARM::dsub_0, RegState::Define, TRI);
913 MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::Define, TRI);
914 MIB = AddDReg(MIB, DestReg, ARM::dsub_2, RegState::Define, TRI);
915 MIB = AddDReg(MIB, DestReg, ARM::dsub_3, RegState::Define, TRI);
916 MIB.addReg(DestReg, RegState::Define | RegState::Implicit);
919 llvm_unreachable("Unknown reg class!");
922 if (ARM::QQQQPRRegClass.hasSubClassEq(RC)) {
923 MachineInstrBuilder MIB =
924 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDMDIA))
927 MIB = AddDReg(MIB, DestReg, ARM::dsub_0, RegState::Define, TRI);
928 MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::Define, TRI);
929 MIB = AddDReg(MIB, DestReg, ARM::dsub_2, RegState::Define, TRI);
930 MIB = AddDReg(MIB, DestReg, ARM::dsub_3, RegState::Define, TRI);
931 MIB = AddDReg(MIB, DestReg, ARM::dsub_4, RegState::Define, TRI);
932 MIB = AddDReg(MIB, DestReg, ARM::dsub_5, RegState::Define, TRI);
933 MIB = AddDReg(MIB, DestReg, ARM::dsub_6, RegState::Define, TRI);
934 MIB = AddDReg(MIB, DestReg, ARM::dsub_7, RegState::Define, TRI);
935 MIB.addReg(DestReg, RegState::Define | RegState::Implicit);
937 llvm_unreachable("Unknown reg class!");
940 llvm_unreachable("Unknown regclass!");
945 ARMBaseInstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
946 int &FrameIndex) const {
947 switch (MI->getOpcode()) {
950 case ARM::t2LDRs: // FIXME: don't use t2LDRs to access frame.
951 if (MI->getOperand(1).isFI() &&
952 MI->getOperand(2).isReg() &&
953 MI->getOperand(3).isImm() &&
954 MI->getOperand(2).getReg() == 0 &&
955 MI->getOperand(3).getImm() == 0) {
956 FrameIndex = MI->getOperand(1).getIndex();
957 return MI->getOperand(0).getReg();
965 if (MI->getOperand(1).isFI() &&
966 MI->getOperand(2).isImm() &&
967 MI->getOperand(2).getImm() == 0) {
968 FrameIndex = MI->getOperand(1).getIndex();
969 return MI->getOperand(0).getReg();
972 case ARM::VLD1q64Pseudo:
973 if (MI->getOperand(1).isFI() &&
974 MI->getOperand(0).getSubReg() == 0) {
975 FrameIndex = MI->getOperand(1).getIndex();
976 return MI->getOperand(0).getReg();
980 if (MI->getOperand(1).isFI() &&
981 MI->getOperand(0).getSubReg() == 0) {
982 FrameIndex = MI->getOperand(1).getIndex();
983 return MI->getOperand(0).getReg();
991 unsigned ARMBaseInstrInfo::isLoadFromStackSlotPostFE(const MachineInstr *MI,
992 int &FrameIndex) const {
993 const MachineMemOperand *Dummy;
994 return MI->getDesc().mayLoad() && hasLoadFromStackSlot(MI, Dummy, FrameIndex);
997 bool ARMBaseInstrInfo::expandPostRAPseudo(MachineBasicBlock::iterator MI) const{
998 // This hook gets to expand COPY instructions before they become
999 // copyPhysReg() calls. Look for VMOVS instructions that can legally be
1000 // widened to VMOVD. We prefer the VMOVD when possible because it may be
1001 // changed into a VORR that can go down the NEON pipeline.
1002 if (!WidenVMOVS || !MI->isCopy())
1005 // Look for a copy between even S-registers. That is where we keep floats
1006 // when using NEON v2f32 instructions for f32 arithmetic.
1007 unsigned DstRegS = MI->getOperand(0).getReg();
1008 unsigned SrcRegS = MI->getOperand(1).getReg();
1009 if (!ARM::SPRRegClass.contains(DstRegS, SrcRegS))
1012 const TargetRegisterInfo *TRI = &getRegisterInfo();
1013 unsigned DstRegD = TRI->getMatchingSuperReg(DstRegS, ARM::ssub_0,
1015 unsigned SrcRegD = TRI->getMatchingSuperReg(SrcRegS, ARM::ssub_0,
1017 if (!DstRegD || !SrcRegD)
1020 // We want to widen this into a DstRegD = VMOVD SrcRegD copy. This is only
1021 // legal if the COPY already defines the full DstRegD, and it isn't a
1022 // sub-register insertion.
1023 if (!MI->definesRegister(DstRegD, TRI) || MI->readsRegister(DstRegD, TRI))
1026 // A dead copy shouldn't show up here, but reject it just in case.
1027 if (MI->getOperand(0).isDead())
1030 // All clear, widen the COPY.
1031 DEBUG(dbgs() << "widening: " << *MI);
1033 // Get rid of the old <imp-def> of DstRegD. Leave it if it defines a Q-reg
1034 // or some other super-register.
1035 int ImpDefIdx = MI->findRegisterDefOperandIdx(DstRegD);
1036 if (ImpDefIdx != -1)
1037 MI->RemoveOperand(ImpDefIdx);
1039 // Change the opcode and operands.
1040 MI->setDesc(get(ARM::VMOVD));
1041 MI->getOperand(0).setReg(DstRegD);
1042 MI->getOperand(1).setReg(SrcRegD);
1043 AddDefaultPred(MachineInstrBuilder(MI));
1045 // We are now reading SrcRegD instead of SrcRegS. This may upset the
1046 // register scavenger and machine verifier, so we need to indicate that we
1047 // are reading an undefined value from SrcRegD, but a proper value from
1049 MI->getOperand(1).setIsUndef();
1050 MachineInstrBuilder(MI).addReg(SrcRegS, RegState::Implicit);
1052 // SrcRegD may actually contain an unrelated value in the ssub_1
1053 // sub-register. Don't kill it. Only kill the ssub_0 sub-register.
1054 if (MI->getOperand(1).isKill()) {
1055 MI->getOperand(1).setIsKill(false);
1056 MI->addRegisterKilled(SrcRegS, TRI, true);
1059 DEBUG(dbgs() << "replaced by: " << *MI);
1064 ARMBaseInstrInfo::emitFrameIndexDebugValue(MachineFunction &MF,
1065 int FrameIx, uint64_t Offset,
1066 const MDNode *MDPtr,
1067 DebugLoc DL) const {
1068 MachineInstrBuilder MIB = BuildMI(MF, DL, get(ARM::DBG_VALUE))
1069 .addFrameIndex(FrameIx).addImm(0).addImm(Offset).addMetadata(MDPtr);
1073 /// Create a copy of a const pool value. Update CPI to the new index and return
1075 static unsigned duplicateCPV(MachineFunction &MF, unsigned &CPI) {
1076 MachineConstantPool *MCP = MF.getConstantPool();
1077 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1079 const MachineConstantPoolEntry &MCPE = MCP->getConstants()[CPI];
1080 assert(MCPE.isMachineConstantPoolEntry() &&
1081 "Expecting a machine constantpool entry!");
1082 ARMConstantPoolValue *ACPV =
1083 static_cast<ARMConstantPoolValue*>(MCPE.Val.MachineCPVal);
1085 unsigned PCLabelId = AFI->createPICLabelUId();
1086 ARMConstantPoolValue *NewCPV = 0;
1087 // FIXME: The below assumes PIC relocation model and that the function
1088 // is Thumb mode (t1 or t2). PCAdjustment would be 8 for ARM mode PIC, and
1089 // zero for non-PIC in ARM or Thumb. The callers are all of thumb LDR
1090 // instructions, so that's probably OK, but is PIC always correct when
1092 if (ACPV->isGlobalValue())
1093 NewCPV = ARMConstantPoolConstant::
1094 Create(cast<ARMConstantPoolConstant>(ACPV)->getGV(), PCLabelId,
1096 else if (ACPV->isExtSymbol())
1097 NewCPV = ARMConstantPoolSymbol::
1098 Create(MF.getFunction()->getContext(),
1099 cast<ARMConstantPoolSymbol>(ACPV)->getSymbol(), PCLabelId, 4);
1100 else if (ACPV->isBlockAddress())
1101 NewCPV = ARMConstantPoolConstant::
1102 Create(cast<ARMConstantPoolConstant>(ACPV)->getBlockAddress(), PCLabelId,
1103 ARMCP::CPBlockAddress, 4);
1104 else if (ACPV->isLSDA())
1105 NewCPV = ARMConstantPoolConstant::Create(MF.getFunction(), PCLabelId,
1107 else if (ACPV->isMachineBasicBlock())
1108 NewCPV = ARMConstantPoolMBB::
1109 Create(MF.getFunction()->getContext(),
1110 cast<ARMConstantPoolMBB>(ACPV)->getMBB(), PCLabelId, 4);
1112 llvm_unreachable("Unexpected ARM constantpool value type!!");
1113 CPI = MCP->getConstantPoolIndex(NewCPV, MCPE.getAlignment());
1117 void ARMBaseInstrInfo::
1118 reMaterialize(MachineBasicBlock &MBB,
1119 MachineBasicBlock::iterator I,
1120 unsigned DestReg, unsigned SubIdx,
1121 const MachineInstr *Orig,
1122 const TargetRegisterInfo &TRI) const {
1123 unsigned Opcode = Orig->getOpcode();
1126 MachineInstr *MI = MBB.getParent()->CloneMachineInstr(Orig);
1127 MI->substituteRegister(Orig->getOperand(0).getReg(), DestReg, SubIdx, TRI);
1131 case ARM::tLDRpci_pic:
1132 case ARM::t2LDRpci_pic: {
1133 MachineFunction &MF = *MBB.getParent();
1134 unsigned CPI = Orig->getOperand(1).getIndex();
1135 unsigned PCLabelId = duplicateCPV(MF, CPI);
1136 MachineInstrBuilder MIB = BuildMI(MBB, I, Orig->getDebugLoc(), get(Opcode),
1138 .addConstantPoolIndex(CPI).addImm(PCLabelId);
1139 MIB->setMemRefs(Orig->memoperands_begin(), Orig->memoperands_end());
1146 ARMBaseInstrInfo::duplicate(MachineInstr *Orig, MachineFunction &MF) const {
1147 MachineInstr *MI = TargetInstrInfoImpl::duplicate(Orig, MF);
1148 switch(Orig->getOpcode()) {
1149 case ARM::tLDRpci_pic:
1150 case ARM::t2LDRpci_pic: {
1151 unsigned CPI = Orig->getOperand(1).getIndex();
1152 unsigned PCLabelId = duplicateCPV(MF, CPI);
1153 Orig->getOperand(1).setIndex(CPI);
1154 Orig->getOperand(2).setImm(PCLabelId);
1161 bool ARMBaseInstrInfo::produceSameValue(const MachineInstr *MI0,
1162 const MachineInstr *MI1,
1163 const MachineRegisterInfo *MRI) const {
1164 int Opcode = MI0->getOpcode();
1165 if (Opcode == ARM::t2LDRpci ||
1166 Opcode == ARM::t2LDRpci_pic ||
1167 Opcode == ARM::tLDRpci ||
1168 Opcode == ARM::tLDRpci_pic ||
1169 Opcode == ARM::MOV_ga_dyn ||
1170 Opcode == ARM::MOV_ga_pcrel ||
1171 Opcode == ARM::MOV_ga_pcrel_ldr ||
1172 Opcode == ARM::t2MOV_ga_dyn ||
1173 Opcode == ARM::t2MOV_ga_pcrel) {
1174 if (MI1->getOpcode() != Opcode)
1176 if (MI0->getNumOperands() != MI1->getNumOperands())
1179 const MachineOperand &MO0 = MI0->getOperand(1);
1180 const MachineOperand &MO1 = MI1->getOperand(1);
1181 if (MO0.getOffset() != MO1.getOffset())
1184 if (Opcode == ARM::MOV_ga_dyn ||
1185 Opcode == ARM::MOV_ga_pcrel ||
1186 Opcode == ARM::MOV_ga_pcrel_ldr ||
1187 Opcode == ARM::t2MOV_ga_dyn ||
1188 Opcode == ARM::t2MOV_ga_pcrel)
1189 // Ignore the PC labels.
1190 return MO0.getGlobal() == MO1.getGlobal();
1192 const MachineFunction *MF = MI0->getParent()->getParent();
1193 const MachineConstantPool *MCP = MF->getConstantPool();
1194 int CPI0 = MO0.getIndex();
1195 int CPI1 = MO1.getIndex();
1196 const MachineConstantPoolEntry &MCPE0 = MCP->getConstants()[CPI0];
1197 const MachineConstantPoolEntry &MCPE1 = MCP->getConstants()[CPI1];
1198 bool isARMCP0 = MCPE0.isMachineConstantPoolEntry();
1199 bool isARMCP1 = MCPE1.isMachineConstantPoolEntry();
1200 if (isARMCP0 && isARMCP1) {
1201 ARMConstantPoolValue *ACPV0 =
1202 static_cast<ARMConstantPoolValue*>(MCPE0.Val.MachineCPVal);
1203 ARMConstantPoolValue *ACPV1 =
1204 static_cast<ARMConstantPoolValue*>(MCPE1.Val.MachineCPVal);
1205 return ACPV0->hasSameValue(ACPV1);
1206 } else if (!isARMCP0 && !isARMCP1) {
1207 return MCPE0.Val.ConstVal == MCPE1.Val.ConstVal;
1210 } else if (Opcode == ARM::PICLDR) {
1211 if (MI1->getOpcode() != Opcode)
1213 if (MI0->getNumOperands() != MI1->getNumOperands())
1216 unsigned Addr0 = MI0->getOperand(1).getReg();
1217 unsigned Addr1 = MI1->getOperand(1).getReg();
1218 if (Addr0 != Addr1) {
1220 !TargetRegisterInfo::isVirtualRegister(Addr0) ||
1221 !TargetRegisterInfo::isVirtualRegister(Addr1))
1224 // This assumes SSA form.
1225 MachineInstr *Def0 = MRI->getVRegDef(Addr0);
1226 MachineInstr *Def1 = MRI->getVRegDef(Addr1);
1227 // Check if the loaded value, e.g. a constantpool of a global address, are
1229 if (!produceSameValue(Def0, Def1, MRI))
1233 for (unsigned i = 3, e = MI0->getNumOperands(); i != e; ++i) {
1234 // %vreg12<def> = PICLDR %vreg11, 0, pred:14, pred:%noreg
1235 const MachineOperand &MO0 = MI0->getOperand(i);
1236 const MachineOperand &MO1 = MI1->getOperand(i);
1237 if (!MO0.isIdenticalTo(MO1))
1243 return MI0->isIdenticalTo(MI1, MachineInstr::IgnoreVRegDefs);
1246 /// areLoadsFromSameBasePtr - This is used by the pre-regalloc scheduler to
1247 /// determine if two loads are loading from the same base address. It should
1248 /// only return true if the base pointers are the same and the only differences
1249 /// between the two addresses is the offset. It also returns the offsets by
1251 bool ARMBaseInstrInfo::areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2,
1253 int64_t &Offset2) const {
1254 // Don't worry about Thumb: just ARM and Thumb2.
1255 if (Subtarget.isThumb1Only()) return false;
1257 if (!Load1->isMachineOpcode() || !Load2->isMachineOpcode())
1260 switch (Load1->getMachineOpcode()) {
1273 case ARM::t2LDRSHi8:
1275 case ARM::t2LDRSHi12:
1279 switch (Load2->getMachineOpcode()) {
1292 case ARM::t2LDRSHi8:
1294 case ARM::t2LDRSHi12:
1298 // Check if base addresses and chain operands match.
1299 if (Load1->getOperand(0) != Load2->getOperand(0) ||
1300 Load1->getOperand(4) != Load2->getOperand(4))
1303 // Index should be Reg0.
1304 if (Load1->getOperand(3) != Load2->getOperand(3))
1307 // Determine the offsets.
1308 if (isa<ConstantSDNode>(Load1->getOperand(1)) &&
1309 isa<ConstantSDNode>(Load2->getOperand(1))) {
1310 Offset1 = cast<ConstantSDNode>(Load1->getOperand(1))->getSExtValue();
1311 Offset2 = cast<ConstantSDNode>(Load2->getOperand(1))->getSExtValue();
1318 /// shouldScheduleLoadsNear - This is a used by the pre-regalloc scheduler to
1319 /// determine (in conjunction with areLoadsFromSameBasePtr) if two loads should
1320 /// be scheduled togther. On some targets if two loads are loading from
1321 /// addresses in the same cache line, it's better if they are scheduled
1322 /// together. This function takes two integers that represent the load offsets
1323 /// from the common base address. It returns true if it decides it's desirable
1324 /// to schedule the two loads together. "NumLoads" is the number of loads that
1325 /// have already been scheduled after Load1.
1326 bool ARMBaseInstrInfo::shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,
1327 int64_t Offset1, int64_t Offset2,
1328 unsigned NumLoads) const {
1329 // Don't worry about Thumb: just ARM and Thumb2.
1330 if (Subtarget.isThumb1Only()) return false;
1332 assert(Offset2 > Offset1);
1334 if ((Offset2 - Offset1) / 8 > 64)
1337 if (Load1->getMachineOpcode() != Load2->getMachineOpcode())
1338 return false; // FIXME: overly conservative?
1340 // Four loads in a row should be sufficient.
1347 bool ARMBaseInstrInfo::isSchedulingBoundary(const MachineInstr *MI,
1348 const MachineBasicBlock *MBB,
1349 const MachineFunction &MF) const {
1350 // Debug info is never a scheduling boundary. It's necessary to be explicit
1351 // due to the special treatment of IT instructions below, otherwise a
1352 // dbg_value followed by an IT will result in the IT instruction being
1353 // considered a scheduling hazard, which is wrong. It should be the actual
1354 // instruction preceding the dbg_value instruction(s), just like it is
1355 // when debug info is not present.
1356 if (MI->isDebugValue())
1359 // Terminators and labels can't be scheduled around.
1360 if (MI->getDesc().isTerminator() || MI->isLabel())
1363 // Treat the start of the IT block as a scheduling boundary, but schedule
1364 // t2IT along with all instructions following it.
1365 // FIXME: This is a big hammer. But the alternative is to add all potential
1366 // true and anti dependencies to IT block instructions as implicit operands
1367 // to the t2IT instruction. The added compile time and complexity does not
1369 MachineBasicBlock::const_iterator I = MI;
1370 // Make sure to skip any dbg_value instructions
1371 while (++I != MBB->end() && I->isDebugValue())
1373 if (I != MBB->end() && I->getOpcode() == ARM::t2IT)
1376 // Don't attempt to schedule around any instruction that defines
1377 // a stack-oriented pointer, as it's unlikely to be profitable. This
1378 // saves compile time, because it doesn't require every single
1379 // stack slot reference to depend on the instruction that does the
1381 if (MI->definesRegister(ARM::SP))
1387 bool ARMBaseInstrInfo::
1388 isProfitableToIfCvt(MachineBasicBlock &MBB,
1389 unsigned NumCycles, unsigned ExtraPredCycles,
1390 const BranchProbability &Probability) const {
1394 // Attempt to estimate the relative costs of predication versus branching.
1395 unsigned UnpredCost = Probability.getNumerator() * NumCycles;
1396 UnpredCost /= Probability.getDenominator();
1397 UnpredCost += 1; // The branch itself
1398 UnpredCost += Subtarget.getMispredictionPenalty() / 10;
1400 return (NumCycles + ExtraPredCycles) <= UnpredCost;
1403 bool ARMBaseInstrInfo::
1404 isProfitableToIfCvt(MachineBasicBlock &TMBB,
1405 unsigned TCycles, unsigned TExtra,
1406 MachineBasicBlock &FMBB,
1407 unsigned FCycles, unsigned FExtra,
1408 const BranchProbability &Probability) const {
1409 if (!TCycles || !FCycles)
1412 // Attempt to estimate the relative costs of predication versus branching.
1413 unsigned TUnpredCost = Probability.getNumerator() * TCycles;
1414 TUnpredCost /= Probability.getDenominator();
1416 uint32_t Comp = Probability.getDenominator() - Probability.getNumerator();
1417 unsigned FUnpredCost = Comp * FCycles;
1418 FUnpredCost /= Probability.getDenominator();
1420 unsigned UnpredCost = TUnpredCost + FUnpredCost;
1421 UnpredCost += 1; // The branch itself
1422 UnpredCost += Subtarget.getMispredictionPenalty() / 10;
1424 return (TCycles + FCycles + TExtra + FExtra) <= UnpredCost;
1427 /// getInstrPredicate - If instruction is predicated, returns its predicate
1428 /// condition, otherwise returns AL. It also returns the condition code
1429 /// register by reference.
1431 llvm::getInstrPredicate(const MachineInstr *MI, unsigned &PredReg) {
1432 int PIdx = MI->findFirstPredOperandIdx();
1438 PredReg = MI->getOperand(PIdx+1).getReg();
1439 return (ARMCC::CondCodes)MI->getOperand(PIdx).getImm();
1443 int llvm::getMatchingCondBranchOpcode(int Opc) {
1446 else if (Opc == ARM::tB)
1448 else if (Opc == ARM::t2B)
1451 llvm_unreachable("Unknown unconditional branch opcode!");
1456 /// Map pseudo instructions that imply an 'S' bit onto real opcodes. Whether the
1457 /// instruction is encoded with an 'S' bit is determined by the optional CPSR
1460 /// This will go away once we can teach tblgen how to set the optional CPSR def
1462 struct AddSubFlagsOpcodePair {
1464 unsigned MachineOpc;
1467 static AddSubFlagsOpcodePair AddSubFlagsOpcodeMap[] = {
1468 {ARM::ADDSri, ARM::ADDri},
1469 {ARM::ADDSrr, ARM::ADDrr},
1470 {ARM::ADDSrsi, ARM::ADDrsi},
1471 {ARM::ADDSrsr, ARM::ADDrsr},
1473 {ARM::SUBSri, ARM::SUBri},
1474 {ARM::SUBSrr, ARM::SUBrr},
1475 {ARM::SUBSrsi, ARM::SUBrsi},
1476 {ARM::SUBSrsr, ARM::SUBrsr},
1478 {ARM::RSBSri, ARM::RSBri},
1479 {ARM::RSBSrsi, ARM::RSBrsi},
1480 {ARM::RSBSrsr, ARM::RSBrsr},
1482 {ARM::t2ADDSri, ARM::t2ADDri},
1483 {ARM::t2ADDSrr, ARM::t2ADDrr},
1484 {ARM::t2ADDSrs, ARM::t2ADDrs},
1486 {ARM::t2SUBSri, ARM::t2SUBri},
1487 {ARM::t2SUBSrr, ARM::t2SUBrr},
1488 {ARM::t2SUBSrs, ARM::t2SUBrs},
1490 {ARM::t2RSBSri, ARM::t2RSBri},
1491 {ARM::t2RSBSrs, ARM::t2RSBrs},
1494 unsigned llvm::convertAddSubFlagsOpcode(unsigned OldOpc) {
1495 static const int NPairs =
1496 sizeof(AddSubFlagsOpcodeMap) / sizeof(AddSubFlagsOpcodePair);
1497 for (AddSubFlagsOpcodePair *OpcPair = &AddSubFlagsOpcodeMap[0],
1498 *End = &AddSubFlagsOpcodeMap[NPairs]; OpcPair != End; ++OpcPair) {
1499 if (OldOpc == OpcPair->PseudoOpc) {
1500 return OpcPair->MachineOpc;
1506 void llvm::emitARMRegPlusImmediate(MachineBasicBlock &MBB,
1507 MachineBasicBlock::iterator &MBBI, DebugLoc dl,
1508 unsigned DestReg, unsigned BaseReg, int NumBytes,
1509 ARMCC::CondCodes Pred, unsigned PredReg,
1510 const ARMBaseInstrInfo &TII, unsigned MIFlags) {
1511 bool isSub = NumBytes < 0;
1512 if (isSub) NumBytes = -NumBytes;
1515 unsigned RotAmt = ARM_AM::getSOImmValRotate(NumBytes);
1516 unsigned ThisVal = NumBytes & ARM_AM::rotr32(0xFF, RotAmt);
1517 assert(ThisVal && "Didn't extract field correctly");
1519 // We will handle these bits from offset, clear them.
1520 NumBytes &= ~ThisVal;
1522 assert(ARM_AM::getSOImmVal(ThisVal) != -1 && "Bit extraction didn't work?");
1524 // Build the new ADD / SUB.
1525 unsigned Opc = isSub ? ARM::SUBri : ARM::ADDri;
1526 BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg)
1527 .addReg(BaseReg, RegState::Kill).addImm(ThisVal)
1528 .addImm((unsigned)Pred).addReg(PredReg).addReg(0)
1529 .setMIFlags(MIFlags);
1534 bool llvm::rewriteARMFrameIndex(MachineInstr &MI, unsigned FrameRegIdx,
1535 unsigned FrameReg, int &Offset,
1536 const ARMBaseInstrInfo &TII) {
1537 unsigned Opcode = MI.getOpcode();
1538 const MCInstrDesc &Desc = MI.getDesc();
1539 unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
1542 // Memory operands in inline assembly always use AddrMode2.
1543 if (Opcode == ARM::INLINEASM)
1544 AddrMode = ARMII::AddrMode2;
1546 if (Opcode == ARM::ADDri) {
1547 Offset += MI.getOperand(FrameRegIdx+1).getImm();
1549 // Turn it into a move.
1550 MI.setDesc(TII.get(ARM::MOVr));
1551 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
1552 MI.RemoveOperand(FrameRegIdx+1);
1555 } else if (Offset < 0) {
1558 MI.setDesc(TII.get(ARM::SUBri));
1561 // Common case: small offset, fits into instruction.
1562 if (ARM_AM::getSOImmVal(Offset) != -1) {
1563 // Replace the FrameIndex with sp / fp
1564 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
1565 MI.getOperand(FrameRegIdx+1).ChangeToImmediate(Offset);
1570 // Otherwise, pull as much of the immedidate into this ADDri/SUBri
1572 unsigned RotAmt = ARM_AM::getSOImmValRotate(Offset);
1573 unsigned ThisImmVal = Offset & ARM_AM::rotr32(0xFF, RotAmt);
1575 // We will handle these bits from offset, clear them.
1576 Offset &= ~ThisImmVal;
1578 // Get the properly encoded SOImmVal field.
1579 assert(ARM_AM::getSOImmVal(ThisImmVal) != -1 &&
1580 "Bit extraction didn't work?");
1581 MI.getOperand(FrameRegIdx+1).ChangeToImmediate(ThisImmVal);
1583 unsigned ImmIdx = 0;
1585 unsigned NumBits = 0;
1588 case ARMII::AddrMode_i12: {
1589 ImmIdx = FrameRegIdx + 1;
1590 InstrOffs = MI.getOperand(ImmIdx).getImm();
1594 case ARMII::AddrMode2: {
1595 ImmIdx = FrameRegIdx+2;
1596 InstrOffs = ARM_AM::getAM2Offset(MI.getOperand(ImmIdx).getImm());
1597 if (ARM_AM::getAM2Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub)
1602 case ARMII::AddrMode3: {
1603 ImmIdx = FrameRegIdx+2;
1604 InstrOffs = ARM_AM::getAM3Offset(MI.getOperand(ImmIdx).getImm());
1605 if (ARM_AM::getAM3Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub)
1610 case ARMII::AddrMode4:
1611 case ARMII::AddrMode6:
1612 // Can't fold any offset even if it's zero.
1614 case ARMII::AddrMode5: {
1615 ImmIdx = FrameRegIdx+1;
1616 InstrOffs = ARM_AM::getAM5Offset(MI.getOperand(ImmIdx).getImm());
1617 if (ARM_AM::getAM5Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub)
1624 llvm_unreachable("Unsupported addressing mode!");
1628 Offset += InstrOffs * Scale;
1629 assert((Offset & (Scale-1)) == 0 && "Can't encode this offset!");
1635 // Attempt to fold address comp. if opcode has offset bits
1637 // Common case: small offset, fits into instruction.
1638 MachineOperand &ImmOp = MI.getOperand(ImmIdx);
1639 int ImmedOffset = Offset / Scale;
1640 unsigned Mask = (1 << NumBits) - 1;
1641 if ((unsigned)Offset <= Mask * Scale) {
1642 // Replace the FrameIndex with sp
1643 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
1644 // FIXME: When addrmode2 goes away, this will simplify (like the
1645 // T2 version), as the LDR.i12 versions don't need the encoding
1646 // tricks for the offset value.
1648 if (AddrMode == ARMII::AddrMode_i12)
1649 ImmedOffset = -ImmedOffset;
1651 ImmedOffset |= 1 << NumBits;
1653 ImmOp.ChangeToImmediate(ImmedOffset);
1658 // Otherwise, it didn't fit. Pull in what we can to simplify the immed.
1659 ImmedOffset = ImmedOffset & Mask;
1661 if (AddrMode == ARMII::AddrMode_i12)
1662 ImmedOffset = -ImmedOffset;
1664 ImmedOffset |= 1 << NumBits;
1666 ImmOp.ChangeToImmediate(ImmedOffset);
1667 Offset &= ~(Mask*Scale);
1671 Offset = (isSub) ? -Offset : Offset;
1675 bool ARMBaseInstrInfo::
1676 AnalyzeCompare(const MachineInstr *MI, unsigned &SrcReg, int &CmpMask,
1677 int &CmpValue) const {
1678 switch (MI->getOpcode()) {
1682 SrcReg = MI->getOperand(0).getReg();
1684 CmpValue = MI->getOperand(1).getImm();
1688 SrcReg = MI->getOperand(0).getReg();
1689 CmpMask = MI->getOperand(1).getImm();
1697 /// isSuitableForMask - Identify a suitable 'and' instruction that
1698 /// operates on the given source register and applies the same mask
1699 /// as a 'tst' instruction. Provide a limited look-through for copies.
1700 /// When successful, MI will hold the found instruction.
1701 static bool isSuitableForMask(MachineInstr *&MI, unsigned SrcReg,
1702 int CmpMask, bool CommonUse) {
1703 switch (MI->getOpcode()) {
1706 if (CmpMask != MI->getOperand(2).getImm())
1708 if (SrcReg == MI->getOperand(CommonUse ? 1 : 0).getReg())
1712 // Walk down one instruction which is potentially an 'and'.
1713 const MachineInstr &Copy = *MI;
1714 MachineBasicBlock::iterator AND(
1715 llvm::next(MachineBasicBlock::iterator(MI)));
1716 if (AND == MI->getParent()->end()) return false;
1718 return isSuitableForMask(MI, Copy.getOperand(0).getReg(),
1726 /// OptimizeCompareInstr - Convert the instruction supplying the argument to the
1727 /// comparison into one that sets the zero bit in the flags register.
1728 bool ARMBaseInstrInfo::
1729 OptimizeCompareInstr(MachineInstr *CmpInstr, unsigned SrcReg, int CmpMask,
1730 int CmpValue, const MachineRegisterInfo *MRI) const {
1734 MachineRegisterInfo::def_iterator DI = MRI->def_begin(SrcReg);
1735 if (llvm::next(DI) != MRI->def_end())
1736 // Only support one definition.
1739 MachineInstr *MI = &*DI;
1741 // Masked compares sometimes use the same register as the corresponding 'and'.
1742 if (CmpMask != ~0) {
1743 if (!isSuitableForMask(MI, SrcReg, CmpMask, false)) {
1745 for (MachineRegisterInfo::use_iterator UI = MRI->use_begin(SrcReg),
1746 UE = MRI->use_end(); UI != UE; ++UI) {
1747 if (UI->getParent() != CmpInstr->getParent()) continue;
1748 MachineInstr *PotentialAND = &*UI;
1749 if (!isSuitableForMask(PotentialAND, SrcReg, CmpMask, true))
1754 if (!MI) return false;
1758 // Conservatively refuse to convert an instruction which isn't in the same BB
1759 // as the comparison.
1760 if (MI->getParent() != CmpInstr->getParent())
1763 // Check that CPSR isn't set between the comparison instruction and the one we
1765 MachineBasicBlock::const_iterator I = CmpInstr, E = MI,
1766 B = MI->getParent()->begin();
1768 // Early exit if CmpInstr is at the beginning of the BB.
1769 if (I == B) return false;
1772 for (; I != E; --I) {
1773 const MachineInstr &Instr = *I;
1775 for (unsigned IO = 0, EO = Instr.getNumOperands(); IO != EO; ++IO) {
1776 const MachineOperand &MO = Instr.getOperand(IO);
1777 if (!MO.isReg()) continue;
1779 // This instruction modifies or uses CPSR after the one we want to
1780 // change. We can't do this transformation.
1781 if (MO.getReg() == ARM::CPSR)
1786 // The 'and' is below the comparison instruction.
1790 // Set the "zero" bit in CPSR.
1791 switch (MI->getOpcode()) {
1825 case ARM::t2EORri: {
1826 // Scan forward for the use of CPSR, if it's a conditional code requires
1827 // checking of V bit, then this is not safe to do. If we can't find the
1828 // CPSR use (i.e. used in another block), then it's not safe to perform
1829 // the optimization.
1830 bool isSafe = false;
1832 E = MI->getParent()->end();
1833 while (!isSafe && ++I != E) {
1834 const MachineInstr &Instr = *I;
1835 for (unsigned IO = 0, EO = Instr.getNumOperands();
1836 !isSafe && IO != EO; ++IO) {
1837 const MachineOperand &MO = Instr.getOperand(IO);
1838 if (!MO.isReg() || MO.getReg() != ARM::CPSR)
1844 // Condition code is after the operand before CPSR.
1845 ARMCC::CondCodes CC = (ARMCC::CondCodes)Instr.getOperand(IO-1).getImm();
1864 // Toggle the optional operand to CPSR.
1865 MI->getOperand(5).setReg(ARM::CPSR);
1866 MI->getOperand(5).setIsDef(true);
1867 CmpInstr->eraseFromParent();
1875 bool ARMBaseInstrInfo::FoldImmediate(MachineInstr *UseMI,
1876 MachineInstr *DefMI, unsigned Reg,
1877 MachineRegisterInfo *MRI) const {
1878 // Fold large immediates into add, sub, or, xor.
1879 unsigned DefOpc = DefMI->getOpcode();
1880 if (DefOpc != ARM::t2MOVi32imm && DefOpc != ARM::MOVi32imm)
1882 if (!DefMI->getOperand(1).isImm())
1883 // Could be t2MOVi32imm <ga:xx>
1886 if (!MRI->hasOneNonDBGUse(Reg))
1889 unsigned UseOpc = UseMI->getOpcode();
1890 unsigned NewUseOpc = 0;
1891 uint32_t ImmVal = (uint32_t)DefMI->getOperand(1).getImm();
1892 uint32_t SOImmValV1 = 0, SOImmValV2 = 0;
1893 bool Commute = false;
1895 default: return false;
1903 case ARM::t2EORrr: {
1904 Commute = UseMI->getOperand(2).getReg() != Reg;
1911 NewUseOpc = ARM::SUBri;
1917 if (!ARM_AM::isSOImmTwoPartVal(ImmVal))
1919 SOImmValV1 = (uint32_t)ARM_AM::getSOImmTwoPartFirst(ImmVal);
1920 SOImmValV2 = (uint32_t)ARM_AM::getSOImmTwoPartSecond(ImmVal);
1923 case ARM::ADDrr: NewUseOpc = ARM::ADDri; break;
1924 case ARM::ORRrr: NewUseOpc = ARM::ORRri; break;
1925 case ARM::EORrr: NewUseOpc = ARM::EORri; break;
1929 case ARM::t2SUBrr: {
1933 NewUseOpc = ARM::t2SUBri;
1938 case ARM::t2EORrr: {
1939 if (!ARM_AM::isT2SOImmTwoPartVal(ImmVal))
1941 SOImmValV1 = (uint32_t)ARM_AM::getT2SOImmTwoPartFirst(ImmVal);
1942 SOImmValV2 = (uint32_t)ARM_AM::getT2SOImmTwoPartSecond(ImmVal);
1945 case ARM::t2ADDrr: NewUseOpc = ARM::t2ADDri; break;
1946 case ARM::t2ORRrr: NewUseOpc = ARM::t2ORRri; break;
1947 case ARM::t2EORrr: NewUseOpc = ARM::t2EORri; break;
1955 unsigned OpIdx = Commute ? 2 : 1;
1956 unsigned Reg1 = UseMI->getOperand(OpIdx).getReg();
1957 bool isKill = UseMI->getOperand(OpIdx).isKill();
1958 unsigned NewReg = MRI->createVirtualRegister(MRI->getRegClass(Reg));
1959 AddDefaultCC(AddDefaultPred(BuildMI(*UseMI->getParent(),
1960 *UseMI, UseMI->getDebugLoc(),
1961 get(NewUseOpc), NewReg)
1962 .addReg(Reg1, getKillRegState(isKill))
1963 .addImm(SOImmValV1)));
1964 UseMI->setDesc(get(NewUseOpc));
1965 UseMI->getOperand(1).setReg(NewReg);
1966 UseMI->getOperand(1).setIsKill();
1967 UseMI->getOperand(2).ChangeToImmediate(SOImmValV2);
1968 DefMI->eraseFromParent();
1973 ARMBaseInstrInfo::getNumMicroOps(const InstrItineraryData *ItinData,
1974 const MachineInstr *MI) const {
1975 if (!ItinData || ItinData->isEmpty())
1978 const MCInstrDesc &Desc = MI->getDesc();
1979 unsigned Class = Desc.getSchedClass();
1980 unsigned UOps = ItinData->Itineraries[Class].NumMicroOps;
1984 unsigned Opc = MI->getOpcode();
1987 llvm_unreachable("Unexpected multi-uops instruction!");
1993 // The number of uOps for load / store multiple are determined by the number
1996 // On Cortex-A8, each pair of register loads / stores can be scheduled on the
1997 // same cycle. The scheduling for the first load / store must be done
1998 // separately by assuming the the address is not 64-bit aligned.
2000 // On Cortex-A9, the formula is simply (#reg / 2) + (#reg % 2). If the address
2001 // is not 64-bit aligned, then AGU would take an extra cycle. For VFP / NEON
2002 // load / store multiple, the formula is (#reg / 2) + (#reg % 2) + 1.
2004 case ARM::VLDMDIA_UPD:
2005 case ARM::VLDMDDB_UPD:
2007 case ARM::VLDMSIA_UPD:
2008 case ARM::VLDMSDB_UPD:
2010 case ARM::VSTMDIA_UPD:
2011 case ARM::VSTMDDB_UPD:
2013 case ARM::VSTMSIA_UPD:
2014 case ARM::VSTMSDB_UPD: {
2015 unsigned NumRegs = MI->getNumOperands() - Desc.getNumOperands();
2016 return (NumRegs / 2) + (NumRegs % 2) + 1;
2019 case ARM::LDMIA_RET:
2024 case ARM::LDMIA_UPD:
2025 case ARM::LDMDA_UPD:
2026 case ARM::LDMDB_UPD:
2027 case ARM::LDMIB_UPD:
2032 case ARM::STMIA_UPD:
2033 case ARM::STMDA_UPD:
2034 case ARM::STMDB_UPD:
2035 case ARM::STMIB_UPD:
2037 case ARM::tLDMIA_UPD:
2038 case ARM::tSTMIA_UPD:
2042 case ARM::t2LDMIA_RET:
2045 case ARM::t2LDMIA_UPD:
2046 case ARM::t2LDMDB_UPD:
2049 case ARM::t2STMIA_UPD:
2050 case ARM::t2STMDB_UPD: {
2051 unsigned NumRegs = MI->getNumOperands() - Desc.getNumOperands() + 1;
2052 if (Subtarget.isCortexA8()) {
2055 // 4 registers would be issued: 2, 2.
2056 // 5 registers would be issued: 2, 2, 1.
2057 UOps = (NumRegs / 2);
2061 } else if (Subtarget.isCortexA9()) {
2062 UOps = (NumRegs / 2);
2063 // If there are odd number of registers or if it's not 64-bit aligned,
2064 // then it takes an extra AGU (Address Generation Unit) cycle.
2065 if ((NumRegs % 2) ||
2066 !MI->hasOneMemOperand() ||
2067 (*MI->memoperands_begin())->getAlignment() < 8)
2071 // Assume the worst.
2079 ARMBaseInstrInfo::getVLDMDefCycle(const InstrItineraryData *ItinData,
2080 const MCInstrDesc &DefMCID,
2082 unsigned DefIdx, unsigned DefAlign) const {
2083 int RegNo = (int)(DefIdx+1) - DefMCID.getNumOperands() + 1;
2085 // Def is the address writeback.
2086 return ItinData->getOperandCycle(DefClass, DefIdx);
2089 if (Subtarget.isCortexA8()) {
2090 // (regno / 2) + (regno % 2) + 1
2091 DefCycle = RegNo / 2 + 1;
2094 } else if (Subtarget.isCortexA9()) {
2096 bool isSLoad = false;
2098 switch (DefMCID.getOpcode()) {
2101 case ARM::VLDMSIA_UPD:
2102 case ARM::VLDMSDB_UPD:
2107 // If there are odd number of 'S' registers or if it's not 64-bit aligned,
2108 // then it takes an extra cycle.
2109 if ((isSLoad && (RegNo % 2)) || DefAlign < 8)
2112 // Assume the worst.
2113 DefCycle = RegNo + 2;
2120 ARMBaseInstrInfo::getLDMDefCycle(const InstrItineraryData *ItinData,
2121 const MCInstrDesc &DefMCID,
2123 unsigned DefIdx, unsigned DefAlign) const {
2124 int RegNo = (int)(DefIdx+1) - DefMCID.getNumOperands() + 1;
2126 // Def is the address writeback.
2127 return ItinData->getOperandCycle(DefClass, DefIdx);
2130 if (Subtarget.isCortexA8()) {
2131 // 4 registers would be issued: 1, 2, 1.
2132 // 5 registers would be issued: 1, 2, 2.
2133 DefCycle = RegNo / 2;
2136 // Result latency is issue cycle + 2: E2.
2138 } else if (Subtarget.isCortexA9()) {
2139 DefCycle = (RegNo / 2);
2140 // If there are odd number of registers or if it's not 64-bit aligned,
2141 // then it takes an extra AGU (Address Generation Unit) cycle.
2142 if ((RegNo % 2) || DefAlign < 8)
2144 // Result latency is AGU cycles + 2.
2147 // Assume the worst.
2148 DefCycle = RegNo + 2;
2155 ARMBaseInstrInfo::getVSTMUseCycle(const InstrItineraryData *ItinData,
2156 const MCInstrDesc &UseMCID,
2158 unsigned UseIdx, unsigned UseAlign) const {
2159 int RegNo = (int)(UseIdx+1) - UseMCID.getNumOperands() + 1;
2161 return ItinData->getOperandCycle(UseClass, UseIdx);
2164 if (Subtarget.isCortexA8()) {
2165 // (regno / 2) + (regno % 2) + 1
2166 UseCycle = RegNo / 2 + 1;
2169 } else if (Subtarget.isCortexA9()) {
2171 bool isSStore = false;
2173 switch (UseMCID.getOpcode()) {
2176 case ARM::VSTMSIA_UPD:
2177 case ARM::VSTMSDB_UPD:
2182 // If there are odd number of 'S' registers or if it's not 64-bit aligned,
2183 // then it takes an extra cycle.
2184 if ((isSStore && (RegNo % 2)) || UseAlign < 8)
2187 // Assume the worst.
2188 UseCycle = RegNo + 2;
2195 ARMBaseInstrInfo::getSTMUseCycle(const InstrItineraryData *ItinData,
2196 const MCInstrDesc &UseMCID,
2198 unsigned UseIdx, unsigned UseAlign) const {
2199 int RegNo = (int)(UseIdx+1) - UseMCID.getNumOperands() + 1;
2201 return ItinData->getOperandCycle(UseClass, UseIdx);
2204 if (Subtarget.isCortexA8()) {
2205 UseCycle = RegNo / 2;
2210 } else if (Subtarget.isCortexA9()) {
2211 UseCycle = (RegNo / 2);
2212 // If there are odd number of registers or if it's not 64-bit aligned,
2213 // then it takes an extra AGU (Address Generation Unit) cycle.
2214 if ((RegNo % 2) || UseAlign < 8)
2217 // Assume the worst.
2224 ARMBaseInstrInfo::getOperandLatency(const InstrItineraryData *ItinData,
2225 const MCInstrDesc &DefMCID,
2226 unsigned DefIdx, unsigned DefAlign,
2227 const MCInstrDesc &UseMCID,
2228 unsigned UseIdx, unsigned UseAlign) const {
2229 unsigned DefClass = DefMCID.getSchedClass();
2230 unsigned UseClass = UseMCID.getSchedClass();
2232 if (DefIdx < DefMCID.getNumDefs() && UseIdx < UseMCID.getNumOperands())
2233 return ItinData->getOperandLatency(DefClass, DefIdx, UseClass, UseIdx);
2235 // This may be a def / use of a variable_ops instruction, the operand
2236 // latency might be determinable dynamically. Let the target try to
2239 bool LdmBypass = false;
2240 switch (DefMCID.getOpcode()) {
2242 DefCycle = ItinData->getOperandCycle(DefClass, DefIdx);
2246 case ARM::VLDMDIA_UPD:
2247 case ARM::VLDMDDB_UPD:
2249 case ARM::VLDMSIA_UPD:
2250 case ARM::VLDMSDB_UPD:
2251 DefCycle = getVLDMDefCycle(ItinData, DefMCID, DefClass, DefIdx, DefAlign);
2254 case ARM::LDMIA_RET:
2259 case ARM::LDMIA_UPD:
2260 case ARM::LDMDA_UPD:
2261 case ARM::LDMDB_UPD:
2262 case ARM::LDMIB_UPD:
2264 case ARM::tLDMIA_UPD:
2266 case ARM::t2LDMIA_RET:
2269 case ARM::t2LDMIA_UPD:
2270 case ARM::t2LDMDB_UPD:
2272 DefCycle = getLDMDefCycle(ItinData, DefMCID, DefClass, DefIdx, DefAlign);
2277 // We can't seem to determine the result latency of the def, assume it's 2.
2281 switch (UseMCID.getOpcode()) {
2283 UseCycle = ItinData->getOperandCycle(UseClass, UseIdx);
2287 case ARM::VSTMDIA_UPD:
2288 case ARM::VSTMDDB_UPD:
2290 case ARM::VSTMSIA_UPD:
2291 case ARM::VSTMSDB_UPD:
2292 UseCycle = getVSTMUseCycle(ItinData, UseMCID, UseClass, UseIdx, UseAlign);
2299 case ARM::STMIA_UPD:
2300 case ARM::STMDA_UPD:
2301 case ARM::STMDB_UPD:
2302 case ARM::STMIB_UPD:
2303 case ARM::tSTMIA_UPD:
2308 case ARM::t2STMIA_UPD:
2309 case ARM::t2STMDB_UPD:
2310 UseCycle = getSTMUseCycle(ItinData, UseMCID, UseClass, UseIdx, UseAlign);
2315 // Assume it's read in the first stage.
2318 UseCycle = DefCycle - UseCycle + 1;
2321 // It's a variable_ops instruction so we can't use DefIdx here. Just use
2322 // first def operand.
2323 if (ItinData->hasPipelineForwarding(DefClass, DefMCID.getNumOperands()-1,
2326 } else if (ItinData->hasPipelineForwarding(DefClass, DefIdx,
2327 UseClass, UseIdx)) {
2336 ARMBaseInstrInfo::getOperandLatency(const InstrItineraryData *ItinData,
2337 const MachineInstr *DefMI, unsigned DefIdx,
2338 const MachineInstr *UseMI, unsigned UseIdx) const {
2339 if (DefMI->isCopyLike() || DefMI->isInsertSubreg() ||
2340 DefMI->isRegSequence() || DefMI->isImplicitDef())
2343 const MCInstrDesc &DefMCID = DefMI->getDesc();
2344 if (!ItinData || ItinData->isEmpty())
2345 return DefMCID.mayLoad() ? 3 : 1;
2347 const MCInstrDesc &UseMCID = UseMI->getDesc();
2348 const MachineOperand &DefMO = DefMI->getOperand(DefIdx);
2349 if (DefMO.getReg() == ARM::CPSR) {
2350 if (DefMI->getOpcode() == ARM::FMSTAT) {
2351 // fpscr -> cpsr stalls over 20 cycles on A8 (and earlier?)
2352 return Subtarget.isCortexA9() ? 1 : 20;
2355 // CPSR set and branch can be paired in the same cycle.
2356 if (UseMCID.isBranch())
2360 unsigned DefAlign = DefMI->hasOneMemOperand()
2361 ? (*DefMI->memoperands_begin())->getAlignment() : 0;
2362 unsigned UseAlign = UseMI->hasOneMemOperand()
2363 ? (*UseMI->memoperands_begin())->getAlignment() : 0;
2364 int Latency = getOperandLatency(ItinData, DefMCID, DefIdx, DefAlign,
2365 UseMCID, UseIdx, UseAlign);
2368 (Subtarget.isCortexA8() || Subtarget.isCortexA9())) {
2369 // FIXME: Shifter op hack: no shift (i.e. [r +/- r]) or [r + r << 2]
2370 // variants are one cycle cheaper.
2371 switch (DefMCID.getOpcode()) {
2375 unsigned ShOpVal = DefMI->getOperand(3).getImm();
2376 unsigned ShImm = ARM_AM::getAM2Offset(ShOpVal);
2378 (ShImm == 2 && ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl))
2385 case ARM::t2LDRSHs: {
2386 // Thumb2 mode: lsl only.
2387 unsigned ShAmt = DefMI->getOperand(3).getImm();
2388 if (ShAmt == 0 || ShAmt == 2)
2395 if (DefAlign < 8 && Subtarget.isCortexA9())
2396 switch (DefMCID.getOpcode()) {
2402 case ARM::VLD1q8wb_fixed:
2403 case ARM::VLD1q16wb_fixed:
2404 case ARM::VLD1q32wb_fixed:
2405 case ARM::VLD1q64wb_fixed:
2406 case ARM::VLD1q8wb_register:
2407 case ARM::VLD1q16wb_register:
2408 case ARM::VLD1q32wb_register:
2409 case ARM::VLD1q64wb_register:
2416 case ARM::VLD2d8_UPD:
2417 case ARM::VLD2d16_UPD:
2418 case ARM::VLD2d32_UPD:
2419 case ARM::VLD2q8_UPD:
2420 case ARM::VLD2q16_UPD:
2421 case ARM::VLD2q32_UPD:
2426 case ARM::VLD3d8_UPD:
2427 case ARM::VLD3d16_UPD:
2428 case ARM::VLD3d32_UPD:
2429 case ARM::VLD1d64Twb_fixed:
2430 case ARM::VLD1d64Twb_register:
2431 case ARM::VLD3q8_UPD:
2432 case ARM::VLD3q16_UPD:
2433 case ARM::VLD3q32_UPD:
2438 case ARM::VLD4d8_UPD:
2439 case ARM::VLD4d16_UPD:
2440 case ARM::VLD4d32_UPD:
2441 case ARM::VLD1d64Qwb_fixed:
2442 case ARM::VLD1d64Qwb_register:
2443 case ARM::VLD4q8_UPD:
2444 case ARM::VLD4q16_UPD:
2445 case ARM::VLD4q32_UPD:
2446 case ARM::VLD1DUPq8:
2447 case ARM::VLD1DUPq16:
2448 case ARM::VLD1DUPq32:
2449 case ARM::VLD1DUPq8wb_fixed:
2450 case ARM::VLD1DUPq16wb_fixed:
2451 case ARM::VLD1DUPq32wb_fixed:
2452 case ARM::VLD1DUPq8wb_register:
2453 case ARM::VLD1DUPq16wb_register:
2454 case ARM::VLD1DUPq32wb_register:
2455 case ARM::VLD2DUPd8:
2456 case ARM::VLD2DUPd16:
2457 case ARM::VLD2DUPd32:
2458 case ARM::VLD2DUPd8_UPD:
2459 case ARM::VLD2DUPd16_UPD:
2460 case ARM::VLD2DUPd32_UPD:
2461 case ARM::VLD4DUPd8:
2462 case ARM::VLD4DUPd16:
2463 case ARM::VLD4DUPd32:
2464 case ARM::VLD4DUPd8_UPD:
2465 case ARM::VLD4DUPd16_UPD:
2466 case ARM::VLD4DUPd32_UPD:
2468 case ARM::VLD1LNd16:
2469 case ARM::VLD1LNd32:
2470 case ARM::VLD1LNd8_UPD:
2471 case ARM::VLD1LNd16_UPD:
2472 case ARM::VLD1LNd32_UPD:
2474 case ARM::VLD2LNd16:
2475 case ARM::VLD2LNd32:
2476 case ARM::VLD2LNq16:
2477 case ARM::VLD2LNq32:
2478 case ARM::VLD2LNd8_UPD:
2479 case ARM::VLD2LNd16_UPD:
2480 case ARM::VLD2LNd32_UPD:
2481 case ARM::VLD2LNq16_UPD:
2482 case ARM::VLD2LNq32_UPD:
2484 case ARM::VLD4LNd16:
2485 case ARM::VLD4LNd32:
2486 case ARM::VLD4LNq16:
2487 case ARM::VLD4LNq32:
2488 case ARM::VLD4LNd8_UPD:
2489 case ARM::VLD4LNd16_UPD:
2490 case ARM::VLD4LNd32_UPD:
2491 case ARM::VLD4LNq16_UPD:
2492 case ARM::VLD4LNq32_UPD:
2493 // If the address is not 64-bit aligned, the latencies of these
2494 // instructions increases by one.
2503 ARMBaseInstrInfo::getOperandLatency(const InstrItineraryData *ItinData,
2504 SDNode *DefNode, unsigned DefIdx,
2505 SDNode *UseNode, unsigned UseIdx) const {
2506 if (!DefNode->isMachineOpcode())
2509 const MCInstrDesc &DefMCID = get(DefNode->getMachineOpcode());
2511 if (isZeroCost(DefMCID.Opcode))
2514 if (!ItinData || ItinData->isEmpty())
2515 return DefMCID.mayLoad() ? 3 : 1;
2517 if (!UseNode->isMachineOpcode()) {
2518 int Latency = ItinData->getOperandCycle(DefMCID.getSchedClass(), DefIdx);
2519 if (Subtarget.isCortexA9())
2520 return Latency <= 2 ? 1 : Latency - 1;
2522 return Latency <= 3 ? 1 : Latency - 2;
2525 const MCInstrDesc &UseMCID = get(UseNode->getMachineOpcode());
2526 const MachineSDNode *DefMN = dyn_cast<MachineSDNode>(DefNode);
2527 unsigned DefAlign = !DefMN->memoperands_empty()
2528 ? (*DefMN->memoperands_begin())->getAlignment() : 0;
2529 const MachineSDNode *UseMN = dyn_cast<MachineSDNode>(UseNode);
2530 unsigned UseAlign = !UseMN->memoperands_empty()
2531 ? (*UseMN->memoperands_begin())->getAlignment() : 0;
2532 int Latency = getOperandLatency(ItinData, DefMCID, DefIdx, DefAlign,
2533 UseMCID, UseIdx, UseAlign);
2536 (Subtarget.isCortexA8() || Subtarget.isCortexA9())) {
2537 // FIXME: Shifter op hack: no shift (i.e. [r +/- r]) or [r + r << 2]
2538 // variants are one cycle cheaper.
2539 switch (DefMCID.getOpcode()) {
2544 cast<ConstantSDNode>(DefNode->getOperand(2))->getZExtValue();
2545 unsigned ShImm = ARM_AM::getAM2Offset(ShOpVal);
2547 (ShImm == 2 && ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl))
2554 case ARM::t2LDRSHs: {
2555 // Thumb2 mode: lsl only.
2557 cast<ConstantSDNode>(DefNode->getOperand(2))->getZExtValue();
2558 if (ShAmt == 0 || ShAmt == 2)
2565 if (DefAlign < 8 && Subtarget.isCortexA9())
2566 switch (DefMCID.getOpcode()) {
2568 case ARM::VLD1q8Pseudo:
2569 case ARM::VLD1q16Pseudo:
2570 case ARM::VLD1q32Pseudo:
2571 case ARM::VLD1q64Pseudo:
2572 case ARM::VLD1q8PseudoWB_register:
2573 case ARM::VLD1q16PseudoWB_register:
2574 case ARM::VLD1q32PseudoWB_register:
2575 case ARM::VLD1q64PseudoWB_register:
2576 case ARM::VLD1q8PseudoWB_fixed:
2577 case ARM::VLD1q16PseudoWB_fixed:
2578 case ARM::VLD1q32PseudoWB_fixed:
2579 case ARM::VLD1q64PseudoWB_fixed:
2580 case ARM::VLD2d8Pseudo:
2581 case ARM::VLD2d16Pseudo:
2582 case ARM::VLD2d32Pseudo:
2583 case ARM::VLD2q8Pseudo:
2584 case ARM::VLD2q16Pseudo:
2585 case ARM::VLD2q32Pseudo:
2586 case ARM::VLD2d8Pseudo_UPD:
2587 case ARM::VLD2d16Pseudo_UPD:
2588 case ARM::VLD2d32Pseudo_UPD:
2589 case ARM::VLD2q8Pseudo_UPD:
2590 case ARM::VLD2q16Pseudo_UPD:
2591 case ARM::VLD2q32Pseudo_UPD:
2592 case ARM::VLD3d8Pseudo:
2593 case ARM::VLD3d16Pseudo:
2594 case ARM::VLD3d32Pseudo:
2595 case ARM::VLD1d64TPseudo:
2596 case ARM::VLD3d8Pseudo_UPD:
2597 case ARM::VLD3d16Pseudo_UPD:
2598 case ARM::VLD3d32Pseudo_UPD:
2599 case ARM::VLD3q8Pseudo_UPD:
2600 case ARM::VLD3q16Pseudo_UPD:
2601 case ARM::VLD3q32Pseudo_UPD:
2602 case ARM::VLD3q8oddPseudo:
2603 case ARM::VLD3q16oddPseudo:
2604 case ARM::VLD3q32oddPseudo:
2605 case ARM::VLD3q8oddPseudo_UPD:
2606 case ARM::VLD3q16oddPseudo_UPD:
2607 case ARM::VLD3q32oddPseudo_UPD:
2608 case ARM::VLD4d8Pseudo:
2609 case ARM::VLD4d16Pseudo:
2610 case ARM::VLD4d32Pseudo:
2611 case ARM::VLD1d64QPseudo:
2612 case ARM::VLD4d8Pseudo_UPD:
2613 case ARM::VLD4d16Pseudo_UPD:
2614 case ARM::VLD4d32Pseudo_UPD:
2615 case ARM::VLD4q8Pseudo_UPD:
2616 case ARM::VLD4q16Pseudo_UPD:
2617 case ARM::VLD4q32Pseudo_UPD:
2618 case ARM::VLD4q8oddPseudo:
2619 case ARM::VLD4q16oddPseudo:
2620 case ARM::VLD4q32oddPseudo:
2621 case ARM::VLD4q8oddPseudo_UPD:
2622 case ARM::VLD4q16oddPseudo_UPD:
2623 case ARM::VLD4q32oddPseudo_UPD:
2624 case ARM::VLD1DUPq8Pseudo:
2625 case ARM::VLD1DUPq16Pseudo:
2626 case ARM::VLD1DUPq32Pseudo:
2627 case ARM::VLD1DUPq8PseudoWB_fixed:
2628 case ARM::VLD1DUPq16PseudoWB_fixed:
2629 case ARM::VLD1DUPq32PseudoWB_fixed:
2630 case ARM::VLD1DUPq8PseudoWB_register:
2631 case ARM::VLD1DUPq16PseudoWB_register:
2632 case ARM::VLD1DUPq32PseudoWB_register:
2633 case ARM::VLD2DUPd8Pseudo:
2634 case ARM::VLD2DUPd16Pseudo:
2635 case ARM::VLD2DUPd32Pseudo:
2636 case ARM::VLD2DUPd8Pseudo_UPD:
2637 case ARM::VLD2DUPd16Pseudo_UPD:
2638 case ARM::VLD2DUPd32Pseudo_UPD:
2639 case ARM::VLD4DUPd8Pseudo:
2640 case ARM::VLD4DUPd16Pseudo:
2641 case ARM::VLD4DUPd32Pseudo:
2642 case ARM::VLD4DUPd8Pseudo_UPD:
2643 case ARM::VLD4DUPd16Pseudo_UPD:
2644 case ARM::VLD4DUPd32Pseudo_UPD:
2645 case ARM::VLD1LNq8Pseudo:
2646 case ARM::VLD1LNq16Pseudo:
2647 case ARM::VLD1LNq32Pseudo:
2648 case ARM::VLD1LNq8Pseudo_UPD:
2649 case ARM::VLD1LNq16Pseudo_UPD:
2650 case ARM::VLD1LNq32Pseudo_UPD:
2651 case ARM::VLD2LNd8Pseudo:
2652 case ARM::VLD2LNd16Pseudo:
2653 case ARM::VLD2LNd32Pseudo:
2654 case ARM::VLD2LNq16Pseudo:
2655 case ARM::VLD2LNq32Pseudo:
2656 case ARM::VLD2LNd8Pseudo_UPD:
2657 case ARM::VLD2LNd16Pseudo_UPD:
2658 case ARM::VLD2LNd32Pseudo_UPD:
2659 case ARM::VLD2LNq16Pseudo_UPD:
2660 case ARM::VLD2LNq32Pseudo_UPD:
2661 case ARM::VLD4LNd8Pseudo:
2662 case ARM::VLD4LNd16Pseudo:
2663 case ARM::VLD4LNd32Pseudo:
2664 case ARM::VLD4LNq16Pseudo:
2665 case ARM::VLD4LNq32Pseudo:
2666 case ARM::VLD4LNd8Pseudo_UPD:
2667 case ARM::VLD4LNd16Pseudo_UPD:
2668 case ARM::VLD4LNd32Pseudo_UPD:
2669 case ARM::VLD4LNq16Pseudo_UPD:
2670 case ARM::VLD4LNq32Pseudo_UPD:
2671 // If the address is not 64-bit aligned, the latencies of these
2672 // instructions increases by one.
2680 int ARMBaseInstrInfo::getInstrLatency(const InstrItineraryData *ItinData,
2681 const MachineInstr *MI,
2682 unsigned *PredCost) const {
2683 if (MI->isCopyLike() || MI->isInsertSubreg() ||
2684 MI->isRegSequence() || MI->isImplicitDef())
2687 if (!ItinData || ItinData->isEmpty())
2690 const MCInstrDesc &MCID = MI->getDesc();
2691 unsigned Class = MCID.getSchedClass();
2692 unsigned UOps = ItinData->Itineraries[Class].NumMicroOps;
2693 if (PredCost && MCID.hasImplicitDefOfPhysReg(ARM::CPSR))
2694 // When predicated, CPSR is an additional source operand for CPSR updating
2695 // instructions, this apparently increases their latencies.
2698 return ItinData->getStageLatency(Class);
2699 return getNumMicroOps(ItinData, MI);
2702 int ARMBaseInstrInfo::getInstrLatency(const InstrItineraryData *ItinData,
2703 SDNode *Node) const {
2704 if (!Node->isMachineOpcode())
2707 if (!ItinData || ItinData->isEmpty())
2710 unsigned Opcode = Node->getMachineOpcode();
2713 return ItinData->getStageLatency(get(Opcode).getSchedClass());
2720 bool ARMBaseInstrInfo::
2721 hasHighOperandLatency(const InstrItineraryData *ItinData,
2722 const MachineRegisterInfo *MRI,
2723 const MachineInstr *DefMI, unsigned DefIdx,
2724 const MachineInstr *UseMI, unsigned UseIdx) const {
2725 unsigned DDomain = DefMI->getDesc().TSFlags & ARMII::DomainMask;
2726 unsigned UDomain = UseMI->getDesc().TSFlags & ARMII::DomainMask;
2727 if (Subtarget.isCortexA8() &&
2728 (DDomain == ARMII::DomainVFP || UDomain == ARMII::DomainVFP))
2729 // CortexA8 VFP instructions are not pipelined.
2732 // Hoist VFP / NEON instructions with 4 or higher latency.
2733 int Latency = getOperandLatency(ItinData, DefMI, DefIdx, UseMI, UseIdx);
2736 return DDomain == ARMII::DomainVFP || DDomain == ARMII::DomainNEON ||
2737 UDomain == ARMII::DomainVFP || UDomain == ARMII::DomainNEON;
2740 bool ARMBaseInstrInfo::
2741 hasLowDefLatency(const InstrItineraryData *ItinData,
2742 const MachineInstr *DefMI, unsigned DefIdx) const {
2743 if (!ItinData || ItinData->isEmpty())
2746 unsigned DDomain = DefMI->getDesc().TSFlags & ARMII::DomainMask;
2747 if (DDomain == ARMII::DomainGeneral) {
2748 unsigned DefClass = DefMI->getDesc().getSchedClass();
2749 int DefCycle = ItinData->getOperandCycle(DefClass, DefIdx);
2750 return (DefCycle != -1 && DefCycle <= 2);
2755 bool ARMBaseInstrInfo::verifyInstruction(const MachineInstr *MI,
2756 StringRef &ErrInfo) const {
2757 if (convertAddSubFlagsOpcode(MI->getOpcode())) {
2758 ErrInfo = "Pseudo flag setting opcodes only exist in Selection DAG";
2765 ARMBaseInstrInfo::isFpMLxInstruction(unsigned Opcode, unsigned &MulOpc,
2766 unsigned &AddSubOpc,
2767 bool &NegAcc, bool &HasLane) const {
2768 DenseMap<unsigned, unsigned>::const_iterator I = MLxEntryMap.find(Opcode);
2769 if (I == MLxEntryMap.end())
2772 const ARM_MLxEntry &Entry = ARM_MLxTable[I->second];
2773 MulOpc = Entry.MulOpc;
2774 AddSubOpc = Entry.AddSubOpc;
2775 NegAcc = Entry.NegAcc;
2776 HasLane = Entry.HasLane;
2780 //===----------------------------------------------------------------------===//
2781 // Execution domains.
2782 //===----------------------------------------------------------------------===//
2784 // Some instructions go down the NEON pipeline, some go down the VFP pipeline,
2785 // and some can go down both. The vmov instructions go down the VFP pipeline,
2786 // but they can be changed to vorr equivalents that are executed by the NEON
2789 // We use the following execution domain numbering:
2797 // Also see ARMInstrFormats.td and Domain* enums in ARMBaseInfo.h
2799 std::pair<uint16_t, uint16_t>
2800 ARMBaseInstrInfo::getExecutionDomain(const MachineInstr *MI) const {
2801 // VMOVD is a VFP instruction, but can be changed to NEON if it isn't
2803 if (MI->getOpcode() == ARM::VMOVD && !isPredicated(MI))
2804 return std::make_pair(ExeVFP, (1<<ExeVFP) | (1<<ExeNEON));
2806 // No other instructions can be swizzled, so just determine their domain.
2807 unsigned Domain = MI->getDesc().TSFlags & ARMII::DomainMask;
2809 if (Domain & ARMII::DomainNEON)
2810 return std::make_pair(ExeNEON, 0);
2812 // Certain instructions can go either way on Cortex-A8.
2813 // Treat them as NEON instructions.
2814 if ((Domain & ARMII::DomainNEONA8) && Subtarget.isCortexA8())
2815 return std::make_pair(ExeNEON, 0);
2817 if (Domain & ARMII::DomainVFP)
2818 return std::make_pair(ExeVFP, 0);
2820 return std::make_pair(ExeGeneric, 0);
2824 ARMBaseInstrInfo::setExecutionDomain(MachineInstr *MI, unsigned Domain) const {
2825 // We only know how to change VMOVD into VORR.
2826 assert(MI->getOpcode() == ARM::VMOVD && "Can only swizzle VMOVD");
2827 if (Domain != ExeNEON)
2830 // Zap the predicate operands.
2831 assert(!isPredicated(MI) && "Cannot predicate a VORRd");
2832 MI->RemoveOperand(3);
2833 MI->RemoveOperand(2);
2835 // Change to a VORRd which requires two identical use operands.
2836 MI->setDesc(get(ARM::VORRd));
2838 // Add the extra source operand and new predicates.
2839 // This will go before any implicit ops.
2840 AddDefaultPred(MachineInstrBuilder(MI).addOperand(MI->getOperand(1)));