1 //===-- ARMBaseInstrInfo.cpp - ARM Instruction Information ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Base ARM implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "ARMBaseInstrInfo.h"
16 #include "ARMConstantPoolValue.h"
17 #include "ARMHazardRecognizer.h"
18 #include "ARMMachineFunctionInfo.h"
19 #include "ARMRegisterInfo.h"
20 #include "MCTargetDesc/ARMAddressingModes.h"
21 #include "llvm/Constants.h"
22 #include "llvm/Function.h"
23 #include "llvm/GlobalValue.h"
24 #include "llvm/CodeGen/LiveVariables.h"
25 #include "llvm/CodeGen/MachineConstantPool.h"
26 #include "llvm/CodeGen/MachineFrameInfo.h"
27 #include "llvm/CodeGen/MachineInstrBuilder.h"
28 #include "llvm/CodeGen/MachineJumpTableInfo.h"
29 #include "llvm/CodeGen/MachineMemOperand.h"
30 #include "llvm/CodeGen/MachineRegisterInfo.h"
31 #include "llvm/CodeGen/SelectionDAGNodes.h"
32 #include "llvm/MC/MCAsmInfo.h"
33 #include "llvm/Support/BranchProbability.h"
34 #include "llvm/Support/CommandLine.h"
35 #include "llvm/Support/Debug.h"
36 #include "llvm/Support/ErrorHandling.h"
37 #include "llvm/ADT/STLExtras.h"
39 #define GET_INSTRINFO_CTOR
40 #include "ARMGenInstrInfo.inc"
45 EnableARM3Addr("enable-arm-3-addr-conv", cl::Hidden,
46 cl::desc("Enable ARM 2-addr to 3-addr conv"));
49 WidenVMOVS("widen-vmovs", cl::Hidden, cl::init(true),
50 cl::desc("Widen ARM vmovs to vmovd when possible"));
52 /// ARM_MLxEntry - Record information about MLA / MLS instructions.
54 unsigned MLxOpc; // MLA / MLS opcode
55 unsigned MulOpc; // Expanded multiplication opcode
56 unsigned AddSubOpc; // Expanded add / sub opcode
57 bool NegAcc; // True if the acc is negated before the add / sub.
58 bool HasLane; // True if instruction has an extra "lane" operand.
61 static const ARM_MLxEntry ARM_MLxTable[] = {
62 // MLxOpc, MulOpc, AddSubOpc, NegAcc, HasLane
64 { ARM::VMLAS, ARM::VMULS, ARM::VADDS, false, false },
65 { ARM::VMLSS, ARM::VMULS, ARM::VSUBS, false, false },
66 { ARM::VMLAD, ARM::VMULD, ARM::VADDD, false, false },
67 { ARM::VMLSD, ARM::VMULD, ARM::VSUBD, false, false },
68 { ARM::VNMLAS, ARM::VNMULS, ARM::VSUBS, true, false },
69 { ARM::VNMLSS, ARM::VMULS, ARM::VSUBS, true, false },
70 { ARM::VNMLAD, ARM::VNMULD, ARM::VSUBD, true, false },
71 { ARM::VNMLSD, ARM::VMULD, ARM::VSUBD, true, false },
74 { ARM::VMLAfd, ARM::VMULfd, ARM::VADDfd, false, false },
75 { ARM::VMLSfd, ARM::VMULfd, ARM::VSUBfd, false, false },
76 { ARM::VMLAfq, ARM::VMULfq, ARM::VADDfq, false, false },
77 { ARM::VMLSfq, ARM::VMULfq, ARM::VSUBfq, false, false },
78 { ARM::VMLAslfd, ARM::VMULslfd, ARM::VADDfd, false, true },
79 { ARM::VMLSslfd, ARM::VMULslfd, ARM::VSUBfd, false, true },
80 { ARM::VMLAslfq, ARM::VMULslfq, ARM::VADDfq, false, true },
81 { ARM::VMLSslfq, ARM::VMULslfq, ARM::VSUBfq, false, true },
84 ARMBaseInstrInfo::ARMBaseInstrInfo(const ARMSubtarget& STI)
85 : ARMGenInstrInfo(ARM::ADJCALLSTACKDOWN, ARM::ADJCALLSTACKUP),
87 for (unsigned i = 0, e = array_lengthof(ARM_MLxTable); i != e; ++i) {
88 if (!MLxEntryMap.insert(std::make_pair(ARM_MLxTable[i].MLxOpc, i)).second)
89 assert(false && "Duplicated entries?");
90 MLxHazardOpcodes.insert(ARM_MLxTable[i].AddSubOpc);
91 MLxHazardOpcodes.insert(ARM_MLxTable[i].MulOpc);
95 // Use a ScoreboardHazardRecognizer for prepass ARM scheduling. TargetInstrImpl
96 // currently defaults to no prepass hazard recognizer.
97 ScheduleHazardRecognizer *ARMBaseInstrInfo::
98 CreateTargetHazardRecognizer(const TargetMachine *TM,
99 const ScheduleDAG *DAG) const {
100 if (usePreRAHazardRecognizer()) {
101 const InstrItineraryData *II = TM->getInstrItineraryData();
102 return new ScoreboardHazardRecognizer(II, DAG, "pre-RA-sched");
104 return TargetInstrInfoImpl::CreateTargetHazardRecognizer(TM, DAG);
107 ScheduleHazardRecognizer *ARMBaseInstrInfo::
108 CreateTargetPostRAHazardRecognizer(const InstrItineraryData *II,
109 const ScheduleDAG *DAG) const {
110 if (Subtarget.isThumb2() || Subtarget.hasVFP2())
111 return (ScheduleHazardRecognizer *)
112 new ARMHazardRecognizer(II, *this, getRegisterInfo(), Subtarget, DAG);
113 return TargetInstrInfoImpl::CreateTargetPostRAHazardRecognizer(II, DAG);
117 ARMBaseInstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
118 MachineBasicBlock::iterator &MBBI,
119 LiveVariables *LV) const {
120 // FIXME: Thumb2 support.
125 MachineInstr *MI = MBBI;
126 MachineFunction &MF = *MI->getParent()->getParent();
127 uint64_t TSFlags = MI->getDesc().TSFlags;
129 switch ((TSFlags & ARMII::IndexModeMask) >> ARMII::IndexModeShift) {
130 default: return NULL;
131 case ARMII::IndexModePre:
134 case ARMII::IndexModePost:
138 // Try splitting an indexed load/store to an un-indexed one plus an add/sub
140 unsigned MemOpc = getUnindexedOpcode(MI->getOpcode());
144 MachineInstr *UpdateMI = NULL;
145 MachineInstr *MemMI = NULL;
146 unsigned AddrMode = (TSFlags & ARMII::AddrModeMask);
147 const MCInstrDesc &MCID = MI->getDesc();
148 unsigned NumOps = MCID.getNumOperands();
149 bool isLoad = !MI->mayStore();
150 const MachineOperand &WB = isLoad ? MI->getOperand(1) : MI->getOperand(0);
151 const MachineOperand &Base = MI->getOperand(2);
152 const MachineOperand &Offset = MI->getOperand(NumOps-3);
153 unsigned WBReg = WB.getReg();
154 unsigned BaseReg = Base.getReg();
155 unsigned OffReg = Offset.getReg();
156 unsigned OffImm = MI->getOperand(NumOps-2).getImm();
157 ARMCC::CondCodes Pred = (ARMCC::CondCodes)MI->getOperand(NumOps-1).getImm();
159 default: llvm_unreachable("Unknown indexed op!");
160 case ARMII::AddrMode2: {
161 bool isSub = ARM_AM::getAM2Op(OffImm) == ARM_AM::sub;
162 unsigned Amt = ARM_AM::getAM2Offset(OffImm);
164 if (ARM_AM::getSOImmVal(Amt) == -1)
165 // Can't encode it in a so_imm operand. This transformation will
166 // add more than 1 instruction. Abandon!
168 UpdateMI = BuildMI(MF, MI->getDebugLoc(),
169 get(isSub ? ARM::SUBri : ARM::ADDri), WBReg)
170 .addReg(BaseReg).addImm(Amt)
171 .addImm(Pred).addReg(0).addReg(0);
172 } else if (Amt != 0) {
173 ARM_AM::ShiftOpc ShOpc = ARM_AM::getAM2ShiftOpc(OffImm);
174 unsigned SOOpc = ARM_AM::getSORegOpc(ShOpc, Amt);
175 UpdateMI = BuildMI(MF, MI->getDebugLoc(),
176 get(isSub ? ARM::SUBrsi : ARM::ADDrsi), WBReg)
177 .addReg(BaseReg).addReg(OffReg).addReg(0).addImm(SOOpc)
178 .addImm(Pred).addReg(0).addReg(0);
180 UpdateMI = BuildMI(MF, MI->getDebugLoc(),
181 get(isSub ? ARM::SUBrr : ARM::ADDrr), WBReg)
182 .addReg(BaseReg).addReg(OffReg)
183 .addImm(Pred).addReg(0).addReg(0);
186 case ARMII::AddrMode3 : {
187 bool isSub = ARM_AM::getAM3Op(OffImm) == ARM_AM::sub;
188 unsigned Amt = ARM_AM::getAM3Offset(OffImm);
190 // Immediate is 8-bits. It's guaranteed to fit in a so_imm operand.
191 UpdateMI = BuildMI(MF, MI->getDebugLoc(),
192 get(isSub ? ARM::SUBri : ARM::ADDri), WBReg)
193 .addReg(BaseReg).addImm(Amt)
194 .addImm(Pred).addReg(0).addReg(0);
196 UpdateMI = BuildMI(MF, MI->getDebugLoc(),
197 get(isSub ? ARM::SUBrr : ARM::ADDrr), WBReg)
198 .addReg(BaseReg).addReg(OffReg)
199 .addImm(Pred).addReg(0).addReg(0);
204 std::vector<MachineInstr*> NewMIs;
207 MemMI = BuildMI(MF, MI->getDebugLoc(),
208 get(MemOpc), MI->getOperand(0).getReg())
209 .addReg(WBReg).addImm(0).addImm(Pred);
211 MemMI = BuildMI(MF, MI->getDebugLoc(),
212 get(MemOpc)).addReg(MI->getOperand(1).getReg())
213 .addReg(WBReg).addReg(0).addImm(0).addImm(Pred);
214 NewMIs.push_back(MemMI);
215 NewMIs.push_back(UpdateMI);
218 MemMI = BuildMI(MF, MI->getDebugLoc(),
219 get(MemOpc), MI->getOperand(0).getReg())
220 .addReg(BaseReg).addImm(0).addImm(Pred);
222 MemMI = BuildMI(MF, MI->getDebugLoc(),
223 get(MemOpc)).addReg(MI->getOperand(1).getReg())
224 .addReg(BaseReg).addReg(0).addImm(0).addImm(Pred);
226 UpdateMI->getOperand(0).setIsDead();
227 NewMIs.push_back(UpdateMI);
228 NewMIs.push_back(MemMI);
231 // Transfer LiveVariables states, kill / dead info.
233 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
234 MachineOperand &MO = MI->getOperand(i);
235 if (MO.isReg() && TargetRegisterInfo::isVirtualRegister(MO.getReg())) {
236 unsigned Reg = MO.getReg();
238 LiveVariables::VarInfo &VI = LV->getVarInfo(Reg);
240 MachineInstr *NewMI = (Reg == WBReg) ? UpdateMI : MemMI;
242 LV->addVirtualRegisterDead(Reg, NewMI);
244 if (MO.isUse() && MO.isKill()) {
245 for (unsigned j = 0; j < 2; ++j) {
246 // Look at the two new MI's in reverse order.
247 MachineInstr *NewMI = NewMIs[j];
248 if (!NewMI->readsRegister(Reg))
250 LV->addVirtualRegisterKilled(Reg, NewMI);
251 if (VI.removeKill(MI))
252 VI.Kills.push_back(NewMI);
260 MFI->insert(MBBI, NewMIs[1]);
261 MFI->insert(MBBI, NewMIs[0]);
267 ARMBaseInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB,
268 MachineBasicBlock *&FBB,
269 SmallVectorImpl<MachineOperand> &Cond,
270 bool AllowModify) const {
271 // If the block has no terminators, it just falls into the block after it.
272 MachineBasicBlock::iterator I = MBB.end();
273 if (I == MBB.begin())
276 while (I->isDebugValue()) {
277 if (I == MBB.begin())
281 if (!isUnpredicatedTerminator(I))
284 // Get the last instruction in the block.
285 MachineInstr *LastInst = I;
287 // If there is only one terminator instruction, process it.
288 unsigned LastOpc = LastInst->getOpcode();
289 if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) {
290 if (isUncondBranchOpcode(LastOpc)) {
291 TBB = LastInst->getOperand(0).getMBB();
294 if (isCondBranchOpcode(LastOpc)) {
295 // Block ends with fall-through condbranch.
296 TBB = LastInst->getOperand(0).getMBB();
297 Cond.push_back(LastInst->getOperand(1));
298 Cond.push_back(LastInst->getOperand(2));
301 return true; // Can't handle indirect branch.
304 // Get the instruction before it if it is a terminator.
305 MachineInstr *SecondLastInst = I;
306 unsigned SecondLastOpc = SecondLastInst->getOpcode();
308 // If AllowModify is true and the block ends with two or more unconditional
309 // branches, delete all but the first unconditional branch.
310 if (AllowModify && isUncondBranchOpcode(LastOpc)) {
311 while (isUncondBranchOpcode(SecondLastOpc)) {
312 LastInst->eraseFromParent();
313 LastInst = SecondLastInst;
314 LastOpc = LastInst->getOpcode();
315 if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) {
316 // Return now the only terminator is an unconditional branch.
317 TBB = LastInst->getOperand(0).getMBB();
321 SecondLastOpc = SecondLastInst->getOpcode();
326 // If there are three terminators, we don't know what sort of block this is.
327 if (SecondLastInst && I != MBB.begin() && isUnpredicatedTerminator(--I))
330 // If the block ends with a B and a Bcc, handle it.
331 if (isCondBranchOpcode(SecondLastOpc) && isUncondBranchOpcode(LastOpc)) {
332 TBB = SecondLastInst->getOperand(0).getMBB();
333 Cond.push_back(SecondLastInst->getOperand(1));
334 Cond.push_back(SecondLastInst->getOperand(2));
335 FBB = LastInst->getOperand(0).getMBB();
339 // If the block ends with two unconditional branches, handle it. The second
340 // one is not executed, so remove it.
341 if (isUncondBranchOpcode(SecondLastOpc) && isUncondBranchOpcode(LastOpc)) {
342 TBB = SecondLastInst->getOperand(0).getMBB();
345 I->eraseFromParent();
349 // ...likewise if it ends with a branch table followed by an unconditional
350 // branch. The branch folder can create these, and we must get rid of them for
351 // correctness of Thumb constant islands.
352 if ((isJumpTableBranchOpcode(SecondLastOpc) ||
353 isIndirectBranchOpcode(SecondLastOpc)) &&
354 isUncondBranchOpcode(LastOpc)) {
357 I->eraseFromParent();
361 // Otherwise, can't handle this.
366 unsigned ARMBaseInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
367 MachineBasicBlock::iterator I = MBB.end();
368 if (I == MBB.begin()) return 0;
370 while (I->isDebugValue()) {
371 if (I == MBB.begin())
375 if (!isUncondBranchOpcode(I->getOpcode()) &&
376 !isCondBranchOpcode(I->getOpcode()))
379 // Remove the branch.
380 I->eraseFromParent();
384 if (I == MBB.begin()) return 1;
386 if (!isCondBranchOpcode(I->getOpcode()))
389 // Remove the branch.
390 I->eraseFromParent();
395 ARMBaseInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
396 MachineBasicBlock *FBB,
397 const SmallVectorImpl<MachineOperand> &Cond,
399 ARMFunctionInfo *AFI = MBB.getParent()->getInfo<ARMFunctionInfo>();
400 int BOpc = !AFI->isThumbFunction()
401 ? ARM::B : (AFI->isThumb2Function() ? ARM::t2B : ARM::tB);
402 int BccOpc = !AFI->isThumbFunction()
403 ? ARM::Bcc : (AFI->isThumb2Function() ? ARM::t2Bcc : ARM::tBcc);
404 bool isThumb = AFI->isThumbFunction() || AFI->isThumb2Function();
406 // Shouldn't be a fall through.
407 assert(TBB && "InsertBranch must not be told to insert a fallthrough");
408 assert((Cond.size() == 2 || Cond.size() == 0) &&
409 "ARM branch conditions have two components!");
412 if (Cond.empty()) { // Unconditional branch?
414 BuildMI(&MBB, DL, get(BOpc)).addMBB(TBB).addImm(ARMCC::AL).addReg(0);
416 BuildMI(&MBB, DL, get(BOpc)).addMBB(TBB);
418 BuildMI(&MBB, DL, get(BccOpc)).addMBB(TBB)
419 .addImm(Cond[0].getImm()).addReg(Cond[1].getReg());
423 // Two-way conditional branch.
424 BuildMI(&MBB, DL, get(BccOpc)).addMBB(TBB)
425 .addImm(Cond[0].getImm()).addReg(Cond[1].getReg());
427 BuildMI(&MBB, DL, get(BOpc)).addMBB(FBB).addImm(ARMCC::AL).addReg(0);
429 BuildMI(&MBB, DL, get(BOpc)).addMBB(FBB);
433 bool ARMBaseInstrInfo::
434 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
435 ARMCC::CondCodes CC = (ARMCC::CondCodes)(int)Cond[0].getImm();
436 Cond[0].setImm(ARMCC::getOppositeCondition(CC));
440 bool ARMBaseInstrInfo::isPredicated(const MachineInstr *MI) const {
441 if (MI->isBundle()) {
442 MachineBasicBlock::const_instr_iterator I = MI;
443 MachineBasicBlock::const_instr_iterator E = MI->getParent()->instr_end();
444 while (++I != E && I->isInsideBundle()) {
445 int PIdx = I->findFirstPredOperandIdx();
446 if (PIdx != -1 && I->getOperand(PIdx).getImm() != ARMCC::AL)
452 int PIdx = MI->findFirstPredOperandIdx();
453 return PIdx != -1 && MI->getOperand(PIdx).getImm() != ARMCC::AL;
456 bool ARMBaseInstrInfo::
457 PredicateInstruction(MachineInstr *MI,
458 const SmallVectorImpl<MachineOperand> &Pred) const {
459 unsigned Opc = MI->getOpcode();
460 if (isUncondBranchOpcode(Opc)) {
461 MI->setDesc(get(getMatchingCondBranchOpcode(Opc)));
462 MI->addOperand(MachineOperand::CreateImm(Pred[0].getImm()));
463 MI->addOperand(MachineOperand::CreateReg(Pred[1].getReg(), false));
467 int PIdx = MI->findFirstPredOperandIdx();
469 MachineOperand &PMO = MI->getOperand(PIdx);
470 PMO.setImm(Pred[0].getImm());
471 MI->getOperand(PIdx+1).setReg(Pred[1].getReg());
477 bool ARMBaseInstrInfo::
478 SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1,
479 const SmallVectorImpl<MachineOperand> &Pred2) const {
480 if (Pred1.size() > 2 || Pred2.size() > 2)
483 ARMCC::CondCodes CC1 = (ARMCC::CondCodes)Pred1[0].getImm();
484 ARMCC::CondCodes CC2 = (ARMCC::CondCodes)Pred2[0].getImm();
494 return CC2 == ARMCC::HI;
496 return CC2 == ARMCC::LO || CC2 == ARMCC::EQ;
498 return CC2 == ARMCC::GT;
500 return CC2 == ARMCC::LT;
504 bool ARMBaseInstrInfo::DefinesPredicate(MachineInstr *MI,
505 std::vector<MachineOperand> &Pred) const {
507 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
508 const MachineOperand &MO = MI->getOperand(i);
509 if ((MO.isRegMask() && MO.clobbersPhysReg(ARM::CPSR)) ||
510 (MO.isReg() && MO.isDef() && MO.getReg() == ARM::CPSR)) {
519 /// isPredicable - Return true if the specified instruction can be predicated.
520 /// By default, this returns true for every instruction with a
521 /// PredicateOperand.
522 bool ARMBaseInstrInfo::isPredicable(MachineInstr *MI) const {
523 if (!MI->isPredicable())
526 if ((MI->getDesc().TSFlags & ARMII::DomainMask) == ARMII::DomainNEON) {
527 ARMFunctionInfo *AFI =
528 MI->getParent()->getParent()->getInfo<ARMFunctionInfo>();
529 return AFI->isThumb2Function();
534 /// FIXME: Works around a gcc miscompilation with -fstrict-aliasing.
535 LLVM_ATTRIBUTE_NOINLINE
536 static unsigned getNumJTEntries(const std::vector<MachineJumpTableEntry> &JT,
538 static unsigned getNumJTEntries(const std::vector<MachineJumpTableEntry> &JT,
540 assert(JTI < JT.size());
541 return JT[JTI].MBBs.size();
544 /// GetInstSize - Return the size of the specified MachineInstr.
546 unsigned ARMBaseInstrInfo::GetInstSizeInBytes(const MachineInstr *MI) const {
547 const MachineBasicBlock &MBB = *MI->getParent();
548 const MachineFunction *MF = MBB.getParent();
549 const MCAsmInfo *MAI = MF->getTarget().getMCAsmInfo();
551 const MCInstrDesc &MCID = MI->getDesc();
553 return MCID.getSize();
555 // If this machine instr is an inline asm, measure it.
556 if (MI->getOpcode() == ARM::INLINEASM)
557 return getInlineAsmLength(MI->getOperand(0).getSymbolName(), *MAI);
560 unsigned Opc = MI->getOpcode();
562 case TargetOpcode::IMPLICIT_DEF:
563 case TargetOpcode::KILL:
564 case TargetOpcode::PROLOG_LABEL:
565 case TargetOpcode::EH_LABEL:
566 case TargetOpcode::DBG_VALUE:
568 case TargetOpcode::BUNDLE:
569 return getInstBundleLength(MI);
570 case ARM::MOVi16_ga_pcrel:
571 case ARM::MOVTi16_ga_pcrel:
572 case ARM::t2MOVi16_ga_pcrel:
573 case ARM::t2MOVTi16_ga_pcrel:
576 case ARM::t2MOVi32imm:
578 case ARM::CONSTPOOL_ENTRY:
579 // If this machine instr is a constant pool entry, its size is recorded as
581 return MI->getOperand(2).getImm();
582 case ARM::Int_eh_sjlj_longjmp:
584 case ARM::tInt_eh_sjlj_longjmp:
586 case ARM::Int_eh_sjlj_setjmp:
587 case ARM::Int_eh_sjlj_setjmp_nofp:
589 case ARM::tInt_eh_sjlj_setjmp:
590 case ARM::t2Int_eh_sjlj_setjmp:
591 case ARM::t2Int_eh_sjlj_setjmp_nofp:
599 case ARM::t2TBH_JT: {
600 // These are jumptable branches, i.e. a branch followed by an inlined
601 // jumptable. The size is 4 + 4 * number of entries. For TBB, each
602 // entry is one byte; TBH two byte each.
603 unsigned EntrySize = (Opc == ARM::t2TBB_JT)
604 ? 1 : ((Opc == ARM::t2TBH_JT) ? 2 : 4);
605 unsigned NumOps = MCID.getNumOperands();
606 MachineOperand JTOP =
607 MI->getOperand(NumOps - (MI->isPredicable() ? 3 : 2));
608 unsigned JTI = JTOP.getIndex();
609 const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
611 const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
612 assert(JTI < JT.size());
613 // Thumb instructions are 2 byte aligned, but JT entries are 4 byte
614 // 4 aligned. The assembler / linker may add 2 byte padding just before
615 // the JT entries. The size does not include this padding; the
616 // constant islands pass does separate bookkeeping for it.
617 // FIXME: If we know the size of the function is less than (1 << 16) *2
618 // bytes, we can use 16-bit entries instead. Then there won't be an
620 unsigned InstSize = (Opc == ARM::tBR_JTr || Opc == ARM::t2BR_JT) ? 2 : 4;
621 unsigned NumEntries = getNumJTEntries(JT, JTI);
622 if (Opc == ARM::t2TBB_JT && (NumEntries & 1))
623 // Make sure the instruction that follows TBB is 2-byte aligned.
624 // FIXME: Constant island pass should insert an "ALIGN" instruction
627 return NumEntries * EntrySize + InstSize;
630 // Otherwise, pseudo-instruction sizes are zero.
635 unsigned ARMBaseInstrInfo::getInstBundleLength(const MachineInstr *MI) const {
637 MachineBasicBlock::const_instr_iterator I = MI;
638 MachineBasicBlock::const_instr_iterator E = MI->getParent()->instr_end();
639 while (++I != E && I->isInsideBundle()) {
640 assert(!I->isBundle() && "No nested bundle!");
641 Size += GetInstSizeInBytes(&*I);
646 void ARMBaseInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
647 MachineBasicBlock::iterator I, DebugLoc DL,
648 unsigned DestReg, unsigned SrcReg,
649 bool KillSrc) const {
650 bool GPRDest = ARM::GPRRegClass.contains(DestReg);
651 bool GPRSrc = ARM::GPRRegClass.contains(SrcReg);
653 if (GPRDest && GPRSrc) {
654 AddDefaultCC(AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::MOVr), DestReg)
655 .addReg(SrcReg, getKillRegState(KillSrc))));
659 bool SPRDest = ARM::SPRRegClass.contains(DestReg);
660 bool SPRSrc = ARM::SPRRegClass.contains(SrcReg);
663 if (SPRDest && SPRSrc)
665 else if (GPRDest && SPRSrc)
667 else if (SPRDest && GPRSrc)
669 else if (ARM::DPRRegClass.contains(DestReg, SrcReg))
671 else if (ARM::QPRRegClass.contains(DestReg, SrcReg))
675 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(Opc), DestReg);
676 MIB.addReg(SrcReg, getKillRegState(KillSrc));
677 if (Opc == ARM::VORRq)
678 MIB.addReg(SrcReg, getKillRegState(KillSrc));
683 // Generate instructions for VMOVQQ and VMOVQQQQ pseudos in place.
684 if (ARM::QQPRRegClass.contains(DestReg, SrcReg) ||
685 ARM::QQQQPRRegClass.contains(DestReg, SrcReg)) {
686 const TargetRegisterInfo *TRI = &getRegisterInfo();
687 assert(ARM::qsub_0 + 3 == ARM::qsub_3 && "Expected contiguous enum.");
688 unsigned EndSubReg = ARM::QQPRRegClass.contains(DestReg, SrcReg) ?
689 ARM::qsub_1 : ARM::qsub_3;
690 for (unsigned i = ARM::qsub_0, e = EndSubReg + 1; i != e; ++i) {
691 unsigned Dst = TRI->getSubReg(DestReg, i);
692 unsigned Src = TRI->getSubReg(SrcReg, i);
693 MachineInstrBuilder Mov =
694 AddDefaultPred(BuildMI(MBB, I, I->getDebugLoc(), get(ARM::VORRq))
695 .addReg(Dst, RegState::Define)
696 .addReg(Src, getKillRegState(KillSrc))
697 .addReg(Src, getKillRegState(KillSrc)));
698 if (i == EndSubReg) {
699 Mov->addRegisterDefined(DestReg, TRI);
701 Mov->addRegisterKilled(SrcReg, TRI);
706 llvm_unreachable("Impossible reg-to-reg copy");
710 MachineInstrBuilder &AddDReg(MachineInstrBuilder &MIB,
711 unsigned Reg, unsigned SubIdx, unsigned State,
712 const TargetRegisterInfo *TRI) {
714 return MIB.addReg(Reg, State);
716 if (TargetRegisterInfo::isPhysicalRegister(Reg))
717 return MIB.addReg(TRI->getSubReg(Reg, SubIdx), State);
718 return MIB.addReg(Reg, State, SubIdx);
721 void ARMBaseInstrInfo::
722 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
723 unsigned SrcReg, bool isKill, int FI,
724 const TargetRegisterClass *RC,
725 const TargetRegisterInfo *TRI) const {
727 if (I != MBB.end()) DL = I->getDebugLoc();
728 MachineFunction &MF = *MBB.getParent();
729 MachineFrameInfo &MFI = *MF.getFrameInfo();
730 unsigned Align = MFI.getObjectAlignment(FI);
732 MachineMemOperand *MMO =
733 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(FI),
734 MachineMemOperand::MOStore,
735 MFI.getObjectSize(FI),
738 switch (RC->getSize()) {
740 if (ARM::GPRRegClass.hasSubClassEq(RC)) {
741 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::STRi12))
742 .addReg(SrcReg, getKillRegState(isKill))
743 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
744 } else if (ARM::SPRRegClass.hasSubClassEq(RC)) {
745 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTRS))
746 .addReg(SrcReg, getKillRegState(isKill))
747 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
749 llvm_unreachable("Unknown reg class!");
752 if (ARM::DPRRegClass.hasSubClassEq(RC)) {
753 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTRD))
754 .addReg(SrcReg, getKillRegState(isKill))
755 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
757 llvm_unreachable("Unknown reg class!");
760 if (ARM::QPRRegClass.hasSubClassEq(RC)) {
761 // Use aligned spills if the stack can be realigned.
762 if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) {
763 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VST1q64Pseudo))
764 .addFrameIndex(FI).addImm(16)
765 .addReg(SrcReg, getKillRegState(isKill))
766 .addMemOperand(MMO));
768 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTMQIA))
769 .addReg(SrcReg, getKillRegState(isKill))
771 .addMemOperand(MMO));
774 llvm_unreachable("Unknown reg class!");
777 if (ARM::QQPRRegClass.hasSubClassEq(RC)) {
778 if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) {
779 // FIXME: It's possible to only store part of the QQ register if the
780 // spilled def has a sub-register index.
781 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VST1d64QPseudo))
782 .addFrameIndex(FI).addImm(16)
783 .addReg(SrcReg, getKillRegState(isKill))
784 .addMemOperand(MMO));
786 MachineInstrBuilder MIB =
787 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTMDIA))
790 MIB = AddDReg(MIB, SrcReg, ARM::dsub_0, getKillRegState(isKill), TRI);
791 MIB = AddDReg(MIB, SrcReg, ARM::dsub_1, 0, TRI);
792 MIB = AddDReg(MIB, SrcReg, ARM::dsub_2, 0, TRI);
793 AddDReg(MIB, SrcReg, ARM::dsub_3, 0, TRI);
796 llvm_unreachable("Unknown reg class!");
799 if (ARM::QQQQPRRegClass.hasSubClassEq(RC)) {
800 MachineInstrBuilder MIB =
801 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTMDIA))
804 MIB = AddDReg(MIB, SrcReg, ARM::dsub_0, getKillRegState(isKill), TRI);
805 MIB = AddDReg(MIB, SrcReg, ARM::dsub_1, 0, TRI);
806 MIB = AddDReg(MIB, SrcReg, ARM::dsub_2, 0, TRI);
807 MIB = AddDReg(MIB, SrcReg, ARM::dsub_3, 0, TRI);
808 MIB = AddDReg(MIB, SrcReg, ARM::dsub_4, 0, TRI);
809 MIB = AddDReg(MIB, SrcReg, ARM::dsub_5, 0, TRI);
810 MIB = AddDReg(MIB, SrcReg, ARM::dsub_6, 0, TRI);
811 AddDReg(MIB, SrcReg, ARM::dsub_7, 0, TRI);
813 llvm_unreachable("Unknown reg class!");
816 llvm_unreachable("Unknown reg class!");
821 ARMBaseInstrInfo::isStoreToStackSlot(const MachineInstr *MI,
822 int &FrameIndex) const {
823 switch (MI->getOpcode()) {
826 case ARM::t2STRs: // FIXME: don't use t2STRs to access frame.
827 if (MI->getOperand(1).isFI() &&
828 MI->getOperand(2).isReg() &&
829 MI->getOperand(3).isImm() &&
830 MI->getOperand(2).getReg() == 0 &&
831 MI->getOperand(3).getImm() == 0) {
832 FrameIndex = MI->getOperand(1).getIndex();
833 return MI->getOperand(0).getReg();
841 if (MI->getOperand(1).isFI() &&
842 MI->getOperand(2).isImm() &&
843 MI->getOperand(2).getImm() == 0) {
844 FrameIndex = MI->getOperand(1).getIndex();
845 return MI->getOperand(0).getReg();
848 case ARM::VST1q64Pseudo:
849 if (MI->getOperand(0).isFI() &&
850 MI->getOperand(2).getSubReg() == 0) {
851 FrameIndex = MI->getOperand(0).getIndex();
852 return MI->getOperand(2).getReg();
856 if (MI->getOperand(1).isFI() &&
857 MI->getOperand(0).getSubReg() == 0) {
858 FrameIndex = MI->getOperand(1).getIndex();
859 return MI->getOperand(0).getReg();
867 unsigned ARMBaseInstrInfo::isStoreToStackSlotPostFE(const MachineInstr *MI,
868 int &FrameIndex) const {
869 const MachineMemOperand *Dummy;
870 return MI->mayStore() && hasStoreToStackSlot(MI, Dummy, FrameIndex);
873 void ARMBaseInstrInfo::
874 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
875 unsigned DestReg, int FI,
876 const TargetRegisterClass *RC,
877 const TargetRegisterInfo *TRI) const {
879 if (I != MBB.end()) DL = I->getDebugLoc();
880 MachineFunction &MF = *MBB.getParent();
881 MachineFrameInfo &MFI = *MF.getFrameInfo();
882 unsigned Align = MFI.getObjectAlignment(FI);
883 MachineMemOperand *MMO =
884 MF.getMachineMemOperand(
885 MachinePointerInfo::getFixedStack(FI),
886 MachineMemOperand::MOLoad,
887 MFI.getObjectSize(FI),
890 switch (RC->getSize()) {
892 if (ARM::GPRRegClass.hasSubClassEq(RC)) {
893 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::LDRi12), DestReg)
894 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
896 } else if (ARM::SPRRegClass.hasSubClassEq(RC)) {
897 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDRS), DestReg)
898 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
900 llvm_unreachable("Unknown reg class!");
903 if (ARM::DPRRegClass.hasSubClassEq(RC)) {
904 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDRD), DestReg)
905 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
907 llvm_unreachable("Unknown reg class!");
910 if (ARM::QPRRegClass.hasSubClassEq(RC)) {
911 if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) {
912 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLD1q64Pseudo), DestReg)
913 .addFrameIndex(FI).addImm(16)
914 .addMemOperand(MMO));
916 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDMQIA), DestReg)
918 .addMemOperand(MMO));
921 llvm_unreachable("Unknown reg class!");
924 if (ARM::QQPRRegClass.hasSubClassEq(RC)) {
925 if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) {
926 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLD1d64QPseudo), DestReg)
927 .addFrameIndex(FI).addImm(16)
928 .addMemOperand(MMO));
930 MachineInstrBuilder MIB =
931 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDMDIA))
934 MIB = AddDReg(MIB, DestReg, ARM::dsub_0, RegState::Define, TRI);
935 MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::Define, TRI);
936 MIB = AddDReg(MIB, DestReg, ARM::dsub_2, RegState::Define, TRI);
937 MIB = AddDReg(MIB, DestReg, ARM::dsub_3, RegState::Define, TRI);
938 MIB.addReg(DestReg, RegState::Define | RegState::Implicit);
941 llvm_unreachable("Unknown reg class!");
944 if (ARM::QQQQPRRegClass.hasSubClassEq(RC)) {
945 MachineInstrBuilder MIB =
946 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDMDIA))
949 MIB = AddDReg(MIB, DestReg, ARM::dsub_0, RegState::Define, TRI);
950 MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::Define, TRI);
951 MIB = AddDReg(MIB, DestReg, ARM::dsub_2, RegState::Define, TRI);
952 MIB = AddDReg(MIB, DestReg, ARM::dsub_3, RegState::Define, TRI);
953 MIB = AddDReg(MIB, DestReg, ARM::dsub_4, RegState::Define, TRI);
954 MIB = AddDReg(MIB, DestReg, ARM::dsub_5, RegState::Define, TRI);
955 MIB = AddDReg(MIB, DestReg, ARM::dsub_6, RegState::Define, TRI);
956 MIB = AddDReg(MIB, DestReg, ARM::dsub_7, RegState::Define, TRI);
957 MIB.addReg(DestReg, RegState::Define | RegState::Implicit);
959 llvm_unreachable("Unknown reg class!");
962 llvm_unreachable("Unknown regclass!");
967 ARMBaseInstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
968 int &FrameIndex) const {
969 switch (MI->getOpcode()) {
972 case ARM::t2LDRs: // FIXME: don't use t2LDRs to access frame.
973 if (MI->getOperand(1).isFI() &&
974 MI->getOperand(2).isReg() &&
975 MI->getOperand(3).isImm() &&
976 MI->getOperand(2).getReg() == 0 &&
977 MI->getOperand(3).getImm() == 0) {
978 FrameIndex = MI->getOperand(1).getIndex();
979 return MI->getOperand(0).getReg();
987 if (MI->getOperand(1).isFI() &&
988 MI->getOperand(2).isImm() &&
989 MI->getOperand(2).getImm() == 0) {
990 FrameIndex = MI->getOperand(1).getIndex();
991 return MI->getOperand(0).getReg();
994 case ARM::VLD1q64Pseudo:
995 if (MI->getOperand(1).isFI() &&
996 MI->getOperand(0).getSubReg() == 0) {
997 FrameIndex = MI->getOperand(1).getIndex();
998 return MI->getOperand(0).getReg();
1002 if (MI->getOperand(1).isFI() &&
1003 MI->getOperand(0).getSubReg() == 0) {
1004 FrameIndex = MI->getOperand(1).getIndex();
1005 return MI->getOperand(0).getReg();
1013 unsigned ARMBaseInstrInfo::isLoadFromStackSlotPostFE(const MachineInstr *MI,
1014 int &FrameIndex) const {
1015 const MachineMemOperand *Dummy;
1016 return MI->mayLoad() && hasLoadFromStackSlot(MI, Dummy, FrameIndex);
1019 bool ARMBaseInstrInfo::expandPostRAPseudo(MachineBasicBlock::iterator MI) const{
1020 // This hook gets to expand COPY instructions before they become
1021 // copyPhysReg() calls. Look for VMOVS instructions that can legally be
1022 // widened to VMOVD. We prefer the VMOVD when possible because it may be
1023 // changed into a VORR that can go down the NEON pipeline.
1024 if (!WidenVMOVS || !MI->isCopy())
1027 // Look for a copy between even S-registers. That is where we keep floats
1028 // when using NEON v2f32 instructions for f32 arithmetic.
1029 unsigned DstRegS = MI->getOperand(0).getReg();
1030 unsigned SrcRegS = MI->getOperand(1).getReg();
1031 if (!ARM::SPRRegClass.contains(DstRegS, SrcRegS))
1034 const TargetRegisterInfo *TRI = &getRegisterInfo();
1035 unsigned DstRegD = TRI->getMatchingSuperReg(DstRegS, ARM::ssub_0,
1037 unsigned SrcRegD = TRI->getMatchingSuperReg(SrcRegS, ARM::ssub_0,
1039 if (!DstRegD || !SrcRegD)
1042 // We want to widen this into a DstRegD = VMOVD SrcRegD copy. This is only
1043 // legal if the COPY already defines the full DstRegD, and it isn't a
1044 // sub-register insertion.
1045 if (!MI->definesRegister(DstRegD, TRI) || MI->readsRegister(DstRegD, TRI))
1048 // A dead copy shouldn't show up here, but reject it just in case.
1049 if (MI->getOperand(0).isDead())
1052 // All clear, widen the COPY.
1053 DEBUG(dbgs() << "widening: " << *MI);
1055 // Get rid of the old <imp-def> of DstRegD. Leave it if it defines a Q-reg
1056 // or some other super-register.
1057 int ImpDefIdx = MI->findRegisterDefOperandIdx(DstRegD);
1058 if (ImpDefIdx != -1)
1059 MI->RemoveOperand(ImpDefIdx);
1061 // Change the opcode and operands.
1062 MI->setDesc(get(ARM::VMOVD));
1063 MI->getOperand(0).setReg(DstRegD);
1064 MI->getOperand(1).setReg(SrcRegD);
1065 AddDefaultPred(MachineInstrBuilder(MI));
1067 // We are now reading SrcRegD instead of SrcRegS. This may upset the
1068 // register scavenger and machine verifier, so we need to indicate that we
1069 // are reading an undefined value from SrcRegD, but a proper value from
1071 MI->getOperand(1).setIsUndef();
1072 MachineInstrBuilder(MI).addReg(SrcRegS, RegState::Implicit);
1074 // SrcRegD may actually contain an unrelated value in the ssub_1
1075 // sub-register. Don't kill it. Only kill the ssub_0 sub-register.
1076 if (MI->getOperand(1).isKill()) {
1077 MI->getOperand(1).setIsKill(false);
1078 MI->addRegisterKilled(SrcRegS, TRI, true);
1081 DEBUG(dbgs() << "replaced by: " << *MI);
1086 ARMBaseInstrInfo::emitFrameIndexDebugValue(MachineFunction &MF,
1087 int FrameIx, uint64_t Offset,
1088 const MDNode *MDPtr,
1089 DebugLoc DL) const {
1090 MachineInstrBuilder MIB = BuildMI(MF, DL, get(ARM::DBG_VALUE))
1091 .addFrameIndex(FrameIx).addImm(0).addImm(Offset).addMetadata(MDPtr);
1095 /// Create a copy of a const pool value. Update CPI to the new index and return
1097 static unsigned duplicateCPV(MachineFunction &MF, unsigned &CPI) {
1098 MachineConstantPool *MCP = MF.getConstantPool();
1099 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1101 const MachineConstantPoolEntry &MCPE = MCP->getConstants()[CPI];
1102 assert(MCPE.isMachineConstantPoolEntry() &&
1103 "Expecting a machine constantpool entry!");
1104 ARMConstantPoolValue *ACPV =
1105 static_cast<ARMConstantPoolValue*>(MCPE.Val.MachineCPVal);
1107 unsigned PCLabelId = AFI->createPICLabelUId();
1108 ARMConstantPoolValue *NewCPV = 0;
1109 // FIXME: The below assumes PIC relocation model and that the function
1110 // is Thumb mode (t1 or t2). PCAdjustment would be 8 for ARM mode PIC, and
1111 // zero for non-PIC in ARM or Thumb. The callers are all of thumb LDR
1112 // instructions, so that's probably OK, but is PIC always correct when
1114 if (ACPV->isGlobalValue())
1115 NewCPV = ARMConstantPoolConstant::
1116 Create(cast<ARMConstantPoolConstant>(ACPV)->getGV(), PCLabelId,
1118 else if (ACPV->isExtSymbol())
1119 NewCPV = ARMConstantPoolSymbol::
1120 Create(MF.getFunction()->getContext(),
1121 cast<ARMConstantPoolSymbol>(ACPV)->getSymbol(), PCLabelId, 4);
1122 else if (ACPV->isBlockAddress())
1123 NewCPV = ARMConstantPoolConstant::
1124 Create(cast<ARMConstantPoolConstant>(ACPV)->getBlockAddress(), PCLabelId,
1125 ARMCP::CPBlockAddress, 4);
1126 else if (ACPV->isLSDA())
1127 NewCPV = ARMConstantPoolConstant::Create(MF.getFunction(), PCLabelId,
1129 else if (ACPV->isMachineBasicBlock())
1130 NewCPV = ARMConstantPoolMBB::
1131 Create(MF.getFunction()->getContext(),
1132 cast<ARMConstantPoolMBB>(ACPV)->getMBB(), PCLabelId, 4);
1134 llvm_unreachable("Unexpected ARM constantpool value type!!");
1135 CPI = MCP->getConstantPoolIndex(NewCPV, MCPE.getAlignment());
1139 void ARMBaseInstrInfo::
1140 reMaterialize(MachineBasicBlock &MBB,
1141 MachineBasicBlock::iterator I,
1142 unsigned DestReg, unsigned SubIdx,
1143 const MachineInstr *Orig,
1144 const TargetRegisterInfo &TRI) const {
1145 unsigned Opcode = Orig->getOpcode();
1148 MachineInstr *MI = MBB.getParent()->CloneMachineInstr(Orig);
1149 MI->substituteRegister(Orig->getOperand(0).getReg(), DestReg, SubIdx, TRI);
1153 case ARM::tLDRpci_pic:
1154 case ARM::t2LDRpci_pic: {
1155 MachineFunction &MF = *MBB.getParent();
1156 unsigned CPI = Orig->getOperand(1).getIndex();
1157 unsigned PCLabelId = duplicateCPV(MF, CPI);
1158 MachineInstrBuilder MIB = BuildMI(MBB, I, Orig->getDebugLoc(), get(Opcode),
1160 .addConstantPoolIndex(CPI).addImm(PCLabelId);
1161 MIB->setMemRefs(Orig->memoperands_begin(), Orig->memoperands_end());
1168 ARMBaseInstrInfo::duplicate(MachineInstr *Orig, MachineFunction &MF) const {
1169 MachineInstr *MI = TargetInstrInfoImpl::duplicate(Orig, MF);
1170 switch(Orig->getOpcode()) {
1171 case ARM::tLDRpci_pic:
1172 case ARM::t2LDRpci_pic: {
1173 unsigned CPI = Orig->getOperand(1).getIndex();
1174 unsigned PCLabelId = duplicateCPV(MF, CPI);
1175 Orig->getOperand(1).setIndex(CPI);
1176 Orig->getOperand(2).setImm(PCLabelId);
1183 bool ARMBaseInstrInfo::produceSameValue(const MachineInstr *MI0,
1184 const MachineInstr *MI1,
1185 const MachineRegisterInfo *MRI) const {
1186 int Opcode = MI0->getOpcode();
1187 if (Opcode == ARM::t2LDRpci ||
1188 Opcode == ARM::t2LDRpci_pic ||
1189 Opcode == ARM::tLDRpci ||
1190 Opcode == ARM::tLDRpci_pic ||
1191 Opcode == ARM::MOV_ga_dyn ||
1192 Opcode == ARM::MOV_ga_pcrel ||
1193 Opcode == ARM::MOV_ga_pcrel_ldr ||
1194 Opcode == ARM::t2MOV_ga_dyn ||
1195 Opcode == ARM::t2MOV_ga_pcrel) {
1196 if (MI1->getOpcode() != Opcode)
1198 if (MI0->getNumOperands() != MI1->getNumOperands())
1201 const MachineOperand &MO0 = MI0->getOperand(1);
1202 const MachineOperand &MO1 = MI1->getOperand(1);
1203 if (MO0.getOffset() != MO1.getOffset())
1206 if (Opcode == ARM::MOV_ga_dyn ||
1207 Opcode == ARM::MOV_ga_pcrel ||
1208 Opcode == ARM::MOV_ga_pcrel_ldr ||
1209 Opcode == ARM::t2MOV_ga_dyn ||
1210 Opcode == ARM::t2MOV_ga_pcrel)
1211 // Ignore the PC labels.
1212 return MO0.getGlobal() == MO1.getGlobal();
1214 const MachineFunction *MF = MI0->getParent()->getParent();
1215 const MachineConstantPool *MCP = MF->getConstantPool();
1216 int CPI0 = MO0.getIndex();
1217 int CPI1 = MO1.getIndex();
1218 const MachineConstantPoolEntry &MCPE0 = MCP->getConstants()[CPI0];
1219 const MachineConstantPoolEntry &MCPE1 = MCP->getConstants()[CPI1];
1220 bool isARMCP0 = MCPE0.isMachineConstantPoolEntry();
1221 bool isARMCP1 = MCPE1.isMachineConstantPoolEntry();
1222 if (isARMCP0 && isARMCP1) {
1223 ARMConstantPoolValue *ACPV0 =
1224 static_cast<ARMConstantPoolValue*>(MCPE0.Val.MachineCPVal);
1225 ARMConstantPoolValue *ACPV1 =
1226 static_cast<ARMConstantPoolValue*>(MCPE1.Val.MachineCPVal);
1227 return ACPV0->hasSameValue(ACPV1);
1228 } else if (!isARMCP0 && !isARMCP1) {
1229 return MCPE0.Val.ConstVal == MCPE1.Val.ConstVal;
1232 } else if (Opcode == ARM::PICLDR) {
1233 if (MI1->getOpcode() != Opcode)
1235 if (MI0->getNumOperands() != MI1->getNumOperands())
1238 unsigned Addr0 = MI0->getOperand(1).getReg();
1239 unsigned Addr1 = MI1->getOperand(1).getReg();
1240 if (Addr0 != Addr1) {
1242 !TargetRegisterInfo::isVirtualRegister(Addr0) ||
1243 !TargetRegisterInfo::isVirtualRegister(Addr1))
1246 // This assumes SSA form.
1247 MachineInstr *Def0 = MRI->getVRegDef(Addr0);
1248 MachineInstr *Def1 = MRI->getVRegDef(Addr1);
1249 // Check if the loaded value, e.g. a constantpool of a global address, are
1251 if (!produceSameValue(Def0, Def1, MRI))
1255 for (unsigned i = 3, e = MI0->getNumOperands(); i != e; ++i) {
1256 // %vreg12<def> = PICLDR %vreg11, 0, pred:14, pred:%noreg
1257 const MachineOperand &MO0 = MI0->getOperand(i);
1258 const MachineOperand &MO1 = MI1->getOperand(i);
1259 if (!MO0.isIdenticalTo(MO1))
1265 return MI0->isIdenticalTo(MI1, MachineInstr::IgnoreVRegDefs);
1268 /// areLoadsFromSameBasePtr - This is used by the pre-regalloc scheduler to
1269 /// determine if two loads are loading from the same base address. It should
1270 /// only return true if the base pointers are the same and the only differences
1271 /// between the two addresses is the offset. It also returns the offsets by
1273 bool ARMBaseInstrInfo::areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2,
1275 int64_t &Offset2) const {
1276 // Don't worry about Thumb: just ARM and Thumb2.
1277 if (Subtarget.isThumb1Only()) return false;
1279 if (!Load1->isMachineOpcode() || !Load2->isMachineOpcode())
1282 switch (Load1->getMachineOpcode()) {
1295 case ARM::t2LDRSHi8:
1297 case ARM::t2LDRSHi12:
1301 switch (Load2->getMachineOpcode()) {
1314 case ARM::t2LDRSHi8:
1316 case ARM::t2LDRSHi12:
1320 // Check if base addresses and chain operands match.
1321 if (Load1->getOperand(0) != Load2->getOperand(0) ||
1322 Load1->getOperand(4) != Load2->getOperand(4))
1325 // Index should be Reg0.
1326 if (Load1->getOperand(3) != Load2->getOperand(3))
1329 // Determine the offsets.
1330 if (isa<ConstantSDNode>(Load1->getOperand(1)) &&
1331 isa<ConstantSDNode>(Load2->getOperand(1))) {
1332 Offset1 = cast<ConstantSDNode>(Load1->getOperand(1))->getSExtValue();
1333 Offset2 = cast<ConstantSDNode>(Load2->getOperand(1))->getSExtValue();
1340 /// shouldScheduleLoadsNear - This is a used by the pre-regalloc scheduler to
1341 /// determine (in conjunction with areLoadsFromSameBasePtr) if two loads should
1342 /// be scheduled togther. On some targets if two loads are loading from
1343 /// addresses in the same cache line, it's better if they are scheduled
1344 /// together. This function takes two integers that represent the load offsets
1345 /// from the common base address. It returns true if it decides it's desirable
1346 /// to schedule the two loads together. "NumLoads" is the number of loads that
1347 /// have already been scheduled after Load1.
1348 bool ARMBaseInstrInfo::shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,
1349 int64_t Offset1, int64_t Offset2,
1350 unsigned NumLoads) const {
1351 // Don't worry about Thumb: just ARM and Thumb2.
1352 if (Subtarget.isThumb1Only()) return false;
1354 assert(Offset2 > Offset1);
1356 if ((Offset2 - Offset1) / 8 > 64)
1359 if (Load1->getMachineOpcode() != Load2->getMachineOpcode())
1360 return false; // FIXME: overly conservative?
1362 // Four loads in a row should be sufficient.
1369 bool ARMBaseInstrInfo::isSchedulingBoundary(const MachineInstr *MI,
1370 const MachineBasicBlock *MBB,
1371 const MachineFunction &MF) const {
1372 // Debug info is never a scheduling boundary. It's necessary to be explicit
1373 // due to the special treatment of IT instructions below, otherwise a
1374 // dbg_value followed by an IT will result in the IT instruction being
1375 // considered a scheduling hazard, which is wrong. It should be the actual
1376 // instruction preceding the dbg_value instruction(s), just like it is
1377 // when debug info is not present.
1378 if (MI->isDebugValue())
1381 // Terminators and labels can't be scheduled around.
1382 if (MI->isTerminator() || MI->isLabel())
1385 // Treat the start of the IT block as a scheduling boundary, but schedule
1386 // t2IT along with all instructions following it.
1387 // FIXME: This is a big hammer. But the alternative is to add all potential
1388 // true and anti dependencies to IT block instructions as implicit operands
1389 // to the t2IT instruction. The added compile time and complexity does not
1391 MachineBasicBlock::const_iterator I = MI;
1392 // Make sure to skip any dbg_value instructions
1393 while (++I != MBB->end() && I->isDebugValue())
1395 if (I != MBB->end() && I->getOpcode() == ARM::t2IT)
1398 // Don't attempt to schedule around any instruction that defines
1399 // a stack-oriented pointer, as it's unlikely to be profitable. This
1400 // saves compile time, because it doesn't require every single
1401 // stack slot reference to depend on the instruction that does the
1403 // Calls don't actually change the stack pointer, even if they have imp-defs.
1404 // No ARM calling conventions change the stack pointer. (X86 calling
1405 // conventions sometimes do).
1406 if (!MI->isCall() && MI->definesRegister(ARM::SP))
1412 bool ARMBaseInstrInfo::
1413 isProfitableToIfCvt(MachineBasicBlock &MBB,
1414 unsigned NumCycles, unsigned ExtraPredCycles,
1415 const BranchProbability &Probability) const {
1419 // Attempt to estimate the relative costs of predication versus branching.
1420 unsigned UnpredCost = Probability.getNumerator() * NumCycles;
1421 UnpredCost /= Probability.getDenominator();
1422 UnpredCost += 1; // The branch itself
1423 UnpredCost += Subtarget.getMispredictionPenalty() / 10;
1425 return (NumCycles + ExtraPredCycles) <= UnpredCost;
1428 bool ARMBaseInstrInfo::
1429 isProfitableToIfCvt(MachineBasicBlock &TMBB,
1430 unsigned TCycles, unsigned TExtra,
1431 MachineBasicBlock &FMBB,
1432 unsigned FCycles, unsigned FExtra,
1433 const BranchProbability &Probability) const {
1434 if (!TCycles || !FCycles)
1437 // Attempt to estimate the relative costs of predication versus branching.
1438 unsigned TUnpredCost = Probability.getNumerator() * TCycles;
1439 TUnpredCost /= Probability.getDenominator();
1441 uint32_t Comp = Probability.getDenominator() - Probability.getNumerator();
1442 unsigned FUnpredCost = Comp * FCycles;
1443 FUnpredCost /= Probability.getDenominator();
1445 unsigned UnpredCost = TUnpredCost + FUnpredCost;
1446 UnpredCost += 1; // The branch itself
1447 UnpredCost += Subtarget.getMispredictionPenalty() / 10;
1449 return (TCycles + FCycles + TExtra + FExtra) <= UnpredCost;
1452 /// getInstrPredicate - If instruction is predicated, returns its predicate
1453 /// condition, otherwise returns AL. It also returns the condition code
1454 /// register by reference.
1456 llvm::getInstrPredicate(const MachineInstr *MI, unsigned &PredReg) {
1457 int PIdx = MI->findFirstPredOperandIdx();
1463 PredReg = MI->getOperand(PIdx+1).getReg();
1464 return (ARMCC::CondCodes)MI->getOperand(PIdx).getImm();
1468 int llvm::getMatchingCondBranchOpcode(int Opc) {
1473 if (Opc == ARM::t2B)
1476 llvm_unreachable("Unknown unconditional branch opcode!");
1480 /// Map pseudo instructions that imply an 'S' bit onto real opcodes. Whether the
1481 /// instruction is encoded with an 'S' bit is determined by the optional CPSR
1484 /// This will go away once we can teach tblgen how to set the optional CPSR def
1486 struct AddSubFlagsOpcodePair {
1488 unsigned MachineOpc;
1491 static AddSubFlagsOpcodePair AddSubFlagsOpcodeMap[] = {
1492 {ARM::ADDSri, ARM::ADDri},
1493 {ARM::ADDSrr, ARM::ADDrr},
1494 {ARM::ADDSrsi, ARM::ADDrsi},
1495 {ARM::ADDSrsr, ARM::ADDrsr},
1497 {ARM::SUBSri, ARM::SUBri},
1498 {ARM::SUBSrr, ARM::SUBrr},
1499 {ARM::SUBSrsi, ARM::SUBrsi},
1500 {ARM::SUBSrsr, ARM::SUBrsr},
1502 {ARM::RSBSri, ARM::RSBri},
1503 {ARM::RSBSrsi, ARM::RSBrsi},
1504 {ARM::RSBSrsr, ARM::RSBrsr},
1506 {ARM::t2ADDSri, ARM::t2ADDri},
1507 {ARM::t2ADDSrr, ARM::t2ADDrr},
1508 {ARM::t2ADDSrs, ARM::t2ADDrs},
1510 {ARM::t2SUBSri, ARM::t2SUBri},
1511 {ARM::t2SUBSrr, ARM::t2SUBrr},
1512 {ARM::t2SUBSrs, ARM::t2SUBrs},
1514 {ARM::t2RSBSri, ARM::t2RSBri},
1515 {ARM::t2RSBSrs, ARM::t2RSBrs},
1518 unsigned llvm::convertAddSubFlagsOpcode(unsigned OldOpc) {
1519 static const int NPairs =
1520 sizeof(AddSubFlagsOpcodeMap) / sizeof(AddSubFlagsOpcodePair);
1521 for (AddSubFlagsOpcodePair *OpcPair = &AddSubFlagsOpcodeMap[0],
1522 *End = &AddSubFlagsOpcodeMap[NPairs]; OpcPair != End; ++OpcPair) {
1523 if (OldOpc == OpcPair->PseudoOpc) {
1524 return OpcPair->MachineOpc;
1530 void llvm::emitARMRegPlusImmediate(MachineBasicBlock &MBB,
1531 MachineBasicBlock::iterator &MBBI, DebugLoc dl,
1532 unsigned DestReg, unsigned BaseReg, int NumBytes,
1533 ARMCC::CondCodes Pred, unsigned PredReg,
1534 const ARMBaseInstrInfo &TII, unsigned MIFlags) {
1535 bool isSub = NumBytes < 0;
1536 if (isSub) NumBytes = -NumBytes;
1539 unsigned RotAmt = ARM_AM::getSOImmValRotate(NumBytes);
1540 unsigned ThisVal = NumBytes & ARM_AM::rotr32(0xFF, RotAmt);
1541 assert(ThisVal && "Didn't extract field correctly");
1543 // We will handle these bits from offset, clear them.
1544 NumBytes &= ~ThisVal;
1546 assert(ARM_AM::getSOImmVal(ThisVal) != -1 && "Bit extraction didn't work?");
1548 // Build the new ADD / SUB.
1549 unsigned Opc = isSub ? ARM::SUBri : ARM::ADDri;
1550 BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg)
1551 .addReg(BaseReg, RegState::Kill).addImm(ThisVal)
1552 .addImm((unsigned)Pred).addReg(PredReg).addReg(0)
1553 .setMIFlags(MIFlags);
1558 bool llvm::rewriteARMFrameIndex(MachineInstr &MI, unsigned FrameRegIdx,
1559 unsigned FrameReg, int &Offset,
1560 const ARMBaseInstrInfo &TII) {
1561 unsigned Opcode = MI.getOpcode();
1562 const MCInstrDesc &Desc = MI.getDesc();
1563 unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
1566 // Memory operands in inline assembly always use AddrMode2.
1567 if (Opcode == ARM::INLINEASM)
1568 AddrMode = ARMII::AddrMode2;
1570 if (Opcode == ARM::ADDri) {
1571 Offset += MI.getOperand(FrameRegIdx+1).getImm();
1573 // Turn it into a move.
1574 MI.setDesc(TII.get(ARM::MOVr));
1575 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
1576 MI.RemoveOperand(FrameRegIdx+1);
1579 } else if (Offset < 0) {
1582 MI.setDesc(TII.get(ARM::SUBri));
1585 // Common case: small offset, fits into instruction.
1586 if (ARM_AM::getSOImmVal(Offset) != -1) {
1587 // Replace the FrameIndex with sp / fp
1588 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
1589 MI.getOperand(FrameRegIdx+1).ChangeToImmediate(Offset);
1594 // Otherwise, pull as much of the immedidate into this ADDri/SUBri
1596 unsigned RotAmt = ARM_AM::getSOImmValRotate(Offset);
1597 unsigned ThisImmVal = Offset & ARM_AM::rotr32(0xFF, RotAmt);
1599 // We will handle these bits from offset, clear them.
1600 Offset &= ~ThisImmVal;
1602 // Get the properly encoded SOImmVal field.
1603 assert(ARM_AM::getSOImmVal(ThisImmVal) != -1 &&
1604 "Bit extraction didn't work?");
1605 MI.getOperand(FrameRegIdx+1).ChangeToImmediate(ThisImmVal);
1607 unsigned ImmIdx = 0;
1609 unsigned NumBits = 0;
1612 case ARMII::AddrMode_i12: {
1613 ImmIdx = FrameRegIdx + 1;
1614 InstrOffs = MI.getOperand(ImmIdx).getImm();
1618 case ARMII::AddrMode2: {
1619 ImmIdx = FrameRegIdx+2;
1620 InstrOffs = ARM_AM::getAM2Offset(MI.getOperand(ImmIdx).getImm());
1621 if (ARM_AM::getAM2Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub)
1626 case ARMII::AddrMode3: {
1627 ImmIdx = FrameRegIdx+2;
1628 InstrOffs = ARM_AM::getAM3Offset(MI.getOperand(ImmIdx).getImm());
1629 if (ARM_AM::getAM3Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub)
1634 case ARMII::AddrMode4:
1635 case ARMII::AddrMode6:
1636 // Can't fold any offset even if it's zero.
1638 case ARMII::AddrMode5: {
1639 ImmIdx = FrameRegIdx+1;
1640 InstrOffs = ARM_AM::getAM5Offset(MI.getOperand(ImmIdx).getImm());
1641 if (ARM_AM::getAM5Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub)
1648 llvm_unreachable("Unsupported addressing mode!");
1651 Offset += InstrOffs * Scale;
1652 assert((Offset & (Scale-1)) == 0 && "Can't encode this offset!");
1658 // Attempt to fold address comp. if opcode has offset bits
1660 // Common case: small offset, fits into instruction.
1661 MachineOperand &ImmOp = MI.getOperand(ImmIdx);
1662 int ImmedOffset = Offset / Scale;
1663 unsigned Mask = (1 << NumBits) - 1;
1664 if ((unsigned)Offset <= Mask * Scale) {
1665 // Replace the FrameIndex with sp
1666 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
1667 // FIXME: When addrmode2 goes away, this will simplify (like the
1668 // T2 version), as the LDR.i12 versions don't need the encoding
1669 // tricks for the offset value.
1671 if (AddrMode == ARMII::AddrMode_i12)
1672 ImmedOffset = -ImmedOffset;
1674 ImmedOffset |= 1 << NumBits;
1676 ImmOp.ChangeToImmediate(ImmedOffset);
1681 // Otherwise, it didn't fit. Pull in what we can to simplify the immed.
1682 ImmedOffset = ImmedOffset & Mask;
1684 if (AddrMode == ARMII::AddrMode_i12)
1685 ImmedOffset = -ImmedOffset;
1687 ImmedOffset |= 1 << NumBits;
1689 ImmOp.ChangeToImmediate(ImmedOffset);
1690 Offset &= ~(Mask*Scale);
1694 Offset = (isSub) ? -Offset : Offset;
1698 bool ARMBaseInstrInfo::
1699 AnalyzeCompare(const MachineInstr *MI, unsigned &SrcReg, int &CmpMask,
1700 int &CmpValue) const {
1701 switch (MI->getOpcode()) {
1705 SrcReg = MI->getOperand(0).getReg();
1707 CmpValue = MI->getOperand(1).getImm();
1711 SrcReg = MI->getOperand(0).getReg();
1712 CmpMask = MI->getOperand(1).getImm();
1720 /// isSuitableForMask - Identify a suitable 'and' instruction that
1721 /// operates on the given source register and applies the same mask
1722 /// as a 'tst' instruction. Provide a limited look-through for copies.
1723 /// When successful, MI will hold the found instruction.
1724 static bool isSuitableForMask(MachineInstr *&MI, unsigned SrcReg,
1725 int CmpMask, bool CommonUse) {
1726 switch (MI->getOpcode()) {
1729 if (CmpMask != MI->getOperand(2).getImm())
1731 if (SrcReg == MI->getOperand(CommonUse ? 1 : 0).getReg())
1735 // Walk down one instruction which is potentially an 'and'.
1736 const MachineInstr &Copy = *MI;
1737 MachineBasicBlock::iterator AND(
1738 llvm::next(MachineBasicBlock::iterator(MI)));
1739 if (AND == MI->getParent()->end()) return false;
1741 return isSuitableForMask(MI, Copy.getOperand(0).getReg(),
1749 /// OptimizeCompareInstr - Convert the instruction supplying the argument to the
1750 /// comparison into one that sets the zero bit in the flags register.
1751 bool ARMBaseInstrInfo::
1752 OptimizeCompareInstr(MachineInstr *CmpInstr, unsigned SrcReg, int CmpMask,
1753 int CmpValue, const MachineRegisterInfo *MRI) const {
1757 MachineRegisterInfo::def_iterator DI = MRI->def_begin(SrcReg);
1758 if (llvm::next(DI) != MRI->def_end())
1759 // Only support one definition.
1762 MachineInstr *MI = &*DI;
1764 // Masked compares sometimes use the same register as the corresponding 'and'.
1765 if (CmpMask != ~0) {
1766 if (!isSuitableForMask(MI, SrcReg, CmpMask, false)) {
1768 for (MachineRegisterInfo::use_iterator UI = MRI->use_begin(SrcReg),
1769 UE = MRI->use_end(); UI != UE; ++UI) {
1770 if (UI->getParent() != CmpInstr->getParent()) continue;
1771 MachineInstr *PotentialAND = &*UI;
1772 if (!isSuitableForMask(PotentialAND, SrcReg, CmpMask, true))
1777 if (!MI) return false;
1781 // Conservatively refuse to convert an instruction which isn't in the same BB
1782 // as the comparison.
1783 if (MI->getParent() != CmpInstr->getParent())
1786 // Check that CPSR isn't set between the comparison instruction and the one we
1788 MachineBasicBlock::iterator I = CmpInstr,E = MI, B = MI->getParent()->begin();
1790 // Early exit if CmpInstr is at the beginning of the BB.
1791 if (I == B) return false;
1794 for (; I != E; --I) {
1795 const MachineInstr &Instr = *I;
1797 for (unsigned IO = 0, EO = Instr.getNumOperands(); IO != EO; ++IO) {
1798 const MachineOperand &MO = Instr.getOperand(IO);
1799 if (MO.isRegMask() && MO.clobbersPhysReg(ARM::CPSR))
1801 if (!MO.isReg()) continue;
1803 // This instruction modifies or uses CPSR after the one we want to
1804 // change. We can't do this transformation.
1805 if (MO.getReg() == ARM::CPSR)
1810 // The 'and' is below the comparison instruction.
1814 // Set the "zero" bit in CPSR.
1815 switch (MI->getOpcode()) {
1849 case ARM::t2EORri: {
1850 // Scan forward for the use of CPSR, if it's a conditional code requires
1851 // checking of V bit, then this is not safe to do. If we can't find the
1852 // CPSR use (i.e. used in another block), then it's not safe to perform
1853 // the optimization.
1854 bool isSafe = false;
1856 E = MI->getParent()->end();
1857 while (!isSafe && ++I != E) {
1858 const MachineInstr &Instr = *I;
1859 for (unsigned IO = 0, EO = Instr.getNumOperands();
1860 !isSafe && IO != EO; ++IO) {
1861 const MachineOperand &MO = Instr.getOperand(IO);
1862 if (MO.isRegMask() && MO.clobbersPhysReg(ARM::CPSR)) {
1866 if (!MO.isReg() || MO.getReg() != ARM::CPSR)
1872 // Condition code is after the operand before CPSR.
1873 ARMCC::CondCodes CC = (ARMCC::CondCodes)Instr.getOperand(IO-1).getImm();
1892 // Toggle the optional operand to CPSR.
1893 MI->getOperand(5).setReg(ARM::CPSR);
1894 MI->getOperand(5).setIsDef(true);
1895 CmpInstr->eraseFromParent();
1903 bool ARMBaseInstrInfo::FoldImmediate(MachineInstr *UseMI,
1904 MachineInstr *DefMI, unsigned Reg,
1905 MachineRegisterInfo *MRI) const {
1906 // Fold large immediates into add, sub, or, xor.
1907 unsigned DefOpc = DefMI->getOpcode();
1908 if (DefOpc != ARM::t2MOVi32imm && DefOpc != ARM::MOVi32imm)
1910 if (!DefMI->getOperand(1).isImm())
1911 // Could be t2MOVi32imm <ga:xx>
1914 if (!MRI->hasOneNonDBGUse(Reg))
1917 unsigned UseOpc = UseMI->getOpcode();
1918 unsigned NewUseOpc = 0;
1919 uint32_t ImmVal = (uint32_t)DefMI->getOperand(1).getImm();
1920 uint32_t SOImmValV1 = 0, SOImmValV2 = 0;
1921 bool Commute = false;
1923 default: return false;
1931 case ARM::t2EORrr: {
1932 Commute = UseMI->getOperand(2).getReg() != Reg;
1939 NewUseOpc = ARM::SUBri;
1945 if (!ARM_AM::isSOImmTwoPartVal(ImmVal))
1947 SOImmValV1 = (uint32_t)ARM_AM::getSOImmTwoPartFirst(ImmVal);
1948 SOImmValV2 = (uint32_t)ARM_AM::getSOImmTwoPartSecond(ImmVal);
1951 case ARM::ADDrr: NewUseOpc = ARM::ADDri; break;
1952 case ARM::ORRrr: NewUseOpc = ARM::ORRri; break;
1953 case ARM::EORrr: NewUseOpc = ARM::EORri; break;
1957 case ARM::t2SUBrr: {
1961 NewUseOpc = ARM::t2SUBri;
1966 case ARM::t2EORrr: {
1967 if (!ARM_AM::isT2SOImmTwoPartVal(ImmVal))
1969 SOImmValV1 = (uint32_t)ARM_AM::getT2SOImmTwoPartFirst(ImmVal);
1970 SOImmValV2 = (uint32_t)ARM_AM::getT2SOImmTwoPartSecond(ImmVal);
1973 case ARM::t2ADDrr: NewUseOpc = ARM::t2ADDri; break;
1974 case ARM::t2ORRrr: NewUseOpc = ARM::t2ORRri; break;
1975 case ARM::t2EORrr: NewUseOpc = ARM::t2EORri; break;
1983 unsigned OpIdx = Commute ? 2 : 1;
1984 unsigned Reg1 = UseMI->getOperand(OpIdx).getReg();
1985 bool isKill = UseMI->getOperand(OpIdx).isKill();
1986 unsigned NewReg = MRI->createVirtualRegister(MRI->getRegClass(Reg));
1987 AddDefaultCC(AddDefaultPred(BuildMI(*UseMI->getParent(),
1988 UseMI, UseMI->getDebugLoc(),
1989 get(NewUseOpc), NewReg)
1990 .addReg(Reg1, getKillRegState(isKill))
1991 .addImm(SOImmValV1)));
1992 UseMI->setDesc(get(NewUseOpc));
1993 UseMI->getOperand(1).setReg(NewReg);
1994 UseMI->getOperand(1).setIsKill();
1995 UseMI->getOperand(2).ChangeToImmediate(SOImmValV2);
1996 DefMI->eraseFromParent();
2001 ARMBaseInstrInfo::getNumMicroOps(const InstrItineraryData *ItinData,
2002 const MachineInstr *MI) const {
2003 if (!ItinData || ItinData->isEmpty())
2006 const MCInstrDesc &Desc = MI->getDesc();
2007 unsigned Class = Desc.getSchedClass();
2008 unsigned UOps = ItinData->Itineraries[Class].NumMicroOps;
2012 unsigned Opc = MI->getOpcode();
2015 llvm_unreachable("Unexpected multi-uops instruction!");
2020 // The number of uOps for load / store multiple are determined by the number
2023 // On Cortex-A8, each pair of register loads / stores can be scheduled on the
2024 // same cycle. The scheduling for the first load / store must be done
2025 // separately by assuming the the address is not 64-bit aligned.
2027 // On Cortex-A9, the formula is simply (#reg / 2) + (#reg % 2). If the address
2028 // is not 64-bit aligned, then AGU would take an extra cycle. For VFP / NEON
2029 // load / store multiple, the formula is (#reg / 2) + (#reg % 2) + 1.
2031 case ARM::VLDMDIA_UPD:
2032 case ARM::VLDMDDB_UPD:
2034 case ARM::VLDMSIA_UPD:
2035 case ARM::VLDMSDB_UPD:
2037 case ARM::VSTMDIA_UPD:
2038 case ARM::VSTMDDB_UPD:
2040 case ARM::VSTMSIA_UPD:
2041 case ARM::VSTMSDB_UPD: {
2042 unsigned NumRegs = MI->getNumOperands() - Desc.getNumOperands();
2043 return (NumRegs / 2) + (NumRegs % 2) + 1;
2046 case ARM::LDMIA_RET:
2051 case ARM::LDMIA_UPD:
2052 case ARM::LDMDA_UPD:
2053 case ARM::LDMDB_UPD:
2054 case ARM::LDMIB_UPD:
2059 case ARM::STMIA_UPD:
2060 case ARM::STMDA_UPD:
2061 case ARM::STMDB_UPD:
2062 case ARM::STMIB_UPD:
2064 case ARM::tLDMIA_UPD:
2065 case ARM::tSTMIA_UPD:
2069 case ARM::t2LDMIA_RET:
2072 case ARM::t2LDMIA_UPD:
2073 case ARM::t2LDMDB_UPD:
2076 case ARM::t2STMIA_UPD:
2077 case ARM::t2STMDB_UPD: {
2078 unsigned NumRegs = MI->getNumOperands() - Desc.getNumOperands() + 1;
2079 if (Subtarget.isCortexA8()) {
2082 // 4 registers would be issued: 2, 2.
2083 // 5 registers would be issued: 2, 2, 1.
2084 UOps = (NumRegs / 2);
2088 } else if (Subtarget.isCortexA9()) {
2089 UOps = (NumRegs / 2);
2090 // If there are odd number of registers or if it's not 64-bit aligned,
2091 // then it takes an extra AGU (Address Generation Unit) cycle.
2092 if ((NumRegs % 2) ||
2093 !MI->hasOneMemOperand() ||
2094 (*MI->memoperands_begin())->getAlignment() < 8)
2098 // Assume the worst.
2106 ARMBaseInstrInfo::getVLDMDefCycle(const InstrItineraryData *ItinData,
2107 const MCInstrDesc &DefMCID,
2109 unsigned DefIdx, unsigned DefAlign) const {
2110 int RegNo = (int)(DefIdx+1) - DefMCID.getNumOperands() + 1;
2112 // Def is the address writeback.
2113 return ItinData->getOperandCycle(DefClass, DefIdx);
2116 if (Subtarget.isCortexA8()) {
2117 // (regno / 2) + (regno % 2) + 1
2118 DefCycle = RegNo / 2 + 1;
2121 } else if (Subtarget.isCortexA9()) {
2123 bool isSLoad = false;
2125 switch (DefMCID.getOpcode()) {
2128 case ARM::VLDMSIA_UPD:
2129 case ARM::VLDMSDB_UPD:
2134 // If there are odd number of 'S' registers or if it's not 64-bit aligned,
2135 // then it takes an extra cycle.
2136 if ((isSLoad && (RegNo % 2)) || DefAlign < 8)
2139 // Assume the worst.
2140 DefCycle = RegNo + 2;
2147 ARMBaseInstrInfo::getLDMDefCycle(const InstrItineraryData *ItinData,
2148 const MCInstrDesc &DefMCID,
2150 unsigned DefIdx, unsigned DefAlign) const {
2151 int RegNo = (int)(DefIdx+1) - DefMCID.getNumOperands() + 1;
2153 // Def is the address writeback.
2154 return ItinData->getOperandCycle(DefClass, DefIdx);
2157 if (Subtarget.isCortexA8()) {
2158 // 4 registers would be issued: 1, 2, 1.
2159 // 5 registers would be issued: 1, 2, 2.
2160 DefCycle = RegNo / 2;
2163 // Result latency is issue cycle + 2: E2.
2165 } else if (Subtarget.isCortexA9()) {
2166 DefCycle = (RegNo / 2);
2167 // If there are odd number of registers or if it's not 64-bit aligned,
2168 // then it takes an extra AGU (Address Generation Unit) cycle.
2169 if ((RegNo % 2) || DefAlign < 8)
2171 // Result latency is AGU cycles + 2.
2174 // Assume the worst.
2175 DefCycle = RegNo + 2;
2182 ARMBaseInstrInfo::getVSTMUseCycle(const InstrItineraryData *ItinData,
2183 const MCInstrDesc &UseMCID,
2185 unsigned UseIdx, unsigned UseAlign) const {
2186 int RegNo = (int)(UseIdx+1) - UseMCID.getNumOperands() + 1;
2188 return ItinData->getOperandCycle(UseClass, UseIdx);
2191 if (Subtarget.isCortexA8()) {
2192 // (regno / 2) + (regno % 2) + 1
2193 UseCycle = RegNo / 2 + 1;
2196 } else if (Subtarget.isCortexA9()) {
2198 bool isSStore = false;
2200 switch (UseMCID.getOpcode()) {
2203 case ARM::VSTMSIA_UPD:
2204 case ARM::VSTMSDB_UPD:
2209 // If there are odd number of 'S' registers or if it's not 64-bit aligned,
2210 // then it takes an extra cycle.
2211 if ((isSStore && (RegNo % 2)) || UseAlign < 8)
2214 // Assume the worst.
2215 UseCycle = RegNo + 2;
2222 ARMBaseInstrInfo::getSTMUseCycle(const InstrItineraryData *ItinData,
2223 const MCInstrDesc &UseMCID,
2225 unsigned UseIdx, unsigned UseAlign) const {
2226 int RegNo = (int)(UseIdx+1) - UseMCID.getNumOperands() + 1;
2228 return ItinData->getOperandCycle(UseClass, UseIdx);
2231 if (Subtarget.isCortexA8()) {
2232 UseCycle = RegNo / 2;
2237 } else if (Subtarget.isCortexA9()) {
2238 UseCycle = (RegNo / 2);
2239 // If there are odd number of registers or if it's not 64-bit aligned,
2240 // then it takes an extra AGU (Address Generation Unit) cycle.
2241 if ((RegNo % 2) || UseAlign < 8)
2244 // Assume the worst.
2251 ARMBaseInstrInfo::getOperandLatency(const InstrItineraryData *ItinData,
2252 const MCInstrDesc &DefMCID,
2253 unsigned DefIdx, unsigned DefAlign,
2254 const MCInstrDesc &UseMCID,
2255 unsigned UseIdx, unsigned UseAlign) const {
2256 unsigned DefClass = DefMCID.getSchedClass();
2257 unsigned UseClass = UseMCID.getSchedClass();
2259 if (DefIdx < DefMCID.getNumDefs() && UseIdx < UseMCID.getNumOperands())
2260 return ItinData->getOperandLatency(DefClass, DefIdx, UseClass, UseIdx);
2262 // This may be a def / use of a variable_ops instruction, the operand
2263 // latency might be determinable dynamically. Let the target try to
2266 bool LdmBypass = false;
2267 switch (DefMCID.getOpcode()) {
2269 DefCycle = ItinData->getOperandCycle(DefClass, DefIdx);
2273 case ARM::VLDMDIA_UPD:
2274 case ARM::VLDMDDB_UPD:
2276 case ARM::VLDMSIA_UPD:
2277 case ARM::VLDMSDB_UPD:
2278 DefCycle = getVLDMDefCycle(ItinData, DefMCID, DefClass, DefIdx, DefAlign);
2281 case ARM::LDMIA_RET:
2286 case ARM::LDMIA_UPD:
2287 case ARM::LDMDA_UPD:
2288 case ARM::LDMDB_UPD:
2289 case ARM::LDMIB_UPD:
2291 case ARM::tLDMIA_UPD:
2293 case ARM::t2LDMIA_RET:
2296 case ARM::t2LDMIA_UPD:
2297 case ARM::t2LDMDB_UPD:
2299 DefCycle = getLDMDefCycle(ItinData, DefMCID, DefClass, DefIdx, DefAlign);
2304 // We can't seem to determine the result latency of the def, assume it's 2.
2308 switch (UseMCID.getOpcode()) {
2310 UseCycle = ItinData->getOperandCycle(UseClass, UseIdx);
2314 case ARM::VSTMDIA_UPD:
2315 case ARM::VSTMDDB_UPD:
2317 case ARM::VSTMSIA_UPD:
2318 case ARM::VSTMSDB_UPD:
2319 UseCycle = getVSTMUseCycle(ItinData, UseMCID, UseClass, UseIdx, UseAlign);
2326 case ARM::STMIA_UPD:
2327 case ARM::STMDA_UPD:
2328 case ARM::STMDB_UPD:
2329 case ARM::STMIB_UPD:
2330 case ARM::tSTMIA_UPD:
2335 case ARM::t2STMIA_UPD:
2336 case ARM::t2STMDB_UPD:
2337 UseCycle = getSTMUseCycle(ItinData, UseMCID, UseClass, UseIdx, UseAlign);
2342 // Assume it's read in the first stage.
2345 UseCycle = DefCycle - UseCycle + 1;
2348 // It's a variable_ops instruction so we can't use DefIdx here. Just use
2349 // first def operand.
2350 if (ItinData->hasPipelineForwarding(DefClass, DefMCID.getNumOperands()-1,
2353 } else if (ItinData->hasPipelineForwarding(DefClass, DefIdx,
2354 UseClass, UseIdx)) {
2362 static const MachineInstr *getBundledDefMI(const TargetRegisterInfo *TRI,
2363 const MachineInstr *MI, unsigned Reg,
2364 unsigned &DefIdx, unsigned &Dist) {
2367 MachineBasicBlock::const_iterator I = MI; ++I;
2368 MachineBasicBlock::const_instr_iterator II =
2369 llvm::prior(I.getInstrIterator());
2370 assert(II->isInsideBundle() && "Empty bundle?");
2373 while (II->isInsideBundle()) {
2374 Idx = II->findRegisterDefOperandIdx(Reg, false, true, TRI);
2381 assert(Idx != -1 && "Cannot find bundled definition!");
2386 static const MachineInstr *getBundledUseMI(const TargetRegisterInfo *TRI,
2387 const MachineInstr *MI, unsigned Reg,
2388 unsigned &UseIdx, unsigned &Dist) {
2391 MachineBasicBlock::const_instr_iterator II = MI; ++II;
2392 assert(II->isInsideBundle() && "Empty bundle?");
2393 MachineBasicBlock::const_instr_iterator E = MI->getParent()->instr_end();
2395 // FIXME: This doesn't properly handle multiple uses.
2397 while (II != E && II->isInsideBundle()) {
2398 Idx = II->findRegisterUseOperandIdx(Reg, false, TRI);
2401 if (II->getOpcode() != ARM::t2IT)
2416 ARMBaseInstrInfo::getOperandLatency(const InstrItineraryData *ItinData,
2417 const MachineInstr *DefMI, unsigned DefIdx,
2418 const MachineInstr *UseMI, unsigned UseIdx) const {
2419 if (DefMI->isCopyLike() || DefMI->isInsertSubreg() ||
2420 DefMI->isRegSequence() || DefMI->isImplicitDef())
2423 if (!ItinData || ItinData->isEmpty())
2424 return DefMI->mayLoad() ? 3 : 1;
2426 const MCInstrDesc *DefMCID = &DefMI->getDesc();
2427 const MCInstrDesc *UseMCID = &UseMI->getDesc();
2428 const MachineOperand &DefMO = DefMI->getOperand(DefIdx);
2429 unsigned Reg = DefMO.getReg();
2430 if (Reg == ARM::CPSR) {
2431 if (DefMI->getOpcode() == ARM::FMSTAT) {
2432 // fpscr -> cpsr stalls over 20 cycles on A8 (and earlier?)
2433 return Subtarget.isCortexA9() ? 1 : 20;
2436 // CPSR set and branch can be paired in the same cycle.
2437 if (UseMI->isBranch())
2440 // Otherwise it takes the instruction latency (generally one).
2441 int Latency = getInstrLatency(ItinData, DefMI);
2443 // For Thumb2 and -Os, prefer scheduling CPSR setting instruction close to
2444 // its uses. Instructions which are otherwise scheduled between them may
2445 // incur a code size penalty (not able to use the CPSR setting 16-bit
2447 if (Latency > 0 && Subtarget.isThumb2()) {
2448 const MachineFunction *MF = DefMI->getParent()->getParent();
2449 if (MF->getFunction()->hasFnAttr(Attribute::OptimizeForSize))
2455 unsigned DefAlign = DefMI->hasOneMemOperand()
2456 ? (*DefMI->memoperands_begin())->getAlignment() : 0;
2457 unsigned UseAlign = UseMI->hasOneMemOperand()
2458 ? (*UseMI->memoperands_begin())->getAlignment() : 0;
2460 unsigned DefAdj = 0;
2461 if (DefMI->isBundle()) {
2462 DefMI = getBundledDefMI(&getRegisterInfo(), DefMI, Reg, DefIdx, DefAdj);
2463 if (DefMI->isCopyLike() || DefMI->isInsertSubreg() ||
2464 DefMI->isRegSequence() || DefMI->isImplicitDef())
2466 DefMCID = &DefMI->getDesc();
2468 unsigned UseAdj = 0;
2469 if (UseMI->isBundle()) {
2471 const MachineInstr *NewUseMI = getBundledUseMI(&getRegisterInfo(), UseMI,
2472 Reg, NewUseIdx, UseAdj);
2476 UseMCID = &UseMI->getDesc();
2480 int Latency = getOperandLatency(ItinData, *DefMCID, DefIdx, DefAlign,
2481 *UseMCID, UseIdx, UseAlign);
2482 int Adj = DefAdj + UseAdj;
2484 Latency -= (int)(DefAdj + UseAdj);
2490 (Subtarget.isCortexA8() || Subtarget.isCortexA9())) {
2491 // FIXME: Shifter op hack: no shift (i.e. [r +/- r]) or [r + r << 2]
2492 // variants are one cycle cheaper.
2493 switch (DefMCID->getOpcode()) {
2497 unsigned ShOpVal = DefMI->getOperand(3).getImm();
2498 unsigned ShImm = ARM_AM::getAM2Offset(ShOpVal);
2500 (ShImm == 2 && ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl))
2507 case ARM::t2LDRSHs: {
2508 // Thumb2 mode: lsl only.
2509 unsigned ShAmt = DefMI->getOperand(3).getImm();
2510 if (ShAmt == 0 || ShAmt == 2)
2517 if (DefAlign < 8 && Subtarget.isCortexA9())
2518 switch (DefMCID->getOpcode()) {
2524 case ARM::VLD1q8wb_fixed:
2525 case ARM::VLD1q16wb_fixed:
2526 case ARM::VLD1q32wb_fixed:
2527 case ARM::VLD1q64wb_fixed:
2528 case ARM::VLD1q8wb_register:
2529 case ARM::VLD1q16wb_register:
2530 case ARM::VLD1q32wb_register:
2531 case ARM::VLD1q64wb_register:
2538 case ARM::VLD2d8wb_fixed:
2539 case ARM::VLD2d16wb_fixed:
2540 case ARM::VLD2d32wb_fixed:
2541 case ARM::VLD2q8wb_fixed:
2542 case ARM::VLD2q16wb_fixed:
2543 case ARM::VLD2q32wb_fixed:
2544 case ARM::VLD2d8wb_register:
2545 case ARM::VLD2d16wb_register:
2546 case ARM::VLD2d32wb_register:
2547 case ARM::VLD2q8wb_register:
2548 case ARM::VLD2q16wb_register:
2549 case ARM::VLD2q32wb_register:
2554 case ARM::VLD3d8_UPD:
2555 case ARM::VLD3d16_UPD:
2556 case ARM::VLD3d32_UPD:
2557 case ARM::VLD1d64Twb_fixed:
2558 case ARM::VLD1d64Twb_register:
2559 case ARM::VLD3q8_UPD:
2560 case ARM::VLD3q16_UPD:
2561 case ARM::VLD3q32_UPD:
2566 case ARM::VLD4d8_UPD:
2567 case ARM::VLD4d16_UPD:
2568 case ARM::VLD4d32_UPD:
2569 case ARM::VLD1d64Qwb_fixed:
2570 case ARM::VLD1d64Qwb_register:
2571 case ARM::VLD4q8_UPD:
2572 case ARM::VLD4q16_UPD:
2573 case ARM::VLD4q32_UPD:
2574 case ARM::VLD1DUPq8:
2575 case ARM::VLD1DUPq16:
2576 case ARM::VLD1DUPq32:
2577 case ARM::VLD1DUPq8wb_fixed:
2578 case ARM::VLD1DUPq16wb_fixed:
2579 case ARM::VLD1DUPq32wb_fixed:
2580 case ARM::VLD1DUPq8wb_register:
2581 case ARM::VLD1DUPq16wb_register:
2582 case ARM::VLD1DUPq32wb_register:
2583 case ARM::VLD2DUPd8:
2584 case ARM::VLD2DUPd16:
2585 case ARM::VLD2DUPd32:
2586 case ARM::VLD2DUPd8wb_fixed:
2587 case ARM::VLD2DUPd16wb_fixed:
2588 case ARM::VLD2DUPd32wb_fixed:
2589 case ARM::VLD2DUPd8wb_register:
2590 case ARM::VLD2DUPd16wb_register:
2591 case ARM::VLD2DUPd32wb_register:
2592 case ARM::VLD4DUPd8:
2593 case ARM::VLD4DUPd16:
2594 case ARM::VLD4DUPd32:
2595 case ARM::VLD4DUPd8_UPD:
2596 case ARM::VLD4DUPd16_UPD:
2597 case ARM::VLD4DUPd32_UPD:
2599 case ARM::VLD1LNd16:
2600 case ARM::VLD1LNd32:
2601 case ARM::VLD1LNd8_UPD:
2602 case ARM::VLD1LNd16_UPD:
2603 case ARM::VLD1LNd32_UPD:
2605 case ARM::VLD2LNd16:
2606 case ARM::VLD2LNd32:
2607 case ARM::VLD2LNq16:
2608 case ARM::VLD2LNq32:
2609 case ARM::VLD2LNd8_UPD:
2610 case ARM::VLD2LNd16_UPD:
2611 case ARM::VLD2LNd32_UPD:
2612 case ARM::VLD2LNq16_UPD:
2613 case ARM::VLD2LNq32_UPD:
2615 case ARM::VLD4LNd16:
2616 case ARM::VLD4LNd32:
2617 case ARM::VLD4LNq16:
2618 case ARM::VLD4LNq32:
2619 case ARM::VLD4LNd8_UPD:
2620 case ARM::VLD4LNd16_UPD:
2621 case ARM::VLD4LNd32_UPD:
2622 case ARM::VLD4LNq16_UPD:
2623 case ARM::VLD4LNq32_UPD:
2624 // If the address is not 64-bit aligned, the latencies of these
2625 // instructions increases by one.
2634 ARMBaseInstrInfo::getOperandLatency(const InstrItineraryData *ItinData,
2635 SDNode *DefNode, unsigned DefIdx,
2636 SDNode *UseNode, unsigned UseIdx) const {
2637 if (!DefNode->isMachineOpcode())
2640 const MCInstrDesc &DefMCID = get(DefNode->getMachineOpcode());
2642 if (isZeroCost(DefMCID.Opcode))
2645 if (!ItinData || ItinData->isEmpty())
2646 return DefMCID.mayLoad() ? 3 : 1;
2648 if (!UseNode->isMachineOpcode()) {
2649 int Latency = ItinData->getOperandCycle(DefMCID.getSchedClass(), DefIdx);
2650 if (Subtarget.isCortexA9())
2651 return Latency <= 2 ? 1 : Latency - 1;
2653 return Latency <= 3 ? 1 : Latency - 2;
2656 const MCInstrDesc &UseMCID = get(UseNode->getMachineOpcode());
2657 const MachineSDNode *DefMN = dyn_cast<MachineSDNode>(DefNode);
2658 unsigned DefAlign = !DefMN->memoperands_empty()
2659 ? (*DefMN->memoperands_begin())->getAlignment() : 0;
2660 const MachineSDNode *UseMN = dyn_cast<MachineSDNode>(UseNode);
2661 unsigned UseAlign = !UseMN->memoperands_empty()
2662 ? (*UseMN->memoperands_begin())->getAlignment() : 0;
2663 int Latency = getOperandLatency(ItinData, DefMCID, DefIdx, DefAlign,
2664 UseMCID, UseIdx, UseAlign);
2667 (Subtarget.isCortexA8() || Subtarget.isCortexA9())) {
2668 // FIXME: Shifter op hack: no shift (i.e. [r +/- r]) or [r + r << 2]
2669 // variants are one cycle cheaper.
2670 switch (DefMCID.getOpcode()) {
2675 cast<ConstantSDNode>(DefNode->getOperand(2))->getZExtValue();
2676 unsigned ShImm = ARM_AM::getAM2Offset(ShOpVal);
2678 (ShImm == 2 && ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl))
2685 case ARM::t2LDRSHs: {
2686 // Thumb2 mode: lsl only.
2688 cast<ConstantSDNode>(DefNode->getOperand(2))->getZExtValue();
2689 if (ShAmt == 0 || ShAmt == 2)
2696 if (DefAlign < 8 && Subtarget.isCortexA9())
2697 switch (DefMCID.getOpcode()) {
2699 case ARM::VLD1q8Pseudo:
2700 case ARM::VLD1q16Pseudo:
2701 case ARM::VLD1q32Pseudo:
2702 case ARM::VLD1q64Pseudo:
2703 case ARM::VLD1q8PseudoWB_register:
2704 case ARM::VLD1q16PseudoWB_register:
2705 case ARM::VLD1q32PseudoWB_register:
2706 case ARM::VLD1q64PseudoWB_register:
2707 case ARM::VLD1q8PseudoWB_fixed:
2708 case ARM::VLD1q16PseudoWB_fixed:
2709 case ARM::VLD1q32PseudoWB_fixed:
2710 case ARM::VLD1q64PseudoWB_fixed:
2711 case ARM::VLD2d8Pseudo:
2712 case ARM::VLD2d16Pseudo:
2713 case ARM::VLD2d32Pseudo:
2714 case ARM::VLD2q8Pseudo:
2715 case ARM::VLD2q16Pseudo:
2716 case ARM::VLD2q32Pseudo:
2717 case ARM::VLD2d8PseudoWB_fixed:
2718 case ARM::VLD2d16PseudoWB_fixed:
2719 case ARM::VLD2d32PseudoWB_fixed:
2720 case ARM::VLD2q8PseudoWB_fixed:
2721 case ARM::VLD2q16PseudoWB_fixed:
2722 case ARM::VLD2q32PseudoWB_fixed:
2723 case ARM::VLD2d8PseudoWB_register:
2724 case ARM::VLD2d16PseudoWB_register:
2725 case ARM::VLD2d32PseudoWB_register:
2726 case ARM::VLD2q8PseudoWB_register:
2727 case ARM::VLD2q16PseudoWB_register:
2728 case ARM::VLD2q32PseudoWB_register:
2729 case ARM::VLD3d8Pseudo:
2730 case ARM::VLD3d16Pseudo:
2731 case ARM::VLD3d32Pseudo:
2732 case ARM::VLD1d64TPseudo:
2733 case ARM::VLD3d8Pseudo_UPD:
2734 case ARM::VLD3d16Pseudo_UPD:
2735 case ARM::VLD3d32Pseudo_UPD:
2736 case ARM::VLD3q8Pseudo_UPD:
2737 case ARM::VLD3q16Pseudo_UPD:
2738 case ARM::VLD3q32Pseudo_UPD:
2739 case ARM::VLD3q8oddPseudo:
2740 case ARM::VLD3q16oddPseudo:
2741 case ARM::VLD3q32oddPseudo:
2742 case ARM::VLD3q8oddPseudo_UPD:
2743 case ARM::VLD3q16oddPseudo_UPD:
2744 case ARM::VLD3q32oddPseudo_UPD:
2745 case ARM::VLD4d8Pseudo:
2746 case ARM::VLD4d16Pseudo:
2747 case ARM::VLD4d32Pseudo:
2748 case ARM::VLD1d64QPseudo:
2749 case ARM::VLD4d8Pseudo_UPD:
2750 case ARM::VLD4d16Pseudo_UPD:
2751 case ARM::VLD4d32Pseudo_UPD:
2752 case ARM::VLD4q8Pseudo_UPD:
2753 case ARM::VLD4q16Pseudo_UPD:
2754 case ARM::VLD4q32Pseudo_UPD:
2755 case ARM::VLD4q8oddPseudo:
2756 case ARM::VLD4q16oddPseudo:
2757 case ARM::VLD4q32oddPseudo:
2758 case ARM::VLD4q8oddPseudo_UPD:
2759 case ARM::VLD4q16oddPseudo_UPD:
2760 case ARM::VLD4q32oddPseudo_UPD:
2761 case ARM::VLD1DUPq8Pseudo:
2762 case ARM::VLD1DUPq16Pseudo:
2763 case ARM::VLD1DUPq32Pseudo:
2764 case ARM::VLD1DUPq8PseudoWB_fixed:
2765 case ARM::VLD1DUPq16PseudoWB_fixed:
2766 case ARM::VLD1DUPq32PseudoWB_fixed:
2767 case ARM::VLD1DUPq8PseudoWB_register:
2768 case ARM::VLD1DUPq16PseudoWB_register:
2769 case ARM::VLD1DUPq32PseudoWB_register:
2770 case ARM::VLD2DUPd8Pseudo:
2771 case ARM::VLD2DUPd16Pseudo:
2772 case ARM::VLD2DUPd32Pseudo:
2773 case ARM::VLD2DUPd8PseudoWB_fixed:
2774 case ARM::VLD2DUPd16PseudoWB_fixed:
2775 case ARM::VLD2DUPd32PseudoWB_fixed:
2776 case ARM::VLD2DUPd8PseudoWB_register:
2777 case ARM::VLD2DUPd16PseudoWB_register:
2778 case ARM::VLD2DUPd32PseudoWB_register:
2779 case ARM::VLD4DUPd8Pseudo:
2780 case ARM::VLD4DUPd16Pseudo:
2781 case ARM::VLD4DUPd32Pseudo:
2782 case ARM::VLD4DUPd8Pseudo_UPD:
2783 case ARM::VLD4DUPd16Pseudo_UPD:
2784 case ARM::VLD4DUPd32Pseudo_UPD:
2785 case ARM::VLD1LNq8Pseudo:
2786 case ARM::VLD1LNq16Pseudo:
2787 case ARM::VLD1LNq32Pseudo:
2788 case ARM::VLD1LNq8Pseudo_UPD:
2789 case ARM::VLD1LNq16Pseudo_UPD:
2790 case ARM::VLD1LNq32Pseudo_UPD:
2791 case ARM::VLD2LNd8Pseudo:
2792 case ARM::VLD2LNd16Pseudo:
2793 case ARM::VLD2LNd32Pseudo:
2794 case ARM::VLD2LNq16Pseudo:
2795 case ARM::VLD2LNq32Pseudo:
2796 case ARM::VLD2LNd8Pseudo_UPD:
2797 case ARM::VLD2LNd16Pseudo_UPD:
2798 case ARM::VLD2LNd32Pseudo_UPD:
2799 case ARM::VLD2LNq16Pseudo_UPD:
2800 case ARM::VLD2LNq32Pseudo_UPD:
2801 case ARM::VLD4LNd8Pseudo:
2802 case ARM::VLD4LNd16Pseudo:
2803 case ARM::VLD4LNd32Pseudo:
2804 case ARM::VLD4LNq16Pseudo:
2805 case ARM::VLD4LNq32Pseudo:
2806 case ARM::VLD4LNd8Pseudo_UPD:
2807 case ARM::VLD4LNd16Pseudo_UPD:
2808 case ARM::VLD4LNd32Pseudo_UPD:
2809 case ARM::VLD4LNq16Pseudo_UPD:
2810 case ARM::VLD4LNq32Pseudo_UPD:
2811 // If the address is not 64-bit aligned, the latencies of these
2812 // instructions increases by one.
2821 ARMBaseInstrInfo::getOutputLatency(const InstrItineraryData *ItinData,
2822 const MachineInstr *DefMI, unsigned DefIdx,
2823 const MachineInstr *DepMI) const {
2824 unsigned Reg = DefMI->getOperand(DefIdx).getReg();
2825 if (DepMI->readsRegister(Reg, &getRegisterInfo()) || !isPredicated(DepMI))
2828 // If the second MI is predicated, then there is an implicit use dependency.
2829 return getOperandLatency(ItinData, DefMI, DefIdx, DepMI,
2830 DepMI->getNumOperands());
2833 int ARMBaseInstrInfo::getInstrLatency(const InstrItineraryData *ItinData,
2834 const MachineInstr *MI,
2835 unsigned *PredCost) const {
2836 if (MI->isCopyLike() || MI->isInsertSubreg() ||
2837 MI->isRegSequence() || MI->isImplicitDef())
2840 if (!ItinData || ItinData->isEmpty())
2843 if (MI->isBundle()) {
2845 MachineBasicBlock::const_instr_iterator I = MI;
2846 MachineBasicBlock::const_instr_iterator E = MI->getParent()->instr_end();
2847 while (++I != E && I->isInsideBundle()) {
2848 if (I->getOpcode() != ARM::t2IT)
2849 Latency += getInstrLatency(ItinData, I, PredCost);
2854 const MCInstrDesc &MCID = MI->getDesc();
2855 unsigned Class = MCID.getSchedClass();
2856 unsigned UOps = ItinData->Itineraries[Class].NumMicroOps;
2857 if (PredCost && (MCID.isCall() || MCID.hasImplicitDefOfPhysReg(ARM::CPSR)))
2858 // When predicated, CPSR is an additional source operand for CPSR updating
2859 // instructions, this apparently increases their latencies.
2862 return ItinData->getStageLatency(Class);
2863 return getNumMicroOps(ItinData, MI);
2866 int ARMBaseInstrInfo::getInstrLatency(const InstrItineraryData *ItinData,
2867 SDNode *Node) const {
2868 if (!Node->isMachineOpcode())
2871 if (!ItinData || ItinData->isEmpty())
2874 unsigned Opcode = Node->getMachineOpcode();
2877 return ItinData->getStageLatency(get(Opcode).getSchedClass());
2884 bool ARMBaseInstrInfo::
2885 hasHighOperandLatency(const InstrItineraryData *ItinData,
2886 const MachineRegisterInfo *MRI,
2887 const MachineInstr *DefMI, unsigned DefIdx,
2888 const MachineInstr *UseMI, unsigned UseIdx) const {
2889 unsigned DDomain = DefMI->getDesc().TSFlags & ARMII::DomainMask;
2890 unsigned UDomain = UseMI->getDesc().TSFlags & ARMII::DomainMask;
2891 if (Subtarget.isCortexA8() &&
2892 (DDomain == ARMII::DomainVFP || UDomain == ARMII::DomainVFP))
2893 // CortexA8 VFP instructions are not pipelined.
2896 // Hoist VFP / NEON instructions with 4 or higher latency.
2897 int Latency = getOperandLatency(ItinData, DefMI, DefIdx, UseMI, UseIdx);
2900 return DDomain == ARMII::DomainVFP || DDomain == ARMII::DomainNEON ||
2901 UDomain == ARMII::DomainVFP || UDomain == ARMII::DomainNEON;
2904 bool ARMBaseInstrInfo::
2905 hasLowDefLatency(const InstrItineraryData *ItinData,
2906 const MachineInstr *DefMI, unsigned DefIdx) const {
2907 if (!ItinData || ItinData->isEmpty())
2910 unsigned DDomain = DefMI->getDesc().TSFlags & ARMII::DomainMask;
2911 if (DDomain == ARMII::DomainGeneral) {
2912 unsigned DefClass = DefMI->getDesc().getSchedClass();
2913 int DefCycle = ItinData->getOperandCycle(DefClass, DefIdx);
2914 return (DefCycle != -1 && DefCycle <= 2);
2919 bool ARMBaseInstrInfo::verifyInstruction(const MachineInstr *MI,
2920 StringRef &ErrInfo) const {
2921 if (convertAddSubFlagsOpcode(MI->getOpcode())) {
2922 ErrInfo = "Pseudo flag setting opcodes only exist in Selection DAG";
2929 ARMBaseInstrInfo::isFpMLxInstruction(unsigned Opcode, unsigned &MulOpc,
2930 unsigned &AddSubOpc,
2931 bool &NegAcc, bool &HasLane) const {
2932 DenseMap<unsigned, unsigned>::const_iterator I = MLxEntryMap.find(Opcode);
2933 if (I == MLxEntryMap.end())
2936 const ARM_MLxEntry &Entry = ARM_MLxTable[I->second];
2937 MulOpc = Entry.MulOpc;
2938 AddSubOpc = Entry.AddSubOpc;
2939 NegAcc = Entry.NegAcc;
2940 HasLane = Entry.HasLane;
2944 //===----------------------------------------------------------------------===//
2945 // Execution domains.
2946 //===----------------------------------------------------------------------===//
2948 // Some instructions go down the NEON pipeline, some go down the VFP pipeline,
2949 // and some can go down both. The vmov instructions go down the VFP pipeline,
2950 // but they can be changed to vorr equivalents that are executed by the NEON
2953 // We use the following execution domain numbering:
2961 // Also see ARMInstrFormats.td and Domain* enums in ARMBaseInfo.h
2963 std::pair<uint16_t, uint16_t>
2964 ARMBaseInstrInfo::getExecutionDomain(const MachineInstr *MI) const {
2965 // VMOVD is a VFP instruction, but can be changed to NEON if it isn't
2967 if (MI->getOpcode() == ARM::VMOVD && !isPredicated(MI))
2968 return std::make_pair(ExeVFP, (1<<ExeVFP) | (1<<ExeNEON));
2970 // No other instructions can be swizzled, so just determine their domain.
2971 unsigned Domain = MI->getDesc().TSFlags & ARMII::DomainMask;
2973 if (Domain & ARMII::DomainNEON)
2974 return std::make_pair(ExeNEON, 0);
2976 // Certain instructions can go either way on Cortex-A8.
2977 // Treat them as NEON instructions.
2978 if ((Domain & ARMII::DomainNEONA8) && Subtarget.isCortexA8())
2979 return std::make_pair(ExeNEON, 0);
2981 if (Domain & ARMII::DomainVFP)
2982 return std::make_pair(ExeVFP, 0);
2984 return std::make_pair(ExeGeneric, 0);
2988 ARMBaseInstrInfo::setExecutionDomain(MachineInstr *MI, unsigned Domain) const {
2989 // We only know how to change VMOVD into VORR.
2990 assert(MI->getOpcode() == ARM::VMOVD && "Can only swizzle VMOVD");
2991 if (Domain != ExeNEON)
2994 // Zap the predicate operands.
2995 assert(!isPredicated(MI) && "Cannot predicate a VORRd");
2996 MI->RemoveOperand(3);
2997 MI->RemoveOperand(2);
2999 // Change to a VORRd which requires two identical use operands.
3000 MI->setDesc(get(ARM::VORRd));
3002 // Add the extra source operand and new predicates.
3003 // This will go before any implicit ops.
3004 AddDefaultPred(MachineInstrBuilder(MI).addOperand(MI->getOperand(1)));