1 //===- ARMBaseInstrInfo.cpp - ARM Instruction Information -------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Base ARM implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "ARMBaseInstrInfo.h"
16 #include "ARMAddressingModes.h"
17 #include "ARMConstantPoolValue.h"
18 #include "ARMGenInstrInfo.inc"
19 #include "ARMMachineFunctionInfo.h"
20 #include "ARMRegisterInfo.h"
21 #include "llvm/Constants.h"
22 #include "llvm/Function.h"
23 #include "llvm/GlobalValue.h"
24 #include "llvm/ADT/STLExtras.h"
25 #include "llvm/CodeGen/LiveVariables.h"
26 #include "llvm/CodeGen/MachineConstantPool.h"
27 #include "llvm/CodeGen/MachineFrameInfo.h"
28 #include "llvm/CodeGen/MachineInstrBuilder.h"
29 #include "llvm/CodeGen/MachineJumpTableInfo.h"
30 #include "llvm/CodeGen/MachineMemOperand.h"
31 #include "llvm/CodeGen/MachineRegisterInfo.h"
32 #include "llvm/CodeGen/PseudoSourceValue.h"
33 #include "llvm/MC/MCAsmInfo.h"
34 #include "llvm/Support/CommandLine.h"
35 #include "llvm/Support/Debug.h"
36 #include "llvm/Support/ErrorHandling.h"
40 EnableARM3Addr("enable-arm-3-addr-conv", cl::Hidden,
41 cl::desc("Enable ARM 2-addr to 3-addr conv"));
43 ARMBaseInstrInfo::ARMBaseInstrInfo(const ARMSubtarget& STI)
44 : TargetInstrInfoImpl(ARMInsts, array_lengthof(ARMInsts)),
49 ARMBaseInstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
50 MachineBasicBlock::iterator &MBBI,
51 LiveVariables *LV) const {
52 // FIXME: Thumb2 support.
57 MachineInstr *MI = MBBI;
58 MachineFunction &MF = *MI->getParent()->getParent();
59 unsigned TSFlags = MI->getDesc().TSFlags;
61 switch ((TSFlags & ARMII::IndexModeMask) >> ARMII::IndexModeShift) {
63 case ARMII::IndexModePre:
66 case ARMII::IndexModePost:
70 // Try splitting an indexed load/store to an un-indexed one plus an add/sub
72 unsigned MemOpc = getUnindexedOpcode(MI->getOpcode());
76 MachineInstr *UpdateMI = NULL;
77 MachineInstr *MemMI = NULL;
78 unsigned AddrMode = (TSFlags & ARMII::AddrModeMask);
79 const TargetInstrDesc &TID = MI->getDesc();
80 unsigned NumOps = TID.getNumOperands();
81 bool isLoad = !TID.mayStore();
82 const MachineOperand &WB = isLoad ? MI->getOperand(1) : MI->getOperand(0);
83 const MachineOperand &Base = MI->getOperand(2);
84 const MachineOperand &Offset = MI->getOperand(NumOps-3);
85 unsigned WBReg = WB.getReg();
86 unsigned BaseReg = Base.getReg();
87 unsigned OffReg = Offset.getReg();
88 unsigned OffImm = MI->getOperand(NumOps-2).getImm();
89 ARMCC::CondCodes Pred = (ARMCC::CondCodes)MI->getOperand(NumOps-1).getImm();
92 assert(false && "Unknown indexed op!");
94 case ARMII::AddrMode2: {
95 bool isSub = ARM_AM::getAM2Op(OffImm) == ARM_AM::sub;
96 unsigned Amt = ARM_AM::getAM2Offset(OffImm);
98 if (ARM_AM::getSOImmVal(Amt) == -1)
99 // Can't encode it in a so_imm operand. This transformation will
100 // add more than 1 instruction. Abandon!
102 UpdateMI = BuildMI(MF, MI->getDebugLoc(),
103 get(isSub ? ARM::SUBri : ARM::ADDri), WBReg)
104 .addReg(BaseReg).addImm(Amt)
105 .addImm(Pred).addReg(0).addReg(0);
106 } else if (Amt != 0) {
107 ARM_AM::ShiftOpc ShOpc = ARM_AM::getAM2ShiftOpc(OffImm);
108 unsigned SOOpc = ARM_AM::getSORegOpc(ShOpc, Amt);
109 UpdateMI = BuildMI(MF, MI->getDebugLoc(),
110 get(isSub ? ARM::SUBrs : ARM::ADDrs), WBReg)
111 .addReg(BaseReg).addReg(OffReg).addReg(0).addImm(SOOpc)
112 .addImm(Pred).addReg(0).addReg(0);
114 UpdateMI = BuildMI(MF, MI->getDebugLoc(),
115 get(isSub ? ARM::SUBrr : ARM::ADDrr), WBReg)
116 .addReg(BaseReg).addReg(OffReg)
117 .addImm(Pred).addReg(0).addReg(0);
120 case ARMII::AddrMode3 : {
121 bool isSub = ARM_AM::getAM3Op(OffImm) == ARM_AM::sub;
122 unsigned Amt = ARM_AM::getAM3Offset(OffImm);
124 // Immediate is 8-bits. It's guaranteed to fit in a so_imm operand.
125 UpdateMI = BuildMI(MF, MI->getDebugLoc(),
126 get(isSub ? ARM::SUBri : ARM::ADDri), WBReg)
127 .addReg(BaseReg).addImm(Amt)
128 .addImm(Pred).addReg(0).addReg(0);
130 UpdateMI = BuildMI(MF, MI->getDebugLoc(),
131 get(isSub ? ARM::SUBrr : ARM::ADDrr), WBReg)
132 .addReg(BaseReg).addReg(OffReg)
133 .addImm(Pred).addReg(0).addReg(0);
138 std::vector<MachineInstr*> NewMIs;
141 MemMI = BuildMI(MF, MI->getDebugLoc(),
142 get(MemOpc), MI->getOperand(0).getReg())
143 .addReg(WBReg).addReg(0).addImm(0).addImm(Pred);
145 MemMI = BuildMI(MF, MI->getDebugLoc(),
146 get(MemOpc)).addReg(MI->getOperand(1).getReg())
147 .addReg(WBReg).addReg(0).addImm(0).addImm(Pred);
148 NewMIs.push_back(MemMI);
149 NewMIs.push_back(UpdateMI);
152 MemMI = BuildMI(MF, MI->getDebugLoc(),
153 get(MemOpc), MI->getOperand(0).getReg())
154 .addReg(BaseReg).addReg(0).addImm(0).addImm(Pred);
156 MemMI = BuildMI(MF, MI->getDebugLoc(),
157 get(MemOpc)).addReg(MI->getOperand(1).getReg())
158 .addReg(BaseReg).addReg(0).addImm(0).addImm(Pred);
160 UpdateMI->getOperand(0).setIsDead();
161 NewMIs.push_back(UpdateMI);
162 NewMIs.push_back(MemMI);
165 // Transfer LiveVariables states, kill / dead info.
167 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
168 MachineOperand &MO = MI->getOperand(i);
169 if (MO.isReg() && MO.getReg() &&
170 TargetRegisterInfo::isVirtualRegister(MO.getReg())) {
171 unsigned Reg = MO.getReg();
173 LiveVariables::VarInfo &VI = LV->getVarInfo(Reg);
175 MachineInstr *NewMI = (Reg == WBReg) ? UpdateMI : MemMI;
177 LV->addVirtualRegisterDead(Reg, NewMI);
179 if (MO.isUse() && MO.isKill()) {
180 for (unsigned j = 0; j < 2; ++j) {
181 // Look at the two new MI's in reverse order.
182 MachineInstr *NewMI = NewMIs[j];
183 if (!NewMI->readsRegister(Reg))
185 LV->addVirtualRegisterKilled(Reg, NewMI);
186 if (VI.removeKill(MI))
187 VI.Kills.push_back(NewMI);
195 MFI->insert(MBBI, NewMIs[1]);
196 MFI->insert(MBBI, NewMIs[0]);
201 ARMBaseInstrInfo::spillCalleeSavedRegisters(MachineBasicBlock &MBB,
202 MachineBasicBlock::iterator MI,
203 const std::vector<CalleeSavedInfo> &CSI,
204 const TargetRegisterInfo *TRI) const {
209 if (MI != MBB.end()) DL = MI->getDebugLoc();
211 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
212 unsigned Reg = CSI[i].getReg();
215 // Add the callee-saved register as live-in unless it's LR and
216 // @llvm.returnaddress is called. If LR is returned for @llvm.returnaddress
217 // then it's already added to the function and entry block live-in sets.
218 if (Reg == ARM::LR) {
219 MachineFunction &MF = *MBB.getParent();
220 if (MF.getFrameInfo()->isReturnAddressTaken() &&
221 MF.getRegInfo().isLiveIn(Reg))
228 // Insert the spill to the stack frame. The register is killed at the spill
230 storeRegToStackSlot(MBB, MI, Reg, isKill,
231 CSI[i].getFrameIdx(), CSI[i].getRegClass(), TRI);
238 ARMBaseInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB,
239 MachineBasicBlock *&FBB,
240 SmallVectorImpl<MachineOperand> &Cond,
241 bool AllowModify) const {
242 // If the block has no terminators, it just falls into the block after it.
243 MachineBasicBlock::iterator I = MBB.end();
244 if (I == MBB.begin())
247 while (I->isDebugValue()) {
248 if (I == MBB.begin())
252 if (!isUnpredicatedTerminator(I))
255 // Get the last instruction in the block.
256 MachineInstr *LastInst = I;
258 // If there is only one terminator instruction, process it.
259 unsigned LastOpc = LastInst->getOpcode();
260 if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) {
261 if (isUncondBranchOpcode(LastOpc)) {
262 TBB = LastInst->getOperand(0).getMBB();
265 if (isCondBranchOpcode(LastOpc)) {
266 // Block ends with fall-through condbranch.
267 TBB = LastInst->getOperand(0).getMBB();
268 Cond.push_back(LastInst->getOperand(1));
269 Cond.push_back(LastInst->getOperand(2));
272 return true; // Can't handle indirect branch.
275 // Get the instruction before it if it is a terminator.
276 MachineInstr *SecondLastInst = I;
278 // If there are three terminators, we don't know what sort of block this is.
279 if (SecondLastInst && I != MBB.begin() && isUnpredicatedTerminator(--I))
282 // If the block ends with a B and a Bcc, handle it.
283 unsigned SecondLastOpc = SecondLastInst->getOpcode();
284 if (isCondBranchOpcode(SecondLastOpc) && isUncondBranchOpcode(LastOpc)) {
285 TBB = SecondLastInst->getOperand(0).getMBB();
286 Cond.push_back(SecondLastInst->getOperand(1));
287 Cond.push_back(SecondLastInst->getOperand(2));
288 FBB = LastInst->getOperand(0).getMBB();
292 // If the block ends with two unconditional branches, handle it. The second
293 // one is not executed, so remove it.
294 if (isUncondBranchOpcode(SecondLastOpc) && isUncondBranchOpcode(LastOpc)) {
295 TBB = SecondLastInst->getOperand(0).getMBB();
298 I->eraseFromParent();
302 // ...likewise if it ends with a branch table followed by an unconditional
303 // branch. The branch folder can create these, and we must get rid of them for
304 // correctness of Thumb constant islands.
305 if ((isJumpTableBranchOpcode(SecondLastOpc) ||
306 isIndirectBranchOpcode(SecondLastOpc)) &&
307 isUncondBranchOpcode(LastOpc)) {
310 I->eraseFromParent();
314 // Otherwise, can't handle this.
319 unsigned ARMBaseInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
320 MachineBasicBlock::iterator I = MBB.end();
321 if (I == MBB.begin()) return 0;
323 while (I->isDebugValue()) {
324 if (I == MBB.begin())
328 if (!isUncondBranchOpcode(I->getOpcode()) &&
329 !isCondBranchOpcode(I->getOpcode()))
332 // Remove the branch.
333 I->eraseFromParent();
337 if (I == MBB.begin()) return 1;
339 if (!isCondBranchOpcode(I->getOpcode()))
342 // Remove the branch.
343 I->eraseFromParent();
348 ARMBaseInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
349 MachineBasicBlock *FBB,
350 const SmallVectorImpl<MachineOperand> &Cond) const {
351 // FIXME this should probably have a DebugLoc argument
354 ARMFunctionInfo *AFI = MBB.getParent()->getInfo<ARMFunctionInfo>();
355 int BOpc = !AFI->isThumbFunction()
356 ? ARM::B : (AFI->isThumb2Function() ? ARM::t2B : ARM::tB);
357 int BccOpc = !AFI->isThumbFunction()
358 ? ARM::Bcc : (AFI->isThumb2Function() ? ARM::t2Bcc : ARM::tBcc);
360 // Shouldn't be a fall through.
361 assert(TBB && "InsertBranch must not be told to insert a fallthrough");
362 assert((Cond.size() == 2 || Cond.size() == 0) &&
363 "ARM branch conditions have two components!");
366 if (Cond.empty()) // Unconditional branch?
367 BuildMI(&MBB, dl, get(BOpc)).addMBB(TBB);
369 BuildMI(&MBB, dl, get(BccOpc)).addMBB(TBB)
370 .addImm(Cond[0].getImm()).addReg(Cond[1].getReg());
374 // Two-way conditional branch.
375 BuildMI(&MBB, dl, get(BccOpc)).addMBB(TBB)
376 .addImm(Cond[0].getImm()).addReg(Cond[1].getReg());
377 BuildMI(&MBB, dl, get(BOpc)).addMBB(FBB);
381 bool ARMBaseInstrInfo::
382 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
383 ARMCC::CondCodes CC = (ARMCC::CondCodes)(int)Cond[0].getImm();
384 Cond[0].setImm(ARMCC::getOppositeCondition(CC));
388 bool ARMBaseInstrInfo::
389 PredicateInstruction(MachineInstr *MI,
390 const SmallVectorImpl<MachineOperand> &Pred) const {
391 unsigned Opc = MI->getOpcode();
392 if (isUncondBranchOpcode(Opc)) {
393 MI->setDesc(get(getMatchingCondBranchOpcode(Opc)));
394 MI->addOperand(MachineOperand::CreateImm(Pred[0].getImm()));
395 MI->addOperand(MachineOperand::CreateReg(Pred[1].getReg(), false));
399 int PIdx = MI->findFirstPredOperandIdx();
401 MachineOperand &PMO = MI->getOperand(PIdx);
402 PMO.setImm(Pred[0].getImm());
403 MI->getOperand(PIdx+1).setReg(Pred[1].getReg());
409 bool ARMBaseInstrInfo::
410 SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1,
411 const SmallVectorImpl<MachineOperand> &Pred2) const {
412 if (Pred1.size() > 2 || Pred2.size() > 2)
415 ARMCC::CondCodes CC1 = (ARMCC::CondCodes)Pred1[0].getImm();
416 ARMCC::CondCodes CC2 = (ARMCC::CondCodes)Pred2[0].getImm();
426 return CC2 == ARMCC::HI;
428 return CC2 == ARMCC::LO || CC2 == ARMCC::EQ;
430 return CC2 == ARMCC::GT;
432 return CC2 == ARMCC::LT;
436 bool ARMBaseInstrInfo::DefinesPredicate(MachineInstr *MI,
437 std::vector<MachineOperand> &Pred) const {
438 // FIXME: This confuses implicit_def with optional CPSR def.
439 const TargetInstrDesc &TID = MI->getDesc();
440 if (!TID.getImplicitDefs() && !TID.hasOptionalDef())
444 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
445 const MachineOperand &MO = MI->getOperand(i);
446 if (MO.isReg() && MO.getReg() == ARM::CPSR) {
455 /// isPredicable - Return true if the specified instruction can be predicated.
456 /// By default, this returns true for every instruction with a
457 /// PredicateOperand.
458 bool ARMBaseInstrInfo::isPredicable(MachineInstr *MI) const {
459 const TargetInstrDesc &TID = MI->getDesc();
460 if (!TID.isPredicable())
463 if ((TID.TSFlags & ARMII::DomainMask) == ARMII::DomainNEON) {
464 ARMFunctionInfo *AFI =
465 MI->getParent()->getParent()->getInfo<ARMFunctionInfo>();
466 return AFI->isThumb2Function();
471 /// FIXME: Works around a gcc miscompilation with -fstrict-aliasing.
473 static unsigned getNumJTEntries(const std::vector<MachineJumpTableEntry> &JT,
475 static unsigned getNumJTEntries(const std::vector<MachineJumpTableEntry> &JT,
477 assert(JTI < JT.size());
478 return JT[JTI].MBBs.size();
481 /// GetInstSize - Return the size of the specified MachineInstr.
483 unsigned ARMBaseInstrInfo::GetInstSizeInBytes(const MachineInstr *MI) const {
484 const MachineBasicBlock &MBB = *MI->getParent();
485 const MachineFunction *MF = MBB.getParent();
486 const MCAsmInfo *MAI = MF->getTarget().getMCAsmInfo();
488 // Basic size info comes from the TSFlags field.
489 const TargetInstrDesc &TID = MI->getDesc();
490 unsigned TSFlags = TID.TSFlags;
492 unsigned Opc = MI->getOpcode();
493 switch ((TSFlags & ARMII::SizeMask) >> ARMII::SizeShift) {
495 // If this machine instr is an inline asm, measure it.
496 if (MI->getOpcode() == ARM::INLINEASM)
497 return getInlineAsmLength(MI->getOperand(0).getSymbolName(), *MAI);
502 llvm_unreachable("Unknown or unset size field for instr!");
503 case TargetOpcode::IMPLICIT_DEF:
504 case TargetOpcode::KILL:
505 case TargetOpcode::DBG_LABEL:
506 case TargetOpcode::EH_LABEL:
507 case TargetOpcode::DBG_VALUE:
512 case ARMII::Size8Bytes: return 8; // ARM instruction x 2.
513 case ARMII::Size4Bytes: return 4; // ARM / Thumb2 instruction.
514 case ARMII::Size2Bytes: return 2; // Thumb1 instruction.
515 case ARMII::SizeSpecial: {
517 case ARM::CONSTPOOL_ENTRY:
518 // If this machine instr is a constant pool entry, its size is recorded as
520 return MI->getOperand(2).getImm();
521 case ARM::Int_eh_sjlj_longjmp:
523 case ARM::tInt_eh_sjlj_longjmp:
525 case ARM::Int_eh_sjlj_setjmp:
526 case ARM::Int_eh_sjlj_setjmp_nofp:
528 case ARM::tInt_eh_sjlj_setjmp:
529 case ARM::t2Int_eh_sjlj_setjmp:
530 case ARM::t2Int_eh_sjlj_setjmp_nofp:
539 // These are jumptable branches, i.e. a branch followed by an inlined
540 // jumptable. The size is 4 + 4 * number of entries. For TBB, each
541 // entry is one byte; TBH two byte each.
542 unsigned EntrySize = (Opc == ARM::t2TBB)
543 ? 1 : ((Opc == ARM::t2TBH) ? 2 : 4);
544 unsigned NumOps = TID.getNumOperands();
545 MachineOperand JTOP =
546 MI->getOperand(NumOps - (TID.isPredicable() ? 3 : 2));
547 unsigned JTI = JTOP.getIndex();
548 const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
550 const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
551 assert(JTI < JT.size());
552 // Thumb instructions are 2 byte aligned, but JT entries are 4 byte
553 // 4 aligned. The assembler / linker may add 2 byte padding just before
554 // the JT entries. The size does not include this padding; the
555 // constant islands pass does separate bookkeeping for it.
556 // FIXME: If we know the size of the function is less than (1 << 16) *2
557 // bytes, we can use 16-bit entries instead. Then there won't be an
559 unsigned InstSize = (Opc == ARM::tBR_JTr || Opc == ARM::t2BR_JT) ? 2 : 4;
560 unsigned NumEntries = getNumJTEntries(JT, JTI);
561 if (Opc == ARM::t2TBB && (NumEntries & 1))
562 // Make sure the instruction that follows TBB is 2-byte aligned.
563 // FIXME: Constant island pass should insert an "ALIGN" instruction
566 return NumEntries * EntrySize + InstSize;
569 // Otherwise, pseudo-instruction sizes are zero.
574 return 0; // Not reached
577 /// Return true if the instruction is a register to register move and
578 /// leave the source and dest operands in the passed parameters.
581 ARMBaseInstrInfo::isMoveInstr(const MachineInstr &MI,
582 unsigned &SrcReg, unsigned &DstReg,
583 unsigned& SrcSubIdx, unsigned& DstSubIdx) const {
584 switch (MI.getOpcode()) {
591 SrcReg = MI.getOperand(1).getReg();
592 DstReg = MI.getOperand(0).getReg();
593 SrcSubIdx = MI.getOperand(1).getSubReg();
594 DstSubIdx = MI.getOperand(0).getSubReg();
599 case ARM::tMOVgpr2tgpr:
600 case ARM::tMOVtgpr2gpr:
601 case ARM::tMOVgpr2gpr:
603 assert(MI.getDesc().getNumOperands() >= 2 &&
604 MI.getOperand(0).isReg() &&
605 MI.getOperand(1).isReg() &&
606 "Invalid ARM MOV instruction");
607 SrcReg = MI.getOperand(1).getReg();
608 DstReg = MI.getOperand(0).getReg();
609 SrcSubIdx = MI.getOperand(1).getSubReg();
610 DstSubIdx = MI.getOperand(0).getSubReg();
619 ARMBaseInstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
620 int &FrameIndex) const {
621 switch (MI->getOpcode()) {
624 case ARM::t2LDRs: // FIXME: don't use t2LDRs to access frame.
625 if (MI->getOperand(1).isFI() &&
626 MI->getOperand(2).isReg() &&
627 MI->getOperand(3).isImm() &&
628 MI->getOperand(2).getReg() == 0 &&
629 MI->getOperand(3).getImm() == 0) {
630 FrameIndex = MI->getOperand(1).getIndex();
631 return MI->getOperand(0).getReg();
636 if (MI->getOperand(1).isFI() &&
637 MI->getOperand(2).isImm() &&
638 MI->getOperand(2).getImm() == 0) {
639 FrameIndex = MI->getOperand(1).getIndex();
640 return MI->getOperand(0).getReg();
645 if (MI->getOperand(1).isFI() &&
646 MI->getOperand(2).isImm() &&
647 MI->getOperand(2).getImm() == 0) {
648 FrameIndex = MI->getOperand(1).getIndex();
649 return MI->getOperand(0).getReg();
658 ARMBaseInstrInfo::isStoreToStackSlot(const MachineInstr *MI,
659 int &FrameIndex) const {
660 switch (MI->getOpcode()) {
663 case ARM::t2STRs: // FIXME: don't use t2STRs to access frame.
664 if (MI->getOperand(1).isFI() &&
665 MI->getOperand(2).isReg() &&
666 MI->getOperand(3).isImm() &&
667 MI->getOperand(2).getReg() == 0 &&
668 MI->getOperand(3).getImm() == 0) {
669 FrameIndex = MI->getOperand(1).getIndex();
670 return MI->getOperand(0).getReg();
675 if (MI->getOperand(1).isFI() &&
676 MI->getOperand(2).isImm() &&
677 MI->getOperand(2).getImm() == 0) {
678 FrameIndex = MI->getOperand(1).getIndex();
679 return MI->getOperand(0).getReg();
684 if (MI->getOperand(1).isFI() &&
685 MI->getOperand(2).isImm() &&
686 MI->getOperand(2).getImm() == 0) {
687 FrameIndex = MI->getOperand(1).getIndex();
688 return MI->getOperand(0).getReg();
697 ARMBaseInstrInfo::copyRegToReg(MachineBasicBlock &MBB,
698 MachineBasicBlock::iterator I,
699 unsigned DestReg, unsigned SrcReg,
700 const TargetRegisterClass *DestRC,
701 const TargetRegisterClass *SrcRC,
703 // tGPR is used sometimes in ARM instructions that need to avoid using
704 // certain registers. Just treat it as GPR here.
705 if (DestRC == ARM::tGPRRegisterClass)
706 DestRC = ARM::GPRRegisterClass;
707 if (SrcRC == ARM::tGPRRegisterClass)
708 SrcRC = ARM::GPRRegisterClass;
710 // Allow DPR / DPR_VFP2 / DPR_8 cross-class copies.
711 if (DestRC == ARM::DPR_8RegisterClass)
712 DestRC = ARM::DPR_VFP2RegisterClass;
713 if (SrcRC == ARM::DPR_8RegisterClass)
714 SrcRC = ARM::DPR_VFP2RegisterClass;
716 // Allow QPR / QPR_VFP2 / QPR_8 cross-class copies.
717 if (DestRC == ARM::QPR_VFP2RegisterClass ||
718 DestRC == ARM::QPR_8RegisterClass)
719 DestRC = ARM::QPRRegisterClass;
720 if (SrcRC == ARM::QPR_VFP2RegisterClass ||
721 SrcRC == ARM::QPR_8RegisterClass)
722 SrcRC = ARM::QPRRegisterClass;
724 // Allow QQPR / QQPR_VFP2 cross-class copies.
725 if (DestRC == ARM::QQPR_VFP2RegisterClass)
726 DestRC = ARM::QQPRRegisterClass;
727 if (SrcRC == ARM::QQPR_VFP2RegisterClass)
728 SrcRC = ARM::QQPRRegisterClass;
730 // Disallow copies of unequal sizes.
731 if (DestRC != SrcRC && DestRC->getSize() != SrcRC->getSize())
734 if (DestRC == ARM::GPRRegisterClass) {
735 if (SrcRC == ARM::SPRRegisterClass)
736 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VMOVRS), DestReg)
739 AddDefaultCC(AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::MOVr),
740 DestReg).addReg(SrcReg)));
744 if (DestRC == ARM::SPRRegisterClass)
745 Opc = (SrcRC == ARM::GPRRegisterClass ? ARM::VMOVSR : ARM::VMOVS);
746 else if (DestRC == ARM::DPRRegisterClass)
748 else if (DestRC == ARM::DPR_VFP2RegisterClass ||
749 SrcRC == ARM::DPR_VFP2RegisterClass)
750 // Always use neon reg-reg move if source or dest is NEON-only regclass.
751 Opc = ARM::VMOVDneon;
752 else if (DestRC == ARM::QPRRegisterClass)
754 else if (DestRC == ARM::QQPRRegisterClass)
756 else if (DestRC == ARM::QQQQPRRegisterClass)
761 AddDefaultPred(BuildMI(MBB, I, DL, get(Opc), DestReg).addReg(SrcReg));
768 MachineInstrBuilder &AddDReg(MachineInstrBuilder &MIB,
769 unsigned Reg, unsigned SubIdx, unsigned State,
770 const TargetRegisterInfo *TRI) {
772 return MIB.addReg(Reg, State);
774 if (TargetRegisterInfo::isPhysicalRegister(Reg))
775 return MIB.addReg(TRI->getSubReg(Reg, SubIdx), State);
776 return MIB.addReg(Reg, State, SubIdx);
779 void ARMBaseInstrInfo::
780 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
781 unsigned SrcReg, bool isKill, int FI,
782 const TargetRegisterClass *RC,
783 const TargetRegisterInfo *TRI) const {
785 if (I != MBB.end()) DL = I->getDebugLoc();
786 MachineFunction &MF = *MBB.getParent();
787 MachineFrameInfo &MFI = *MF.getFrameInfo();
788 unsigned Align = MFI.getObjectAlignment(FI);
790 MachineMemOperand *MMO =
791 MF.getMachineMemOperand(PseudoSourceValue::getFixedStack(FI),
792 MachineMemOperand::MOStore, 0,
793 MFI.getObjectSize(FI),
796 // tGPR is used sometimes in ARM instructions that need to avoid using
797 // certain registers. Just treat it as GPR here.
798 if (RC == ARM::tGPRRegisterClass)
799 RC = ARM::GPRRegisterClass;
801 if (RC == ARM::GPRRegisterClass) {
802 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::STR))
803 .addReg(SrcReg, getKillRegState(isKill))
804 .addFrameIndex(FI).addReg(0).addImm(0).addMemOperand(MMO));
805 } else if (RC == ARM::SPRRegisterClass) {
806 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTRS))
807 .addReg(SrcReg, getKillRegState(isKill))
808 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
809 } else if (RC == ARM::DPRRegisterClass ||
810 RC == ARM::DPR_VFP2RegisterClass ||
811 RC == ARM::DPR_8RegisterClass) {
812 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTRD))
813 .addReg(SrcReg, getKillRegState(isKill))
814 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
815 } else if (RC == ARM::QPRRegisterClass ||
816 RC == ARM::QPR_VFP2RegisterClass ||
817 RC == ARM::QPR_8RegisterClass) {
818 // FIXME: Neon instructions should support predicates
819 if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) {
820 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VST1q))
821 .addFrameIndex(FI).addImm(128)
822 .addReg(SrcReg, getKillRegState(isKill))
823 .addMemOperand(MMO));
825 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTMQ))
826 .addReg(SrcReg, getKillRegState(isKill))
828 .addImm(ARM_AM::getAM5Opc(ARM_AM::ia, 4))
829 .addMemOperand(MMO));
831 } else if (RC == ARM::QQPRRegisterClass || RC == ARM::QQPR_VFP2RegisterClass){
832 if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) {
833 // FIXME: It's possible to only store part of the QQ register if the
834 // spilled def has a sub-register index.
835 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(ARM::VST2q32))
836 .addFrameIndex(FI).addImm(128);
837 MIB = AddDReg(MIB, SrcReg, ARM::DSUBREG_0, getKillRegState(isKill), TRI);
838 MIB = AddDReg(MIB, SrcReg, ARM::DSUBREG_1, 0, TRI);
839 MIB = AddDReg(MIB, SrcReg, ARM::DSUBREG_2, 0, TRI);
840 MIB = AddDReg(MIB, SrcReg, ARM::DSUBREG_3, 0, TRI);
841 AddDefaultPred(MIB.addMemOperand(MMO));
843 MachineInstrBuilder MIB =
844 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTMD))
846 .addImm(ARM_AM::getAM5Opc(ARM_AM::ia, 4)))
848 MIB = AddDReg(MIB, SrcReg, ARM::DSUBREG_0, getKillRegState(isKill), TRI);
849 MIB = AddDReg(MIB, SrcReg, ARM::DSUBREG_1, 0, TRI);
850 MIB = AddDReg(MIB, SrcReg, ARM::DSUBREG_2, 0, TRI);
851 AddDReg(MIB, SrcReg, ARM::DSUBREG_3, 0, TRI);
854 assert(RC == ARM::QQQQPRRegisterClass && "Unknown regclass!");
855 MachineInstrBuilder MIB =
856 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTMD))
858 .addImm(ARM_AM::getAM5Opc(ARM_AM::ia, 4)))
860 MIB = AddDReg(MIB, SrcReg, ARM::DSUBREG_0, getKillRegState(isKill), TRI);
861 MIB = AddDReg(MIB, SrcReg, ARM::DSUBREG_1, 0, TRI);
862 MIB = AddDReg(MIB, SrcReg, ARM::DSUBREG_2, 0, TRI);
863 MIB = AddDReg(MIB, SrcReg, ARM::DSUBREG_3, 0, TRI);
864 MIB = AddDReg(MIB, SrcReg, ARM::DSUBREG_4, 0, TRI);
865 MIB = AddDReg(MIB, SrcReg, ARM::DSUBREG_5, 0, TRI);
866 MIB = AddDReg(MIB, SrcReg, ARM::DSUBREG_6, 0, TRI);
867 AddDReg(MIB, SrcReg, ARM::DSUBREG_7, 0, TRI);
871 void ARMBaseInstrInfo::
872 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
873 unsigned DestReg, int FI,
874 const TargetRegisterClass *RC,
875 const TargetRegisterInfo *TRI) const {
877 if (I != MBB.end()) DL = I->getDebugLoc();
878 MachineFunction &MF = *MBB.getParent();
879 MachineFrameInfo &MFI = *MF.getFrameInfo();
880 unsigned Align = MFI.getObjectAlignment(FI);
881 MachineMemOperand *MMO =
882 MF.getMachineMemOperand(PseudoSourceValue::getFixedStack(FI),
883 MachineMemOperand::MOLoad, 0,
884 MFI.getObjectSize(FI),
887 // tGPR is used sometimes in ARM instructions that need to avoid using
888 // certain registers. Just treat it as GPR here.
889 if (RC == ARM::tGPRRegisterClass)
890 RC = ARM::GPRRegisterClass;
892 if (RC == ARM::GPRRegisterClass) {
893 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::LDR), DestReg)
894 .addFrameIndex(FI).addReg(0).addImm(0).addMemOperand(MMO));
895 } else if (RC == ARM::SPRRegisterClass) {
896 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDRS), DestReg)
897 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
898 } else if (RC == ARM::DPRRegisterClass ||
899 RC == ARM::DPR_VFP2RegisterClass ||
900 RC == ARM::DPR_8RegisterClass) {
901 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDRD), DestReg)
902 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
903 } else if (RC == ARM::QPRRegisterClass ||
904 RC == ARM::QPR_VFP2RegisterClass ||
905 RC == ARM::QPR_8RegisterClass) {
906 if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) {
907 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLD1q), DestReg)
908 .addFrameIndex(FI).addImm(128)
909 .addMemOperand(MMO));
911 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDMQ), DestReg)
913 .addImm(ARM_AM::getAM5Opc(ARM_AM::ia, 4))
914 .addMemOperand(MMO));
916 } else if (RC == ARM::QQPRRegisterClass || RC == ARM::QQPR_VFP2RegisterClass){
917 if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) {
918 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(ARM::VLD2q32));
919 MIB = AddDReg(MIB, DestReg, ARM::DSUBREG_0, RegState::Define, TRI);
920 MIB = AddDReg(MIB, DestReg, ARM::DSUBREG_1, RegState::Define, TRI);
921 MIB = AddDReg(MIB, DestReg, ARM::DSUBREG_2, RegState::Define, TRI);
922 MIB = AddDReg(MIB, DestReg, ARM::DSUBREG_3, RegState::Define, TRI);
923 AddDefaultPred(MIB.addFrameIndex(FI).addImm(128).addMemOperand(MMO));
925 MachineInstrBuilder MIB =
926 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDMD))
928 .addImm(ARM_AM::getAM5Opc(ARM_AM::ia, 4)))
930 MIB = AddDReg(MIB, DestReg, ARM::DSUBREG_0, RegState::Define, TRI);
931 MIB = AddDReg(MIB, DestReg, ARM::DSUBREG_1, RegState::Define, TRI);
932 MIB = AddDReg(MIB, DestReg, ARM::DSUBREG_2, RegState::Define, TRI);
933 AddDReg(MIB, DestReg, ARM::DSUBREG_3, RegState::Define, TRI);
936 assert(RC == ARM::QQQQPRRegisterClass && "Unknown regclass!");
937 MachineInstrBuilder MIB =
938 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDMD))
940 .addImm(ARM_AM::getAM5Opc(ARM_AM::ia, 4)))
942 MIB = AddDReg(MIB, DestReg, ARM::DSUBREG_0, RegState::Define, TRI);
943 MIB = AddDReg(MIB, DestReg, ARM::DSUBREG_1, RegState::Define, TRI);
944 MIB = AddDReg(MIB, DestReg, ARM::DSUBREG_2, RegState::Define, TRI);
945 MIB = AddDReg(MIB, DestReg, ARM::DSUBREG_3, RegState::Define, TRI);
946 MIB = AddDReg(MIB, DestReg, ARM::DSUBREG_4, RegState::Define, TRI);
947 MIB = AddDReg(MIB, DestReg, ARM::DSUBREG_5, RegState::Define, TRI);
948 MIB = AddDReg(MIB, DestReg, ARM::DSUBREG_6, RegState::Define, TRI);
949 AddDReg(MIB, DestReg, ARM::DSUBREG_7, RegState::Define, TRI);
954 ARMBaseInstrInfo::emitFrameIndexDebugValue(MachineFunction &MF,
955 int FrameIx, uint64_t Offset,
958 MachineInstrBuilder MIB = BuildMI(MF, DL, get(ARM::DBG_VALUE))
959 .addFrameIndex(FrameIx).addImm(0).addImm(Offset).addMetadata(MDPtr);
963 MachineInstr *ARMBaseInstrInfo::
964 foldMemoryOperandImpl(MachineFunction &MF, MachineInstr *MI,
965 const SmallVectorImpl<unsigned> &Ops, int FI) const {
966 if (Ops.size() != 1) return NULL;
968 unsigned OpNum = Ops[0];
969 unsigned Opc = MI->getOpcode();
970 MachineInstr *NewMI = NULL;
971 if (Opc == ARM::MOVr || Opc == ARM::t2MOVr) {
972 // If it is updating CPSR, then it cannot be folded.
973 if (MI->getOperand(4).getReg() == ARM::CPSR && !MI->getOperand(4).isDead())
975 unsigned Pred = MI->getOperand(2).getImm();
976 unsigned PredReg = MI->getOperand(3).getReg();
977 if (OpNum == 0) { // move -> store
978 unsigned SrcReg = MI->getOperand(1).getReg();
979 unsigned SrcSubReg = MI->getOperand(1).getSubReg();
980 bool isKill = MI->getOperand(1).isKill();
981 bool isUndef = MI->getOperand(1).isUndef();
982 if (Opc == ARM::MOVr)
983 NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::STR))
985 getKillRegState(isKill) | getUndefRegState(isUndef),
987 .addFrameIndex(FI).addReg(0).addImm(0).addImm(Pred).addReg(PredReg);
989 NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::t2STRi12))
991 getKillRegState(isKill) | getUndefRegState(isUndef),
993 .addFrameIndex(FI).addImm(0).addImm(Pred).addReg(PredReg);
994 } else { // move -> load
995 unsigned DstReg = MI->getOperand(0).getReg();
996 unsigned DstSubReg = MI->getOperand(0).getSubReg();
997 bool isDead = MI->getOperand(0).isDead();
998 bool isUndef = MI->getOperand(0).isUndef();
999 if (Opc == ARM::MOVr)
1000 NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::LDR))
1003 getDeadRegState(isDead) |
1004 getUndefRegState(isUndef), DstSubReg)
1005 .addFrameIndex(FI).addReg(0).addImm(0).addImm(Pred).addReg(PredReg);
1007 NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::t2LDRi12))
1010 getDeadRegState(isDead) |
1011 getUndefRegState(isUndef), DstSubReg)
1012 .addFrameIndex(FI).addImm(0).addImm(Pred).addReg(PredReg);
1014 } else if (Opc == ARM::tMOVgpr2gpr ||
1015 Opc == ARM::tMOVtgpr2gpr ||
1016 Opc == ARM::tMOVgpr2tgpr) {
1017 if (OpNum == 0) { // move -> store
1018 unsigned SrcReg = MI->getOperand(1).getReg();
1019 unsigned SrcSubReg = MI->getOperand(1).getSubReg();
1020 bool isKill = MI->getOperand(1).isKill();
1021 bool isUndef = MI->getOperand(1).isUndef();
1022 NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::t2STRi12))
1024 getKillRegState(isKill) | getUndefRegState(isUndef),
1026 .addFrameIndex(FI).addImm(0).addImm(ARMCC::AL).addReg(0);
1027 } else { // move -> load
1028 unsigned DstReg = MI->getOperand(0).getReg();
1029 unsigned DstSubReg = MI->getOperand(0).getSubReg();
1030 bool isDead = MI->getOperand(0).isDead();
1031 bool isUndef = MI->getOperand(0).isUndef();
1032 NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::t2LDRi12))
1035 getDeadRegState(isDead) |
1036 getUndefRegState(isUndef),
1038 .addFrameIndex(FI).addImm(0).addImm(ARMCC::AL).addReg(0);
1040 } else if (Opc == ARM::VMOVS) {
1041 unsigned Pred = MI->getOperand(2).getImm();
1042 unsigned PredReg = MI->getOperand(3).getReg();
1043 if (OpNum == 0) { // move -> store
1044 unsigned SrcReg = MI->getOperand(1).getReg();
1045 unsigned SrcSubReg = MI->getOperand(1).getSubReg();
1046 bool isKill = MI->getOperand(1).isKill();
1047 bool isUndef = MI->getOperand(1).isUndef();
1048 NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::VSTRS))
1049 .addReg(SrcReg, getKillRegState(isKill) | getUndefRegState(isUndef),
1052 .addImm(0).addImm(Pred).addReg(PredReg);
1053 } else { // move -> load
1054 unsigned DstReg = MI->getOperand(0).getReg();
1055 unsigned DstSubReg = MI->getOperand(0).getSubReg();
1056 bool isDead = MI->getOperand(0).isDead();
1057 bool isUndef = MI->getOperand(0).isUndef();
1058 NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::VLDRS))
1061 getDeadRegState(isDead) |
1062 getUndefRegState(isUndef),
1064 .addFrameIndex(FI).addImm(0).addImm(Pred).addReg(PredReg);
1066 } else if (Opc == ARM::VMOVD || Opc == ARM::VMOVDneon) {
1067 unsigned Pred = MI->getOperand(2).getImm();
1068 unsigned PredReg = MI->getOperand(3).getReg();
1069 if (OpNum == 0) { // move -> store
1070 unsigned SrcReg = MI->getOperand(1).getReg();
1071 unsigned SrcSubReg = MI->getOperand(1).getSubReg();
1072 bool isKill = MI->getOperand(1).isKill();
1073 bool isUndef = MI->getOperand(1).isUndef();
1074 NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::VSTRD))
1076 getKillRegState(isKill) | getUndefRegState(isUndef),
1078 .addFrameIndex(FI).addImm(0).addImm(Pred).addReg(PredReg);
1079 } else { // move -> load
1080 unsigned DstReg = MI->getOperand(0).getReg();
1081 unsigned DstSubReg = MI->getOperand(0).getSubReg();
1082 bool isDead = MI->getOperand(0).isDead();
1083 bool isUndef = MI->getOperand(0).isUndef();
1084 NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::VLDRD))
1087 getDeadRegState(isDead) |
1088 getUndefRegState(isUndef),
1090 .addFrameIndex(FI).addImm(0).addImm(Pred).addReg(PredReg);
1092 } else if (Opc == ARM::VMOVQ) {
1093 MachineFrameInfo &MFI = *MF.getFrameInfo();
1094 unsigned Pred = MI->getOperand(2).getImm();
1095 unsigned PredReg = MI->getOperand(3).getReg();
1096 if (OpNum == 0) { // move -> store
1097 unsigned SrcReg = MI->getOperand(1).getReg();
1098 unsigned SrcSubReg = MI->getOperand(1).getSubReg();
1099 bool isKill = MI->getOperand(1).isKill();
1100 bool isUndef = MI->getOperand(1).isUndef();
1101 if (MFI.getObjectAlignment(FI) >= 16 &&
1102 getRegisterInfo().canRealignStack(MF)) {
1103 NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::VST1q))
1104 .addFrameIndex(FI).addImm(128)
1106 getKillRegState(isKill) | getUndefRegState(isUndef),
1108 .addImm(Pred).addReg(PredReg);
1110 NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::VSTMQ))
1112 getKillRegState(isKill) | getUndefRegState(isUndef),
1114 .addFrameIndex(FI).addImm(ARM_AM::getAM5Opc(ARM_AM::ia, 4))
1115 .addImm(Pred).addReg(PredReg);
1117 } else { // move -> load
1118 unsigned DstReg = MI->getOperand(0).getReg();
1119 unsigned DstSubReg = MI->getOperand(0).getSubReg();
1120 bool isDead = MI->getOperand(0).isDead();
1121 bool isUndef = MI->getOperand(0).isUndef();
1122 if (MFI.getObjectAlignment(FI) >= 16 &&
1123 getRegisterInfo().canRealignStack(MF)) {
1124 NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::VLD1q))
1127 getDeadRegState(isDead) |
1128 getUndefRegState(isUndef),
1130 .addFrameIndex(FI).addImm(128).addImm(Pred).addReg(PredReg);
1132 NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::VLDMQ))
1135 getDeadRegState(isDead) |
1136 getUndefRegState(isUndef),
1138 .addFrameIndex(FI).addImm(ARM_AM::getAM5Opc(ARM_AM::ia, 4))
1139 .addImm(Pred).addReg(PredReg);
1148 ARMBaseInstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
1150 const SmallVectorImpl<unsigned> &Ops,
1151 MachineInstr* LoadMI) const {
1157 ARMBaseInstrInfo::canFoldMemoryOperand(const MachineInstr *MI,
1158 const SmallVectorImpl<unsigned> &Ops) const {
1159 if (Ops.size() != 1) return false;
1161 unsigned Opc = MI->getOpcode();
1162 if (Opc == ARM::MOVr || Opc == ARM::t2MOVr) {
1163 // If it is updating CPSR, then it cannot be folded.
1164 return MI->getOperand(4).getReg() != ARM::CPSR ||
1165 MI->getOperand(4).isDead();
1166 } else if (Opc == ARM::tMOVgpr2gpr ||
1167 Opc == ARM::tMOVtgpr2gpr ||
1168 Opc == ARM::tMOVgpr2tgpr) {
1170 } else if (Opc == ARM::VMOVS || Opc == ARM::VMOVD ||
1171 Opc == ARM::VMOVDneon || Opc == ARM::VMOVQ) {
1175 // FIXME: VMOVQQ and VMOVQQQQ?
1180 /// Create a copy of a const pool value. Update CPI to the new index and return
1182 static unsigned duplicateCPV(MachineFunction &MF, unsigned &CPI) {
1183 MachineConstantPool *MCP = MF.getConstantPool();
1184 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1186 const MachineConstantPoolEntry &MCPE = MCP->getConstants()[CPI];
1187 assert(MCPE.isMachineConstantPoolEntry() &&
1188 "Expecting a machine constantpool entry!");
1189 ARMConstantPoolValue *ACPV =
1190 static_cast<ARMConstantPoolValue*>(MCPE.Val.MachineCPVal);
1192 unsigned PCLabelId = AFI->createConstPoolEntryUId();
1193 ARMConstantPoolValue *NewCPV = 0;
1194 if (ACPV->isGlobalValue())
1195 NewCPV = new ARMConstantPoolValue(ACPV->getGV(), PCLabelId,
1197 else if (ACPV->isExtSymbol())
1198 NewCPV = new ARMConstantPoolValue(MF.getFunction()->getContext(),
1199 ACPV->getSymbol(), PCLabelId, 4);
1200 else if (ACPV->isBlockAddress())
1201 NewCPV = new ARMConstantPoolValue(ACPV->getBlockAddress(), PCLabelId,
1202 ARMCP::CPBlockAddress, 4);
1204 llvm_unreachable("Unexpected ARM constantpool value type!!");
1205 CPI = MCP->getConstantPoolIndex(NewCPV, MCPE.getAlignment());
1209 void ARMBaseInstrInfo::
1210 reMaterialize(MachineBasicBlock &MBB,
1211 MachineBasicBlock::iterator I,
1212 unsigned DestReg, unsigned SubIdx,
1213 const MachineInstr *Orig,
1214 const TargetRegisterInfo *TRI) const {
1215 if (SubIdx && TargetRegisterInfo::isPhysicalRegister(DestReg)) {
1216 DestReg = TRI->getSubReg(DestReg, SubIdx);
1220 unsigned Opcode = Orig->getOpcode();
1223 MachineInstr *MI = MBB.getParent()->CloneMachineInstr(Orig);
1224 MI->getOperand(0).setReg(DestReg);
1228 case ARM::tLDRpci_pic:
1229 case ARM::t2LDRpci_pic: {
1230 MachineFunction &MF = *MBB.getParent();
1231 unsigned CPI = Orig->getOperand(1).getIndex();
1232 unsigned PCLabelId = duplicateCPV(MF, CPI);
1233 MachineInstrBuilder MIB = BuildMI(MBB, I, Orig->getDebugLoc(), get(Opcode),
1235 .addConstantPoolIndex(CPI).addImm(PCLabelId);
1236 (*MIB).setMemRefs(Orig->memoperands_begin(), Orig->memoperands_end());
1241 MachineInstr *NewMI = prior(I);
1242 NewMI->getOperand(0).setSubReg(SubIdx);
1246 ARMBaseInstrInfo::duplicate(MachineInstr *Orig, MachineFunction &MF) const {
1247 MachineInstr *MI = TargetInstrInfoImpl::duplicate(Orig, MF);
1248 switch(Orig->getOpcode()) {
1249 case ARM::tLDRpci_pic:
1250 case ARM::t2LDRpci_pic: {
1251 unsigned CPI = Orig->getOperand(1).getIndex();
1252 unsigned PCLabelId = duplicateCPV(MF, CPI);
1253 Orig->getOperand(1).setIndex(CPI);
1254 Orig->getOperand(2).setImm(PCLabelId);
1261 bool ARMBaseInstrInfo::produceSameValue(const MachineInstr *MI0,
1262 const MachineInstr *MI1) const {
1263 int Opcode = MI0->getOpcode();
1264 if (Opcode == ARM::t2LDRpci ||
1265 Opcode == ARM::t2LDRpci_pic ||
1266 Opcode == ARM::tLDRpci ||
1267 Opcode == ARM::tLDRpci_pic) {
1268 if (MI1->getOpcode() != Opcode)
1270 if (MI0->getNumOperands() != MI1->getNumOperands())
1273 const MachineOperand &MO0 = MI0->getOperand(1);
1274 const MachineOperand &MO1 = MI1->getOperand(1);
1275 if (MO0.getOffset() != MO1.getOffset())
1278 const MachineFunction *MF = MI0->getParent()->getParent();
1279 const MachineConstantPool *MCP = MF->getConstantPool();
1280 int CPI0 = MO0.getIndex();
1281 int CPI1 = MO1.getIndex();
1282 const MachineConstantPoolEntry &MCPE0 = MCP->getConstants()[CPI0];
1283 const MachineConstantPoolEntry &MCPE1 = MCP->getConstants()[CPI1];
1284 ARMConstantPoolValue *ACPV0 =
1285 static_cast<ARMConstantPoolValue*>(MCPE0.Val.MachineCPVal);
1286 ARMConstantPoolValue *ACPV1 =
1287 static_cast<ARMConstantPoolValue*>(MCPE1.Val.MachineCPVal);
1288 return ACPV0->hasSameValue(ACPV1);
1291 return MI0->isIdenticalTo(MI1, MachineInstr::IgnoreVRegDefs);
1294 /// getInstrPredicate - If instruction is predicated, returns its predicate
1295 /// condition, otherwise returns AL. It also returns the condition code
1296 /// register by reference.
1298 llvm::getInstrPredicate(const MachineInstr *MI, unsigned &PredReg) {
1299 int PIdx = MI->findFirstPredOperandIdx();
1305 PredReg = MI->getOperand(PIdx+1).getReg();
1306 return (ARMCC::CondCodes)MI->getOperand(PIdx).getImm();
1310 int llvm::getMatchingCondBranchOpcode(int Opc) {
1313 else if (Opc == ARM::tB)
1315 else if (Opc == ARM::t2B)
1318 llvm_unreachable("Unknown unconditional branch opcode!");
1323 void llvm::emitARMRegPlusImmediate(MachineBasicBlock &MBB,
1324 MachineBasicBlock::iterator &MBBI, DebugLoc dl,
1325 unsigned DestReg, unsigned BaseReg, int NumBytes,
1326 ARMCC::CondCodes Pred, unsigned PredReg,
1327 const ARMBaseInstrInfo &TII) {
1328 bool isSub = NumBytes < 0;
1329 if (isSub) NumBytes = -NumBytes;
1332 unsigned RotAmt = ARM_AM::getSOImmValRotate(NumBytes);
1333 unsigned ThisVal = NumBytes & ARM_AM::rotr32(0xFF, RotAmt);
1334 assert(ThisVal && "Didn't extract field correctly");
1336 // We will handle these bits from offset, clear them.
1337 NumBytes &= ~ThisVal;
1339 assert(ARM_AM::getSOImmVal(ThisVal) != -1 && "Bit extraction didn't work?");
1341 // Build the new ADD / SUB.
1342 unsigned Opc = isSub ? ARM::SUBri : ARM::ADDri;
1343 BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg)
1344 .addReg(BaseReg, RegState::Kill).addImm(ThisVal)
1345 .addImm((unsigned)Pred).addReg(PredReg).addReg(0);
1350 bool llvm::rewriteARMFrameIndex(MachineInstr &MI, unsigned FrameRegIdx,
1351 unsigned FrameReg, int &Offset,
1352 const ARMBaseInstrInfo &TII) {
1353 unsigned Opcode = MI.getOpcode();
1354 const TargetInstrDesc &Desc = MI.getDesc();
1355 unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
1358 // Memory operands in inline assembly always use AddrMode2.
1359 if (Opcode == ARM::INLINEASM)
1360 AddrMode = ARMII::AddrMode2;
1362 if (Opcode == ARM::ADDri) {
1363 Offset += MI.getOperand(FrameRegIdx+1).getImm();
1365 // Turn it into a move.
1366 MI.setDesc(TII.get(ARM::MOVr));
1367 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
1368 MI.RemoveOperand(FrameRegIdx+1);
1371 } else if (Offset < 0) {
1374 MI.setDesc(TII.get(ARM::SUBri));
1377 // Common case: small offset, fits into instruction.
1378 if (ARM_AM::getSOImmVal(Offset) != -1) {
1379 // Replace the FrameIndex with sp / fp
1380 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
1381 MI.getOperand(FrameRegIdx+1).ChangeToImmediate(Offset);
1386 // Otherwise, pull as much of the immedidate into this ADDri/SUBri
1388 unsigned RotAmt = ARM_AM::getSOImmValRotate(Offset);
1389 unsigned ThisImmVal = Offset & ARM_AM::rotr32(0xFF, RotAmt);
1391 // We will handle these bits from offset, clear them.
1392 Offset &= ~ThisImmVal;
1394 // Get the properly encoded SOImmVal field.
1395 assert(ARM_AM::getSOImmVal(ThisImmVal) != -1 &&
1396 "Bit extraction didn't work?");
1397 MI.getOperand(FrameRegIdx+1).ChangeToImmediate(ThisImmVal);
1399 unsigned ImmIdx = 0;
1401 unsigned NumBits = 0;
1404 case ARMII::AddrMode2: {
1405 ImmIdx = FrameRegIdx+2;
1406 InstrOffs = ARM_AM::getAM2Offset(MI.getOperand(ImmIdx).getImm());
1407 if (ARM_AM::getAM2Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub)
1412 case ARMII::AddrMode3: {
1413 ImmIdx = FrameRegIdx+2;
1414 InstrOffs = ARM_AM::getAM3Offset(MI.getOperand(ImmIdx).getImm());
1415 if (ARM_AM::getAM3Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub)
1420 case ARMII::AddrMode4:
1421 case ARMII::AddrMode6:
1422 // Can't fold any offset even if it's zero.
1424 case ARMII::AddrMode5: {
1425 ImmIdx = FrameRegIdx+1;
1426 InstrOffs = ARM_AM::getAM5Offset(MI.getOperand(ImmIdx).getImm());
1427 if (ARM_AM::getAM5Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub)
1434 llvm_unreachable("Unsupported addressing mode!");
1438 Offset += InstrOffs * Scale;
1439 assert((Offset & (Scale-1)) == 0 && "Can't encode this offset!");
1445 // Attempt to fold address comp. if opcode has offset bits
1447 // Common case: small offset, fits into instruction.
1448 MachineOperand &ImmOp = MI.getOperand(ImmIdx);
1449 int ImmedOffset = Offset / Scale;
1450 unsigned Mask = (1 << NumBits) - 1;
1451 if ((unsigned)Offset <= Mask * Scale) {
1452 // Replace the FrameIndex with sp
1453 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
1455 ImmedOffset |= 1 << NumBits;
1456 ImmOp.ChangeToImmediate(ImmedOffset);
1461 // Otherwise, it didn't fit. Pull in what we can to simplify the immed.
1462 ImmedOffset = ImmedOffset & Mask;
1464 ImmedOffset |= 1 << NumBits;
1465 ImmOp.ChangeToImmediate(ImmedOffset);
1466 Offset &= ~(Mask*Scale);
1470 Offset = (isSub) ? -Offset : Offset;