1 //===- ARMBaseInstrInfo.cpp - ARM Instruction Information -------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Base ARM implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "ARMBaseInstrInfo.h"
16 #include "ARMConstantPoolValue.h"
17 #include "ARMHazardRecognizer.h"
18 #include "ARMMachineFunctionInfo.h"
19 #include "ARMRegisterInfo.h"
20 #include "MCTargetDesc/ARMAddressingModes.h"
21 #include "llvm/Constants.h"
22 #include "llvm/Function.h"
23 #include "llvm/GlobalValue.h"
24 #include "llvm/CodeGen/LiveVariables.h"
25 #include "llvm/CodeGen/MachineConstantPool.h"
26 #include "llvm/CodeGen/MachineFrameInfo.h"
27 #include "llvm/CodeGen/MachineInstrBuilder.h"
28 #include "llvm/CodeGen/MachineJumpTableInfo.h"
29 #include "llvm/CodeGen/MachineMemOperand.h"
30 #include "llvm/CodeGen/MachineRegisterInfo.h"
31 #include "llvm/CodeGen/PseudoSourceValue.h"
32 #include "llvm/CodeGen/SelectionDAGNodes.h"
33 #include "llvm/MC/MCAsmInfo.h"
34 #include "llvm/Support/BranchProbability.h"
35 #include "llvm/Support/CommandLine.h"
36 #include "llvm/Support/Debug.h"
37 #include "llvm/Support/ErrorHandling.h"
38 #include "llvm/ADT/STLExtras.h"
40 #define GET_INSTRINFO_CTOR
41 #include "ARMGenInstrInfo.inc"
46 EnableARM3Addr("enable-arm-3-addr-conv", cl::Hidden,
47 cl::desc("Enable ARM 2-addr to 3-addr conv"));
49 /// ARM_MLxEntry - Record information about MLA / MLS instructions.
51 unsigned MLxOpc; // MLA / MLS opcode
52 unsigned MulOpc; // Expanded multiplication opcode
53 unsigned AddSubOpc; // Expanded add / sub opcode
54 bool NegAcc; // True if the acc is negated before the add / sub.
55 bool HasLane; // True if instruction has an extra "lane" operand.
58 static const ARM_MLxEntry ARM_MLxTable[] = {
59 // MLxOpc, MulOpc, AddSubOpc, NegAcc, HasLane
61 { ARM::VMLAS, ARM::VMULS, ARM::VADDS, false, false },
62 { ARM::VMLSS, ARM::VMULS, ARM::VSUBS, false, false },
63 { ARM::VMLAD, ARM::VMULD, ARM::VADDD, false, false },
64 { ARM::VMLSD, ARM::VMULD, ARM::VSUBD, false, false },
65 { ARM::VNMLAS, ARM::VNMULS, ARM::VSUBS, true, false },
66 { ARM::VNMLSS, ARM::VMULS, ARM::VSUBS, true, false },
67 { ARM::VNMLAD, ARM::VNMULD, ARM::VSUBD, true, false },
68 { ARM::VNMLSD, ARM::VMULD, ARM::VSUBD, true, false },
71 { ARM::VMLAfd, ARM::VMULfd, ARM::VADDfd, false, false },
72 { ARM::VMLSfd, ARM::VMULfd, ARM::VSUBfd, false, false },
73 { ARM::VMLAfq, ARM::VMULfq, ARM::VADDfq, false, false },
74 { ARM::VMLSfq, ARM::VMULfq, ARM::VSUBfq, false, false },
75 { ARM::VMLAslfd, ARM::VMULslfd, ARM::VADDfd, false, true },
76 { ARM::VMLSslfd, ARM::VMULslfd, ARM::VSUBfd, false, true },
77 { ARM::VMLAslfq, ARM::VMULslfq, ARM::VADDfq, false, true },
78 { ARM::VMLSslfq, ARM::VMULslfq, ARM::VSUBfq, false, true },
81 ARMBaseInstrInfo::ARMBaseInstrInfo(const ARMSubtarget& STI)
82 : ARMGenInstrInfo(ARM::ADJCALLSTACKDOWN, ARM::ADJCALLSTACKUP),
84 for (unsigned i = 0, e = array_lengthof(ARM_MLxTable); i != e; ++i) {
85 if (!MLxEntryMap.insert(std::make_pair(ARM_MLxTable[i].MLxOpc, i)).second)
86 assert(false && "Duplicated entries?");
87 MLxHazardOpcodes.insert(ARM_MLxTable[i].AddSubOpc);
88 MLxHazardOpcodes.insert(ARM_MLxTable[i].MulOpc);
92 // Use a ScoreboardHazardRecognizer for prepass ARM scheduling. TargetInstrImpl
93 // currently defaults to no prepass hazard recognizer.
94 ScheduleHazardRecognizer *ARMBaseInstrInfo::
95 CreateTargetHazardRecognizer(const TargetMachine *TM,
96 const ScheduleDAG *DAG) const {
97 if (usePreRAHazardRecognizer()) {
98 const InstrItineraryData *II = TM->getInstrItineraryData();
99 return new ScoreboardHazardRecognizer(II, DAG, "pre-RA-sched");
101 return TargetInstrInfoImpl::CreateTargetHazardRecognizer(TM, DAG);
104 ScheduleHazardRecognizer *ARMBaseInstrInfo::
105 CreateTargetPostRAHazardRecognizer(const InstrItineraryData *II,
106 const ScheduleDAG *DAG) const {
107 if (Subtarget.isThumb2() || Subtarget.hasVFP2())
108 return (ScheduleHazardRecognizer *)
109 new ARMHazardRecognizer(II, *this, getRegisterInfo(), Subtarget, DAG);
110 return TargetInstrInfoImpl::CreateTargetPostRAHazardRecognizer(II, DAG);
114 ARMBaseInstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
115 MachineBasicBlock::iterator &MBBI,
116 LiveVariables *LV) const {
117 // FIXME: Thumb2 support.
122 MachineInstr *MI = MBBI;
123 MachineFunction &MF = *MI->getParent()->getParent();
124 uint64_t TSFlags = MI->getDesc().TSFlags;
126 switch ((TSFlags & ARMII::IndexModeMask) >> ARMII::IndexModeShift) {
127 default: return NULL;
128 case ARMII::IndexModePre:
131 case ARMII::IndexModePost:
135 // Try splitting an indexed load/store to an un-indexed one plus an add/sub
137 unsigned MemOpc = getUnindexedOpcode(MI->getOpcode());
141 MachineInstr *UpdateMI = NULL;
142 MachineInstr *MemMI = NULL;
143 unsigned AddrMode = (TSFlags & ARMII::AddrModeMask);
144 const MCInstrDesc &MCID = MI->getDesc();
145 unsigned NumOps = MCID.getNumOperands();
146 bool isLoad = !MCID.mayStore();
147 const MachineOperand &WB = isLoad ? MI->getOperand(1) : MI->getOperand(0);
148 const MachineOperand &Base = MI->getOperand(2);
149 const MachineOperand &Offset = MI->getOperand(NumOps-3);
150 unsigned WBReg = WB.getReg();
151 unsigned BaseReg = Base.getReg();
152 unsigned OffReg = Offset.getReg();
153 unsigned OffImm = MI->getOperand(NumOps-2).getImm();
154 ARMCC::CondCodes Pred = (ARMCC::CondCodes)MI->getOperand(NumOps-1).getImm();
157 assert(false && "Unknown indexed op!");
159 case ARMII::AddrMode2: {
160 bool isSub = ARM_AM::getAM2Op(OffImm) == ARM_AM::sub;
161 unsigned Amt = ARM_AM::getAM2Offset(OffImm);
163 if (ARM_AM::getSOImmVal(Amt) == -1)
164 // Can't encode it in a so_imm operand. This transformation will
165 // add more than 1 instruction. Abandon!
167 UpdateMI = BuildMI(MF, MI->getDebugLoc(),
168 get(isSub ? ARM::SUBri : ARM::ADDri), WBReg)
169 .addReg(BaseReg).addImm(Amt)
170 .addImm(Pred).addReg(0).addReg(0);
171 } else if (Amt != 0) {
172 ARM_AM::ShiftOpc ShOpc = ARM_AM::getAM2ShiftOpc(OffImm);
173 unsigned SOOpc = ARM_AM::getSORegOpc(ShOpc, Amt);
174 UpdateMI = BuildMI(MF, MI->getDebugLoc(),
175 get(isSub ? ARM::SUBrsi : ARM::ADDrsi), WBReg)
176 .addReg(BaseReg).addReg(OffReg).addReg(0).addImm(SOOpc)
177 .addImm(Pred).addReg(0).addReg(0);
179 UpdateMI = BuildMI(MF, MI->getDebugLoc(),
180 get(isSub ? ARM::SUBrr : ARM::ADDrr), WBReg)
181 .addReg(BaseReg).addReg(OffReg)
182 .addImm(Pred).addReg(0).addReg(0);
185 case ARMII::AddrMode3 : {
186 bool isSub = ARM_AM::getAM3Op(OffImm) == ARM_AM::sub;
187 unsigned Amt = ARM_AM::getAM3Offset(OffImm);
189 // Immediate is 8-bits. It's guaranteed to fit in a so_imm operand.
190 UpdateMI = BuildMI(MF, MI->getDebugLoc(),
191 get(isSub ? ARM::SUBri : ARM::ADDri), WBReg)
192 .addReg(BaseReg).addImm(Amt)
193 .addImm(Pred).addReg(0).addReg(0);
195 UpdateMI = BuildMI(MF, MI->getDebugLoc(),
196 get(isSub ? ARM::SUBrr : ARM::ADDrr), WBReg)
197 .addReg(BaseReg).addReg(OffReg)
198 .addImm(Pred).addReg(0).addReg(0);
203 std::vector<MachineInstr*> NewMIs;
206 MemMI = BuildMI(MF, MI->getDebugLoc(),
207 get(MemOpc), MI->getOperand(0).getReg())
208 .addReg(WBReg).addImm(0).addImm(Pred);
210 MemMI = BuildMI(MF, MI->getDebugLoc(),
211 get(MemOpc)).addReg(MI->getOperand(1).getReg())
212 .addReg(WBReg).addReg(0).addImm(0).addImm(Pred);
213 NewMIs.push_back(MemMI);
214 NewMIs.push_back(UpdateMI);
217 MemMI = BuildMI(MF, MI->getDebugLoc(),
218 get(MemOpc), MI->getOperand(0).getReg())
219 .addReg(BaseReg).addImm(0).addImm(Pred);
221 MemMI = BuildMI(MF, MI->getDebugLoc(),
222 get(MemOpc)).addReg(MI->getOperand(1).getReg())
223 .addReg(BaseReg).addReg(0).addImm(0).addImm(Pred);
225 UpdateMI->getOperand(0).setIsDead();
226 NewMIs.push_back(UpdateMI);
227 NewMIs.push_back(MemMI);
230 // Transfer LiveVariables states, kill / dead info.
232 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
233 MachineOperand &MO = MI->getOperand(i);
234 if (MO.isReg() && TargetRegisterInfo::isVirtualRegister(MO.getReg())) {
235 unsigned Reg = MO.getReg();
237 LiveVariables::VarInfo &VI = LV->getVarInfo(Reg);
239 MachineInstr *NewMI = (Reg == WBReg) ? UpdateMI : MemMI;
241 LV->addVirtualRegisterDead(Reg, NewMI);
243 if (MO.isUse() && MO.isKill()) {
244 for (unsigned j = 0; j < 2; ++j) {
245 // Look at the two new MI's in reverse order.
246 MachineInstr *NewMI = NewMIs[j];
247 if (!NewMI->readsRegister(Reg))
249 LV->addVirtualRegisterKilled(Reg, NewMI);
250 if (VI.removeKill(MI))
251 VI.Kills.push_back(NewMI);
259 MFI->insert(MBBI, NewMIs[1]);
260 MFI->insert(MBBI, NewMIs[0]);
266 ARMBaseInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB,
267 MachineBasicBlock *&FBB,
268 SmallVectorImpl<MachineOperand> &Cond,
269 bool AllowModify) const {
270 // If the block has no terminators, it just falls into the block after it.
271 MachineBasicBlock::iterator I = MBB.end();
272 if (I == MBB.begin())
275 while (I->isDebugValue()) {
276 if (I == MBB.begin())
280 if (!isUnpredicatedTerminator(I))
283 // Get the last instruction in the block.
284 MachineInstr *LastInst = I;
286 // If there is only one terminator instruction, process it.
287 unsigned LastOpc = LastInst->getOpcode();
288 if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) {
289 if (isUncondBranchOpcode(LastOpc)) {
290 TBB = LastInst->getOperand(0).getMBB();
293 if (isCondBranchOpcode(LastOpc)) {
294 // Block ends with fall-through condbranch.
295 TBB = LastInst->getOperand(0).getMBB();
296 Cond.push_back(LastInst->getOperand(1));
297 Cond.push_back(LastInst->getOperand(2));
300 return true; // Can't handle indirect branch.
303 // Get the instruction before it if it is a terminator.
304 MachineInstr *SecondLastInst = I;
305 unsigned SecondLastOpc = SecondLastInst->getOpcode();
307 // If AllowModify is true and the block ends with two or more unconditional
308 // branches, delete all but the first unconditional branch.
309 if (AllowModify && isUncondBranchOpcode(LastOpc)) {
310 while (isUncondBranchOpcode(SecondLastOpc)) {
311 LastInst->eraseFromParent();
312 LastInst = SecondLastInst;
313 LastOpc = LastInst->getOpcode();
314 if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) {
315 // Return now the only terminator is an unconditional branch.
316 TBB = LastInst->getOperand(0).getMBB();
320 SecondLastOpc = SecondLastInst->getOpcode();
325 // If there are three terminators, we don't know what sort of block this is.
326 if (SecondLastInst && I != MBB.begin() && isUnpredicatedTerminator(--I))
329 // If the block ends with a B and a Bcc, handle it.
330 if (isCondBranchOpcode(SecondLastOpc) && isUncondBranchOpcode(LastOpc)) {
331 TBB = SecondLastInst->getOperand(0).getMBB();
332 Cond.push_back(SecondLastInst->getOperand(1));
333 Cond.push_back(SecondLastInst->getOperand(2));
334 FBB = LastInst->getOperand(0).getMBB();
338 // If the block ends with two unconditional branches, handle it. The second
339 // one is not executed, so remove it.
340 if (isUncondBranchOpcode(SecondLastOpc) && isUncondBranchOpcode(LastOpc)) {
341 TBB = SecondLastInst->getOperand(0).getMBB();
344 I->eraseFromParent();
348 // ...likewise if it ends with a branch table followed by an unconditional
349 // branch. The branch folder can create these, and we must get rid of them for
350 // correctness of Thumb constant islands.
351 if ((isJumpTableBranchOpcode(SecondLastOpc) ||
352 isIndirectBranchOpcode(SecondLastOpc)) &&
353 isUncondBranchOpcode(LastOpc)) {
356 I->eraseFromParent();
360 // Otherwise, can't handle this.
365 unsigned ARMBaseInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
366 MachineBasicBlock::iterator I = MBB.end();
367 if (I == MBB.begin()) return 0;
369 while (I->isDebugValue()) {
370 if (I == MBB.begin())
374 if (!isUncondBranchOpcode(I->getOpcode()) &&
375 !isCondBranchOpcode(I->getOpcode()))
378 // Remove the branch.
379 I->eraseFromParent();
383 if (I == MBB.begin()) return 1;
385 if (!isCondBranchOpcode(I->getOpcode()))
388 // Remove the branch.
389 I->eraseFromParent();
394 ARMBaseInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
395 MachineBasicBlock *FBB,
396 const SmallVectorImpl<MachineOperand> &Cond,
398 ARMFunctionInfo *AFI = MBB.getParent()->getInfo<ARMFunctionInfo>();
399 int BOpc = !AFI->isThumbFunction()
400 ? ARM::B : (AFI->isThumb2Function() ? ARM::t2B : ARM::tB);
401 int BccOpc = !AFI->isThumbFunction()
402 ? ARM::Bcc : (AFI->isThumb2Function() ? ARM::t2Bcc : ARM::tBcc);
404 // Shouldn't be a fall through.
405 assert(TBB && "InsertBranch must not be told to insert a fallthrough");
406 assert((Cond.size() == 2 || Cond.size() == 0) &&
407 "ARM branch conditions have two components!");
410 if (Cond.empty()) // Unconditional branch?
411 BuildMI(&MBB, DL, get(BOpc)).addMBB(TBB);
413 BuildMI(&MBB, DL, get(BccOpc)).addMBB(TBB)
414 .addImm(Cond[0].getImm()).addReg(Cond[1].getReg());
418 // Two-way conditional branch.
419 BuildMI(&MBB, DL, get(BccOpc)).addMBB(TBB)
420 .addImm(Cond[0].getImm()).addReg(Cond[1].getReg());
421 BuildMI(&MBB, DL, get(BOpc)).addMBB(FBB);
425 bool ARMBaseInstrInfo::
426 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
427 ARMCC::CondCodes CC = (ARMCC::CondCodes)(int)Cond[0].getImm();
428 Cond[0].setImm(ARMCC::getOppositeCondition(CC));
432 bool ARMBaseInstrInfo::
433 PredicateInstruction(MachineInstr *MI,
434 const SmallVectorImpl<MachineOperand> &Pred) const {
435 unsigned Opc = MI->getOpcode();
436 if (isUncondBranchOpcode(Opc)) {
437 MI->setDesc(get(getMatchingCondBranchOpcode(Opc)));
438 MI->addOperand(MachineOperand::CreateImm(Pred[0].getImm()));
439 MI->addOperand(MachineOperand::CreateReg(Pred[1].getReg(), false));
443 int PIdx = MI->findFirstPredOperandIdx();
445 MachineOperand &PMO = MI->getOperand(PIdx);
446 PMO.setImm(Pred[0].getImm());
447 MI->getOperand(PIdx+1).setReg(Pred[1].getReg());
453 bool ARMBaseInstrInfo::
454 SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1,
455 const SmallVectorImpl<MachineOperand> &Pred2) const {
456 if (Pred1.size() > 2 || Pred2.size() > 2)
459 ARMCC::CondCodes CC1 = (ARMCC::CondCodes)Pred1[0].getImm();
460 ARMCC::CondCodes CC2 = (ARMCC::CondCodes)Pred2[0].getImm();
470 return CC2 == ARMCC::HI;
472 return CC2 == ARMCC::LO || CC2 == ARMCC::EQ;
474 return CC2 == ARMCC::GT;
476 return CC2 == ARMCC::LT;
480 bool ARMBaseInstrInfo::DefinesPredicate(MachineInstr *MI,
481 std::vector<MachineOperand> &Pred) const {
482 // FIXME: This confuses implicit_def with optional CPSR def.
483 const MCInstrDesc &MCID = MI->getDesc();
484 if (!MCID.getImplicitDefs() && !MCID.hasOptionalDef())
488 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
489 const MachineOperand &MO = MI->getOperand(i);
490 if (MO.isReg() && MO.getReg() == ARM::CPSR) {
499 /// isPredicable - Return true if the specified instruction can be predicated.
500 /// By default, this returns true for every instruction with a
501 /// PredicateOperand.
502 bool ARMBaseInstrInfo::isPredicable(MachineInstr *MI) const {
503 const MCInstrDesc &MCID = MI->getDesc();
504 if (!MCID.isPredicable())
507 if ((MCID.TSFlags & ARMII::DomainMask) == ARMII::DomainNEON) {
508 ARMFunctionInfo *AFI =
509 MI->getParent()->getParent()->getInfo<ARMFunctionInfo>();
510 return AFI->isThumb2Function();
515 /// FIXME: Works around a gcc miscompilation with -fstrict-aliasing.
516 LLVM_ATTRIBUTE_NOINLINE
517 static unsigned getNumJTEntries(const std::vector<MachineJumpTableEntry> &JT,
519 static unsigned getNumJTEntries(const std::vector<MachineJumpTableEntry> &JT,
521 assert(JTI < JT.size());
522 return JT[JTI].MBBs.size();
525 /// GetInstSize - Return the size of the specified MachineInstr.
527 unsigned ARMBaseInstrInfo::GetInstSizeInBytes(const MachineInstr *MI) const {
528 const MachineBasicBlock &MBB = *MI->getParent();
529 const MachineFunction *MF = MBB.getParent();
530 const MCAsmInfo *MAI = MF->getTarget().getMCAsmInfo();
532 const MCInstrDesc &MCID = MI->getDesc();
534 return MCID.getSize();
536 // If this machine instr is an inline asm, measure it.
537 if (MI->getOpcode() == ARM::INLINEASM)
538 return getInlineAsmLength(MI->getOperand(0).getSymbolName(), *MAI);
541 unsigned Opc = MI->getOpcode();
543 case TargetOpcode::IMPLICIT_DEF:
544 case TargetOpcode::KILL:
545 case TargetOpcode::PROLOG_LABEL:
546 case TargetOpcode::EH_LABEL:
547 case TargetOpcode::DBG_VALUE:
549 case ARM::MOVi16_ga_pcrel:
550 case ARM::MOVTi16_ga_pcrel:
551 case ARM::t2MOVi16_ga_pcrel:
552 case ARM::t2MOVTi16_ga_pcrel:
555 case ARM::t2MOVi32imm:
557 case ARM::CONSTPOOL_ENTRY:
558 // If this machine instr is a constant pool entry, its size is recorded as
560 return MI->getOperand(2).getImm();
561 case ARM::Int_eh_sjlj_longjmp:
563 case ARM::tInt_eh_sjlj_longjmp:
565 case ARM::Int_eh_sjlj_setjmp:
566 case ARM::Int_eh_sjlj_setjmp_nofp:
568 case ARM::tInt_eh_sjlj_setjmp:
569 case ARM::t2Int_eh_sjlj_setjmp:
570 case ARM::t2Int_eh_sjlj_setjmp_nofp:
578 case ARM::t2TBH_JT: {
579 // These are jumptable branches, i.e. a branch followed by an inlined
580 // jumptable. The size is 4 + 4 * number of entries. For TBB, each
581 // entry is one byte; TBH two byte each.
582 unsigned EntrySize = (Opc == ARM::t2TBB_JT)
583 ? 1 : ((Opc == ARM::t2TBH_JT) ? 2 : 4);
584 unsigned NumOps = MCID.getNumOperands();
585 MachineOperand JTOP =
586 MI->getOperand(NumOps - (MCID.isPredicable() ? 3 : 2));
587 unsigned JTI = JTOP.getIndex();
588 const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
590 const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
591 assert(JTI < JT.size());
592 // Thumb instructions are 2 byte aligned, but JT entries are 4 byte
593 // 4 aligned. The assembler / linker may add 2 byte padding just before
594 // the JT entries. The size does not include this padding; the
595 // constant islands pass does separate bookkeeping for it.
596 // FIXME: If we know the size of the function is less than (1 << 16) *2
597 // bytes, we can use 16-bit entries instead. Then there won't be an
599 unsigned InstSize = (Opc == ARM::tBR_JTr || Opc == ARM::t2BR_JT) ? 2 : 4;
600 unsigned NumEntries = getNumJTEntries(JT, JTI);
601 if (Opc == ARM::t2TBB_JT && (NumEntries & 1))
602 // Make sure the instruction that follows TBB is 2-byte aligned.
603 // FIXME: Constant island pass should insert an "ALIGN" instruction
606 return NumEntries * EntrySize + InstSize;
609 // Otherwise, pseudo-instruction sizes are zero.
612 return 0; // Not reached
615 void ARMBaseInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
616 MachineBasicBlock::iterator I, DebugLoc DL,
617 unsigned DestReg, unsigned SrcReg,
618 bool KillSrc) const {
619 bool GPRDest = ARM::GPRRegClass.contains(DestReg);
620 bool GPRSrc = ARM::GPRRegClass.contains(SrcReg);
622 if (GPRDest && GPRSrc) {
623 AddDefaultCC(AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::MOVr), DestReg)
624 .addReg(SrcReg, getKillRegState(KillSrc))));
628 bool SPRDest = ARM::SPRRegClass.contains(DestReg);
629 bool SPRSrc = ARM::SPRRegClass.contains(SrcReg);
632 if (SPRDest && SPRSrc)
634 else if (GPRDest && SPRSrc)
636 else if (SPRDest && GPRSrc)
638 else if (ARM::DPRRegClass.contains(DestReg, SrcReg))
640 else if (ARM::QPRRegClass.contains(DestReg, SrcReg))
642 else if (ARM::QQPRRegClass.contains(DestReg, SrcReg))
644 else if (ARM::QQQQPRRegClass.contains(DestReg, SrcReg))
647 llvm_unreachable("Impossible reg-to-reg copy");
649 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(Opc), DestReg);
650 MIB.addReg(SrcReg, getKillRegState(KillSrc));
651 if (Opc == ARM::VORRq)
652 MIB.addReg(SrcReg, getKillRegState(KillSrc));
653 if (Opc != ARM::VMOVQQ && Opc != ARM::VMOVQQQQ)
658 MachineInstrBuilder &AddDReg(MachineInstrBuilder &MIB,
659 unsigned Reg, unsigned SubIdx, unsigned State,
660 const TargetRegisterInfo *TRI) {
662 return MIB.addReg(Reg, State);
664 if (TargetRegisterInfo::isPhysicalRegister(Reg))
665 return MIB.addReg(TRI->getSubReg(Reg, SubIdx), State);
666 return MIB.addReg(Reg, State, SubIdx);
669 void ARMBaseInstrInfo::
670 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
671 unsigned SrcReg, bool isKill, int FI,
672 const TargetRegisterClass *RC,
673 const TargetRegisterInfo *TRI) const {
675 if (I != MBB.end()) DL = I->getDebugLoc();
676 MachineFunction &MF = *MBB.getParent();
677 MachineFrameInfo &MFI = *MF.getFrameInfo();
678 unsigned Align = MFI.getObjectAlignment(FI);
680 MachineMemOperand *MMO =
681 MF.getMachineMemOperand(MachinePointerInfo(
682 PseudoSourceValue::getFixedStack(FI)),
683 MachineMemOperand::MOStore,
684 MFI.getObjectSize(FI),
687 // tGPR is used sometimes in ARM instructions that need to avoid using
688 // certain registers. Just treat it as GPR here. Likewise, rGPR.
689 if (RC == ARM::tGPRRegisterClass || RC == ARM::tcGPRRegisterClass
690 || RC == ARM::rGPRRegisterClass)
691 RC = ARM::GPRRegisterClass;
693 switch (RC->getID()) {
694 case ARM::GPRRegClassID:
695 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::STRi12))
696 .addReg(SrcReg, getKillRegState(isKill))
697 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
699 case ARM::SPRRegClassID:
700 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTRS))
701 .addReg(SrcReg, getKillRegState(isKill))
702 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
704 case ARM::DPRRegClassID:
705 case ARM::DPR_VFP2RegClassID:
706 case ARM::DPR_8RegClassID:
707 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTRD))
708 .addReg(SrcReg, getKillRegState(isKill))
709 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
711 case ARM::QPRRegClassID:
712 case ARM::QPR_VFP2RegClassID:
713 case ARM::QPR_8RegClassID:
714 if (Align >= 16 && getRegisterInfo().needsStackRealignment(MF)) {
715 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VST1q64Pseudo))
716 .addFrameIndex(FI).addImm(16)
717 .addReg(SrcReg, getKillRegState(isKill))
718 .addMemOperand(MMO));
720 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTMQIA))
721 .addReg(SrcReg, getKillRegState(isKill))
723 .addMemOperand(MMO));
726 case ARM::QQPRRegClassID:
727 case ARM::QQPR_VFP2RegClassID:
728 if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) {
729 // FIXME: It's possible to only store part of the QQ register if the
730 // spilled def has a sub-register index.
731 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VST1d64QPseudo))
732 .addFrameIndex(FI).addImm(16)
733 .addReg(SrcReg, getKillRegState(isKill))
734 .addMemOperand(MMO));
736 MachineInstrBuilder MIB =
737 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTMDIA))
740 MIB = AddDReg(MIB, SrcReg, ARM::dsub_0, getKillRegState(isKill), TRI);
741 MIB = AddDReg(MIB, SrcReg, ARM::dsub_1, 0, TRI);
742 MIB = AddDReg(MIB, SrcReg, ARM::dsub_2, 0, TRI);
743 AddDReg(MIB, SrcReg, ARM::dsub_3, 0, TRI);
746 case ARM::QQQQPRRegClassID: {
747 MachineInstrBuilder MIB =
748 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTMDIA))
751 MIB = AddDReg(MIB, SrcReg, ARM::dsub_0, getKillRegState(isKill), TRI);
752 MIB = AddDReg(MIB, SrcReg, ARM::dsub_1, 0, TRI);
753 MIB = AddDReg(MIB, SrcReg, ARM::dsub_2, 0, TRI);
754 MIB = AddDReg(MIB, SrcReg, ARM::dsub_3, 0, TRI);
755 MIB = AddDReg(MIB, SrcReg, ARM::dsub_4, 0, TRI);
756 MIB = AddDReg(MIB, SrcReg, ARM::dsub_5, 0, TRI);
757 MIB = AddDReg(MIB, SrcReg, ARM::dsub_6, 0, TRI);
758 AddDReg(MIB, SrcReg, ARM::dsub_7, 0, TRI);
762 llvm_unreachable("Unknown regclass!");
767 ARMBaseInstrInfo::isStoreToStackSlot(const MachineInstr *MI,
768 int &FrameIndex) const {
769 switch (MI->getOpcode()) {
772 case ARM::t2STRs: // FIXME: don't use t2STRs to access frame.
773 if (MI->getOperand(1).isFI() &&
774 MI->getOperand(2).isReg() &&
775 MI->getOperand(3).isImm() &&
776 MI->getOperand(2).getReg() == 0 &&
777 MI->getOperand(3).getImm() == 0) {
778 FrameIndex = MI->getOperand(1).getIndex();
779 return MI->getOperand(0).getReg();
787 if (MI->getOperand(1).isFI() &&
788 MI->getOperand(2).isImm() &&
789 MI->getOperand(2).getImm() == 0) {
790 FrameIndex = MI->getOperand(1).getIndex();
791 return MI->getOperand(0).getReg();
794 case ARM::VST1q64Pseudo:
795 if (MI->getOperand(0).isFI() &&
796 MI->getOperand(2).getSubReg() == 0) {
797 FrameIndex = MI->getOperand(0).getIndex();
798 return MI->getOperand(2).getReg();
802 if (MI->getOperand(1).isFI() &&
803 MI->getOperand(0).getSubReg() == 0) {
804 FrameIndex = MI->getOperand(1).getIndex();
805 return MI->getOperand(0).getReg();
813 void ARMBaseInstrInfo::
814 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
815 unsigned DestReg, int FI,
816 const TargetRegisterClass *RC,
817 const TargetRegisterInfo *TRI) const {
819 if (I != MBB.end()) DL = I->getDebugLoc();
820 MachineFunction &MF = *MBB.getParent();
821 MachineFrameInfo &MFI = *MF.getFrameInfo();
822 unsigned Align = MFI.getObjectAlignment(FI);
823 MachineMemOperand *MMO =
824 MF.getMachineMemOperand(
825 MachinePointerInfo(PseudoSourceValue::getFixedStack(FI)),
826 MachineMemOperand::MOLoad,
827 MFI.getObjectSize(FI),
830 // tGPR is used sometimes in ARM instructions that need to avoid using
831 // certain registers. Just treat it as GPR here.
832 if (RC == ARM::tGPRRegisterClass || RC == ARM::tcGPRRegisterClass
833 || RC == ARM::rGPRRegisterClass)
834 RC = ARM::GPRRegisterClass;
836 switch (RC->getID()) {
837 case ARM::GPRRegClassID:
838 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::LDRi12), DestReg)
839 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
841 case ARM::SPRRegClassID:
842 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDRS), DestReg)
843 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
845 case ARM::DPRRegClassID:
846 case ARM::DPR_VFP2RegClassID:
847 case ARM::DPR_8RegClassID:
848 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDRD), DestReg)
849 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
851 case ARM::QPRRegClassID:
852 case ARM::QPR_VFP2RegClassID:
853 case ARM::QPR_8RegClassID:
854 if (Align >= 16 && getRegisterInfo().needsStackRealignment(MF)) {
855 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLD1q64Pseudo), DestReg)
856 .addFrameIndex(FI).addImm(16)
857 .addMemOperand(MMO));
859 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDMQIA), DestReg)
861 .addMemOperand(MMO));
864 case ARM::QQPRRegClassID:
865 case ARM::QQPR_VFP2RegClassID:
866 if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) {
867 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLD1d64QPseudo), DestReg)
868 .addFrameIndex(FI).addImm(16)
869 .addMemOperand(MMO));
871 MachineInstrBuilder MIB =
872 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDMDIA))
875 MIB = AddDReg(MIB, DestReg, ARM::dsub_0, RegState::Define, TRI);
876 MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::Define, TRI);
877 MIB = AddDReg(MIB, DestReg, ARM::dsub_2, RegState::Define, TRI);
878 AddDReg(MIB, DestReg, ARM::dsub_3, RegState::Define, TRI);
881 case ARM::QQQQPRRegClassID: {
882 MachineInstrBuilder MIB =
883 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDMDIA))
886 MIB = AddDReg(MIB, DestReg, ARM::dsub_0, RegState::Define, TRI);
887 MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::Define, TRI);
888 MIB = AddDReg(MIB, DestReg, ARM::dsub_2, RegState::Define, TRI);
889 MIB = AddDReg(MIB, DestReg, ARM::dsub_3, RegState::Define, TRI);
890 MIB = AddDReg(MIB, DestReg, ARM::dsub_4, RegState::Define, TRI);
891 MIB = AddDReg(MIB, DestReg, ARM::dsub_5, RegState::Define, TRI);
892 MIB = AddDReg(MIB, DestReg, ARM::dsub_6, RegState::Define, TRI);
893 AddDReg(MIB, DestReg, ARM::dsub_7, RegState::Define, TRI);
897 llvm_unreachable("Unknown regclass!");
902 ARMBaseInstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
903 int &FrameIndex) const {
904 switch (MI->getOpcode()) {
907 case ARM::t2LDRs: // FIXME: don't use t2LDRs to access frame.
908 if (MI->getOperand(1).isFI() &&
909 MI->getOperand(2).isReg() &&
910 MI->getOperand(3).isImm() &&
911 MI->getOperand(2).getReg() == 0 &&
912 MI->getOperand(3).getImm() == 0) {
913 FrameIndex = MI->getOperand(1).getIndex();
914 return MI->getOperand(0).getReg();
922 if (MI->getOperand(1).isFI() &&
923 MI->getOperand(2).isImm() &&
924 MI->getOperand(2).getImm() == 0) {
925 FrameIndex = MI->getOperand(1).getIndex();
926 return MI->getOperand(0).getReg();
929 case ARM::VLD1q64Pseudo:
930 if (MI->getOperand(1).isFI() &&
931 MI->getOperand(0).getSubReg() == 0) {
932 FrameIndex = MI->getOperand(1).getIndex();
933 return MI->getOperand(0).getReg();
937 if (MI->getOperand(1).isFI() &&
938 MI->getOperand(0).getSubReg() == 0) {
939 FrameIndex = MI->getOperand(1).getIndex();
940 return MI->getOperand(0).getReg();
949 ARMBaseInstrInfo::emitFrameIndexDebugValue(MachineFunction &MF,
950 int FrameIx, uint64_t Offset,
953 MachineInstrBuilder MIB = BuildMI(MF, DL, get(ARM::DBG_VALUE))
954 .addFrameIndex(FrameIx).addImm(0).addImm(Offset).addMetadata(MDPtr);
958 /// Create a copy of a const pool value. Update CPI to the new index and return
960 static unsigned duplicateCPV(MachineFunction &MF, unsigned &CPI) {
961 MachineConstantPool *MCP = MF.getConstantPool();
962 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
964 const MachineConstantPoolEntry &MCPE = MCP->getConstants()[CPI];
965 assert(MCPE.isMachineConstantPoolEntry() &&
966 "Expecting a machine constantpool entry!");
967 ARMConstantPoolValue *ACPV =
968 static_cast<ARMConstantPoolValue*>(MCPE.Val.MachineCPVal);
970 unsigned PCLabelId = AFI->createPICLabelUId();
971 ARMConstantPoolValue *NewCPV = 0;
972 // FIXME: The below assumes PIC relocation model and that the function
973 // is Thumb mode (t1 or t2). PCAdjustment would be 8 for ARM mode PIC, and
974 // zero for non-PIC in ARM or Thumb. The callers are all of thumb LDR
975 // instructions, so that's probably OK, but is PIC always correct when
977 if (ACPV->isGlobalValue())
978 NewCPV = new ARMConstantPoolValue(ACPV->getGV(), PCLabelId,
980 else if (ACPV->isExtSymbol())
981 NewCPV = new ARMConstantPoolValue(MF.getFunction()->getContext(),
982 ACPV->getSymbol(), PCLabelId, 4);
983 else if (ACPV->isBlockAddress())
984 NewCPV = new ARMConstantPoolValue(ACPV->getBlockAddress(), PCLabelId,
985 ARMCP::CPBlockAddress, 4);
986 else if (ACPV->isLSDA())
987 NewCPV = new ARMConstantPoolValue(MF.getFunction(), PCLabelId,
990 llvm_unreachable("Unexpected ARM constantpool value type!!");
991 CPI = MCP->getConstantPoolIndex(NewCPV, MCPE.getAlignment());
995 void ARMBaseInstrInfo::
996 reMaterialize(MachineBasicBlock &MBB,
997 MachineBasicBlock::iterator I,
998 unsigned DestReg, unsigned SubIdx,
999 const MachineInstr *Orig,
1000 const TargetRegisterInfo &TRI) const {
1001 unsigned Opcode = Orig->getOpcode();
1004 MachineInstr *MI = MBB.getParent()->CloneMachineInstr(Orig);
1005 MI->substituteRegister(Orig->getOperand(0).getReg(), DestReg, SubIdx, TRI);
1009 case ARM::tLDRpci_pic:
1010 case ARM::t2LDRpci_pic: {
1011 MachineFunction &MF = *MBB.getParent();
1012 unsigned CPI = Orig->getOperand(1).getIndex();
1013 unsigned PCLabelId = duplicateCPV(MF, CPI);
1014 MachineInstrBuilder MIB = BuildMI(MBB, I, Orig->getDebugLoc(), get(Opcode),
1016 .addConstantPoolIndex(CPI).addImm(PCLabelId);
1017 MIB->setMemRefs(Orig->memoperands_begin(), Orig->memoperands_end());
1024 ARMBaseInstrInfo::duplicate(MachineInstr *Orig, MachineFunction &MF) const {
1025 MachineInstr *MI = TargetInstrInfoImpl::duplicate(Orig, MF);
1026 switch(Orig->getOpcode()) {
1027 case ARM::tLDRpci_pic:
1028 case ARM::t2LDRpci_pic: {
1029 unsigned CPI = Orig->getOperand(1).getIndex();
1030 unsigned PCLabelId = duplicateCPV(MF, CPI);
1031 Orig->getOperand(1).setIndex(CPI);
1032 Orig->getOperand(2).setImm(PCLabelId);
1039 bool ARMBaseInstrInfo::produceSameValue(const MachineInstr *MI0,
1040 const MachineInstr *MI1,
1041 const MachineRegisterInfo *MRI) const {
1042 int Opcode = MI0->getOpcode();
1043 if (Opcode == ARM::t2LDRpci ||
1044 Opcode == ARM::t2LDRpci_pic ||
1045 Opcode == ARM::tLDRpci ||
1046 Opcode == ARM::tLDRpci_pic ||
1047 Opcode == ARM::MOV_ga_dyn ||
1048 Opcode == ARM::MOV_ga_pcrel ||
1049 Opcode == ARM::MOV_ga_pcrel_ldr ||
1050 Opcode == ARM::t2MOV_ga_dyn ||
1051 Opcode == ARM::t2MOV_ga_pcrel) {
1052 if (MI1->getOpcode() != Opcode)
1054 if (MI0->getNumOperands() != MI1->getNumOperands())
1057 const MachineOperand &MO0 = MI0->getOperand(1);
1058 const MachineOperand &MO1 = MI1->getOperand(1);
1059 if (MO0.getOffset() != MO1.getOffset())
1062 if (Opcode == ARM::MOV_ga_dyn ||
1063 Opcode == ARM::MOV_ga_pcrel ||
1064 Opcode == ARM::MOV_ga_pcrel_ldr ||
1065 Opcode == ARM::t2MOV_ga_dyn ||
1066 Opcode == ARM::t2MOV_ga_pcrel)
1067 // Ignore the PC labels.
1068 return MO0.getGlobal() == MO1.getGlobal();
1070 const MachineFunction *MF = MI0->getParent()->getParent();
1071 const MachineConstantPool *MCP = MF->getConstantPool();
1072 int CPI0 = MO0.getIndex();
1073 int CPI1 = MO1.getIndex();
1074 const MachineConstantPoolEntry &MCPE0 = MCP->getConstants()[CPI0];
1075 const MachineConstantPoolEntry &MCPE1 = MCP->getConstants()[CPI1];
1076 bool isARMCP0 = MCPE0.isMachineConstantPoolEntry();
1077 bool isARMCP1 = MCPE1.isMachineConstantPoolEntry();
1078 if (isARMCP0 && isARMCP1) {
1079 ARMConstantPoolValue *ACPV0 =
1080 static_cast<ARMConstantPoolValue*>(MCPE0.Val.MachineCPVal);
1081 ARMConstantPoolValue *ACPV1 =
1082 static_cast<ARMConstantPoolValue*>(MCPE1.Val.MachineCPVal);
1083 return ACPV0->hasSameValue(ACPV1);
1084 } else if (!isARMCP0 && !isARMCP1) {
1085 return MCPE0.Val.ConstVal == MCPE1.Val.ConstVal;
1088 } else if (Opcode == ARM::PICLDR) {
1089 if (MI1->getOpcode() != Opcode)
1091 if (MI0->getNumOperands() != MI1->getNumOperands())
1094 unsigned Addr0 = MI0->getOperand(1).getReg();
1095 unsigned Addr1 = MI1->getOperand(1).getReg();
1096 if (Addr0 != Addr1) {
1098 !TargetRegisterInfo::isVirtualRegister(Addr0) ||
1099 !TargetRegisterInfo::isVirtualRegister(Addr1))
1102 // This assumes SSA form.
1103 MachineInstr *Def0 = MRI->getVRegDef(Addr0);
1104 MachineInstr *Def1 = MRI->getVRegDef(Addr1);
1105 // Check if the loaded value, e.g. a constantpool of a global address, are
1107 if (!produceSameValue(Def0, Def1, MRI))
1111 for (unsigned i = 3, e = MI0->getNumOperands(); i != e; ++i) {
1112 // %vreg12<def> = PICLDR %vreg11, 0, pred:14, pred:%noreg
1113 const MachineOperand &MO0 = MI0->getOperand(i);
1114 const MachineOperand &MO1 = MI1->getOperand(i);
1115 if (!MO0.isIdenticalTo(MO1))
1121 return MI0->isIdenticalTo(MI1, MachineInstr::IgnoreVRegDefs);
1124 /// areLoadsFromSameBasePtr - This is used by the pre-regalloc scheduler to
1125 /// determine if two loads are loading from the same base address. It should
1126 /// only return true if the base pointers are the same and the only differences
1127 /// between the two addresses is the offset. It also returns the offsets by
1129 bool ARMBaseInstrInfo::areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2,
1131 int64_t &Offset2) const {
1132 // Don't worry about Thumb: just ARM and Thumb2.
1133 if (Subtarget.isThumb1Only()) return false;
1135 if (!Load1->isMachineOpcode() || !Load2->isMachineOpcode())
1138 switch (Load1->getMachineOpcode()) {
1151 case ARM::t2LDRSHi8:
1153 case ARM::t2LDRSHi12:
1157 switch (Load2->getMachineOpcode()) {
1170 case ARM::t2LDRSHi8:
1172 case ARM::t2LDRSHi12:
1176 // Check if base addresses and chain operands match.
1177 if (Load1->getOperand(0) != Load2->getOperand(0) ||
1178 Load1->getOperand(4) != Load2->getOperand(4))
1181 // Index should be Reg0.
1182 if (Load1->getOperand(3) != Load2->getOperand(3))
1185 // Determine the offsets.
1186 if (isa<ConstantSDNode>(Load1->getOperand(1)) &&
1187 isa<ConstantSDNode>(Load2->getOperand(1))) {
1188 Offset1 = cast<ConstantSDNode>(Load1->getOperand(1))->getSExtValue();
1189 Offset2 = cast<ConstantSDNode>(Load2->getOperand(1))->getSExtValue();
1196 /// shouldScheduleLoadsNear - This is a used by the pre-regalloc scheduler to
1197 /// determine (in conjunction with areLoadsFromSameBasePtr) if two loads should
1198 /// be scheduled togther. On some targets if two loads are loading from
1199 /// addresses in the same cache line, it's better if they are scheduled
1200 /// together. This function takes two integers that represent the load offsets
1201 /// from the common base address. It returns true if it decides it's desirable
1202 /// to schedule the two loads together. "NumLoads" is the number of loads that
1203 /// have already been scheduled after Load1.
1204 bool ARMBaseInstrInfo::shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,
1205 int64_t Offset1, int64_t Offset2,
1206 unsigned NumLoads) const {
1207 // Don't worry about Thumb: just ARM and Thumb2.
1208 if (Subtarget.isThumb1Only()) return false;
1210 assert(Offset2 > Offset1);
1212 if ((Offset2 - Offset1) / 8 > 64)
1215 if (Load1->getMachineOpcode() != Load2->getMachineOpcode())
1216 return false; // FIXME: overly conservative?
1218 // Four loads in a row should be sufficient.
1225 bool ARMBaseInstrInfo::isSchedulingBoundary(const MachineInstr *MI,
1226 const MachineBasicBlock *MBB,
1227 const MachineFunction &MF) const {
1228 // Debug info is never a scheduling boundary. It's necessary to be explicit
1229 // due to the special treatment of IT instructions below, otherwise a
1230 // dbg_value followed by an IT will result in the IT instruction being
1231 // considered a scheduling hazard, which is wrong. It should be the actual
1232 // instruction preceding the dbg_value instruction(s), just like it is
1233 // when debug info is not present.
1234 if (MI->isDebugValue())
1237 // Terminators and labels can't be scheduled around.
1238 if (MI->getDesc().isTerminator() || MI->isLabel())
1241 // Treat the start of the IT block as a scheduling boundary, but schedule
1242 // t2IT along with all instructions following it.
1243 // FIXME: This is a big hammer. But the alternative is to add all potential
1244 // true and anti dependencies to IT block instructions as implicit operands
1245 // to the t2IT instruction. The added compile time and complexity does not
1247 MachineBasicBlock::const_iterator I = MI;
1248 // Make sure to skip any dbg_value instructions
1249 while (++I != MBB->end() && I->isDebugValue())
1251 if (I != MBB->end() && I->getOpcode() == ARM::t2IT)
1254 // Don't attempt to schedule around any instruction that defines
1255 // a stack-oriented pointer, as it's unlikely to be profitable. This
1256 // saves compile time, because it doesn't require every single
1257 // stack slot reference to depend on the instruction that does the
1259 if (MI->definesRegister(ARM::SP))
1265 bool ARMBaseInstrInfo::
1266 isProfitableToIfCvt(MachineBasicBlock &MBB,
1267 unsigned NumCycles, unsigned ExtraPredCycles,
1268 const BranchProbability &Probability) const {
1272 // Attempt to estimate the relative costs of predication versus branching.
1273 unsigned UnpredCost = Probability.getNumerator() * NumCycles;
1274 UnpredCost /= Probability.getDenominator();
1275 UnpredCost += 1; // The branch itself
1276 UnpredCost += Subtarget.getMispredictionPenalty() / 10;
1278 return (NumCycles + ExtraPredCycles) <= UnpredCost;
1281 bool ARMBaseInstrInfo::
1282 isProfitableToIfCvt(MachineBasicBlock &TMBB,
1283 unsigned TCycles, unsigned TExtra,
1284 MachineBasicBlock &FMBB,
1285 unsigned FCycles, unsigned FExtra,
1286 const BranchProbability &Probability) const {
1287 if (!TCycles || !FCycles)
1290 // Attempt to estimate the relative costs of predication versus branching.
1291 unsigned TUnpredCost = Probability.getNumerator() * TCycles;
1292 TUnpredCost /= Probability.getDenominator();
1294 uint32_t Comp = Probability.getDenominator() - Probability.getNumerator();
1295 unsigned FUnpredCost = Comp * FCycles;
1296 FUnpredCost /= Probability.getDenominator();
1298 unsigned UnpredCost = TUnpredCost + FUnpredCost;
1299 UnpredCost += 1; // The branch itself
1300 UnpredCost += Subtarget.getMispredictionPenalty() / 10;
1302 return (TCycles + FCycles + TExtra + FExtra) <= UnpredCost;
1305 /// getInstrPredicate - If instruction is predicated, returns its predicate
1306 /// condition, otherwise returns AL. It also returns the condition code
1307 /// register by reference.
1309 llvm::getInstrPredicate(const MachineInstr *MI, unsigned &PredReg) {
1310 int PIdx = MI->findFirstPredOperandIdx();
1316 PredReg = MI->getOperand(PIdx+1).getReg();
1317 return (ARMCC::CondCodes)MI->getOperand(PIdx).getImm();
1321 int llvm::getMatchingCondBranchOpcode(int Opc) {
1324 else if (Opc == ARM::tB)
1326 else if (Opc == ARM::t2B)
1329 llvm_unreachable("Unknown unconditional branch opcode!");
1334 void llvm::emitARMRegPlusImmediate(MachineBasicBlock &MBB,
1335 MachineBasicBlock::iterator &MBBI, DebugLoc dl,
1336 unsigned DestReg, unsigned BaseReg, int NumBytes,
1337 ARMCC::CondCodes Pred, unsigned PredReg,
1338 const ARMBaseInstrInfo &TII, unsigned MIFlags) {
1339 bool isSub = NumBytes < 0;
1340 if (isSub) NumBytes = -NumBytes;
1343 unsigned RotAmt = ARM_AM::getSOImmValRotate(NumBytes);
1344 unsigned ThisVal = NumBytes & ARM_AM::rotr32(0xFF, RotAmt);
1345 assert(ThisVal && "Didn't extract field correctly");
1347 // We will handle these bits from offset, clear them.
1348 NumBytes &= ~ThisVal;
1350 assert(ARM_AM::getSOImmVal(ThisVal) != -1 && "Bit extraction didn't work?");
1352 // Build the new ADD / SUB.
1353 unsigned Opc = isSub ? ARM::SUBri : ARM::ADDri;
1354 BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg)
1355 .addReg(BaseReg, RegState::Kill).addImm(ThisVal)
1356 .addImm((unsigned)Pred).addReg(PredReg).addReg(0)
1357 .setMIFlags(MIFlags);
1362 bool llvm::rewriteARMFrameIndex(MachineInstr &MI, unsigned FrameRegIdx,
1363 unsigned FrameReg, int &Offset,
1364 const ARMBaseInstrInfo &TII) {
1365 unsigned Opcode = MI.getOpcode();
1366 const MCInstrDesc &Desc = MI.getDesc();
1367 unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
1370 // Memory operands in inline assembly always use AddrMode2.
1371 if (Opcode == ARM::INLINEASM)
1372 AddrMode = ARMII::AddrMode2;
1374 if (Opcode == ARM::ADDri) {
1375 Offset += MI.getOperand(FrameRegIdx+1).getImm();
1377 // Turn it into a move.
1378 MI.setDesc(TII.get(ARM::MOVr));
1379 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
1380 MI.RemoveOperand(FrameRegIdx+1);
1383 } else if (Offset < 0) {
1386 MI.setDesc(TII.get(ARM::SUBri));
1389 // Common case: small offset, fits into instruction.
1390 if (ARM_AM::getSOImmVal(Offset) != -1) {
1391 // Replace the FrameIndex with sp / fp
1392 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
1393 MI.getOperand(FrameRegIdx+1).ChangeToImmediate(Offset);
1398 // Otherwise, pull as much of the immedidate into this ADDri/SUBri
1400 unsigned RotAmt = ARM_AM::getSOImmValRotate(Offset);
1401 unsigned ThisImmVal = Offset & ARM_AM::rotr32(0xFF, RotAmt);
1403 // We will handle these bits from offset, clear them.
1404 Offset &= ~ThisImmVal;
1406 // Get the properly encoded SOImmVal field.
1407 assert(ARM_AM::getSOImmVal(ThisImmVal) != -1 &&
1408 "Bit extraction didn't work?");
1409 MI.getOperand(FrameRegIdx+1).ChangeToImmediate(ThisImmVal);
1411 unsigned ImmIdx = 0;
1413 unsigned NumBits = 0;
1416 case ARMII::AddrMode_i12: {
1417 ImmIdx = FrameRegIdx + 1;
1418 InstrOffs = MI.getOperand(ImmIdx).getImm();
1422 case ARMII::AddrMode2: {
1423 ImmIdx = FrameRegIdx+2;
1424 InstrOffs = ARM_AM::getAM2Offset(MI.getOperand(ImmIdx).getImm());
1425 if (ARM_AM::getAM2Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub)
1430 case ARMII::AddrMode3: {
1431 ImmIdx = FrameRegIdx+2;
1432 InstrOffs = ARM_AM::getAM3Offset(MI.getOperand(ImmIdx).getImm());
1433 if (ARM_AM::getAM3Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub)
1438 case ARMII::AddrMode4:
1439 case ARMII::AddrMode6:
1440 // Can't fold any offset even if it's zero.
1442 case ARMII::AddrMode5: {
1443 ImmIdx = FrameRegIdx+1;
1444 InstrOffs = ARM_AM::getAM5Offset(MI.getOperand(ImmIdx).getImm());
1445 if (ARM_AM::getAM5Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub)
1452 llvm_unreachable("Unsupported addressing mode!");
1456 Offset += InstrOffs * Scale;
1457 assert((Offset & (Scale-1)) == 0 && "Can't encode this offset!");
1463 // Attempt to fold address comp. if opcode has offset bits
1465 // Common case: small offset, fits into instruction.
1466 MachineOperand &ImmOp = MI.getOperand(ImmIdx);
1467 int ImmedOffset = Offset / Scale;
1468 unsigned Mask = (1 << NumBits) - 1;
1469 if ((unsigned)Offset <= Mask * Scale) {
1470 // Replace the FrameIndex with sp
1471 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
1472 // FIXME: When addrmode2 goes away, this will simplify (like the
1473 // T2 version), as the LDR.i12 versions don't need the encoding
1474 // tricks for the offset value.
1476 if (AddrMode == ARMII::AddrMode_i12)
1477 ImmedOffset = -ImmedOffset;
1479 ImmedOffset |= 1 << NumBits;
1481 ImmOp.ChangeToImmediate(ImmedOffset);
1486 // Otherwise, it didn't fit. Pull in what we can to simplify the immed.
1487 ImmedOffset = ImmedOffset & Mask;
1489 if (AddrMode == ARMII::AddrMode_i12)
1490 ImmedOffset = -ImmedOffset;
1492 ImmedOffset |= 1 << NumBits;
1494 ImmOp.ChangeToImmediate(ImmedOffset);
1495 Offset &= ~(Mask*Scale);
1499 Offset = (isSub) ? -Offset : Offset;
1503 bool ARMBaseInstrInfo::
1504 AnalyzeCompare(const MachineInstr *MI, unsigned &SrcReg, int &CmpMask,
1505 int &CmpValue) const {
1506 switch (MI->getOpcode()) {
1510 SrcReg = MI->getOperand(0).getReg();
1512 CmpValue = MI->getOperand(1).getImm();
1516 SrcReg = MI->getOperand(0).getReg();
1517 CmpMask = MI->getOperand(1).getImm();
1525 /// isSuitableForMask - Identify a suitable 'and' instruction that
1526 /// operates on the given source register and applies the same mask
1527 /// as a 'tst' instruction. Provide a limited look-through for copies.
1528 /// When successful, MI will hold the found instruction.
1529 static bool isSuitableForMask(MachineInstr *&MI, unsigned SrcReg,
1530 int CmpMask, bool CommonUse) {
1531 switch (MI->getOpcode()) {
1534 if (CmpMask != MI->getOperand(2).getImm())
1536 if (SrcReg == MI->getOperand(CommonUse ? 1 : 0).getReg())
1540 // Walk down one instruction which is potentially an 'and'.
1541 const MachineInstr &Copy = *MI;
1542 MachineBasicBlock::iterator AND(
1543 llvm::next(MachineBasicBlock::iterator(MI)));
1544 if (AND == MI->getParent()->end()) return false;
1546 return isSuitableForMask(MI, Copy.getOperand(0).getReg(),
1554 /// OptimizeCompareInstr - Convert the instruction supplying the argument to the
1555 /// comparison into one that sets the zero bit in the flags register.
1556 bool ARMBaseInstrInfo::
1557 OptimizeCompareInstr(MachineInstr *CmpInstr, unsigned SrcReg, int CmpMask,
1558 int CmpValue, const MachineRegisterInfo *MRI) const {
1562 MachineRegisterInfo::def_iterator DI = MRI->def_begin(SrcReg);
1563 if (llvm::next(DI) != MRI->def_end())
1564 // Only support one definition.
1567 MachineInstr *MI = &*DI;
1569 // Masked compares sometimes use the same register as the corresponding 'and'.
1570 if (CmpMask != ~0) {
1571 if (!isSuitableForMask(MI, SrcReg, CmpMask, false)) {
1573 for (MachineRegisterInfo::use_iterator UI = MRI->use_begin(SrcReg),
1574 UE = MRI->use_end(); UI != UE; ++UI) {
1575 if (UI->getParent() != CmpInstr->getParent()) continue;
1576 MachineInstr *PotentialAND = &*UI;
1577 if (!isSuitableForMask(PotentialAND, SrcReg, CmpMask, true))
1582 if (!MI) return false;
1586 // Conservatively refuse to convert an instruction which isn't in the same BB
1587 // as the comparison.
1588 if (MI->getParent() != CmpInstr->getParent())
1591 // Check that CPSR isn't set between the comparison instruction and the one we
1593 MachineBasicBlock::const_iterator I = CmpInstr, E = MI,
1594 B = MI->getParent()->begin();
1596 // Early exit if CmpInstr is at the beginning of the BB.
1597 if (I == B) return false;
1600 for (; I != E; --I) {
1601 const MachineInstr &Instr = *I;
1603 for (unsigned IO = 0, EO = Instr.getNumOperands(); IO != EO; ++IO) {
1604 const MachineOperand &MO = Instr.getOperand(IO);
1605 if (!MO.isReg()) continue;
1607 // This instruction modifies or uses CPSR after the one we want to
1608 // change. We can't do this transformation.
1609 if (MO.getReg() == ARM::CPSR)
1614 // The 'and' is below the comparison instruction.
1618 // Set the "zero" bit in CPSR.
1619 switch (MI->getOpcode()) {
1653 case ARM::t2EORri: {
1654 // Scan forward for the use of CPSR, if it's a conditional code requires
1655 // checking of V bit, then this is not safe to do. If we can't find the
1656 // CPSR use (i.e. used in another block), then it's not safe to perform
1657 // the optimization.
1658 bool isSafe = false;
1660 E = MI->getParent()->end();
1661 while (!isSafe && ++I != E) {
1662 const MachineInstr &Instr = *I;
1663 for (unsigned IO = 0, EO = Instr.getNumOperands();
1664 !isSafe && IO != EO; ++IO) {
1665 const MachineOperand &MO = Instr.getOperand(IO);
1666 if (!MO.isReg() || MO.getReg() != ARM::CPSR)
1672 // Condition code is after the operand before CPSR.
1673 ARMCC::CondCodes CC = (ARMCC::CondCodes)Instr.getOperand(IO-1).getImm();
1692 // Toggle the optional operand to CPSR.
1693 MI->getOperand(5).setReg(ARM::CPSR);
1694 MI->getOperand(5).setIsDef(true);
1695 CmpInstr->eraseFromParent();
1703 bool ARMBaseInstrInfo::FoldImmediate(MachineInstr *UseMI,
1704 MachineInstr *DefMI, unsigned Reg,
1705 MachineRegisterInfo *MRI) const {
1706 // Fold large immediates into add, sub, or, xor.
1707 unsigned DefOpc = DefMI->getOpcode();
1708 if (DefOpc != ARM::t2MOVi32imm && DefOpc != ARM::MOVi32imm)
1710 if (!DefMI->getOperand(1).isImm())
1711 // Could be t2MOVi32imm <ga:xx>
1714 if (!MRI->hasOneNonDBGUse(Reg))
1717 unsigned UseOpc = UseMI->getOpcode();
1718 unsigned NewUseOpc = 0;
1719 uint32_t ImmVal = (uint32_t)DefMI->getOperand(1).getImm();
1720 uint32_t SOImmValV1 = 0, SOImmValV2 = 0;
1721 bool Commute = false;
1723 default: return false;
1731 case ARM::t2EORrr: {
1732 Commute = UseMI->getOperand(2).getReg() != Reg;
1739 NewUseOpc = ARM::SUBri;
1745 if (!ARM_AM::isSOImmTwoPartVal(ImmVal))
1747 SOImmValV1 = (uint32_t)ARM_AM::getSOImmTwoPartFirst(ImmVal);
1748 SOImmValV2 = (uint32_t)ARM_AM::getSOImmTwoPartSecond(ImmVal);
1751 case ARM::ADDrr: NewUseOpc = ARM::ADDri; break;
1752 case ARM::ORRrr: NewUseOpc = ARM::ORRri; break;
1753 case ARM::EORrr: NewUseOpc = ARM::EORri; break;
1757 case ARM::t2SUBrr: {
1761 NewUseOpc = ARM::t2SUBri;
1766 case ARM::t2EORrr: {
1767 if (!ARM_AM::isT2SOImmTwoPartVal(ImmVal))
1769 SOImmValV1 = (uint32_t)ARM_AM::getT2SOImmTwoPartFirst(ImmVal);
1770 SOImmValV2 = (uint32_t)ARM_AM::getT2SOImmTwoPartSecond(ImmVal);
1773 case ARM::t2ADDrr: NewUseOpc = ARM::t2ADDri; break;
1774 case ARM::t2ORRrr: NewUseOpc = ARM::t2ORRri; break;
1775 case ARM::t2EORrr: NewUseOpc = ARM::t2EORri; break;
1783 unsigned OpIdx = Commute ? 2 : 1;
1784 unsigned Reg1 = UseMI->getOperand(OpIdx).getReg();
1785 bool isKill = UseMI->getOperand(OpIdx).isKill();
1786 unsigned NewReg = MRI->createVirtualRegister(MRI->getRegClass(Reg));
1787 AddDefaultCC(AddDefaultPred(BuildMI(*UseMI->getParent(),
1788 *UseMI, UseMI->getDebugLoc(),
1789 get(NewUseOpc), NewReg)
1790 .addReg(Reg1, getKillRegState(isKill))
1791 .addImm(SOImmValV1)));
1792 UseMI->setDesc(get(NewUseOpc));
1793 UseMI->getOperand(1).setReg(NewReg);
1794 UseMI->getOperand(1).setIsKill();
1795 UseMI->getOperand(2).ChangeToImmediate(SOImmValV2);
1796 DefMI->eraseFromParent();
1801 ARMBaseInstrInfo::getNumMicroOps(const InstrItineraryData *ItinData,
1802 const MachineInstr *MI) const {
1803 if (!ItinData || ItinData->isEmpty())
1806 const MCInstrDesc &Desc = MI->getDesc();
1807 unsigned Class = Desc.getSchedClass();
1808 unsigned UOps = ItinData->Itineraries[Class].NumMicroOps;
1812 unsigned Opc = MI->getOpcode();
1815 llvm_unreachable("Unexpected multi-uops instruction!");
1821 // The number of uOps for load / store multiple are determined by the number
1824 // On Cortex-A8, each pair of register loads / stores can be scheduled on the
1825 // same cycle. The scheduling for the first load / store must be done
1826 // separately by assuming the the address is not 64-bit aligned.
1828 // On Cortex-A9, the formula is simply (#reg / 2) + (#reg % 2). If the address
1829 // is not 64-bit aligned, then AGU would take an extra cycle. For VFP / NEON
1830 // load / store multiple, the formula is (#reg / 2) + (#reg % 2) + 1.
1832 case ARM::VLDMDIA_UPD:
1833 case ARM::VLDMDDB_UPD:
1835 case ARM::VLDMSIA_UPD:
1836 case ARM::VLDMSDB_UPD:
1838 case ARM::VSTMDIA_UPD:
1839 case ARM::VSTMDDB_UPD:
1841 case ARM::VSTMSIA_UPD:
1842 case ARM::VSTMSDB_UPD: {
1843 unsigned NumRegs = MI->getNumOperands() - Desc.getNumOperands();
1844 return (NumRegs / 2) + (NumRegs % 2) + 1;
1847 case ARM::LDMIA_RET:
1852 case ARM::LDMIA_UPD:
1853 case ARM::LDMDA_UPD:
1854 case ARM::LDMDB_UPD:
1855 case ARM::LDMIB_UPD:
1860 case ARM::STMIA_UPD:
1861 case ARM::STMDA_UPD:
1862 case ARM::STMDB_UPD:
1863 case ARM::STMIB_UPD:
1865 case ARM::tLDMIA_UPD:
1867 case ARM::tSTMIA_UPD:
1871 case ARM::t2LDMIA_RET:
1874 case ARM::t2LDMIA_UPD:
1875 case ARM::t2LDMDB_UPD:
1878 case ARM::t2STMIA_UPD:
1879 case ARM::t2STMDB_UPD: {
1880 unsigned NumRegs = MI->getNumOperands() - Desc.getNumOperands() + 1;
1881 if (Subtarget.isCortexA8()) {
1884 // 4 registers would be issued: 2, 2.
1885 // 5 registers would be issued: 2, 2, 1.
1886 UOps = (NumRegs / 2);
1890 } else if (Subtarget.isCortexA9()) {
1891 UOps = (NumRegs / 2);
1892 // If there are odd number of registers or if it's not 64-bit aligned,
1893 // then it takes an extra AGU (Address Generation Unit) cycle.
1894 if ((NumRegs % 2) ||
1895 !MI->hasOneMemOperand() ||
1896 (*MI->memoperands_begin())->getAlignment() < 8)
1900 // Assume the worst.
1908 ARMBaseInstrInfo::getVLDMDefCycle(const InstrItineraryData *ItinData,
1909 const MCInstrDesc &DefMCID,
1911 unsigned DefIdx, unsigned DefAlign) const {
1912 int RegNo = (int)(DefIdx+1) - DefMCID.getNumOperands() + 1;
1914 // Def is the address writeback.
1915 return ItinData->getOperandCycle(DefClass, DefIdx);
1918 if (Subtarget.isCortexA8()) {
1919 // (regno / 2) + (regno % 2) + 1
1920 DefCycle = RegNo / 2 + 1;
1923 } else if (Subtarget.isCortexA9()) {
1925 bool isSLoad = false;
1927 switch (DefMCID.getOpcode()) {
1930 case ARM::VLDMSIA_UPD:
1931 case ARM::VLDMSDB_UPD:
1936 // If there are odd number of 'S' registers or if it's not 64-bit aligned,
1937 // then it takes an extra cycle.
1938 if ((isSLoad && (RegNo % 2)) || DefAlign < 8)
1941 // Assume the worst.
1942 DefCycle = RegNo + 2;
1949 ARMBaseInstrInfo::getLDMDefCycle(const InstrItineraryData *ItinData,
1950 const MCInstrDesc &DefMCID,
1952 unsigned DefIdx, unsigned DefAlign) const {
1953 int RegNo = (int)(DefIdx+1) - DefMCID.getNumOperands() + 1;
1955 // Def is the address writeback.
1956 return ItinData->getOperandCycle(DefClass, DefIdx);
1959 if (Subtarget.isCortexA8()) {
1960 // 4 registers would be issued: 1, 2, 1.
1961 // 5 registers would be issued: 1, 2, 2.
1962 DefCycle = RegNo / 2;
1965 // Result latency is issue cycle + 2: E2.
1967 } else if (Subtarget.isCortexA9()) {
1968 DefCycle = (RegNo / 2);
1969 // If there are odd number of registers or if it's not 64-bit aligned,
1970 // then it takes an extra AGU (Address Generation Unit) cycle.
1971 if ((RegNo % 2) || DefAlign < 8)
1973 // Result latency is AGU cycles + 2.
1976 // Assume the worst.
1977 DefCycle = RegNo + 2;
1984 ARMBaseInstrInfo::getVSTMUseCycle(const InstrItineraryData *ItinData,
1985 const MCInstrDesc &UseMCID,
1987 unsigned UseIdx, unsigned UseAlign) const {
1988 int RegNo = (int)(UseIdx+1) - UseMCID.getNumOperands() + 1;
1990 return ItinData->getOperandCycle(UseClass, UseIdx);
1993 if (Subtarget.isCortexA8()) {
1994 // (regno / 2) + (regno % 2) + 1
1995 UseCycle = RegNo / 2 + 1;
1998 } else if (Subtarget.isCortexA9()) {
2000 bool isSStore = false;
2002 switch (UseMCID.getOpcode()) {
2005 case ARM::VSTMSIA_UPD:
2006 case ARM::VSTMSDB_UPD:
2011 // If there are odd number of 'S' registers or if it's not 64-bit aligned,
2012 // then it takes an extra cycle.
2013 if ((isSStore && (RegNo % 2)) || UseAlign < 8)
2016 // Assume the worst.
2017 UseCycle = RegNo + 2;
2024 ARMBaseInstrInfo::getSTMUseCycle(const InstrItineraryData *ItinData,
2025 const MCInstrDesc &UseMCID,
2027 unsigned UseIdx, unsigned UseAlign) const {
2028 int RegNo = (int)(UseIdx+1) - UseMCID.getNumOperands() + 1;
2030 return ItinData->getOperandCycle(UseClass, UseIdx);
2033 if (Subtarget.isCortexA8()) {
2034 UseCycle = RegNo / 2;
2039 } else if (Subtarget.isCortexA9()) {
2040 UseCycle = (RegNo / 2);
2041 // If there are odd number of registers or if it's not 64-bit aligned,
2042 // then it takes an extra AGU (Address Generation Unit) cycle.
2043 if ((RegNo % 2) || UseAlign < 8)
2046 // Assume the worst.
2053 ARMBaseInstrInfo::getOperandLatency(const InstrItineraryData *ItinData,
2054 const MCInstrDesc &DefMCID,
2055 unsigned DefIdx, unsigned DefAlign,
2056 const MCInstrDesc &UseMCID,
2057 unsigned UseIdx, unsigned UseAlign) const {
2058 unsigned DefClass = DefMCID.getSchedClass();
2059 unsigned UseClass = UseMCID.getSchedClass();
2061 if (DefIdx < DefMCID.getNumDefs() && UseIdx < UseMCID.getNumOperands())
2062 return ItinData->getOperandLatency(DefClass, DefIdx, UseClass, UseIdx);
2064 // This may be a def / use of a variable_ops instruction, the operand
2065 // latency might be determinable dynamically. Let the target try to
2068 bool LdmBypass = false;
2069 switch (DefMCID.getOpcode()) {
2071 DefCycle = ItinData->getOperandCycle(DefClass, DefIdx);
2075 case ARM::VLDMDIA_UPD:
2076 case ARM::VLDMDDB_UPD:
2078 case ARM::VLDMSIA_UPD:
2079 case ARM::VLDMSDB_UPD:
2080 DefCycle = getVLDMDefCycle(ItinData, DefMCID, DefClass, DefIdx, DefAlign);
2083 case ARM::LDMIA_RET:
2088 case ARM::LDMIA_UPD:
2089 case ARM::LDMDA_UPD:
2090 case ARM::LDMDB_UPD:
2091 case ARM::LDMIB_UPD:
2093 case ARM::tLDMIA_UPD:
2095 case ARM::t2LDMIA_RET:
2098 case ARM::t2LDMIA_UPD:
2099 case ARM::t2LDMDB_UPD:
2101 DefCycle = getLDMDefCycle(ItinData, DefMCID, DefClass, DefIdx, DefAlign);
2106 // We can't seem to determine the result latency of the def, assume it's 2.
2110 switch (UseMCID.getOpcode()) {
2112 UseCycle = ItinData->getOperandCycle(UseClass, UseIdx);
2116 case ARM::VSTMDIA_UPD:
2117 case ARM::VSTMDDB_UPD:
2119 case ARM::VSTMSIA_UPD:
2120 case ARM::VSTMSDB_UPD:
2121 UseCycle = getVSTMUseCycle(ItinData, UseMCID, UseClass, UseIdx, UseAlign);
2128 case ARM::STMIA_UPD:
2129 case ARM::STMDA_UPD:
2130 case ARM::STMDB_UPD:
2131 case ARM::STMIB_UPD:
2133 case ARM::tSTMIA_UPD:
2138 case ARM::t2STMIA_UPD:
2139 case ARM::t2STMDB_UPD:
2140 UseCycle = getSTMUseCycle(ItinData, UseMCID, UseClass, UseIdx, UseAlign);
2145 // Assume it's read in the first stage.
2148 UseCycle = DefCycle - UseCycle + 1;
2151 // It's a variable_ops instruction so we can't use DefIdx here. Just use
2152 // first def operand.
2153 if (ItinData->hasPipelineForwarding(DefClass, DefMCID.getNumOperands()-1,
2156 } else if (ItinData->hasPipelineForwarding(DefClass, DefIdx,
2157 UseClass, UseIdx)) {
2166 ARMBaseInstrInfo::getOperandLatency(const InstrItineraryData *ItinData,
2167 const MachineInstr *DefMI, unsigned DefIdx,
2168 const MachineInstr *UseMI, unsigned UseIdx) const {
2169 if (DefMI->isCopyLike() || DefMI->isInsertSubreg() ||
2170 DefMI->isRegSequence() || DefMI->isImplicitDef())
2173 const MCInstrDesc &DefMCID = DefMI->getDesc();
2174 if (!ItinData || ItinData->isEmpty())
2175 return DefMCID.mayLoad() ? 3 : 1;
2177 const MCInstrDesc &UseMCID = UseMI->getDesc();
2178 const MachineOperand &DefMO = DefMI->getOperand(DefIdx);
2179 if (DefMO.getReg() == ARM::CPSR) {
2180 if (DefMI->getOpcode() == ARM::FMSTAT) {
2181 // fpscr -> cpsr stalls over 20 cycles on A8 (and earlier?)
2182 return Subtarget.isCortexA9() ? 1 : 20;
2185 // CPSR set and branch can be paired in the same cycle.
2186 if (UseMCID.isBranch())
2190 unsigned DefAlign = DefMI->hasOneMemOperand()
2191 ? (*DefMI->memoperands_begin())->getAlignment() : 0;
2192 unsigned UseAlign = UseMI->hasOneMemOperand()
2193 ? (*UseMI->memoperands_begin())->getAlignment() : 0;
2194 int Latency = getOperandLatency(ItinData, DefMCID, DefIdx, DefAlign,
2195 UseMCID, UseIdx, UseAlign);
2198 (Subtarget.isCortexA8() || Subtarget.isCortexA9())) {
2199 // FIXME: Shifter op hack: no shift (i.e. [r +/- r]) or [r + r << 2]
2200 // variants are one cycle cheaper.
2201 switch (DefMCID.getOpcode()) {
2205 unsigned ShOpVal = DefMI->getOperand(3).getImm();
2206 unsigned ShImm = ARM_AM::getAM2Offset(ShOpVal);
2208 (ShImm == 2 && ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl))
2215 case ARM::t2LDRSHs: {
2216 // Thumb2 mode: lsl only.
2217 unsigned ShAmt = DefMI->getOperand(3).getImm();
2218 if (ShAmt == 0 || ShAmt == 2)
2225 if (DefAlign < 8 && Subtarget.isCortexA9())
2226 switch (DefMCID.getOpcode()) {
2232 case ARM::VLD1q8_UPD:
2233 case ARM::VLD1q16_UPD:
2234 case ARM::VLD1q32_UPD:
2235 case ARM::VLD1q64_UPD:
2242 case ARM::VLD2d8_UPD:
2243 case ARM::VLD2d16_UPD:
2244 case ARM::VLD2d32_UPD:
2245 case ARM::VLD2q8_UPD:
2246 case ARM::VLD2q16_UPD:
2247 case ARM::VLD2q32_UPD:
2252 case ARM::VLD3d8_UPD:
2253 case ARM::VLD3d16_UPD:
2254 case ARM::VLD3d32_UPD:
2255 case ARM::VLD1d64T_UPD:
2256 case ARM::VLD3q8_UPD:
2257 case ARM::VLD3q16_UPD:
2258 case ARM::VLD3q32_UPD:
2263 case ARM::VLD4d8_UPD:
2264 case ARM::VLD4d16_UPD:
2265 case ARM::VLD4d32_UPD:
2266 case ARM::VLD1d64Q_UPD:
2267 case ARM::VLD4q8_UPD:
2268 case ARM::VLD4q16_UPD:
2269 case ARM::VLD4q32_UPD:
2270 case ARM::VLD1DUPq8:
2271 case ARM::VLD1DUPq16:
2272 case ARM::VLD1DUPq32:
2273 case ARM::VLD1DUPq8_UPD:
2274 case ARM::VLD1DUPq16_UPD:
2275 case ARM::VLD1DUPq32_UPD:
2276 case ARM::VLD2DUPd8:
2277 case ARM::VLD2DUPd16:
2278 case ARM::VLD2DUPd32:
2279 case ARM::VLD2DUPd8_UPD:
2280 case ARM::VLD2DUPd16_UPD:
2281 case ARM::VLD2DUPd32_UPD:
2282 case ARM::VLD4DUPd8:
2283 case ARM::VLD4DUPd16:
2284 case ARM::VLD4DUPd32:
2285 case ARM::VLD4DUPd8_UPD:
2286 case ARM::VLD4DUPd16_UPD:
2287 case ARM::VLD4DUPd32_UPD:
2289 case ARM::VLD1LNd16:
2290 case ARM::VLD1LNd32:
2291 case ARM::VLD1LNd8_UPD:
2292 case ARM::VLD1LNd16_UPD:
2293 case ARM::VLD1LNd32_UPD:
2295 case ARM::VLD2LNd16:
2296 case ARM::VLD2LNd32:
2297 case ARM::VLD2LNq16:
2298 case ARM::VLD2LNq32:
2299 case ARM::VLD2LNd8_UPD:
2300 case ARM::VLD2LNd16_UPD:
2301 case ARM::VLD2LNd32_UPD:
2302 case ARM::VLD2LNq16_UPD:
2303 case ARM::VLD2LNq32_UPD:
2305 case ARM::VLD4LNd16:
2306 case ARM::VLD4LNd32:
2307 case ARM::VLD4LNq16:
2308 case ARM::VLD4LNq32:
2309 case ARM::VLD4LNd8_UPD:
2310 case ARM::VLD4LNd16_UPD:
2311 case ARM::VLD4LNd32_UPD:
2312 case ARM::VLD4LNq16_UPD:
2313 case ARM::VLD4LNq32_UPD:
2314 // If the address is not 64-bit aligned, the latencies of these
2315 // instructions increases by one.
2324 ARMBaseInstrInfo::getOperandLatency(const InstrItineraryData *ItinData,
2325 SDNode *DefNode, unsigned DefIdx,
2326 SDNode *UseNode, unsigned UseIdx) const {
2327 if (!DefNode->isMachineOpcode())
2330 const MCInstrDesc &DefMCID = get(DefNode->getMachineOpcode());
2332 if (isZeroCost(DefMCID.Opcode))
2335 if (!ItinData || ItinData->isEmpty())
2336 return DefMCID.mayLoad() ? 3 : 1;
2338 if (!UseNode->isMachineOpcode()) {
2339 int Latency = ItinData->getOperandCycle(DefMCID.getSchedClass(), DefIdx);
2340 if (Subtarget.isCortexA9())
2341 return Latency <= 2 ? 1 : Latency - 1;
2343 return Latency <= 3 ? 1 : Latency - 2;
2346 const MCInstrDesc &UseMCID = get(UseNode->getMachineOpcode());
2347 const MachineSDNode *DefMN = dyn_cast<MachineSDNode>(DefNode);
2348 unsigned DefAlign = !DefMN->memoperands_empty()
2349 ? (*DefMN->memoperands_begin())->getAlignment() : 0;
2350 const MachineSDNode *UseMN = dyn_cast<MachineSDNode>(UseNode);
2351 unsigned UseAlign = !UseMN->memoperands_empty()
2352 ? (*UseMN->memoperands_begin())->getAlignment() : 0;
2353 int Latency = getOperandLatency(ItinData, DefMCID, DefIdx, DefAlign,
2354 UseMCID, UseIdx, UseAlign);
2357 (Subtarget.isCortexA8() || Subtarget.isCortexA9())) {
2358 // FIXME: Shifter op hack: no shift (i.e. [r +/- r]) or [r + r << 2]
2359 // variants are one cycle cheaper.
2360 switch (DefMCID.getOpcode()) {
2365 cast<ConstantSDNode>(DefNode->getOperand(2))->getZExtValue();
2366 unsigned ShImm = ARM_AM::getAM2Offset(ShOpVal);
2368 (ShImm == 2 && ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl))
2375 case ARM::t2LDRSHs: {
2376 // Thumb2 mode: lsl only.
2378 cast<ConstantSDNode>(DefNode->getOperand(2))->getZExtValue();
2379 if (ShAmt == 0 || ShAmt == 2)
2386 if (DefAlign < 8 && Subtarget.isCortexA9())
2387 switch (DefMCID.getOpcode()) {
2389 case ARM::VLD1q8Pseudo:
2390 case ARM::VLD1q16Pseudo:
2391 case ARM::VLD1q32Pseudo:
2392 case ARM::VLD1q64Pseudo:
2393 case ARM::VLD1q8Pseudo_UPD:
2394 case ARM::VLD1q16Pseudo_UPD:
2395 case ARM::VLD1q32Pseudo_UPD:
2396 case ARM::VLD1q64Pseudo_UPD:
2397 case ARM::VLD2d8Pseudo:
2398 case ARM::VLD2d16Pseudo:
2399 case ARM::VLD2d32Pseudo:
2400 case ARM::VLD2q8Pseudo:
2401 case ARM::VLD2q16Pseudo:
2402 case ARM::VLD2q32Pseudo:
2403 case ARM::VLD2d8Pseudo_UPD:
2404 case ARM::VLD2d16Pseudo_UPD:
2405 case ARM::VLD2d32Pseudo_UPD:
2406 case ARM::VLD2q8Pseudo_UPD:
2407 case ARM::VLD2q16Pseudo_UPD:
2408 case ARM::VLD2q32Pseudo_UPD:
2409 case ARM::VLD3d8Pseudo:
2410 case ARM::VLD3d16Pseudo:
2411 case ARM::VLD3d32Pseudo:
2412 case ARM::VLD1d64TPseudo:
2413 case ARM::VLD3d8Pseudo_UPD:
2414 case ARM::VLD3d16Pseudo_UPD:
2415 case ARM::VLD3d32Pseudo_UPD:
2416 case ARM::VLD1d64TPseudo_UPD:
2417 case ARM::VLD3q8Pseudo_UPD:
2418 case ARM::VLD3q16Pseudo_UPD:
2419 case ARM::VLD3q32Pseudo_UPD:
2420 case ARM::VLD3q8oddPseudo:
2421 case ARM::VLD3q16oddPseudo:
2422 case ARM::VLD3q32oddPseudo:
2423 case ARM::VLD3q8oddPseudo_UPD:
2424 case ARM::VLD3q16oddPseudo_UPD:
2425 case ARM::VLD3q32oddPseudo_UPD:
2426 case ARM::VLD4d8Pseudo:
2427 case ARM::VLD4d16Pseudo:
2428 case ARM::VLD4d32Pseudo:
2429 case ARM::VLD1d64QPseudo:
2430 case ARM::VLD4d8Pseudo_UPD:
2431 case ARM::VLD4d16Pseudo_UPD:
2432 case ARM::VLD4d32Pseudo_UPD:
2433 case ARM::VLD1d64QPseudo_UPD:
2434 case ARM::VLD4q8Pseudo_UPD:
2435 case ARM::VLD4q16Pseudo_UPD:
2436 case ARM::VLD4q32Pseudo_UPD:
2437 case ARM::VLD4q8oddPseudo:
2438 case ARM::VLD4q16oddPseudo:
2439 case ARM::VLD4q32oddPseudo:
2440 case ARM::VLD4q8oddPseudo_UPD:
2441 case ARM::VLD4q16oddPseudo_UPD:
2442 case ARM::VLD4q32oddPseudo_UPD:
2443 case ARM::VLD1DUPq8Pseudo:
2444 case ARM::VLD1DUPq16Pseudo:
2445 case ARM::VLD1DUPq32Pseudo:
2446 case ARM::VLD1DUPq8Pseudo_UPD:
2447 case ARM::VLD1DUPq16Pseudo_UPD:
2448 case ARM::VLD1DUPq32Pseudo_UPD:
2449 case ARM::VLD2DUPd8Pseudo:
2450 case ARM::VLD2DUPd16Pseudo:
2451 case ARM::VLD2DUPd32Pseudo:
2452 case ARM::VLD2DUPd8Pseudo_UPD:
2453 case ARM::VLD2DUPd16Pseudo_UPD:
2454 case ARM::VLD2DUPd32Pseudo_UPD:
2455 case ARM::VLD4DUPd8Pseudo:
2456 case ARM::VLD4DUPd16Pseudo:
2457 case ARM::VLD4DUPd32Pseudo:
2458 case ARM::VLD4DUPd8Pseudo_UPD:
2459 case ARM::VLD4DUPd16Pseudo_UPD:
2460 case ARM::VLD4DUPd32Pseudo_UPD:
2461 case ARM::VLD1LNq8Pseudo:
2462 case ARM::VLD1LNq16Pseudo:
2463 case ARM::VLD1LNq32Pseudo:
2464 case ARM::VLD1LNq8Pseudo_UPD:
2465 case ARM::VLD1LNq16Pseudo_UPD:
2466 case ARM::VLD1LNq32Pseudo_UPD:
2467 case ARM::VLD2LNd8Pseudo:
2468 case ARM::VLD2LNd16Pseudo:
2469 case ARM::VLD2LNd32Pseudo:
2470 case ARM::VLD2LNq16Pseudo:
2471 case ARM::VLD2LNq32Pseudo:
2472 case ARM::VLD2LNd8Pseudo_UPD:
2473 case ARM::VLD2LNd16Pseudo_UPD:
2474 case ARM::VLD2LNd32Pseudo_UPD:
2475 case ARM::VLD2LNq16Pseudo_UPD:
2476 case ARM::VLD2LNq32Pseudo_UPD:
2477 case ARM::VLD4LNd8Pseudo:
2478 case ARM::VLD4LNd16Pseudo:
2479 case ARM::VLD4LNd32Pseudo:
2480 case ARM::VLD4LNq16Pseudo:
2481 case ARM::VLD4LNq32Pseudo:
2482 case ARM::VLD4LNd8Pseudo_UPD:
2483 case ARM::VLD4LNd16Pseudo_UPD:
2484 case ARM::VLD4LNd32Pseudo_UPD:
2485 case ARM::VLD4LNq16Pseudo_UPD:
2486 case ARM::VLD4LNq32Pseudo_UPD:
2487 // If the address is not 64-bit aligned, the latencies of these
2488 // instructions increases by one.
2496 int ARMBaseInstrInfo::getInstrLatency(const InstrItineraryData *ItinData,
2497 const MachineInstr *MI,
2498 unsigned *PredCost) const {
2499 if (MI->isCopyLike() || MI->isInsertSubreg() ||
2500 MI->isRegSequence() || MI->isImplicitDef())
2503 if (!ItinData || ItinData->isEmpty())
2506 const MCInstrDesc &MCID = MI->getDesc();
2507 unsigned Class = MCID.getSchedClass();
2508 unsigned UOps = ItinData->Itineraries[Class].NumMicroOps;
2509 if (PredCost && MCID.hasImplicitDefOfPhysReg(ARM::CPSR))
2510 // When predicated, CPSR is an additional source operand for CPSR updating
2511 // instructions, this apparently increases their latencies.
2514 return ItinData->getStageLatency(Class);
2515 return getNumMicroOps(ItinData, MI);
2518 int ARMBaseInstrInfo::getInstrLatency(const InstrItineraryData *ItinData,
2519 SDNode *Node) const {
2520 if (!Node->isMachineOpcode())
2523 if (!ItinData || ItinData->isEmpty())
2526 unsigned Opcode = Node->getMachineOpcode();
2529 return ItinData->getStageLatency(get(Opcode).getSchedClass());
2536 bool ARMBaseInstrInfo::
2537 hasHighOperandLatency(const InstrItineraryData *ItinData,
2538 const MachineRegisterInfo *MRI,
2539 const MachineInstr *DefMI, unsigned DefIdx,
2540 const MachineInstr *UseMI, unsigned UseIdx) const {
2541 unsigned DDomain = DefMI->getDesc().TSFlags & ARMII::DomainMask;
2542 unsigned UDomain = UseMI->getDesc().TSFlags & ARMII::DomainMask;
2543 if (Subtarget.isCortexA8() &&
2544 (DDomain == ARMII::DomainVFP || UDomain == ARMII::DomainVFP))
2545 // CortexA8 VFP instructions are not pipelined.
2548 // Hoist VFP / NEON instructions with 4 or higher latency.
2549 int Latency = getOperandLatency(ItinData, DefMI, DefIdx, UseMI, UseIdx);
2552 return DDomain == ARMII::DomainVFP || DDomain == ARMII::DomainNEON ||
2553 UDomain == ARMII::DomainVFP || UDomain == ARMII::DomainNEON;
2556 bool ARMBaseInstrInfo::
2557 hasLowDefLatency(const InstrItineraryData *ItinData,
2558 const MachineInstr *DefMI, unsigned DefIdx) const {
2559 if (!ItinData || ItinData->isEmpty())
2562 unsigned DDomain = DefMI->getDesc().TSFlags & ARMII::DomainMask;
2563 if (DDomain == ARMII::DomainGeneral) {
2564 unsigned DefClass = DefMI->getDesc().getSchedClass();
2565 int DefCycle = ItinData->getOperandCycle(DefClass, DefIdx);
2566 return (DefCycle != -1 && DefCycle <= 2);
2572 ARMBaseInstrInfo::isFpMLxInstruction(unsigned Opcode, unsigned &MulOpc,
2573 unsigned &AddSubOpc,
2574 bool &NegAcc, bool &HasLane) const {
2575 DenseMap<unsigned, unsigned>::const_iterator I = MLxEntryMap.find(Opcode);
2576 if (I == MLxEntryMap.end())
2579 const ARM_MLxEntry &Entry = ARM_MLxTable[I->second];
2580 MulOpc = Entry.MulOpc;
2581 AddSubOpc = Entry.AddSubOpc;
2582 NegAcc = Entry.NegAcc;
2583 HasLane = Entry.HasLane;