1 //===- ARMBaseInstrInfo.cpp - ARM Instruction Information -------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Base ARM implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "ARMBaseInstrInfo.h"
16 #include "ARMAddressingModes.h"
17 #include "ARMConstantPoolValue.h"
18 #include "ARMGenInstrInfo.inc"
19 #include "ARMMachineFunctionInfo.h"
20 #include "ARMRegisterInfo.h"
21 #include "llvm/Constants.h"
22 #include "llvm/Function.h"
23 #include "llvm/GlobalValue.h"
24 #include "llvm/ADT/STLExtras.h"
25 #include "llvm/CodeGen/LiveVariables.h"
26 #include "llvm/CodeGen/MachineConstantPool.h"
27 #include "llvm/CodeGen/MachineFrameInfo.h"
28 #include "llvm/CodeGen/MachineInstrBuilder.h"
29 #include "llvm/CodeGen/MachineJumpTableInfo.h"
30 #include "llvm/CodeGen/MachineMemOperand.h"
31 #include "llvm/CodeGen/PseudoSourceValue.h"
32 #include "llvm/MC/MCAsmInfo.h"
33 #include "llvm/Support/CommandLine.h"
34 #include "llvm/Support/Debug.h"
35 #include "llvm/Support/ErrorHandling.h"
39 EnableARM3Addr("enable-arm-3-addr-conv", cl::Hidden,
40 cl::desc("Enable ARM 2-addr to 3-addr conv"));
42 ARMBaseInstrInfo::ARMBaseInstrInfo(const ARMSubtarget& STI)
43 : TargetInstrInfoImpl(ARMInsts, array_lengthof(ARMInsts)),
48 ARMBaseInstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
49 MachineBasicBlock::iterator &MBBI,
50 LiveVariables *LV) const {
51 // FIXME: Thumb2 support.
56 MachineInstr *MI = MBBI;
57 MachineFunction &MF = *MI->getParent()->getParent();
58 unsigned TSFlags = MI->getDesc().TSFlags;
60 switch ((TSFlags & ARMII::IndexModeMask) >> ARMII::IndexModeShift) {
62 case ARMII::IndexModePre:
65 case ARMII::IndexModePost:
69 // Try splitting an indexed load/store to an un-indexed one plus an add/sub
71 unsigned MemOpc = getUnindexedOpcode(MI->getOpcode());
75 MachineInstr *UpdateMI = NULL;
76 MachineInstr *MemMI = NULL;
77 unsigned AddrMode = (TSFlags & ARMII::AddrModeMask);
78 const TargetInstrDesc &TID = MI->getDesc();
79 unsigned NumOps = TID.getNumOperands();
80 bool isLoad = !TID.mayStore();
81 const MachineOperand &WB = isLoad ? MI->getOperand(1) : MI->getOperand(0);
82 const MachineOperand &Base = MI->getOperand(2);
83 const MachineOperand &Offset = MI->getOperand(NumOps-3);
84 unsigned WBReg = WB.getReg();
85 unsigned BaseReg = Base.getReg();
86 unsigned OffReg = Offset.getReg();
87 unsigned OffImm = MI->getOperand(NumOps-2).getImm();
88 ARMCC::CondCodes Pred = (ARMCC::CondCodes)MI->getOperand(NumOps-1).getImm();
91 assert(false && "Unknown indexed op!");
93 case ARMII::AddrMode2: {
94 bool isSub = ARM_AM::getAM2Op(OffImm) == ARM_AM::sub;
95 unsigned Amt = ARM_AM::getAM2Offset(OffImm);
97 if (ARM_AM::getSOImmVal(Amt) == -1)
98 // Can't encode it in a so_imm operand. This transformation will
99 // add more than 1 instruction. Abandon!
101 UpdateMI = BuildMI(MF, MI->getDebugLoc(),
102 get(isSub ? ARM::SUBri : ARM::ADDri), WBReg)
103 .addReg(BaseReg).addImm(Amt)
104 .addImm(Pred).addReg(0).addReg(0);
105 } else if (Amt != 0) {
106 ARM_AM::ShiftOpc ShOpc = ARM_AM::getAM2ShiftOpc(OffImm);
107 unsigned SOOpc = ARM_AM::getSORegOpc(ShOpc, Amt);
108 UpdateMI = BuildMI(MF, MI->getDebugLoc(),
109 get(isSub ? ARM::SUBrs : ARM::ADDrs), WBReg)
110 .addReg(BaseReg).addReg(OffReg).addReg(0).addImm(SOOpc)
111 .addImm(Pred).addReg(0).addReg(0);
113 UpdateMI = BuildMI(MF, MI->getDebugLoc(),
114 get(isSub ? ARM::SUBrr : ARM::ADDrr), WBReg)
115 .addReg(BaseReg).addReg(OffReg)
116 .addImm(Pred).addReg(0).addReg(0);
119 case ARMII::AddrMode3 : {
120 bool isSub = ARM_AM::getAM3Op(OffImm) == ARM_AM::sub;
121 unsigned Amt = ARM_AM::getAM3Offset(OffImm);
123 // Immediate is 8-bits. It's guaranteed to fit in a so_imm operand.
124 UpdateMI = BuildMI(MF, MI->getDebugLoc(),
125 get(isSub ? ARM::SUBri : ARM::ADDri), WBReg)
126 .addReg(BaseReg).addImm(Amt)
127 .addImm(Pred).addReg(0).addReg(0);
129 UpdateMI = BuildMI(MF, MI->getDebugLoc(),
130 get(isSub ? ARM::SUBrr : ARM::ADDrr), WBReg)
131 .addReg(BaseReg).addReg(OffReg)
132 .addImm(Pred).addReg(0).addReg(0);
137 std::vector<MachineInstr*> NewMIs;
140 MemMI = BuildMI(MF, MI->getDebugLoc(),
141 get(MemOpc), MI->getOperand(0).getReg())
142 .addReg(WBReg).addReg(0).addImm(0).addImm(Pred);
144 MemMI = BuildMI(MF, MI->getDebugLoc(),
145 get(MemOpc)).addReg(MI->getOperand(1).getReg())
146 .addReg(WBReg).addReg(0).addImm(0).addImm(Pred);
147 NewMIs.push_back(MemMI);
148 NewMIs.push_back(UpdateMI);
151 MemMI = BuildMI(MF, MI->getDebugLoc(),
152 get(MemOpc), MI->getOperand(0).getReg())
153 .addReg(BaseReg).addReg(0).addImm(0).addImm(Pred);
155 MemMI = BuildMI(MF, MI->getDebugLoc(),
156 get(MemOpc)).addReg(MI->getOperand(1).getReg())
157 .addReg(BaseReg).addReg(0).addImm(0).addImm(Pred);
159 UpdateMI->getOperand(0).setIsDead();
160 NewMIs.push_back(UpdateMI);
161 NewMIs.push_back(MemMI);
164 // Transfer LiveVariables states, kill / dead info.
166 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
167 MachineOperand &MO = MI->getOperand(i);
168 if (MO.isReg() && MO.getReg() &&
169 TargetRegisterInfo::isVirtualRegister(MO.getReg())) {
170 unsigned Reg = MO.getReg();
172 LiveVariables::VarInfo &VI = LV->getVarInfo(Reg);
174 MachineInstr *NewMI = (Reg == WBReg) ? UpdateMI : MemMI;
176 LV->addVirtualRegisterDead(Reg, NewMI);
178 if (MO.isUse() && MO.isKill()) {
179 for (unsigned j = 0; j < 2; ++j) {
180 // Look at the two new MI's in reverse order.
181 MachineInstr *NewMI = NewMIs[j];
182 if (!NewMI->readsRegister(Reg))
184 LV->addVirtualRegisterKilled(Reg, NewMI);
185 if (VI.removeKill(MI))
186 VI.Kills.push_back(NewMI);
194 MFI->insert(MBBI, NewMIs[1]);
195 MFI->insert(MBBI, NewMIs[0]);
201 ARMBaseInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB,
202 MachineBasicBlock *&FBB,
203 SmallVectorImpl<MachineOperand> &Cond,
204 bool AllowModify) const {
205 // If the block has no terminators, it just falls into the block after it.
206 MachineBasicBlock::iterator I = MBB.end();
207 if (I == MBB.begin() || !isUnpredicatedTerminator(--I))
210 // Get the last instruction in the block.
211 MachineInstr *LastInst = I;
213 // If there is only one terminator instruction, process it.
214 unsigned LastOpc = LastInst->getOpcode();
215 if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) {
216 if (isUncondBranchOpcode(LastOpc)) {
217 TBB = LastInst->getOperand(0).getMBB();
220 if (isCondBranchOpcode(LastOpc)) {
221 // Block ends with fall-through condbranch.
222 TBB = LastInst->getOperand(0).getMBB();
223 Cond.push_back(LastInst->getOperand(1));
224 Cond.push_back(LastInst->getOperand(2));
227 return true; // Can't handle indirect branch.
230 // Get the instruction before it if it is a terminator.
231 MachineInstr *SecondLastInst = I;
233 // If there are three terminators, we don't know what sort of block this is.
234 if (SecondLastInst && I != MBB.begin() && isUnpredicatedTerminator(--I))
237 // If the block ends with a B and a Bcc, handle it.
238 unsigned SecondLastOpc = SecondLastInst->getOpcode();
239 if (isCondBranchOpcode(SecondLastOpc) && isUncondBranchOpcode(LastOpc)) {
240 TBB = SecondLastInst->getOperand(0).getMBB();
241 Cond.push_back(SecondLastInst->getOperand(1));
242 Cond.push_back(SecondLastInst->getOperand(2));
243 FBB = LastInst->getOperand(0).getMBB();
247 // If the block ends with two unconditional branches, handle it. The second
248 // one is not executed, so remove it.
249 if (isUncondBranchOpcode(SecondLastOpc) && isUncondBranchOpcode(LastOpc)) {
250 TBB = SecondLastInst->getOperand(0).getMBB();
253 I->eraseFromParent();
257 // ...likewise if it ends with a branch table followed by an unconditional
258 // branch. The branch folder can create these, and we must get rid of them for
259 // correctness of Thumb constant islands.
260 if ((isJumpTableBranchOpcode(SecondLastOpc) ||
261 isIndirectBranchOpcode(SecondLastOpc)) &&
262 isUncondBranchOpcode(LastOpc)) {
265 I->eraseFromParent();
269 // Otherwise, can't handle this.
274 unsigned ARMBaseInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
275 MachineBasicBlock::iterator I = MBB.end();
276 if (I == MBB.begin()) return 0;
278 if (!isUncondBranchOpcode(I->getOpcode()) &&
279 !isCondBranchOpcode(I->getOpcode()))
282 // Remove the branch.
283 I->eraseFromParent();
287 if (I == MBB.begin()) return 1;
289 if (!isCondBranchOpcode(I->getOpcode()))
292 // Remove the branch.
293 I->eraseFromParent();
298 ARMBaseInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
299 MachineBasicBlock *FBB,
300 const SmallVectorImpl<MachineOperand> &Cond) const {
301 // FIXME this should probably have a DebugLoc argument
302 DebugLoc dl = DebugLoc::getUnknownLoc();
304 ARMFunctionInfo *AFI = MBB.getParent()->getInfo<ARMFunctionInfo>();
305 int BOpc = !AFI->isThumbFunction()
306 ? ARM::B : (AFI->isThumb2Function() ? ARM::t2B : ARM::tB);
307 int BccOpc = !AFI->isThumbFunction()
308 ? ARM::Bcc : (AFI->isThumb2Function() ? ARM::t2Bcc : ARM::tBcc);
310 // Shouldn't be a fall through.
311 assert(TBB && "InsertBranch must not be told to insert a fallthrough");
312 assert((Cond.size() == 2 || Cond.size() == 0) &&
313 "ARM branch conditions have two components!");
316 if (Cond.empty()) // Unconditional branch?
317 BuildMI(&MBB, dl, get(BOpc)).addMBB(TBB);
319 BuildMI(&MBB, dl, get(BccOpc)).addMBB(TBB)
320 .addImm(Cond[0].getImm()).addReg(Cond[1].getReg());
324 // Two-way conditional branch.
325 BuildMI(&MBB, dl, get(BccOpc)).addMBB(TBB)
326 .addImm(Cond[0].getImm()).addReg(Cond[1].getReg());
327 BuildMI(&MBB, dl, get(BOpc)).addMBB(FBB);
331 bool ARMBaseInstrInfo::
332 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
333 ARMCC::CondCodes CC = (ARMCC::CondCodes)(int)Cond[0].getImm();
334 Cond[0].setImm(ARMCC::getOppositeCondition(CC));
338 bool ARMBaseInstrInfo::
339 PredicateInstruction(MachineInstr *MI,
340 const SmallVectorImpl<MachineOperand> &Pred) const {
341 unsigned Opc = MI->getOpcode();
342 if (isUncondBranchOpcode(Opc)) {
343 MI->setDesc(get(getMatchingCondBranchOpcode(Opc)));
344 MI->addOperand(MachineOperand::CreateImm(Pred[0].getImm()));
345 MI->addOperand(MachineOperand::CreateReg(Pred[1].getReg(), false));
349 int PIdx = MI->findFirstPredOperandIdx();
351 MachineOperand &PMO = MI->getOperand(PIdx);
352 PMO.setImm(Pred[0].getImm());
353 MI->getOperand(PIdx+1).setReg(Pred[1].getReg());
359 bool ARMBaseInstrInfo::
360 SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1,
361 const SmallVectorImpl<MachineOperand> &Pred2) const {
362 if (Pred1.size() > 2 || Pred2.size() > 2)
365 ARMCC::CondCodes CC1 = (ARMCC::CondCodes)Pred1[0].getImm();
366 ARMCC::CondCodes CC2 = (ARMCC::CondCodes)Pred2[0].getImm();
376 return CC2 == ARMCC::HI;
378 return CC2 == ARMCC::LO || CC2 == ARMCC::EQ;
380 return CC2 == ARMCC::GT;
382 return CC2 == ARMCC::LT;
386 bool ARMBaseInstrInfo::DefinesPredicate(MachineInstr *MI,
387 std::vector<MachineOperand> &Pred) const {
388 // FIXME: This confuses implicit_def with optional CPSR def.
389 const TargetInstrDesc &TID = MI->getDesc();
390 if (!TID.getImplicitDefs() && !TID.hasOptionalDef())
394 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
395 const MachineOperand &MO = MI->getOperand(i);
396 if (MO.isReg() && MO.getReg() == ARM::CPSR) {
405 /// isPredicable - Return true if the specified instruction can be predicated.
406 /// By default, this returns true for every instruction with a
407 /// PredicateOperand.
408 bool ARMBaseInstrInfo::isPredicable(MachineInstr *MI) const {
409 const TargetInstrDesc &TID = MI->getDesc();
410 if (!TID.isPredicable())
413 if ((TID.TSFlags & ARMII::DomainMask) == ARMII::DomainNEON) {
414 ARMFunctionInfo *AFI =
415 MI->getParent()->getParent()->getInfo<ARMFunctionInfo>();
416 return AFI->isThumb2Function();
421 /// FIXME: Works around a gcc miscompilation with -fstrict-aliasing
422 static unsigned getNumJTEntries(const std::vector<MachineJumpTableEntry> &JT,
423 unsigned JTI) DISABLE_INLINE;
424 static unsigned getNumJTEntries(const std::vector<MachineJumpTableEntry> &JT,
426 return JT[JTI].MBBs.size();
429 /// GetInstSize - Return the size of the specified MachineInstr.
431 unsigned ARMBaseInstrInfo::GetInstSizeInBytes(const MachineInstr *MI) const {
432 const MachineBasicBlock &MBB = *MI->getParent();
433 const MachineFunction *MF = MBB.getParent();
434 const MCAsmInfo *MAI = MF->getTarget().getMCAsmInfo();
436 // Basic size info comes from the TSFlags field.
437 const TargetInstrDesc &TID = MI->getDesc();
438 unsigned TSFlags = TID.TSFlags;
440 unsigned Opc = MI->getOpcode();
441 switch ((TSFlags & ARMII::SizeMask) >> ARMII::SizeShift) {
443 // If this machine instr is an inline asm, measure it.
444 if (MI->getOpcode() == ARM::INLINEASM)
445 return getInlineAsmLength(MI->getOperand(0).getSymbolName(), *MAI);
450 llvm_unreachable("Unknown or unset size field for instr!");
451 case TargetInstrInfo::IMPLICIT_DEF:
452 case TargetInstrInfo::KILL:
453 case TargetInstrInfo::DBG_LABEL:
454 case TargetInstrInfo::EH_LABEL:
459 case ARMII::Size8Bytes: return 8; // ARM instruction x 2.
460 case ARMII::Size4Bytes: return 4; // ARM / Thumb2 instruction.
461 case ARMII::Size2Bytes: return 2; // Thumb1 instruction.
462 case ARMII::SizeSpecial: {
464 case ARM::CONSTPOOL_ENTRY:
465 // If this machine instr is a constant pool entry, its size is recorded as
467 return MI->getOperand(2).getImm();
468 case ARM::Int_eh_sjlj_setjmp:
470 case ARM::t2Int_eh_sjlj_setjmp:
479 // These are jumptable branches, i.e. a branch followed by an inlined
480 // jumptable. The size is 4 + 4 * number of entries. For TBB, each
481 // entry is one byte; TBH two byte each.
482 unsigned EntrySize = (Opc == ARM::t2TBB)
483 ? 1 : ((Opc == ARM::t2TBH) ? 2 : 4);
484 unsigned NumOps = TID.getNumOperands();
485 MachineOperand JTOP =
486 MI->getOperand(NumOps - (TID.isPredicable() ? 3 : 2));
487 unsigned JTI = JTOP.getIndex();
488 const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
489 const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
490 assert(JTI < JT.size());
491 // Thumb instructions are 2 byte aligned, but JT entries are 4 byte
492 // 4 aligned. The assembler / linker may add 2 byte padding just before
493 // the JT entries. The size does not include this padding; the
494 // constant islands pass does separate bookkeeping for it.
495 // FIXME: If we know the size of the function is less than (1 << 16) *2
496 // bytes, we can use 16-bit entries instead. Then there won't be an
498 unsigned InstSize = (Opc == ARM::tBR_JTr || Opc == ARM::t2BR_JT) ? 2 : 4;
499 unsigned NumEntries = getNumJTEntries(JT, JTI);
500 if (Opc == ARM::t2TBB && (NumEntries & 1))
501 // Make sure the instruction that follows TBB is 2-byte aligned.
502 // FIXME: Constant island pass should insert an "ALIGN" instruction
505 return NumEntries * EntrySize + InstSize;
508 // Otherwise, pseudo-instruction sizes are zero.
513 return 0; // Not reached
516 /// Return true if the instruction is a register to register move and
517 /// leave the source and dest operands in the passed parameters.
520 ARMBaseInstrInfo::isMoveInstr(const MachineInstr &MI,
521 unsigned &SrcReg, unsigned &DstReg,
522 unsigned& SrcSubIdx, unsigned& DstSubIdx) const {
523 SrcSubIdx = DstSubIdx = 0; // No sub-registers.
525 switch (MI.getOpcode()) {
531 SrcReg = MI.getOperand(1).getReg();
532 DstReg = MI.getOperand(0).getReg();
537 case ARM::tMOVgpr2tgpr:
538 case ARM::tMOVtgpr2gpr:
539 case ARM::tMOVgpr2gpr:
541 assert(MI.getDesc().getNumOperands() >= 2 &&
542 MI.getOperand(0).isReg() &&
543 MI.getOperand(1).isReg() &&
544 "Invalid ARM MOV instruction");
545 SrcReg = MI.getOperand(1).getReg();
546 DstReg = MI.getOperand(0).getReg();
555 ARMBaseInstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
556 int &FrameIndex) const {
557 switch (MI->getOpcode()) {
560 case ARM::t2LDRs: // FIXME: don't use t2LDRs to access frame.
561 if (MI->getOperand(1).isFI() &&
562 MI->getOperand(2).isReg() &&
563 MI->getOperand(3).isImm() &&
564 MI->getOperand(2).getReg() == 0 &&
565 MI->getOperand(3).getImm() == 0) {
566 FrameIndex = MI->getOperand(1).getIndex();
567 return MI->getOperand(0).getReg();
572 if (MI->getOperand(1).isFI() &&
573 MI->getOperand(2).isImm() &&
574 MI->getOperand(2).getImm() == 0) {
575 FrameIndex = MI->getOperand(1).getIndex();
576 return MI->getOperand(0).getReg();
581 if (MI->getOperand(1).isFI() &&
582 MI->getOperand(2).isImm() &&
583 MI->getOperand(2).getImm() == 0) {
584 FrameIndex = MI->getOperand(1).getIndex();
585 return MI->getOperand(0).getReg();
594 ARMBaseInstrInfo::isStoreToStackSlot(const MachineInstr *MI,
595 int &FrameIndex) const {
596 switch (MI->getOpcode()) {
599 case ARM::t2STRs: // FIXME: don't use t2STRs to access frame.
600 if (MI->getOperand(1).isFI() &&
601 MI->getOperand(2).isReg() &&
602 MI->getOperand(3).isImm() &&
603 MI->getOperand(2).getReg() == 0 &&
604 MI->getOperand(3).getImm() == 0) {
605 FrameIndex = MI->getOperand(1).getIndex();
606 return MI->getOperand(0).getReg();
611 if (MI->getOperand(1).isFI() &&
612 MI->getOperand(2).isImm() &&
613 MI->getOperand(2).getImm() == 0) {
614 FrameIndex = MI->getOperand(1).getIndex();
615 return MI->getOperand(0).getReg();
620 if (MI->getOperand(1).isFI() &&
621 MI->getOperand(2).isImm() &&
622 MI->getOperand(2).getImm() == 0) {
623 FrameIndex = MI->getOperand(1).getIndex();
624 return MI->getOperand(0).getReg();
633 ARMBaseInstrInfo::copyRegToReg(MachineBasicBlock &MBB,
634 MachineBasicBlock::iterator I,
635 unsigned DestReg, unsigned SrcReg,
636 const TargetRegisterClass *DestRC,
637 const TargetRegisterClass *SrcRC) const {
638 DebugLoc DL = DebugLoc::getUnknownLoc();
639 if (I != MBB.end()) DL = I->getDebugLoc();
641 if (DestRC != SrcRC) {
642 if (DestRC->getSize() != SrcRC->getSize())
645 // Allow DPR / DPR_VFP2 / DPR_8 cross-class copies.
646 // Allow QPR / QPR_VFP2 / QPR_8 cross-class copies.
647 if (DestRC->getSize() != 8 && DestRC->getSize() != 16)
651 if (DestRC == ARM::GPRRegisterClass) {
652 AddDefaultCC(AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::MOVr),
653 DestReg).addReg(SrcReg)));
654 } else if (DestRC == ARM::SPRRegisterClass) {
655 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VMOVS), DestReg)
657 } else if (DestRC == ARM::DPRRegisterClass) {
658 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VMOVD), DestReg)
660 } else if (DestRC == ARM::DPR_VFP2RegisterClass ||
661 DestRC == ARM::DPR_8RegisterClass ||
662 SrcRC == ARM::DPR_VFP2RegisterClass ||
663 SrcRC == ARM::DPR_8RegisterClass) {
664 // Always use neon reg-reg move if source or dest is NEON-only regclass.
665 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VMOVDneon),
666 DestReg).addReg(SrcReg));
667 } else if (DestRC == ARM::QPRRegisterClass ||
668 DestRC == ARM::QPR_VFP2RegisterClass ||
669 DestRC == ARM::QPR_8RegisterClass) {
670 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VMOVQ),
671 DestReg).addReg(SrcReg));
679 void ARMBaseInstrInfo::
680 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
681 unsigned SrcReg, bool isKill, int FI,
682 const TargetRegisterClass *RC) const {
683 DebugLoc DL = DebugLoc::getUnknownLoc();
684 if (I != MBB.end()) DL = I->getDebugLoc();
685 MachineFunction &MF = *MBB.getParent();
686 MachineFrameInfo &MFI = *MF.getFrameInfo();
687 unsigned Align = MFI.getObjectAlignment(FI);
689 MachineMemOperand *MMO =
690 MF.getMachineMemOperand(PseudoSourceValue::getFixedStack(FI),
691 MachineMemOperand::MOStore, 0,
692 MFI.getObjectSize(FI),
695 if (RC == ARM::GPRRegisterClass) {
696 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::STR))
697 .addReg(SrcReg, getKillRegState(isKill))
698 .addFrameIndex(FI).addReg(0).addImm(0).addMemOperand(MMO));
699 } else if (RC == ARM::DPRRegisterClass ||
700 RC == ARM::DPR_VFP2RegisterClass ||
701 RC == ARM::DPR_8RegisterClass) {
702 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTRD))
703 .addReg(SrcReg, getKillRegState(isKill))
704 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
705 } else if (RC == ARM::SPRRegisterClass) {
706 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTRS))
707 .addReg(SrcReg, getKillRegState(isKill))
708 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
710 assert((RC == ARM::QPRRegisterClass ||
711 RC == ARM::QPR_VFP2RegisterClass) && "Unknown regclass!");
712 // FIXME: Neon instructions should support predicates
714 && (getRegisterInfo().needsStackRealignment(MF))) {
715 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VST1q64))
716 .addFrameIndex(FI).addImm(0).addImm(0).addImm(128)
718 .addReg(SrcReg, getKillRegState(isKill)));
720 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTRQ)).
721 addReg(SrcReg, getKillRegState(isKill))
722 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
727 void ARMBaseInstrInfo::
728 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
729 unsigned DestReg, int FI,
730 const TargetRegisterClass *RC) const {
731 DebugLoc DL = DebugLoc::getUnknownLoc();
732 if (I != MBB.end()) DL = I->getDebugLoc();
733 MachineFunction &MF = *MBB.getParent();
734 MachineFrameInfo &MFI = *MF.getFrameInfo();
735 unsigned Align = MFI.getObjectAlignment(FI);
737 MachineMemOperand *MMO =
738 MF.getMachineMemOperand(PseudoSourceValue::getFixedStack(FI),
739 MachineMemOperand::MOLoad, 0,
740 MFI.getObjectSize(FI),
743 if (RC == ARM::GPRRegisterClass) {
744 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::LDR), DestReg)
745 .addFrameIndex(FI).addReg(0).addImm(0).addMemOperand(MMO));
746 } else if (RC == ARM::DPRRegisterClass ||
747 RC == ARM::DPR_VFP2RegisterClass ||
748 RC == ARM::DPR_8RegisterClass) {
749 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDRD), DestReg)
750 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
751 } else if (RC == ARM::SPRRegisterClass) {
752 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDRS), DestReg)
753 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
755 assert((RC == ARM::QPRRegisterClass ||
756 RC == ARM::QPR_VFP2RegisterClass ||
757 RC == ARM::QPR_8RegisterClass) && "Unknown regclass!");
758 // FIXME: Neon instructions should support predicates
760 && (getRegisterInfo().needsStackRealignment(MF))) {
761 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLD1q64), DestReg)
762 .addFrameIndex(FI).addImm(0).addImm(0).addImm(128)
763 .addMemOperand(MMO));
765 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDRQ), DestReg)
766 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
771 MachineInstr *ARMBaseInstrInfo::
772 foldMemoryOperandImpl(MachineFunction &MF, MachineInstr *MI,
773 const SmallVectorImpl<unsigned> &Ops, int FI) const {
774 if (Ops.size() != 1) return NULL;
776 unsigned OpNum = Ops[0];
777 unsigned Opc = MI->getOpcode();
778 MachineInstr *NewMI = NULL;
779 if (Opc == ARM::MOVr || Opc == ARM::t2MOVr) {
780 // If it is updating CPSR, then it cannot be folded.
781 if (MI->getOperand(4).getReg() == ARM::CPSR && !MI->getOperand(4).isDead())
783 unsigned Pred = MI->getOperand(2).getImm();
784 unsigned PredReg = MI->getOperand(3).getReg();
785 if (OpNum == 0) { // move -> store
786 unsigned SrcReg = MI->getOperand(1).getReg();
787 unsigned SrcSubReg = MI->getOperand(1).getSubReg();
788 bool isKill = MI->getOperand(1).isKill();
789 bool isUndef = MI->getOperand(1).isUndef();
790 if (Opc == ARM::MOVr)
791 NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::STR))
793 getKillRegState(isKill) | getUndefRegState(isUndef),
795 .addFrameIndex(FI).addReg(0).addImm(0).addImm(Pred).addReg(PredReg);
797 NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::t2STRi12))
799 getKillRegState(isKill) | getUndefRegState(isUndef),
801 .addFrameIndex(FI).addImm(0).addImm(Pred).addReg(PredReg);
802 } else { // move -> load
803 unsigned DstReg = MI->getOperand(0).getReg();
804 unsigned DstSubReg = MI->getOperand(0).getSubReg();
805 bool isDead = MI->getOperand(0).isDead();
806 bool isUndef = MI->getOperand(0).isUndef();
807 if (Opc == ARM::MOVr)
808 NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::LDR))
811 getDeadRegState(isDead) |
812 getUndefRegState(isUndef), DstSubReg)
813 .addFrameIndex(FI).addReg(0).addImm(0).addImm(Pred).addReg(PredReg);
815 NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::t2LDRi12))
818 getDeadRegState(isDead) |
819 getUndefRegState(isUndef), DstSubReg)
820 .addFrameIndex(FI).addImm(0).addImm(Pred).addReg(PredReg);
822 } else if (Opc == ARM::tMOVgpr2gpr ||
823 Opc == ARM::tMOVtgpr2gpr ||
824 Opc == ARM::tMOVgpr2tgpr) {
825 if (OpNum == 0) { // move -> store
826 unsigned SrcReg = MI->getOperand(1).getReg();
827 unsigned SrcSubReg = MI->getOperand(1).getSubReg();
828 bool isKill = MI->getOperand(1).isKill();
829 bool isUndef = MI->getOperand(1).isUndef();
830 NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::t2STRi12))
832 getKillRegState(isKill) | getUndefRegState(isUndef),
834 .addFrameIndex(FI).addImm(0).addImm(ARMCC::AL).addReg(0);
835 } else { // move -> load
836 unsigned DstReg = MI->getOperand(0).getReg();
837 unsigned DstSubReg = MI->getOperand(0).getSubReg();
838 bool isDead = MI->getOperand(0).isDead();
839 bool isUndef = MI->getOperand(0).isUndef();
840 NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::t2LDRi12))
843 getDeadRegState(isDead) |
844 getUndefRegState(isUndef),
846 .addFrameIndex(FI).addImm(0).addImm(ARMCC::AL).addReg(0);
848 } else if (Opc == ARM::VMOVS) {
849 unsigned Pred = MI->getOperand(2).getImm();
850 unsigned PredReg = MI->getOperand(3).getReg();
851 if (OpNum == 0) { // move -> store
852 unsigned SrcReg = MI->getOperand(1).getReg();
853 unsigned SrcSubReg = MI->getOperand(1).getSubReg();
854 bool isKill = MI->getOperand(1).isKill();
855 bool isUndef = MI->getOperand(1).isUndef();
856 NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::VSTRS))
857 .addReg(SrcReg, getKillRegState(isKill) | getUndefRegState(isUndef),
860 .addImm(0).addImm(Pred).addReg(PredReg);
861 } else { // move -> load
862 unsigned DstReg = MI->getOperand(0).getReg();
863 unsigned DstSubReg = MI->getOperand(0).getSubReg();
864 bool isDead = MI->getOperand(0).isDead();
865 bool isUndef = MI->getOperand(0).isUndef();
866 NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::VLDRS))
869 getDeadRegState(isDead) |
870 getUndefRegState(isUndef),
872 .addFrameIndex(FI).addImm(0).addImm(Pred).addReg(PredReg);
875 else if (Opc == ARM::VMOVD) {
876 unsigned Pred = MI->getOperand(2).getImm();
877 unsigned PredReg = MI->getOperand(3).getReg();
878 if (OpNum == 0) { // move -> store
879 unsigned SrcReg = MI->getOperand(1).getReg();
880 unsigned SrcSubReg = MI->getOperand(1).getSubReg();
881 bool isKill = MI->getOperand(1).isKill();
882 bool isUndef = MI->getOperand(1).isUndef();
883 NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::VSTRD))
885 getKillRegState(isKill) | getUndefRegState(isUndef),
887 .addFrameIndex(FI).addImm(0).addImm(Pred).addReg(PredReg);
888 } else { // move -> load
889 unsigned DstReg = MI->getOperand(0).getReg();
890 unsigned DstSubReg = MI->getOperand(0).getSubReg();
891 bool isDead = MI->getOperand(0).isDead();
892 bool isUndef = MI->getOperand(0).isUndef();
893 NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::VLDRD))
896 getDeadRegState(isDead) |
897 getUndefRegState(isUndef),
899 .addFrameIndex(FI).addImm(0).addImm(Pred).addReg(PredReg);
907 ARMBaseInstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
909 const SmallVectorImpl<unsigned> &Ops,
910 MachineInstr* LoadMI) const {
916 ARMBaseInstrInfo::canFoldMemoryOperand(const MachineInstr *MI,
917 const SmallVectorImpl<unsigned> &Ops) const {
918 if (Ops.size() != 1) return false;
920 unsigned Opc = MI->getOpcode();
921 if (Opc == ARM::MOVr || Opc == ARM::t2MOVr) {
922 // If it is updating CPSR, then it cannot be folded.
923 return MI->getOperand(4).getReg() != ARM::CPSR ||
924 MI->getOperand(4).isDead();
925 } else if (Opc == ARM::tMOVgpr2gpr ||
926 Opc == ARM::tMOVtgpr2gpr ||
927 Opc == ARM::tMOVgpr2tgpr) {
929 } else if (Opc == ARM::VMOVS || Opc == ARM::VMOVD) {
931 } else if (Opc == ARM::VMOVDneon || Opc == ARM::VMOVQ) {
932 return false; // FIXME
938 void ARMBaseInstrInfo::
939 reMaterialize(MachineBasicBlock &MBB,
940 MachineBasicBlock::iterator I,
941 unsigned DestReg, unsigned SubIdx,
942 const MachineInstr *Orig,
943 const TargetRegisterInfo *TRI) const {
944 DebugLoc dl = Orig->getDebugLoc();
946 if (SubIdx && TargetRegisterInfo::isPhysicalRegister(DestReg)) {
947 DestReg = TRI->getSubReg(DestReg, SubIdx);
951 unsigned Opcode = Orig->getOpcode();
954 MachineInstr *MI = MBB.getParent()->CloneMachineInstr(Orig);
955 MI->getOperand(0).setReg(DestReg);
959 case ARM::tLDRpci_pic:
960 case ARM::t2LDRpci_pic: {
961 MachineFunction &MF = *MBB.getParent();
962 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
963 MachineConstantPool *MCP = MF.getConstantPool();
964 unsigned CPI = Orig->getOperand(1).getIndex();
965 const MachineConstantPoolEntry &MCPE = MCP->getConstants()[CPI];
966 assert(MCPE.isMachineConstantPoolEntry() &&
967 "Expecting a machine constantpool entry!");
968 ARMConstantPoolValue *ACPV =
969 static_cast<ARMConstantPoolValue*>(MCPE.Val.MachineCPVal);
970 unsigned PCLabelId = AFI->createConstPoolEntryUId();
971 ARMConstantPoolValue *NewCPV = 0;
972 if (ACPV->isGlobalValue())
973 NewCPV = new ARMConstantPoolValue(ACPV->getGV(), PCLabelId,
975 else if (ACPV->isExtSymbol())
976 NewCPV = new ARMConstantPoolValue(MF.getFunction()->getContext(),
977 ACPV->getSymbol(), PCLabelId, 4);
978 else if (ACPV->isBlockAddress())
979 NewCPV = new ARMConstantPoolValue(ACPV->getBlockAddress(), PCLabelId,
980 ARMCP::CPBlockAddress, 4);
982 llvm_unreachable("Unexpected ARM constantpool value type!!");
983 CPI = MCP->getConstantPoolIndex(NewCPV, MCPE.getAlignment());
984 MachineInstrBuilder MIB = BuildMI(MBB, I, Orig->getDebugLoc(), get(Opcode),
986 .addConstantPoolIndex(CPI).addImm(PCLabelId);
987 (*MIB).setMemRefs(Orig->memoperands_begin(), Orig->memoperands_end());
992 MachineInstr *NewMI = prior(I);
993 NewMI->getOperand(0).setSubReg(SubIdx);
996 bool ARMBaseInstrInfo::isIdentical(const MachineInstr *MI0,
997 const MachineInstr *MI1,
998 const MachineRegisterInfo *MRI) const {
999 int Opcode = MI0->getOpcode();
1000 if (Opcode == ARM::t2LDRpci ||
1001 Opcode == ARM::t2LDRpci_pic ||
1002 Opcode == ARM::tLDRpci ||
1003 Opcode == ARM::tLDRpci_pic) {
1004 if (MI1->getOpcode() != Opcode)
1006 if (MI0->getNumOperands() != MI1->getNumOperands())
1009 const MachineOperand &MO0 = MI0->getOperand(1);
1010 const MachineOperand &MO1 = MI1->getOperand(1);
1011 if (MO0.getOffset() != MO1.getOffset())
1014 const MachineFunction *MF = MI0->getParent()->getParent();
1015 const MachineConstantPool *MCP = MF->getConstantPool();
1016 int CPI0 = MO0.getIndex();
1017 int CPI1 = MO1.getIndex();
1018 const MachineConstantPoolEntry &MCPE0 = MCP->getConstants()[CPI0];
1019 const MachineConstantPoolEntry &MCPE1 = MCP->getConstants()[CPI1];
1020 ARMConstantPoolValue *ACPV0 =
1021 static_cast<ARMConstantPoolValue*>(MCPE0.Val.MachineCPVal);
1022 ARMConstantPoolValue *ACPV1 =
1023 static_cast<ARMConstantPoolValue*>(MCPE1.Val.MachineCPVal);
1024 return ACPV0->hasSameValue(ACPV1);
1027 return TargetInstrInfoImpl::isIdentical(MI0, MI1, MRI);
1030 bool ARMBaseInstrInfo::isProfitableToDuplicateIndirectBranch() const {
1031 // If the target processor can predict indirect branches, it is highly
1032 // desirable to duplicate them, since it can often make them predictable.
1033 return getSubtarget().hasBranchTargetBuffer();
1036 /// getInstrPredicate - If instruction is predicated, returns its predicate
1037 /// condition, otherwise returns AL. It also returns the condition code
1038 /// register by reference.
1040 llvm::getInstrPredicate(const MachineInstr *MI, unsigned &PredReg) {
1041 int PIdx = MI->findFirstPredOperandIdx();
1047 PredReg = MI->getOperand(PIdx+1).getReg();
1048 return (ARMCC::CondCodes)MI->getOperand(PIdx).getImm();
1052 int llvm::getMatchingCondBranchOpcode(int Opc) {
1055 else if (Opc == ARM::tB)
1057 else if (Opc == ARM::t2B)
1060 llvm_unreachable("Unknown unconditional branch opcode!");
1065 void llvm::emitARMRegPlusImmediate(MachineBasicBlock &MBB,
1066 MachineBasicBlock::iterator &MBBI, DebugLoc dl,
1067 unsigned DestReg, unsigned BaseReg, int NumBytes,
1068 ARMCC::CondCodes Pred, unsigned PredReg,
1069 const ARMBaseInstrInfo &TII) {
1070 bool isSub = NumBytes < 0;
1071 if (isSub) NumBytes = -NumBytes;
1074 unsigned RotAmt = ARM_AM::getSOImmValRotate(NumBytes);
1075 unsigned ThisVal = NumBytes & ARM_AM::rotr32(0xFF, RotAmt);
1076 assert(ThisVal && "Didn't extract field correctly");
1078 // We will handle these bits from offset, clear them.
1079 NumBytes &= ~ThisVal;
1081 assert(ARM_AM::getSOImmVal(ThisVal) != -1 && "Bit extraction didn't work?");
1083 // Build the new ADD / SUB.
1084 unsigned Opc = isSub ? ARM::SUBri : ARM::ADDri;
1085 BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg)
1086 .addReg(BaseReg, RegState::Kill).addImm(ThisVal)
1087 .addImm((unsigned)Pred).addReg(PredReg).addReg(0);
1092 bool llvm::rewriteARMFrameIndex(MachineInstr &MI, unsigned FrameRegIdx,
1093 unsigned FrameReg, int &Offset,
1094 const ARMBaseInstrInfo &TII) {
1095 unsigned Opcode = MI.getOpcode();
1096 const TargetInstrDesc &Desc = MI.getDesc();
1097 unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
1100 // Memory operands in inline assembly always use AddrMode2.
1101 if (Opcode == ARM::INLINEASM)
1102 AddrMode = ARMII::AddrMode2;
1104 if (Opcode == ARM::ADDri) {
1105 Offset += MI.getOperand(FrameRegIdx+1).getImm();
1107 // Turn it into a move.
1108 MI.setDesc(TII.get(ARM::MOVr));
1109 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
1110 MI.RemoveOperand(FrameRegIdx+1);
1113 } else if (Offset < 0) {
1116 MI.setDesc(TII.get(ARM::SUBri));
1119 // Common case: small offset, fits into instruction.
1120 if (ARM_AM::getSOImmVal(Offset) != -1) {
1121 // Replace the FrameIndex with sp / fp
1122 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
1123 MI.getOperand(FrameRegIdx+1).ChangeToImmediate(Offset);
1128 // Otherwise, pull as much of the immedidate into this ADDri/SUBri
1130 unsigned RotAmt = ARM_AM::getSOImmValRotate(Offset);
1131 unsigned ThisImmVal = Offset & ARM_AM::rotr32(0xFF, RotAmt);
1133 // We will handle these bits from offset, clear them.
1134 Offset &= ~ThisImmVal;
1136 // Get the properly encoded SOImmVal field.
1137 assert(ARM_AM::getSOImmVal(ThisImmVal) != -1 &&
1138 "Bit extraction didn't work?");
1139 MI.getOperand(FrameRegIdx+1).ChangeToImmediate(ThisImmVal);
1141 unsigned ImmIdx = 0;
1143 unsigned NumBits = 0;
1146 case ARMII::AddrMode2: {
1147 ImmIdx = FrameRegIdx+2;
1148 InstrOffs = ARM_AM::getAM2Offset(MI.getOperand(ImmIdx).getImm());
1149 if (ARM_AM::getAM2Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub)
1154 case ARMII::AddrMode3: {
1155 ImmIdx = FrameRegIdx+2;
1156 InstrOffs = ARM_AM::getAM3Offset(MI.getOperand(ImmIdx).getImm());
1157 if (ARM_AM::getAM3Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub)
1162 case ARMII::AddrMode4:
1163 case ARMII::AddrMode6:
1164 // Can't fold any offset even if it's zero.
1166 case ARMII::AddrMode5: {
1167 ImmIdx = FrameRegIdx+1;
1168 InstrOffs = ARM_AM::getAM5Offset(MI.getOperand(ImmIdx).getImm());
1169 if (ARM_AM::getAM5Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub)
1176 llvm_unreachable("Unsupported addressing mode!");
1180 Offset += InstrOffs * Scale;
1181 assert((Offset & (Scale-1)) == 0 && "Can't encode this offset!");
1187 // Attempt to fold address comp. if opcode has offset bits
1189 // Common case: small offset, fits into instruction.
1190 MachineOperand &ImmOp = MI.getOperand(ImmIdx);
1191 int ImmedOffset = Offset / Scale;
1192 unsigned Mask = (1 << NumBits) - 1;
1193 if ((unsigned)Offset <= Mask * Scale) {
1194 // Replace the FrameIndex with sp
1195 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
1197 ImmedOffset |= 1 << NumBits;
1198 ImmOp.ChangeToImmediate(ImmedOffset);
1203 // Otherwise, it didn't fit. Pull in what we can to simplify the immed.
1204 ImmedOffset = ImmedOffset & Mask;
1206 ImmedOffset |= 1 << NumBits;
1207 ImmOp.ChangeToImmediate(ImmedOffset);
1208 Offset &= ~(Mask*Scale);
1212 Offset = (isSub) ? -Offset : Offset;