1 //===- ARMBaseInstrInfo.cpp - ARM Instruction Information -------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Base ARM implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "ARMBaseInstrInfo.h"
16 #include "ARMAddressingModes.h"
17 #include "ARMConstantPoolValue.h"
18 #include "ARMMachineFunctionInfo.h"
19 #include "ARMRegisterInfo.h"
20 #include "ARMGenInstrInfo.inc"
21 #include "llvm/Constants.h"
22 #include "llvm/Function.h"
23 #include "llvm/GlobalValue.h"
24 #include "llvm/ADT/STLExtras.h"
25 #include "llvm/CodeGen/LiveVariables.h"
26 #include "llvm/CodeGen/MachineConstantPool.h"
27 #include "llvm/CodeGen/MachineFrameInfo.h"
28 #include "llvm/CodeGen/MachineInstrBuilder.h"
29 #include "llvm/CodeGen/MachineJumpTableInfo.h"
30 #include "llvm/CodeGen/MachineMemOperand.h"
31 #include "llvm/CodeGen/MachineRegisterInfo.h"
32 #include "llvm/CodeGen/PseudoSourceValue.h"
33 #include "llvm/MC/MCAsmInfo.h"
34 #include "llvm/Support/CommandLine.h"
35 #include "llvm/Support/Debug.h"
36 #include "llvm/Support/ErrorHandling.h"
40 EnableARM3Addr("enable-arm-3-addr-conv", cl::Hidden,
41 cl::desc("Enable ARM 2-addr to 3-addr conv"));
43 ARMBaseInstrInfo::ARMBaseInstrInfo(const ARMSubtarget& STI)
44 : TargetInstrInfoImpl(ARMInsts, array_lengthof(ARMInsts)),
49 ARMBaseInstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
50 MachineBasicBlock::iterator &MBBI,
51 LiveVariables *LV) const {
52 // FIXME: Thumb2 support.
57 MachineInstr *MI = MBBI;
58 MachineFunction &MF = *MI->getParent()->getParent();
59 uint64_t TSFlags = MI->getDesc().TSFlags;
61 switch ((TSFlags & ARMII::IndexModeMask) >> ARMII::IndexModeShift) {
63 case ARMII::IndexModePre:
66 case ARMII::IndexModePost:
70 // Try splitting an indexed load/store to an un-indexed one plus an add/sub
72 unsigned MemOpc = getUnindexedOpcode(MI->getOpcode());
76 MachineInstr *UpdateMI = NULL;
77 MachineInstr *MemMI = NULL;
78 unsigned AddrMode = (TSFlags & ARMII::AddrModeMask);
79 const TargetInstrDesc &TID = MI->getDesc();
80 unsigned NumOps = TID.getNumOperands();
81 bool isLoad = !TID.mayStore();
82 const MachineOperand &WB = isLoad ? MI->getOperand(1) : MI->getOperand(0);
83 const MachineOperand &Base = MI->getOperand(2);
84 const MachineOperand &Offset = MI->getOperand(NumOps-3);
85 unsigned WBReg = WB.getReg();
86 unsigned BaseReg = Base.getReg();
87 unsigned OffReg = Offset.getReg();
88 unsigned OffImm = MI->getOperand(NumOps-2).getImm();
89 ARMCC::CondCodes Pred = (ARMCC::CondCodes)MI->getOperand(NumOps-1).getImm();
92 assert(false && "Unknown indexed op!");
94 case ARMII::AddrMode2: {
95 bool isSub = ARM_AM::getAM2Op(OffImm) == ARM_AM::sub;
96 unsigned Amt = ARM_AM::getAM2Offset(OffImm);
98 if (ARM_AM::getSOImmVal(Amt) == -1)
99 // Can't encode it in a so_imm operand. This transformation will
100 // add more than 1 instruction. Abandon!
102 UpdateMI = BuildMI(MF, MI->getDebugLoc(),
103 get(isSub ? ARM::SUBri : ARM::ADDri), WBReg)
104 .addReg(BaseReg).addImm(Amt)
105 .addImm(Pred).addReg(0).addReg(0);
106 } else if (Amt != 0) {
107 ARM_AM::ShiftOpc ShOpc = ARM_AM::getAM2ShiftOpc(OffImm);
108 unsigned SOOpc = ARM_AM::getSORegOpc(ShOpc, Amt);
109 UpdateMI = BuildMI(MF, MI->getDebugLoc(),
110 get(isSub ? ARM::SUBrs : ARM::ADDrs), WBReg)
111 .addReg(BaseReg).addReg(OffReg).addReg(0).addImm(SOOpc)
112 .addImm(Pred).addReg(0).addReg(0);
114 UpdateMI = BuildMI(MF, MI->getDebugLoc(),
115 get(isSub ? ARM::SUBrr : ARM::ADDrr), WBReg)
116 .addReg(BaseReg).addReg(OffReg)
117 .addImm(Pred).addReg(0).addReg(0);
120 case ARMII::AddrMode3 : {
121 bool isSub = ARM_AM::getAM3Op(OffImm) == ARM_AM::sub;
122 unsigned Amt = ARM_AM::getAM3Offset(OffImm);
124 // Immediate is 8-bits. It's guaranteed to fit in a so_imm operand.
125 UpdateMI = BuildMI(MF, MI->getDebugLoc(),
126 get(isSub ? ARM::SUBri : ARM::ADDri), WBReg)
127 .addReg(BaseReg).addImm(Amt)
128 .addImm(Pred).addReg(0).addReg(0);
130 UpdateMI = BuildMI(MF, MI->getDebugLoc(),
131 get(isSub ? ARM::SUBrr : ARM::ADDrr), WBReg)
132 .addReg(BaseReg).addReg(OffReg)
133 .addImm(Pred).addReg(0).addReg(0);
138 std::vector<MachineInstr*> NewMIs;
141 MemMI = BuildMI(MF, MI->getDebugLoc(),
142 get(MemOpc), MI->getOperand(0).getReg())
143 .addReg(WBReg).addReg(0).addImm(0).addImm(Pred);
145 MemMI = BuildMI(MF, MI->getDebugLoc(),
146 get(MemOpc)).addReg(MI->getOperand(1).getReg())
147 .addReg(WBReg).addReg(0).addImm(0).addImm(Pred);
148 NewMIs.push_back(MemMI);
149 NewMIs.push_back(UpdateMI);
152 MemMI = BuildMI(MF, MI->getDebugLoc(),
153 get(MemOpc), MI->getOperand(0).getReg())
154 .addReg(BaseReg).addReg(0).addImm(0).addImm(Pred);
156 MemMI = BuildMI(MF, MI->getDebugLoc(),
157 get(MemOpc)).addReg(MI->getOperand(1).getReg())
158 .addReg(BaseReg).addReg(0).addImm(0).addImm(Pred);
160 UpdateMI->getOperand(0).setIsDead();
161 NewMIs.push_back(UpdateMI);
162 NewMIs.push_back(MemMI);
165 // Transfer LiveVariables states, kill / dead info.
167 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
168 MachineOperand &MO = MI->getOperand(i);
169 if (MO.isReg() && MO.getReg() &&
170 TargetRegisterInfo::isVirtualRegister(MO.getReg())) {
171 unsigned Reg = MO.getReg();
173 LiveVariables::VarInfo &VI = LV->getVarInfo(Reg);
175 MachineInstr *NewMI = (Reg == WBReg) ? UpdateMI : MemMI;
177 LV->addVirtualRegisterDead(Reg, NewMI);
179 if (MO.isUse() && MO.isKill()) {
180 for (unsigned j = 0; j < 2; ++j) {
181 // Look at the two new MI's in reverse order.
182 MachineInstr *NewMI = NewMIs[j];
183 if (!NewMI->readsRegister(Reg))
185 LV->addVirtualRegisterKilled(Reg, NewMI);
186 if (VI.removeKill(MI))
187 VI.Kills.push_back(NewMI);
195 MFI->insert(MBBI, NewMIs[1]);
196 MFI->insert(MBBI, NewMIs[0]);
201 ARMBaseInstrInfo::spillCalleeSavedRegisters(MachineBasicBlock &MBB,
202 MachineBasicBlock::iterator MI,
203 const std::vector<CalleeSavedInfo> &CSI,
204 const TargetRegisterInfo *TRI) const {
209 if (MI != MBB.end()) DL = MI->getDebugLoc();
211 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
212 unsigned Reg = CSI[i].getReg();
215 // Add the callee-saved register as live-in unless it's LR and
216 // @llvm.returnaddress is called. If LR is returned for @llvm.returnaddress
217 // then it's already added to the function and entry block live-in sets.
218 if (Reg == ARM::LR) {
219 MachineFunction &MF = *MBB.getParent();
220 if (MF.getFrameInfo()->isReturnAddressTaken() &&
221 MF.getRegInfo().isLiveIn(Reg))
228 // Insert the spill to the stack frame. The register is killed at the spill
230 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
231 storeRegToStackSlot(MBB, MI, Reg, isKill,
232 CSI[i].getFrameIdx(), RC, TRI);
239 ARMBaseInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB,
240 MachineBasicBlock *&FBB,
241 SmallVectorImpl<MachineOperand> &Cond,
242 bool AllowModify) const {
243 // If the block has no terminators, it just falls into the block after it.
244 MachineBasicBlock::iterator I = MBB.end();
245 if (I == MBB.begin())
248 while (I->isDebugValue()) {
249 if (I == MBB.begin())
253 if (!isUnpredicatedTerminator(I))
256 // Get the last instruction in the block.
257 MachineInstr *LastInst = I;
259 // If there is only one terminator instruction, process it.
260 unsigned LastOpc = LastInst->getOpcode();
261 if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) {
262 if (isUncondBranchOpcode(LastOpc)) {
263 TBB = LastInst->getOperand(0).getMBB();
266 if (isCondBranchOpcode(LastOpc)) {
267 // Block ends with fall-through condbranch.
268 TBB = LastInst->getOperand(0).getMBB();
269 Cond.push_back(LastInst->getOperand(1));
270 Cond.push_back(LastInst->getOperand(2));
273 return true; // Can't handle indirect branch.
276 // Get the instruction before it if it is a terminator.
277 MachineInstr *SecondLastInst = I;
279 // If there are three terminators, we don't know what sort of block this is.
280 if (SecondLastInst && I != MBB.begin() && isUnpredicatedTerminator(--I))
283 // If the block ends with a B and a Bcc, handle it.
284 unsigned SecondLastOpc = SecondLastInst->getOpcode();
285 if (isCondBranchOpcode(SecondLastOpc) && isUncondBranchOpcode(LastOpc)) {
286 TBB = SecondLastInst->getOperand(0).getMBB();
287 Cond.push_back(SecondLastInst->getOperand(1));
288 Cond.push_back(SecondLastInst->getOperand(2));
289 FBB = LastInst->getOperand(0).getMBB();
293 // If the block ends with two unconditional branches, handle it. The second
294 // one is not executed, so remove it.
295 if (isUncondBranchOpcode(SecondLastOpc) && isUncondBranchOpcode(LastOpc)) {
296 TBB = SecondLastInst->getOperand(0).getMBB();
299 I->eraseFromParent();
303 // ...likewise if it ends with a branch table followed by an unconditional
304 // branch. The branch folder can create these, and we must get rid of them for
305 // correctness of Thumb constant islands.
306 if ((isJumpTableBranchOpcode(SecondLastOpc) ||
307 isIndirectBranchOpcode(SecondLastOpc)) &&
308 isUncondBranchOpcode(LastOpc)) {
311 I->eraseFromParent();
315 // Otherwise, can't handle this.
320 unsigned ARMBaseInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
321 MachineBasicBlock::iterator I = MBB.end();
322 if (I == MBB.begin()) return 0;
324 while (I->isDebugValue()) {
325 if (I == MBB.begin())
329 if (!isUncondBranchOpcode(I->getOpcode()) &&
330 !isCondBranchOpcode(I->getOpcode()))
333 // Remove the branch.
334 I->eraseFromParent();
338 if (I == MBB.begin()) return 1;
340 if (!isCondBranchOpcode(I->getOpcode()))
343 // Remove the branch.
344 I->eraseFromParent();
349 ARMBaseInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
350 MachineBasicBlock *FBB,
351 const SmallVectorImpl<MachineOperand> &Cond,
353 ARMFunctionInfo *AFI = MBB.getParent()->getInfo<ARMFunctionInfo>();
354 int BOpc = !AFI->isThumbFunction()
355 ? ARM::B : (AFI->isThumb2Function() ? ARM::t2B : ARM::tB);
356 int BccOpc = !AFI->isThumbFunction()
357 ? ARM::Bcc : (AFI->isThumb2Function() ? ARM::t2Bcc : ARM::tBcc);
359 // Shouldn't be a fall through.
360 assert(TBB && "InsertBranch must not be told to insert a fallthrough");
361 assert((Cond.size() == 2 || Cond.size() == 0) &&
362 "ARM branch conditions have two components!");
365 if (Cond.empty()) // Unconditional branch?
366 BuildMI(&MBB, DL, get(BOpc)).addMBB(TBB);
368 BuildMI(&MBB, DL, get(BccOpc)).addMBB(TBB)
369 .addImm(Cond[0].getImm()).addReg(Cond[1].getReg());
373 // Two-way conditional branch.
374 BuildMI(&MBB, DL, get(BccOpc)).addMBB(TBB)
375 .addImm(Cond[0].getImm()).addReg(Cond[1].getReg());
376 BuildMI(&MBB, DL, get(BOpc)).addMBB(FBB);
380 bool ARMBaseInstrInfo::
381 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
382 ARMCC::CondCodes CC = (ARMCC::CondCodes)(int)Cond[0].getImm();
383 Cond[0].setImm(ARMCC::getOppositeCondition(CC));
387 bool ARMBaseInstrInfo::
388 PredicateInstruction(MachineInstr *MI,
389 const SmallVectorImpl<MachineOperand> &Pred) const {
390 unsigned Opc = MI->getOpcode();
391 if (isUncondBranchOpcode(Opc)) {
392 MI->setDesc(get(getMatchingCondBranchOpcode(Opc)));
393 MI->addOperand(MachineOperand::CreateImm(Pred[0].getImm()));
394 MI->addOperand(MachineOperand::CreateReg(Pred[1].getReg(), false));
398 int PIdx = MI->findFirstPredOperandIdx();
400 MachineOperand &PMO = MI->getOperand(PIdx);
401 PMO.setImm(Pred[0].getImm());
402 MI->getOperand(PIdx+1).setReg(Pred[1].getReg());
408 bool ARMBaseInstrInfo::
409 SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1,
410 const SmallVectorImpl<MachineOperand> &Pred2) const {
411 if (Pred1.size() > 2 || Pred2.size() > 2)
414 ARMCC::CondCodes CC1 = (ARMCC::CondCodes)Pred1[0].getImm();
415 ARMCC::CondCodes CC2 = (ARMCC::CondCodes)Pred2[0].getImm();
425 return CC2 == ARMCC::HI;
427 return CC2 == ARMCC::LO || CC2 == ARMCC::EQ;
429 return CC2 == ARMCC::GT;
431 return CC2 == ARMCC::LT;
435 bool ARMBaseInstrInfo::DefinesPredicate(MachineInstr *MI,
436 std::vector<MachineOperand> &Pred) const {
437 // FIXME: This confuses implicit_def with optional CPSR def.
438 const TargetInstrDesc &TID = MI->getDesc();
439 if (!TID.getImplicitDefs() && !TID.hasOptionalDef())
443 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
444 const MachineOperand &MO = MI->getOperand(i);
445 if (MO.isReg() && MO.getReg() == ARM::CPSR) {
454 /// isPredicable - Return true if the specified instruction can be predicated.
455 /// By default, this returns true for every instruction with a
456 /// PredicateOperand.
457 bool ARMBaseInstrInfo::isPredicable(MachineInstr *MI) const {
458 const TargetInstrDesc &TID = MI->getDesc();
459 if (!TID.isPredicable())
462 if ((TID.TSFlags & ARMII::DomainMask) == ARMII::DomainNEON) {
463 ARMFunctionInfo *AFI =
464 MI->getParent()->getParent()->getInfo<ARMFunctionInfo>();
465 return AFI->isThumb2Function();
470 /// FIXME: Works around a gcc miscompilation with -fstrict-aliasing.
472 static unsigned getNumJTEntries(const std::vector<MachineJumpTableEntry> &JT,
474 static unsigned getNumJTEntries(const std::vector<MachineJumpTableEntry> &JT,
476 assert(JTI < JT.size());
477 return JT[JTI].MBBs.size();
480 /// GetInstSize - Return the size of the specified MachineInstr.
482 unsigned ARMBaseInstrInfo::GetInstSizeInBytes(const MachineInstr *MI) const {
483 const MachineBasicBlock &MBB = *MI->getParent();
484 const MachineFunction *MF = MBB.getParent();
485 const MCAsmInfo *MAI = MF->getTarget().getMCAsmInfo();
487 // Basic size info comes from the TSFlags field.
488 const TargetInstrDesc &TID = MI->getDesc();
489 uint64_t TSFlags = TID.TSFlags;
491 unsigned Opc = MI->getOpcode();
492 switch ((TSFlags & ARMII::SizeMask) >> ARMII::SizeShift) {
494 // If this machine instr is an inline asm, measure it.
495 if (MI->getOpcode() == ARM::INLINEASM)
496 return getInlineAsmLength(MI->getOperand(0).getSymbolName(), *MAI);
501 llvm_unreachable("Unknown or unset size field for instr!");
502 case TargetOpcode::IMPLICIT_DEF:
503 case TargetOpcode::KILL:
504 case TargetOpcode::PROLOG_LABEL:
505 case TargetOpcode::EH_LABEL:
506 case TargetOpcode::DBG_VALUE:
511 case ARMII::Size8Bytes: return 8; // ARM instruction x 2.
512 case ARMII::Size4Bytes: return 4; // ARM / Thumb2 instruction.
513 case ARMII::Size2Bytes: return 2; // Thumb1 instruction.
514 case ARMII::SizeSpecial: {
516 case ARM::CONSTPOOL_ENTRY:
517 // If this machine instr is a constant pool entry, its size is recorded as
519 return MI->getOperand(2).getImm();
520 case ARM::Int_eh_sjlj_longjmp:
522 case ARM::tInt_eh_sjlj_longjmp:
524 case ARM::Int_eh_sjlj_setjmp:
525 case ARM::Int_eh_sjlj_setjmp_nofp:
527 case ARM::tInt_eh_sjlj_setjmp:
528 case ARM::t2Int_eh_sjlj_setjmp:
529 case ARM::t2Int_eh_sjlj_setjmp_nofp:
538 // These are jumptable branches, i.e. a branch followed by an inlined
539 // jumptable. The size is 4 + 4 * number of entries. For TBB, each
540 // entry is one byte; TBH two byte each.
541 unsigned EntrySize = (Opc == ARM::t2TBB)
542 ? 1 : ((Opc == ARM::t2TBH) ? 2 : 4);
543 unsigned NumOps = TID.getNumOperands();
544 MachineOperand JTOP =
545 MI->getOperand(NumOps - (TID.isPredicable() ? 3 : 2));
546 unsigned JTI = JTOP.getIndex();
547 const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
549 const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
550 assert(JTI < JT.size());
551 // Thumb instructions are 2 byte aligned, but JT entries are 4 byte
552 // 4 aligned. The assembler / linker may add 2 byte padding just before
553 // the JT entries. The size does not include this padding; the
554 // constant islands pass does separate bookkeeping for it.
555 // FIXME: If we know the size of the function is less than (1 << 16) *2
556 // bytes, we can use 16-bit entries instead. Then there won't be an
558 unsigned InstSize = (Opc == ARM::tBR_JTr || Opc == ARM::t2BR_JT) ? 2 : 4;
559 unsigned NumEntries = getNumJTEntries(JT, JTI);
560 if (Opc == ARM::t2TBB && (NumEntries & 1))
561 // Make sure the instruction that follows TBB is 2-byte aligned.
562 // FIXME: Constant island pass should insert an "ALIGN" instruction
565 return NumEntries * EntrySize + InstSize;
568 // Otherwise, pseudo-instruction sizes are zero.
573 return 0; // Not reached
576 void ARMBaseInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
577 MachineBasicBlock::iterator I, DebugLoc DL,
578 unsigned DestReg, unsigned SrcReg,
579 bool KillSrc) const {
580 bool GPRDest = ARM::GPRRegClass.contains(DestReg);
581 bool GPRSrc = ARM::GPRRegClass.contains(SrcReg);
583 if (GPRDest && GPRSrc) {
584 AddDefaultCC(AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::MOVr), DestReg)
585 .addReg(SrcReg, getKillRegState(KillSrc))));
589 bool SPRDest = ARM::SPRRegClass.contains(DestReg);
590 bool SPRSrc = ARM::SPRRegClass.contains(SrcReg);
593 if (SPRDest && SPRSrc)
595 else if (GPRDest && SPRSrc)
597 else if (SPRDest && GPRSrc)
599 else if (ARM::DPRRegClass.contains(DestReg, SrcReg))
601 else if (ARM::QPRRegClass.contains(DestReg, SrcReg))
603 else if (ARM::QQPRRegClass.contains(DestReg, SrcReg))
605 else if (ARM::QQQQPRRegClass.contains(DestReg, SrcReg))
608 llvm_unreachable("Impossible reg-to-reg copy");
610 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(Opc), DestReg);
611 MIB.addReg(SrcReg, getKillRegState(KillSrc));
612 if (Opc != ARM::VMOVQQ && Opc != ARM::VMOVQQQQ)
617 MachineInstrBuilder &AddDReg(MachineInstrBuilder &MIB,
618 unsigned Reg, unsigned SubIdx, unsigned State,
619 const TargetRegisterInfo *TRI) {
621 return MIB.addReg(Reg, State);
623 if (TargetRegisterInfo::isPhysicalRegister(Reg))
624 return MIB.addReg(TRI->getSubReg(Reg, SubIdx), State);
625 return MIB.addReg(Reg, State, SubIdx);
628 void ARMBaseInstrInfo::
629 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
630 unsigned SrcReg, bool isKill, int FI,
631 const TargetRegisterClass *RC,
632 const TargetRegisterInfo *TRI) const {
634 if (I != MBB.end()) DL = I->getDebugLoc();
635 MachineFunction &MF = *MBB.getParent();
636 MachineFrameInfo &MFI = *MF.getFrameInfo();
637 unsigned Align = MFI.getObjectAlignment(FI);
639 MachineMemOperand *MMO =
640 MF.getMachineMemOperand(PseudoSourceValue::getFixedStack(FI),
641 MachineMemOperand::MOStore, 0,
642 MFI.getObjectSize(FI),
645 // tGPR is used sometimes in ARM instructions that need to avoid using
646 // certain registers. Just treat it as GPR here. Likewise, rGPR.
647 if (RC == ARM::tGPRRegisterClass || RC == ARM::tcGPRRegisterClass
648 || RC == ARM::rGPRRegisterClass)
649 RC = ARM::GPRRegisterClass;
651 switch (RC->getID()) {
652 case ARM::GPRRegClassID:
653 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::STR))
654 .addReg(SrcReg, getKillRegState(isKill))
655 .addFrameIndex(FI).addReg(0).addImm(0).addMemOperand(MMO));
657 case ARM::SPRRegClassID:
658 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTRS))
659 .addReg(SrcReg, getKillRegState(isKill))
660 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
662 case ARM::DPRRegClassID:
663 case ARM::DPR_VFP2RegClassID:
664 case ARM::DPR_8RegClassID:
665 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTRD))
666 .addReg(SrcReg, getKillRegState(isKill))
667 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
669 case ARM::QPRRegClassID:
670 case ARM::QPR_VFP2RegClassID:
671 case ARM::QPR_8RegClassID:
672 if (Align >= 16 && getRegisterInfo().needsStackRealignment(MF)) {
673 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VST1q64Pseudo))
674 .addFrameIndex(FI).addImm(16)
675 .addReg(SrcReg, getKillRegState(isKill))
676 .addMemOperand(MMO));
678 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTMQ))
679 .addReg(SrcReg, getKillRegState(isKill))
681 .addImm(ARM_AM::getAM4ModeImm(ARM_AM::ia))
682 .addMemOperand(MMO));
685 case ARM::QQPRRegClassID:
686 case ARM::QQPR_VFP2RegClassID:
687 if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) {
688 // FIXME: It's possible to only store part of the QQ register if the
689 // spilled def has a sub-register index.
690 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VST1d64QPseudo))
691 .addFrameIndex(FI).addImm(16)
692 .addReg(SrcReg, getKillRegState(isKill))
693 .addMemOperand(MMO));
695 MachineInstrBuilder MIB =
696 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTMD))
698 .addImm(ARM_AM::getAM4ModeImm(ARM_AM::ia)))
700 MIB = AddDReg(MIB, SrcReg, ARM::dsub_0, getKillRegState(isKill), TRI);
701 MIB = AddDReg(MIB, SrcReg, ARM::dsub_1, 0, TRI);
702 MIB = AddDReg(MIB, SrcReg, ARM::dsub_2, 0, TRI);
703 AddDReg(MIB, SrcReg, ARM::dsub_3, 0, TRI);
706 case ARM::QQQQPRRegClassID: {
707 MachineInstrBuilder MIB =
708 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTMD))
710 .addImm(ARM_AM::getAM4ModeImm(ARM_AM::ia)))
712 MIB = AddDReg(MIB, SrcReg, ARM::dsub_0, getKillRegState(isKill), TRI);
713 MIB = AddDReg(MIB, SrcReg, ARM::dsub_1, 0, TRI);
714 MIB = AddDReg(MIB, SrcReg, ARM::dsub_2, 0, TRI);
715 MIB = AddDReg(MIB, SrcReg, ARM::dsub_3, 0, TRI);
716 MIB = AddDReg(MIB, SrcReg, ARM::dsub_4, 0, TRI);
717 MIB = AddDReg(MIB, SrcReg, ARM::dsub_5, 0, TRI);
718 MIB = AddDReg(MIB, SrcReg, ARM::dsub_6, 0, TRI);
719 AddDReg(MIB, SrcReg, ARM::dsub_7, 0, TRI);
723 llvm_unreachable("Unknown regclass!");
728 ARMBaseInstrInfo::isStoreToStackSlot(const MachineInstr *MI,
729 int &FrameIndex) const {
730 switch (MI->getOpcode()) {
733 case ARM::t2STRs: // FIXME: don't use t2STRs to access frame.
734 if (MI->getOperand(1).isFI() &&
735 MI->getOperand(2).isReg() &&
736 MI->getOperand(3).isImm() &&
737 MI->getOperand(2).getReg() == 0 &&
738 MI->getOperand(3).getImm() == 0) {
739 FrameIndex = MI->getOperand(1).getIndex();
740 return MI->getOperand(0).getReg();
747 if (MI->getOperand(1).isFI() &&
748 MI->getOperand(2).isImm() &&
749 MI->getOperand(2).getImm() == 0) {
750 FrameIndex = MI->getOperand(1).getIndex();
751 return MI->getOperand(0).getReg();
759 void ARMBaseInstrInfo::
760 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
761 unsigned DestReg, int FI,
762 const TargetRegisterClass *RC,
763 const TargetRegisterInfo *TRI) const {
765 if (I != MBB.end()) DL = I->getDebugLoc();
766 MachineFunction &MF = *MBB.getParent();
767 MachineFrameInfo &MFI = *MF.getFrameInfo();
768 unsigned Align = MFI.getObjectAlignment(FI);
769 MachineMemOperand *MMO =
770 MF.getMachineMemOperand(PseudoSourceValue::getFixedStack(FI),
771 MachineMemOperand::MOLoad, 0,
772 MFI.getObjectSize(FI),
775 // tGPR is used sometimes in ARM instructions that need to avoid using
776 // certain registers. Just treat it as GPR here.
777 if (RC == ARM::tGPRRegisterClass || RC == ARM::tcGPRRegisterClass
778 || RC == ARM::rGPRRegisterClass)
779 RC = ARM::GPRRegisterClass;
781 switch (RC->getID()) {
782 case ARM::GPRRegClassID:
783 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::LDR), DestReg)
784 .addFrameIndex(FI).addReg(0).addImm(0).addMemOperand(MMO));
786 case ARM::SPRRegClassID:
787 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDRS), DestReg)
788 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
790 case ARM::DPRRegClassID:
791 case ARM::DPR_VFP2RegClassID:
792 case ARM::DPR_8RegClassID:
793 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDRD), DestReg)
794 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
796 case ARM::QPRRegClassID:
797 case ARM::QPR_VFP2RegClassID:
798 case ARM::QPR_8RegClassID:
799 if (Align >= 16 && getRegisterInfo().needsStackRealignment(MF)) {
800 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLD1q64Pseudo), DestReg)
801 .addFrameIndex(FI).addImm(16)
802 .addMemOperand(MMO));
804 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDMQ), DestReg)
806 .addImm(ARM_AM::getAM4ModeImm(ARM_AM::ia))
807 .addMemOperand(MMO));
810 case ARM::QQPRRegClassID:
811 case ARM::QQPR_VFP2RegClassID:
812 if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) {
813 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLD1d64QPseudo), DestReg)
814 .addFrameIndex(FI).addImm(16)
815 .addMemOperand(MMO));
817 MachineInstrBuilder MIB =
818 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDMD))
820 .addImm(ARM_AM::getAM4ModeImm(ARM_AM::ia)))
822 MIB = AddDReg(MIB, DestReg, ARM::dsub_0, RegState::Define, TRI);
823 MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::Define, TRI);
824 MIB = AddDReg(MIB, DestReg, ARM::dsub_2, RegState::Define, TRI);
825 AddDReg(MIB, DestReg, ARM::dsub_3, RegState::Define, TRI);
828 case ARM::QQQQPRRegClassID: {
829 MachineInstrBuilder MIB =
830 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDMD))
832 .addImm(ARM_AM::getAM4ModeImm(ARM_AM::ia)))
834 MIB = AddDReg(MIB, DestReg, ARM::dsub_0, RegState::Define, TRI);
835 MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::Define, TRI);
836 MIB = AddDReg(MIB, DestReg, ARM::dsub_2, RegState::Define, TRI);
837 MIB = AddDReg(MIB, DestReg, ARM::dsub_3, RegState::Define, TRI);
838 MIB = AddDReg(MIB, DestReg, ARM::dsub_4, RegState::Define, TRI);
839 MIB = AddDReg(MIB, DestReg, ARM::dsub_5, RegState::Define, TRI);
840 MIB = AddDReg(MIB, DestReg, ARM::dsub_6, RegState::Define, TRI);
841 AddDReg(MIB, DestReg, ARM::dsub_7, RegState::Define, TRI);
845 llvm_unreachable("Unknown regclass!");
850 ARMBaseInstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
851 int &FrameIndex) const {
852 switch (MI->getOpcode()) {
855 case ARM::t2LDRs: // FIXME: don't use t2LDRs to access frame.
856 if (MI->getOperand(1).isFI() &&
857 MI->getOperand(2).isReg() &&
858 MI->getOperand(3).isImm() &&
859 MI->getOperand(2).getReg() == 0 &&
860 MI->getOperand(3).getImm() == 0) {
861 FrameIndex = MI->getOperand(1).getIndex();
862 return MI->getOperand(0).getReg();
869 if (MI->getOperand(1).isFI() &&
870 MI->getOperand(2).isImm() &&
871 MI->getOperand(2).getImm() == 0) {
872 FrameIndex = MI->getOperand(1).getIndex();
873 return MI->getOperand(0).getReg();
882 ARMBaseInstrInfo::emitFrameIndexDebugValue(MachineFunction &MF,
883 int FrameIx, uint64_t Offset,
886 MachineInstrBuilder MIB = BuildMI(MF, DL, get(ARM::DBG_VALUE))
887 .addFrameIndex(FrameIx).addImm(0).addImm(Offset).addMetadata(MDPtr);
891 /// Create a copy of a const pool value. Update CPI to the new index and return
893 static unsigned duplicateCPV(MachineFunction &MF, unsigned &CPI) {
894 MachineConstantPool *MCP = MF.getConstantPool();
895 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
897 const MachineConstantPoolEntry &MCPE = MCP->getConstants()[CPI];
898 assert(MCPE.isMachineConstantPoolEntry() &&
899 "Expecting a machine constantpool entry!");
900 ARMConstantPoolValue *ACPV =
901 static_cast<ARMConstantPoolValue*>(MCPE.Val.MachineCPVal);
903 unsigned PCLabelId = AFI->createConstPoolEntryUId();
904 ARMConstantPoolValue *NewCPV = 0;
905 // FIXME: The below assumes PIC relocation model and that the function
906 // is Thumb mode (t1 or t2). PCAdjustment would be 8 for ARM mode PIC, and
907 // zero for non-PIC in ARM or Thumb. The callers are all of thumb LDR
908 // instructions, so that's probably OK, but is PIC always correct when
910 if (ACPV->isGlobalValue())
911 NewCPV = new ARMConstantPoolValue(ACPV->getGV(), PCLabelId,
913 else if (ACPV->isExtSymbol())
914 NewCPV = new ARMConstantPoolValue(MF.getFunction()->getContext(),
915 ACPV->getSymbol(), PCLabelId, 4);
916 else if (ACPV->isBlockAddress())
917 NewCPV = new ARMConstantPoolValue(ACPV->getBlockAddress(), PCLabelId,
918 ARMCP::CPBlockAddress, 4);
919 else if (ACPV->isLSDA())
920 NewCPV = new ARMConstantPoolValue(MF.getFunction(), PCLabelId,
923 llvm_unreachable("Unexpected ARM constantpool value type!!");
924 CPI = MCP->getConstantPoolIndex(NewCPV, MCPE.getAlignment());
928 void ARMBaseInstrInfo::
929 reMaterialize(MachineBasicBlock &MBB,
930 MachineBasicBlock::iterator I,
931 unsigned DestReg, unsigned SubIdx,
932 const MachineInstr *Orig,
933 const TargetRegisterInfo &TRI) const {
934 unsigned Opcode = Orig->getOpcode();
937 MachineInstr *MI = MBB.getParent()->CloneMachineInstr(Orig);
938 MI->substituteRegister(Orig->getOperand(0).getReg(), DestReg, SubIdx, TRI);
942 case ARM::tLDRpci_pic:
943 case ARM::t2LDRpci_pic: {
944 MachineFunction &MF = *MBB.getParent();
945 unsigned CPI = Orig->getOperand(1).getIndex();
946 unsigned PCLabelId = duplicateCPV(MF, CPI);
947 MachineInstrBuilder MIB = BuildMI(MBB, I, Orig->getDebugLoc(), get(Opcode),
949 .addConstantPoolIndex(CPI).addImm(PCLabelId);
950 (*MIB).setMemRefs(Orig->memoperands_begin(), Orig->memoperands_end());
957 ARMBaseInstrInfo::duplicate(MachineInstr *Orig, MachineFunction &MF) const {
958 MachineInstr *MI = TargetInstrInfoImpl::duplicate(Orig, MF);
959 switch(Orig->getOpcode()) {
960 case ARM::tLDRpci_pic:
961 case ARM::t2LDRpci_pic: {
962 unsigned CPI = Orig->getOperand(1).getIndex();
963 unsigned PCLabelId = duplicateCPV(MF, CPI);
964 Orig->getOperand(1).setIndex(CPI);
965 Orig->getOperand(2).setImm(PCLabelId);
972 bool ARMBaseInstrInfo::produceSameValue(const MachineInstr *MI0,
973 const MachineInstr *MI1) const {
974 int Opcode = MI0->getOpcode();
975 if (Opcode == ARM::t2LDRpci ||
976 Opcode == ARM::t2LDRpci_pic ||
977 Opcode == ARM::tLDRpci ||
978 Opcode == ARM::tLDRpci_pic) {
979 if (MI1->getOpcode() != Opcode)
981 if (MI0->getNumOperands() != MI1->getNumOperands())
984 const MachineOperand &MO0 = MI0->getOperand(1);
985 const MachineOperand &MO1 = MI1->getOperand(1);
986 if (MO0.getOffset() != MO1.getOffset())
989 const MachineFunction *MF = MI0->getParent()->getParent();
990 const MachineConstantPool *MCP = MF->getConstantPool();
991 int CPI0 = MO0.getIndex();
992 int CPI1 = MO1.getIndex();
993 const MachineConstantPoolEntry &MCPE0 = MCP->getConstants()[CPI0];
994 const MachineConstantPoolEntry &MCPE1 = MCP->getConstants()[CPI1];
995 ARMConstantPoolValue *ACPV0 =
996 static_cast<ARMConstantPoolValue*>(MCPE0.Val.MachineCPVal);
997 ARMConstantPoolValue *ACPV1 =
998 static_cast<ARMConstantPoolValue*>(MCPE1.Val.MachineCPVal);
999 return ACPV0->hasSameValue(ACPV1);
1002 return MI0->isIdenticalTo(MI1, MachineInstr::IgnoreVRegDefs);
1005 /// areLoadsFromSameBasePtr - This is used by the pre-regalloc scheduler to
1006 /// determine if two loads are loading from the same base address. It should
1007 /// only return true if the base pointers are the same and the only differences
1008 /// between the two addresses is the offset. It also returns the offsets by
1010 bool ARMBaseInstrInfo::areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2,
1012 int64_t &Offset2) const {
1013 // Don't worry about Thumb: just ARM and Thumb2.
1014 if (Subtarget.isThumb1Only()) return false;
1016 if (!Load1->isMachineOpcode() || !Load2->isMachineOpcode())
1019 switch (Load1->getMachineOpcode()) {
1032 case ARM::t2LDRSHi8:
1034 case ARM::t2LDRSHi12:
1038 switch (Load2->getMachineOpcode()) {
1051 case ARM::t2LDRSHi8:
1053 case ARM::t2LDRSHi12:
1057 // Check if base addresses and chain operands match.
1058 if (Load1->getOperand(0) != Load2->getOperand(0) ||
1059 Load1->getOperand(4) != Load2->getOperand(4))
1062 // Index should be Reg0.
1063 if (Load1->getOperand(3) != Load2->getOperand(3))
1066 // Determine the offsets.
1067 if (isa<ConstantSDNode>(Load1->getOperand(1)) &&
1068 isa<ConstantSDNode>(Load2->getOperand(1))) {
1069 Offset1 = cast<ConstantSDNode>(Load1->getOperand(1))->getSExtValue();
1070 Offset2 = cast<ConstantSDNode>(Load2->getOperand(1))->getSExtValue();
1077 /// shouldScheduleLoadsNear - This is a used by the pre-regalloc scheduler to
1078 /// determine (in conjuction with areLoadsFromSameBasePtr) if two loads should
1079 /// be scheduled togther. On some targets if two loads are loading from
1080 /// addresses in the same cache line, it's better if they are scheduled
1081 /// together. This function takes two integers that represent the load offsets
1082 /// from the common base address. It returns true if it decides it's desirable
1083 /// to schedule the two loads together. "NumLoads" is the number of loads that
1084 /// have already been scheduled after Load1.
1085 bool ARMBaseInstrInfo::shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,
1086 int64_t Offset1, int64_t Offset2,
1087 unsigned NumLoads) const {
1088 // Don't worry about Thumb: just ARM and Thumb2.
1089 if (Subtarget.isThumb1Only()) return false;
1091 assert(Offset2 > Offset1);
1093 if ((Offset2 - Offset1) / 8 > 64)
1096 if (Load1->getMachineOpcode() != Load2->getMachineOpcode())
1097 return false; // FIXME: overly conservative?
1099 // Four loads in a row should be sufficient.
1106 bool ARMBaseInstrInfo::isSchedulingBoundary(const MachineInstr *MI,
1107 const MachineBasicBlock *MBB,
1108 const MachineFunction &MF) const {
1109 // Debug info is never a scheduling boundary. It's necessary to be explicit
1110 // due to the special treatment of IT instructions below, otherwise a
1111 // dbg_value followed by an IT will result in the IT instruction being
1112 // considered a scheduling hazard, which is wrong. It should be the actual
1113 // instruction preceding the dbg_value instruction(s), just like it is
1114 // when debug info is not present.
1115 if (MI->isDebugValue())
1118 // Terminators and labels can't be scheduled around.
1119 if (MI->getDesc().isTerminator() || MI->isLabel())
1122 // Treat the start of the IT block as a scheduling boundary, but schedule
1123 // t2IT along with all instructions following it.
1124 // FIXME: This is a big hammer. But the alternative is to add all potential
1125 // true and anti dependencies to IT block instructions as implicit operands
1126 // to the t2IT instruction. The added compile time and complexity does not
1128 MachineBasicBlock::const_iterator I = MI;
1129 // Make sure to skip any dbg_value instructions
1130 while (++I != MBB->end() && I->isDebugValue())
1132 if (I != MBB->end() && I->getOpcode() == ARM::t2IT)
1135 // Don't attempt to schedule around any instruction that defines
1136 // a stack-oriented pointer, as it's unlikely to be profitable. This
1137 // saves compile time, because it doesn't require every single
1138 // stack slot reference to depend on the instruction that does the
1140 if (MI->definesRegister(ARM::SP))
1146 bool ARMBaseInstrInfo::
1147 isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumInstrs) const {
1150 if (Subtarget.getCPUString() == "generic")
1151 // Generic (and overly aggressive) if-conversion limits for testing.
1152 return NumInstrs <= 10;
1153 else if (Subtarget.hasV7Ops())
1154 return NumInstrs <= 3;
1155 return NumInstrs <= 2;
1158 bool ARMBaseInstrInfo::
1159 isProfitableToIfCvt(MachineBasicBlock &TMBB, unsigned NumT,
1160 MachineBasicBlock &FMBB, unsigned NumF) const {
1161 return NumT && NumF && NumT <= 2 && NumF <= 2;
1164 /// getInstrPredicate - If instruction is predicated, returns its predicate
1165 /// condition, otherwise returns AL. It also returns the condition code
1166 /// register by reference.
1168 llvm::getInstrPredicate(const MachineInstr *MI, unsigned &PredReg) {
1169 int PIdx = MI->findFirstPredOperandIdx();
1175 PredReg = MI->getOperand(PIdx+1).getReg();
1176 return (ARMCC::CondCodes)MI->getOperand(PIdx).getImm();
1180 int llvm::getMatchingCondBranchOpcode(int Opc) {
1183 else if (Opc == ARM::tB)
1185 else if (Opc == ARM::t2B)
1188 llvm_unreachable("Unknown unconditional branch opcode!");
1193 void llvm::emitARMRegPlusImmediate(MachineBasicBlock &MBB,
1194 MachineBasicBlock::iterator &MBBI, DebugLoc dl,
1195 unsigned DestReg, unsigned BaseReg, int NumBytes,
1196 ARMCC::CondCodes Pred, unsigned PredReg,
1197 const ARMBaseInstrInfo &TII) {
1198 bool isSub = NumBytes < 0;
1199 if (isSub) NumBytes = -NumBytes;
1202 unsigned RotAmt = ARM_AM::getSOImmValRotate(NumBytes);
1203 unsigned ThisVal = NumBytes & ARM_AM::rotr32(0xFF, RotAmt);
1204 assert(ThisVal && "Didn't extract field correctly");
1206 // We will handle these bits from offset, clear them.
1207 NumBytes &= ~ThisVal;
1209 assert(ARM_AM::getSOImmVal(ThisVal) != -1 && "Bit extraction didn't work?");
1211 // Build the new ADD / SUB.
1212 unsigned Opc = isSub ? ARM::SUBri : ARM::ADDri;
1213 BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg)
1214 .addReg(BaseReg, RegState::Kill).addImm(ThisVal)
1215 .addImm((unsigned)Pred).addReg(PredReg).addReg(0);
1220 bool llvm::rewriteARMFrameIndex(MachineInstr &MI, unsigned FrameRegIdx,
1221 unsigned FrameReg, int &Offset,
1222 const ARMBaseInstrInfo &TII) {
1223 unsigned Opcode = MI.getOpcode();
1224 const TargetInstrDesc &Desc = MI.getDesc();
1225 unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
1228 // Memory operands in inline assembly always use AddrMode2.
1229 if (Opcode == ARM::INLINEASM)
1230 AddrMode = ARMII::AddrMode2;
1232 if (Opcode == ARM::ADDri) {
1233 Offset += MI.getOperand(FrameRegIdx+1).getImm();
1235 // Turn it into a move.
1236 MI.setDesc(TII.get(ARM::MOVr));
1237 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
1238 MI.RemoveOperand(FrameRegIdx+1);
1241 } else if (Offset < 0) {
1244 MI.setDesc(TII.get(ARM::SUBri));
1247 // Common case: small offset, fits into instruction.
1248 if (ARM_AM::getSOImmVal(Offset) != -1) {
1249 // Replace the FrameIndex with sp / fp
1250 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
1251 MI.getOperand(FrameRegIdx+1).ChangeToImmediate(Offset);
1256 // Otherwise, pull as much of the immedidate into this ADDri/SUBri
1258 unsigned RotAmt = ARM_AM::getSOImmValRotate(Offset);
1259 unsigned ThisImmVal = Offset & ARM_AM::rotr32(0xFF, RotAmt);
1261 // We will handle these bits from offset, clear them.
1262 Offset &= ~ThisImmVal;
1264 // Get the properly encoded SOImmVal field.
1265 assert(ARM_AM::getSOImmVal(ThisImmVal) != -1 &&
1266 "Bit extraction didn't work?");
1267 MI.getOperand(FrameRegIdx+1).ChangeToImmediate(ThisImmVal);
1269 unsigned ImmIdx = 0;
1271 unsigned NumBits = 0;
1274 case ARMII::AddrMode2: {
1275 ImmIdx = FrameRegIdx+2;
1276 InstrOffs = ARM_AM::getAM2Offset(MI.getOperand(ImmIdx).getImm());
1277 if (ARM_AM::getAM2Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub)
1282 case ARMII::AddrMode3: {
1283 ImmIdx = FrameRegIdx+2;
1284 InstrOffs = ARM_AM::getAM3Offset(MI.getOperand(ImmIdx).getImm());
1285 if (ARM_AM::getAM3Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub)
1290 case ARMII::AddrMode4:
1291 case ARMII::AddrMode6:
1292 // Can't fold any offset even if it's zero.
1294 case ARMII::AddrMode5: {
1295 ImmIdx = FrameRegIdx+1;
1296 InstrOffs = ARM_AM::getAM5Offset(MI.getOperand(ImmIdx).getImm());
1297 if (ARM_AM::getAM5Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub)
1304 llvm_unreachable("Unsupported addressing mode!");
1308 Offset += InstrOffs * Scale;
1309 assert((Offset & (Scale-1)) == 0 && "Can't encode this offset!");
1315 // Attempt to fold address comp. if opcode has offset bits
1317 // Common case: small offset, fits into instruction.
1318 MachineOperand &ImmOp = MI.getOperand(ImmIdx);
1319 int ImmedOffset = Offset / Scale;
1320 unsigned Mask = (1 << NumBits) - 1;
1321 if ((unsigned)Offset <= Mask * Scale) {
1322 // Replace the FrameIndex with sp
1323 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
1325 ImmedOffset |= 1 << NumBits;
1326 ImmOp.ChangeToImmediate(ImmedOffset);
1331 // Otherwise, it didn't fit. Pull in what we can to simplify the immed.
1332 ImmedOffset = ImmedOffset & Mask;
1334 ImmedOffset |= 1 << NumBits;
1335 ImmOp.ChangeToImmediate(ImmedOffset);
1336 Offset &= ~(Mask*Scale);
1340 Offset = (isSub) ? -Offset : Offset;
1344 bool ARMBaseInstrInfo::
1345 AnalyzeCompare(const MachineInstr *MI, unsigned &SrcReg, int &CmpValue) const {
1346 switch (MI->getOpcode()) {
1352 SrcReg = MI->getOperand(0).getReg();
1353 CmpValue = MI->getOperand(1).getImm();
1356 MachineBasicBlock::const_iterator MII(MI);
1357 if (MI->getParent()->begin() == MII)
1359 const MachineInstr *AND = llvm::prior(MII);
1360 if (AND->getOpcode() != ARM::ANDri)
1362 if (MI->getOperand(0).getReg() == AND->getOperand(1).getReg() &&
1363 MI->getOperand(1).getImm() == AND->getOperand(2).getImm()) {
1364 SrcReg = AND->getOperand(0).getReg();
1375 /// OptimizeCompareInstr - Convert the instruction supplying the argument to the
1376 /// comparison into one that sets the zero bit in the flags register. Update the
1377 /// iterator *only* if a transformation took place.
1378 bool ARMBaseInstrInfo::
1379 OptimizeCompareInstr(MachineInstr *CmpInstr, unsigned SrcReg, int CmpValue,
1380 MachineBasicBlock::iterator &MII) const {
1384 MachineRegisterInfo &MRI = CmpInstr->getParent()->getParent()->getRegInfo();
1385 MachineRegisterInfo::def_iterator DI = MRI.def_begin(SrcReg);
1386 if (llvm::next(DI) != MRI.def_end())
1387 // Only support one definition.
1390 MachineInstr *MI = &*DI;
1392 // Conservatively refuse to convert an instruction which isn't in the same BB
1393 // as the comparison.
1394 if (MI->getParent() != CmpInstr->getParent())
1397 // Check that CPSR isn't set between the comparison instruction and the one we
1399 MachineBasicBlock::const_iterator I = CmpInstr, E = MI;
1401 for (; I != E; --I) {
1402 const MachineInstr &Instr = *I;
1404 for (unsigned IO = 0, EO = Instr.getNumOperands(); IO != EO; ++IO) {
1405 const MachineOperand &MO = Instr.getOperand(IO);
1406 if (!MO.isReg() || !MO.isDef()) continue;
1408 // This instruction modifies CPSR before the one we want to change. We
1409 // can't do this transformation.
1410 if (MO.getReg() == ARM::CPSR)
1415 // Set the "zero" bit in CPSR.
1416 switch (MI->getOpcode()) {
1424 MI->RemoveOperand(5);
1425 MachineInstrBuilder(MI)
1426 .addReg(ARM::CPSR, RegState::Define | RegState::Implicit);
1427 MII = llvm::next(MachineBasicBlock::iterator(CmpInstr));
1428 CmpInstr->eraseFromParent();
1436 ARMBaseInstrInfo::getNumMicroOps(const MachineInstr *MI,
1437 const InstrItineraryData *ItinData) const {
1438 if (!ItinData || ItinData->isEmpty())
1441 const TargetInstrDesc &Desc = MI->getDesc();
1442 unsigned Class = Desc.getSchedClass();
1443 unsigned UOps = ItinData->Itineraries[Class].NumMicroOps;
1447 unsigned Opc = MI->getOpcode();
1450 llvm_unreachable("Unexpected multi-uops instruction!");
1456 // The number of uOps for load / store multiple are determined by the number
1458 // On Cortex-A8, each pair of register loads / stores can be scheduled on the
1459 // same cycle. The scheduling for the first load / store must be done
1460 // separately by assuming the the address is not 64-bit aligned.
1461 // On Cortex-A9, the formula is simply (#reg / 2) + (#reg % 2). If the address
1462 // is not 64-bit aligned, then AGU would take an extra cycle.
1463 // For VFP / NEON load / store multiple, the formula is
1464 // (#reg / 2) + (#reg % 2) + 1.
1467 case ARM::VLDMD_UPD:
1468 case ARM::VLDMS_UPD:
1471 case ARM::VSTMD_UPD:
1472 case ARM::VSTMS_UPD: {
1473 unsigned NumRegs = MI->getNumOperands() - Desc.getNumOperands();
1474 return (NumRegs / 2) + (NumRegs % 2) + 1;
1487 case ARM::t2LDM_RET:
1489 case ARM::t2LDM_UPD:
1491 case ARM::t2STM_UPD: {
1492 unsigned NumRegs = MI->getNumOperands() - Desc.getNumOperands() + 1;
1493 if (Subtarget.isCortexA8()) {
1494 // 4 registers would be issued: 1, 2, 1.
1495 // 5 registers would be issued: 1, 2, 2.
1496 return 1 + (NumRegs / 2);
1497 } else if (Subtarget.isCortexA9()) {
1498 UOps = (NumRegs / 2);
1499 // If there are odd number of registers or if it's not 64-bit aligned,
1500 // then it takes an extra AGU (Address Generation Unit) cycle.
1501 if ((NumRegs % 2) ||
1502 !MI->hasOneMemOperand() ||
1503 (*MI->memoperands_begin())->getAlignment() < 8)
1507 // Assume the worst.