1 //===-- ARMBaseInstrInfo.cpp - ARM Instruction Information ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Base ARM implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
15 #include "ARMBaseInstrInfo.h"
16 #include "ARMBaseRegisterInfo.h"
17 #include "ARMConstantPoolValue.h"
18 #include "ARMFeatures.h"
19 #include "ARMHazardRecognizer.h"
20 #include "ARMMachineFunctionInfo.h"
21 #include "MCTargetDesc/ARMAddressingModes.h"
22 #include "llvm/ADT/STLExtras.h"
23 #include "llvm/CodeGen/LiveVariables.h"
24 #include "llvm/CodeGen/MachineConstantPool.h"
25 #include "llvm/CodeGen/MachineFrameInfo.h"
26 #include "llvm/CodeGen/MachineInstrBuilder.h"
27 #include "llvm/CodeGen/MachineJumpTableInfo.h"
28 #include "llvm/CodeGen/MachineMemOperand.h"
29 #include "llvm/CodeGen/MachineRegisterInfo.h"
30 #include "llvm/CodeGen/SelectionDAGNodes.h"
31 #include "llvm/CodeGen/TargetSchedule.h"
32 #include "llvm/IR/Constants.h"
33 #include "llvm/IR/Function.h"
34 #include "llvm/IR/GlobalValue.h"
35 #include "llvm/MC/MCAsmInfo.h"
36 #include "llvm/MC/MCExpr.h"
37 #include "llvm/Support/BranchProbability.h"
38 #include "llvm/Support/CommandLine.h"
39 #include "llvm/Support/Debug.h"
40 #include "llvm/Support/ErrorHandling.h"
41 #include "llvm/Support/raw_ostream.h"
45 #define DEBUG_TYPE "arm-instrinfo"
47 #define GET_INSTRINFO_CTOR_DTOR
48 #include "ARMGenInstrInfo.inc"
51 EnableARM3Addr("enable-arm-3-addr-conv", cl::Hidden,
52 cl::desc("Enable ARM 2-addr to 3-addr conv"));
55 WidenVMOVS("widen-vmovs", cl::Hidden, cl::init(true),
56 cl::desc("Widen ARM vmovs to vmovd when possible"));
58 static cl::opt<unsigned>
59 SwiftPartialUpdateClearance("swift-partial-update-clearance",
60 cl::Hidden, cl::init(12),
61 cl::desc("Clearance before partial register updates"));
63 /// ARM_MLxEntry - Record information about MLA / MLS instructions.
65 uint16_t MLxOpc; // MLA / MLS opcode
66 uint16_t MulOpc; // Expanded multiplication opcode
67 uint16_t AddSubOpc; // Expanded add / sub opcode
68 bool NegAcc; // True if the acc is negated before the add / sub.
69 bool HasLane; // True if instruction has an extra "lane" operand.
72 static const ARM_MLxEntry ARM_MLxTable[] = {
73 // MLxOpc, MulOpc, AddSubOpc, NegAcc, HasLane
75 { ARM::VMLAS, ARM::VMULS, ARM::VADDS, false, false },
76 { ARM::VMLSS, ARM::VMULS, ARM::VSUBS, false, false },
77 { ARM::VMLAD, ARM::VMULD, ARM::VADDD, false, false },
78 { ARM::VMLSD, ARM::VMULD, ARM::VSUBD, false, false },
79 { ARM::VNMLAS, ARM::VNMULS, ARM::VSUBS, true, false },
80 { ARM::VNMLSS, ARM::VMULS, ARM::VSUBS, true, false },
81 { ARM::VNMLAD, ARM::VNMULD, ARM::VSUBD, true, false },
82 { ARM::VNMLSD, ARM::VMULD, ARM::VSUBD, true, false },
85 { ARM::VMLAfd, ARM::VMULfd, ARM::VADDfd, false, false },
86 { ARM::VMLSfd, ARM::VMULfd, ARM::VSUBfd, false, false },
87 { ARM::VMLAfq, ARM::VMULfq, ARM::VADDfq, false, false },
88 { ARM::VMLSfq, ARM::VMULfq, ARM::VSUBfq, false, false },
89 { ARM::VMLAslfd, ARM::VMULslfd, ARM::VADDfd, false, true },
90 { ARM::VMLSslfd, ARM::VMULslfd, ARM::VSUBfd, false, true },
91 { ARM::VMLAslfq, ARM::VMULslfq, ARM::VADDfq, false, true },
92 { ARM::VMLSslfq, ARM::VMULslfq, ARM::VSUBfq, false, true },
95 ARMBaseInstrInfo::ARMBaseInstrInfo(const ARMSubtarget& STI)
96 : ARMGenInstrInfo(ARM::ADJCALLSTACKDOWN, ARM::ADJCALLSTACKUP),
98 for (unsigned i = 0, e = array_lengthof(ARM_MLxTable); i != e; ++i) {
99 if (!MLxEntryMap.insert(std::make_pair(ARM_MLxTable[i].MLxOpc, i)).second)
100 assert(false && "Duplicated entries?");
101 MLxHazardOpcodes.insert(ARM_MLxTable[i].AddSubOpc);
102 MLxHazardOpcodes.insert(ARM_MLxTable[i].MulOpc);
106 // Use a ScoreboardHazardRecognizer for prepass ARM scheduling. TargetInstrImpl
107 // currently defaults to no prepass hazard recognizer.
108 ScheduleHazardRecognizer *
109 ARMBaseInstrInfo::CreateTargetHazardRecognizer(const TargetSubtargetInfo *STI,
110 const ScheduleDAG *DAG) const {
111 if (usePreRAHazardRecognizer()) {
112 const InstrItineraryData *II =
113 static_cast<const ARMSubtarget *>(STI)->getInstrItineraryData();
114 return new ScoreboardHazardRecognizer(II, DAG, "pre-RA-sched");
116 return TargetInstrInfo::CreateTargetHazardRecognizer(STI, DAG);
119 ScheduleHazardRecognizer *ARMBaseInstrInfo::
120 CreateTargetPostRAHazardRecognizer(const InstrItineraryData *II,
121 const ScheduleDAG *DAG) const {
122 if (Subtarget.isThumb2() || Subtarget.hasVFP2())
123 return (ScheduleHazardRecognizer *)new ARMHazardRecognizer(II, DAG);
124 return TargetInstrInfo::CreateTargetPostRAHazardRecognizer(II, DAG);
128 ARMBaseInstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
129 MachineBasicBlock::iterator &MBBI,
130 LiveVariables *LV) const {
131 // FIXME: Thumb2 support.
136 MachineInstr *MI = MBBI;
137 MachineFunction &MF = *MI->getParent()->getParent();
138 uint64_t TSFlags = MI->getDesc().TSFlags;
140 switch ((TSFlags & ARMII::IndexModeMask) >> ARMII::IndexModeShift) {
141 default: return nullptr;
142 case ARMII::IndexModePre:
145 case ARMII::IndexModePost:
149 // Try splitting an indexed load/store to an un-indexed one plus an add/sub
151 unsigned MemOpc = getUnindexedOpcode(MI->getOpcode());
155 MachineInstr *UpdateMI = nullptr;
156 MachineInstr *MemMI = nullptr;
157 unsigned AddrMode = (TSFlags & ARMII::AddrModeMask);
158 const MCInstrDesc &MCID = MI->getDesc();
159 unsigned NumOps = MCID.getNumOperands();
160 bool isLoad = !MI->mayStore();
161 const MachineOperand &WB = isLoad ? MI->getOperand(1) : MI->getOperand(0);
162 const MachineOperand &Base = MI->getOperand(2);
163 const MachineOperand &Offset = MI->getOperand(NumOps-3);
164 unsigned WBReg = WB.getReg();
165 unsigned BaseReg = Base.getReg();
166 unsigned OffReg = Offset.getReg();
167 unsigned OffImm = MI->getOperand(NumOps-2).getImm();
168 ARMCC::CondCodes Pred = (ARMCC::CondCodes)MI->getOperand(NumOps-1).getImm();
170 default: llvm_unreachable("Unknown indexed op!");
171 case ARMII::AddrMode2: {
172 bool isSub = ARM_AM::getAM2Op(OffImm) == ARM_AM::sub;
173 unsigned Amt = ARM_AM::getAM2Offset(OffImm);
175 if (ARM_AM::getSOImmVal(Amt) == -1)
176 // Can't encode it in a so_imm operand. This transformation will
177 // add more than 1 instruction. Abandon!
179 UpdateMI = BuildMI(MF, MI->getDebugLoc(),
180 get(isSub ? ARM::SUBri : ARM::ADDri), WBReg)
181 .addReg(BaseReg).addImm(Amt)
182 .addImm(Pred).addReg(0).addReg(0);
183 } else if (Amt != 0) {
184 ARM_AM::ShiftOpc ShOpc = ARM_AM::getAM2ShiftOpc(OffImm);
185 unsigned SOOpc = ARM_AM::getSORegOpc(ShOpc, Amt);
186 UpdateMI = BuildMI(MF, MI->getDebugLoc(),
187 get(isSub ? ARM::SUBrsi : ARM::ADDrsi), WBReg)
188 .addReg(BaseReg).addReg(OffReg).addReg(0).addImm(SOOpc)
189 .addImm(Pred).addReg(0).addReg(0);
191 UpdateMI = BuildMI(MF, MI->getDebugLoc(),
192 get(isSub ? ARM::SUBrr : ARM::ADDrr), WBReg)
193 .addReg(BaseReg).addReg(OffReg)
194 .addImm(Pred).addReg(0).addReg(0);
197 case ARMII::AddrMode3 : {
198 bool isSub = ARM_AM::getAM3Op(OffImm) == ARM_AM::sub;
199 unsigned Amt = ARM_AM::getAM3Offset(OffImm);
201 // Immediate is 8-bits. It's guaranteed to fit in a so_imm operand.
202 UpdateMI = BuildMI(MF, MI->getDebugLoc(),
203 get(isSub ? ARM::SUBri : ARM::ADDri), WBReg)
204 .addReg(BaseReg).addImm(Amt)
205 .addImm(Pred).addReg(0).addReg(0);
207 UpdateMI = BuildMI(MF, MI->getDebugLoc(),
208 get(isSub ? ARM::SUBrr : ARM::ADDrr), WBReg)
209 .addReg(BaseReg).addReg(OffReg)
210 .addImm(Pred).addReg(0).addReg(0);
215 std::vector<MachineInstr*> NewMIs;
218 MemMI = BuildMI(MF, MI->getDebugLoc(),
219 get(MemOpc), MI->getOperand(0).getReg())
220 .addReg(WBReg).addImm(0).addImm(Pred);
222 MemMI = BuildMI(MF, MI->getDebugLoc(),
223 get(MemOpc)).addReg(MI->getOperand(1).getReg())
224 .addReg(WBReg).addReg(0).addImm(0).addImm(Pred);
225 NewMIs.push_back(MemMI);
226 NewMIs.push_back(UpdateMI);
229 MemMI = BuildMI(MF, MI->getDebugLoc(),
230 get(MemOpc), MI->getOperand(0).getReg())
231 .addReg(BaseReg).addImm(0).addImm(Pred);
233 MemMI = BuildMI(MF, MI->getDebugLoc(),
234 get(MemOpc)).addReg(MI->getOperand(1).getReg())
235 .addReg(BaseReg).addReg(0).addImm(0).addImm(Pred);
237 UpdateMI->getOperand(0).setIsDead();
238 NewMIs.push_back(UpdateMI);
239 NewMIs.push_back(MemMI);
242 // Transfer LiveVariables states, kill / dead info.
244 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
245 MachineOperand &MO = MI->getOperand(i);
246 if (MO.isReg() && TargetRegisterInfo::isVirtualRegister(MO.getReg())) {
247 unsigned Reg = MO.getReg();
249 LiveVariables::VarInfo &VI = LV->getVarInfo(Reg);
251 MachineInstr *NewMI = (Reg == WBReg) ? UpdateMI : MemMI;
253 LV->addVirtualRegisterDead(Reg, NewMI);
255 if (MO.isUse() && MO.isKill()) {
256 for (unsigned j = 0; j < 2; ++j) {
257 // Look at the two new MI's in reverse order.
258 MachineInstr *NewMI = NewMIs[j];
259 if (!NewMI->readsRegister(Reg))
261 LV->addVirtualRegisterKilled(Reg, NewMI);
262 if (VI.removeKill(MI))
263 VI.Kills.push_back(NewMI);
271 MFI->insert(MBBI, NewMIs[1]);
272 MFI->insert(MBBI, NewMIs[0]);
278 ARMBaseInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB,
279 MachineBasicBlock *&FBB,
280 SmallVectorImpl<MachineOperand> &Cond,
281 bool AllowModify) const {
285 MachineBasicBlock::iterator I = MBB.end();
286 if (I == MBB.begin())
287 return false; // Empty blocks are easy.
290 // Walk backwards from the end of the basic block until the branch is
291 // analyzed or we give up.
292 while (isPredicated(I) || I->isTerminator() || I->isDebugValue()) {
294 // Flag to be raised on unanalyzeable instructions. This is useful in cases
295 // where we want to clean up on the end of the basic block before we bail
297 bool CantAnalyze = false;
299 // Skip over DEBUG values and predicated nonterminators.
300 while (I->isDebugValue() || !I->isTerminator()) {
301 if (I == MBB.begin())
306 if (isIndirectBranchOpcode(I->getOpcode()) ||
307 isJumpTableBranchOpcode(I->getOpcode())) {
308 // Indirect branches and jump tables can't be analyzed, but we still want
309 // to clean up any instructions at the tail of the basic block.
311 } else if (isUncondBranchOpcode(I->getOpcode())) {
312 TBB = I->getOperand(0).getMBB();
313 } else if (isCondBranchOpcode(I->getOpcode())) {
314 // Bail out if we encounter multiple conditional branches.
318 assert(!FBB && "FBB should have been null.");
320 TBB = I->getOperand(0).getMBB();
321 Cond.push_back(I->getOperand(1));
322 Cond.push_back(I->getOperand(2));
323 } else if (I->isReturn()) {
324 // Returns can't be analyzed, but we should run cleanup.
325 CantAnalyze = !isPredicated(I);
327 // We encountered other unrecognized terminator. Bail out immediately.
331 // Cleanup code - to be run for unpredicated unconditional branches and
333 if (!isPredicated(I) &&
334 (isUncondBranchOpcode(I->getOpcode()) ||
335 isIndirectBranchOpcode(I->getOpcode()) ||
336 isJumpTableBranchOpcode(I->getOpcode()) ||
338 // Forget any previous condition branch information - it no longer applies.
342 // If we can modify the function, delete everything below this
343 // unconditional branch.
345 MachineBasicBlock::iterator DI = std::next(I);
346 while (DI != MBB.end()) {
347 MachineInstr *InstToDelete = DI;
349 InstToDelete->eraseFromParent();
357 if (I == MBB.begin())
363 // We made it past the terminators without bailing out - we must have
364 // analyzed this branch successfully.
369 unsigned ARMBaseInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
370 MachineBasicBlock::iterator I = MBB.getLastNonDebugInstr();
374 if (!isUncondBranchOpcode(I->getOpcode()) &&
375 !isCondBranchOpcode(I->getOpcode()))
378 // Remove the branch.
379 I->eraseFromParent();
383 if (I == MBB.begin()) return 1;
385 if (!isCondBranchOpcode(I->getOpcode()))
388 // Remove the branch.
389 I->eraseFromParent();
394 ARMBaseInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
395 MachineBasicBlock *FBB,
396 ArrayRef<MachineOperand> Cond,
398 ARMFunctionInfo *AFI = MBB.getParent()->getInfo<ARMFunctionInfo>();
399 int BOpc = !AFI->isThumbFunction()
400 ? ARM::B : (AFI->isThumb2Function() ? ARM::t2B : ARM::tB);
401 int BccOpc = !AFI->isThumbFunction()
402 ? ARM::Bcc : (AFI->isThumb2Function() ? ARM::t2Bcc : ARM::tBcc);
403 bool isThumb = AFI->isThumbFunction() || AFI->isThumb2Function();
405 // Shouldn't be a fall through.
406 assert(TBB && "InsertBranch must not be told to insert a fallthrough");
407 assert((Cond.size() == 2 || Cond.size() == 0) &&
408 "ARM branch conditions have two components!");
410 // For conditional branches, we use addOperand to preserve CPSR flags.
413 if (Cond.empty()) { // Unconditional branch?
415 BuildMI(&MBB, DL, get(BOpc)).addMBB(TBB).addImm(ARMCC::AL).addReg(0);
417 BuildMI(&MBB, DL, get(BOpc)).addMBB(TBB);
419 BuildMI(&MBB, DL, get(BccOpc)).addMBB(TBB)
420 .addImm(Cond[0].getImm()).addOperand(Cond[1]);
424 // Two-way conditional branch.
425 BuildMI(&MBB, DL, get(BccOpc)).addMBB(TBB)
426 .addImm(Cond[0].getImm()).addOperand(Cond[1]);
428 BuildMI(&MBB, DL, get(BOpc)).addMBB(FBB).addImm(ARMCC::AL).addReg(0);
430 BuildMI(&MBB, DL, get(BOpc)).addMBB(FBB);
434 bool ARMBaseInstrInfo::
435 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
436 ARMCC::CondCodes CC = (ARMCC::CondCodes)(int)Cond[0].getImm();
437 Cond[0].setImm(ARMCC::getOppositeCondition(CC));
441 bool ARMBaseInstrInfo::isPredicated(const MachineInstr *MI) const {
442 if (MI->isBundle()) {
443 MachineBasicBlock::const_instr_iterator I = MI;
444 MachineBasicBlock::const_instr_iterator E = MI->getParent()->instr_end();
445 while (++I != E && I->isInsideBundle()) {
446 int PIdx = I->findFirstPredOperandIdx();
447 if (PIdx != -1 && I->getOperand(PIdx).getImm() != ARMCC::AL)
453 int PIdx = MI->findFirstPredOperandIdx();
454 return PIdx != -1 && MI->getOperand(PIdx).getImm() != ARMCC::AL;
457 bool ARMBaseInstrInfo::
458 PredicateInstruction(MachineInstr *MI, ArrayRef<MachineOperand> Pred) const {
459 unsigned Opc = MI->getOpcode();
460 if (isUncondBranchOpcode(Opc)) {
461 MI->setDesc(get(getMatchingCondBranchOpcode(Opc)));
462 MachineInstrBuilder(*MI->getParent()->getParent(), MI)
463 .addImm(Pred[0].getImm())
464 .addReg(Pred[1].getReg());
468 int PIdx = MI->findFirstPredOperandIdx();
470 MachineOperand &PMO = MI->getOperand(PIdx);
471 PMO.setImm(Pred[0].getImm());
472 MI->getOperand(PIdx+1).setReg(Pred[1].getReg());
478 bool ARMBaseInstrInfo::SubsumesPredicate(ArrayRef<MachineOperand> Pred1,
479 ArrayRef<MachineOperand> Pred2) const {
480 if (Pred1.size() > 2 || Pred2.size() > 2)
483 ARMCC::CondCodes CC1 = (ARMCC::CondCodes)Pred1[0].getImm();
484 ARMCC::CondCodes CC2 = (ARMCC::CondCodes)Pred2[0].getImm();
494 return CC2 == ARMCC::HI;
496 return CC2 == ARMCC::LO || CC2 == ARMCC::EQ;
498 return CC2 == ARMCC::GT;
500 return CC2 == ARMCC::LT;
504 bool ARMBaseInstrInfo::DefinesPredicate(MachineInstr *MI,
505 std::vector<MachineOperand> &Pred) const {
507 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
508 const MachineOperand &MO = MI->getOperand(i);
509 if ((MO.isRegMask() && MO.clobbersPhysReg(ARM::CPSR)) ||
510 (MO.isReg() && MO.isDef() && MO.getReg() == ARM::CPSR)) {
519 static bool isCPSRDefined(const MachineInstr *MI) {
520 for (const auto &MO : MI->operands())
521 if (MO.isReg() && MO.getReg() == ARM::CPSR && MO.isDef() && !MO.isDead())
526 static bool isEligibleForITBlock(const MachineInstr *MI) {
527 switch (MI->getOpcode()) {
528 default: return true;
529 case ARM::tADC: // ADC (register) T1
530 case ARM::tADDi3: // ADD (immediate) T1
531 case ARM::tADDi8: // ADD (immediate) T2
532 case ARM::tADDrr: // ADD (register) T1
533 case ARM::tAND: // AND (register) T1
534 case ARM::tASRri: // ASR (immediate) T1
535 case ARM::tASRrr: // ASR (register) T1
536 case ARM::tBIC: // BIC (register) T1
537 case ARM::tEOR: // EOR (register) T1
538 case ARM::tLSLri: // LSL (immediate) T1
539 case ARM::tLSLrr: // LSL (register) T1
540 case ARM::tLSRri: // LSR (immediate) T1
541 case ARM::tLSRrr: // LSR (register) T1
542 case ARM::tMUL: // MUL T1
543 case ARM::tMVN: // MVN (register) T1
544 case ARM::tORR: // ORR (register) T1
545 case ARM::tROR: // ROR (register) T1
546 case ARM::tRSB: // RSB (immediate) T1
547 case ARM::tSBC: // SBC (register) T1
548 case ARM::tSUBi3: // SUB (immediate) T1
549 case ARM::tSUBi8: // SUB (immediate) T2
550 case ARM::tSUBrr: // SUB (register) T1
551 return !isCPSRDefined(MI);
555 /// isPredicable - Return true if the specified instruction can be predicated.
556 /// By default, this returns true for every instruction with a
557 /// PredicateOperand.
558 bool ARMBaseInstrInfo::isPredicable(MachineInstr *MI) const {
559 if (!MI->isPredicable())
562 if (!isEligibleForITBlock(MI))
565 ARMFunctionInfo *AFI =
566 MI->getParent()->getParent()->getInfo<ARMFunctionInfo>();
568 if (AFI->isThumb2Function()) {
569 if (getSubtarget().restrictIT())
570 return isV8EligibleForIT(MI);
571 } else { // non-Thumb
572 if ((MI->getDesc().TSFlags & ARMII::DomainMask) == ARMII::DomainNEON)
580 template <> bool IsCPSRDead<MachineInstr>(MachineInstr *MI) {
581 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
582 const MachineOperand &MO = MI->getOperand(i);
583 if (!MO.isReg() || MO.isUndef() || MO.isUse())
585 if (MO.getReg() != ARM::CPSR)
590 // all definitions of CPSR are dead
595 /// GetInstSize - Return the size of the specified MachineInstr.
597 unsigned ARMBaseInstrInfo::GetInstSizeInBytes(const MachineInstr *MI) const {
598 const MachineBasicBlock &MBB = *MI->getParent();
599 const MachineFunction *MF = MBB.getParent();
600 const MCAsmInfo *MAI = MF->getTarget().getMCAsmInfo();
602 const MCInstrDesc &MCID = MI->getDesc();
604 return MCID.getSize();
606 // If this machine instr is an inline asm, measure it.
607 if (MI->getOpcode() == ARM::INLINEASM)
608 return getInlineAsmLength(MI->getOperand(0).getSymbolName(), *MAI);
609 unsigned Opc = MI->getOpcode();
612 // pseudo-instruction sizes are zero.
614 case TargetOpcode::BUNDLE:
615 return getInstBundleLength(MI);
616 case ARM::MOVi16_ga_pcrel:
617 case ARM::MOVTi16_ga_pcrel:
618 case ARM::t2MOVi16_ga_pcrel:
619 case ARM::t2MOVTi16_ga_pcrel:
622 case ARM::t2MOVi32imm:
624 case ARM::CONSTPOOL_ENTRY:
625 case ARM::JUMPTABLE_INSTS:
626 case ARM::JUMPTABLE_ADDRS:
627 case ARM::JUMPTABLE_TBB:
628 case ARM::JUMPTABLE_TBH:
629 // If this machine instr is a constant pool entry, its size is recorded as
631 return MI->getOperand(2).getImm();
632 case ARM::Int_eh_sjlj_longjmp:
634 case ARM::tInt_eh_sjlj_longjmp:
636 case ARM::Int_eh_sjlj_setjmp:
637 case ARM::Int_eh_sjlj_setjmp_nofp:
639 case ARM::tInt_eh_sjlj_setjmp:
640 case ARM::t2Int_eh_sjlj_setjmp:
641 case ARM::t2Int_eh_sjlj_setjmp_nofp:
644 return MI->getOperand(1).getImm();
648 unsigned ARMBaseInstrInfo::getInstBundleLength(const MachineInstr *MI) const {
650 MachineBasicBlock::const_instr_iterator I = MI;
651 MachineBasicBlock::const_instr_iterator E = MI->getParent()->instr_end();
652 while (++I != E && I->isInsideBundle()) {
653 assert(!I->isBundle() && "No nested bundle!");
654 Size += GetInstSizeInBytes(&*I);
659 void ARMBaseInstrInfo::copyFromCPSR(MachineBasicBlock &MBB,
660 MachineBasicBlock::iterator I,
661 unsigned DestReg, bool KillSrc,
662 const ARMSubtarget &Subtarget) const {
663 unsigned Opc = Subtarget.isThumb()
664 ? (Subtarget.isMClass() ? ARM::t2MRS_M : ARM::t2MRS_AR)
667 MachineInstrBuilder MIB =
668 BuildMI(MBB, I, I->getDebugLoc(), get(Opc), DestReg);
670 // There is only 1 A/R class MRS instruction, and it always refers to
671 // APSR. However, there are lots of other possibilities on M-class cores.
672 if (Subtarget.isMClass())
677 MIB.addReg(ARM::CPSR, RegState::Implicit | getKillRegState(KillSrc));
680 void ARMBaseInstrInfo::copyToCPSR(MachineBasicBlock &MBB,
681 MachineBasicBlock::iterator I,
682 unsigned SrcReg, bool KillSrc,
683 const ARMSubtarget &Subtarget) const {
684 unsigned Opc = Subtarget.isThumb()
685 ? (Subtarget.isMClass() ? ARM::t2MSR_M : ARM::t2MSR_AR)
688 MachineInstrBuilder MIB = BuildMI(MBB, I, I->getDebugLoc(), get(Opc));
690 if (Subtarget.isMClass())
695 MIB.addReg(SrcReg, getKillRegState(KillSrc));
699 MIB.addReg(ARM::CPSR, RegState::Implicit | RegState::Define);
702 void ARMBaseInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
703 MachineBasicBlock::iterator I, DebugLoc DL,
704 unsigned DestReg, unsigned SrcReg,
705 bool KillSrc) const {
706 bool GPRDest = ARM::GPRRegClass.contains(DestReg);
707 bool GPRSrc = ARM::GPRRegClass.contains(SrcReg);
709 if (GPRDest && GPRSrc) {
710 AddDefaultCC(AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::MOVr), DestReg)
711 .addReg(SrcReg, getKillRegState(KillSrc))));
715 bool SPRDest = ARM::SPRRegClass.contains(DestReg);
716 bool SPRSrc = ARM::SPRRegClass.contains(SrcReg);
719 if (SPRDest && SPRSrc)
721 else if (GPRDest && SPRSrc)
723 else if (SPRDest && GPRSrc)
725 else if (ARM::DPRRegClass.contains(DestReg, SrcReg) && !Subtarget.isFPOnlySP())
727 else if (ARM::QPRRegClass.contains(DestReg, SrcReg))
731 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(Opc), DestReg);
732 MIB.addReg(SrcReg, getKillRegState(KillSrc));
733 if (Opc == ARM::VORRq)
734 MIB.addReg(SrcReg, getKillRegState(KillSrc));
739 // Handle register classes that require multiple instructions.
740 unsigned BeginIdx = 0;
741 unsigned SubRegs = 0;
744 // Use VORRq when possible.
745 if (ARM::QQPRRegClass.contains(DestReg, SrcReg)) {
747 BeginIdx = ARM::qsub_0;
749 } else if (ARM::QQQQPRRegClass.contains(DestReg, SrcReg)) {
751 BeginIdx = ARM::qsub_0;
753 // Fall back to VMOVD.
754 } else if (ARM::DPairRegClass.contains(DestReg, SrcReg)) {
756 BeginIdx = ARM::dsub_0;
758 } else if (ARM::DTripleRegClass.contains(DestReg, SrcReg)) {
760 BeginIdx = ARM::dsub_0;
762 } else if (ARM::DQuadRegClass.contains(DestReg, SrcReg)) {
764 BeginIdx = ARM::dsub_0;
766 } else if (ARM::GPRPairRegClass.contains(DestReg, SrcReg)) {
767 Opc = Subtarget.isThumb2() ? ARM::tMOVr : ARM::MOVr;
768 BeginIdx = ARM::gsub_0;
770 } else if (ARM::DPairSpcRegClass.contains(DestReg, SrcReg)) {
772 BeginIdx = ARM::dsub_0;
775 } else if (ARM::DTripleSpcRegClass.contains(DestReg, SrcReg)) {
777 BeginIdx = ARM::dsub_0;
780 } else if (ARM::DQuadSpcRegClass.contains(DestReg, SrcReg)) {
782 BeginIdx = ARM::dsub_0;
785 } else if (ARM::DPRRegClass.contains(DestReg, SrcReg) && Subtarget.isFPOnlySP()) {
787 BeginIdx = ARM::ssub_0;
789 } else if (SrcReg == ARM::CPSR) {
790 copyFromCPSR(MBB, I, DestReg, KillSrc, Subtarget);
792 } else if (DestReg == ARM::CPSR) {
793 copyToCPSR(MBB, I, SrcReg, KillSrc, Subtarget);
797 assert(Opc && "Impossible reg-to-reg copy");
799 const TargetRegisterInfo *TRI = &getRegisterInfo();
800 MachineInstrBuilder Mov;
802 // Copy register tuples backward when the first Dest reg overlaps with SrcReg.
803 if (TRI->regsOverlap(SrcReg, TRI->getSubReg(DestReg, BeginIdx))) {
804 BeginIdx = BeginIdx + ((SubRegs - 1) * Spacing);
808 SmallSet<unsigned, 4> DstRegs;
810 for (unsigned i = 0; i != SubRegs; ++i) {
811 unsigned Dst = TRI->getSubReg(DestReg, BeginIdx + i * Spacing);
812 unsigned Src = TRI->getSubReg(SrcReg, BeginIdx + i * Spacing);
813 assert(Dst && Src && "Bad sub-register");
815 assert(!DstRegs.count(Src) && "destructive vector copy");
818 Mov = BuildMI(MBB, I, I->getDebugLoc(), get(Opc), Dst).addReg(Src);
819 // VORR takes two source operands.
820 if (Opc == ARM::VORRq)
822 Mov = AddDefaultPred(Mov);
824 if (Opc == ARM::MOVr)
825 Mov = AddDefaultCC(Mov);
827 // Add implicit super-register defs and kills to the last instruction.
828 Mov->addRegisterDefined(DestReg, TRI);
830 Mov->addRegisterKilled(SrcReg, TRI);
833 const MachineInstrBuilder &
834 ARMBaseInstrInfo::AddDReg(MachineInstrBuilder &MIB, unsigned Reg,
835 unsigned SubIdx, unsigned State,
836 const TargetRegisterInfo *TRI) const {
838 return MIB.addReg(Reg, State);
840 if (TargetRegisterInfo::isPhysicalRegister(Reg))
841 return MIB.addReg(TRI->getSubReg(Reg, SubIdx), State);
842 return MIB.addReg(Reg, State, SubIdx);
845 void ARMBaseInstrInfo::
846 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
847 unsigned SrcReg, bool isKill, int FI,
848 const TargetRegisterClass *RC,
849 const TargetRegisterInfo *TRI) const {
851 if (I != MBB.end()) DL = I->getDebugLoc();
852 MachineFunction &MF = *MBB.getParent();
853 MachineFrameInfo &MFI = *MF.getFrameInfo();
854 unsigned Align = MFI.getObjectAlignment(FI);
856 MachineMemOperand *MMO =
857 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(FI),
858 MachineMemOperand::MOStore,
859 MFI.getObjectSize(FI),
862 switch (RC->getSize()) {
864 if (ARM::GPRRegClass.hasSubClassEq(RC)) {
865 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::STRi12))
866 .addReg(SrcReg, getKillRegState(isKill))
867 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
868 } else if (ARM::SPRRegClass.hasSubClassEq(RC)) {
869 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTRS))
870 .addReg(SrcReg, getKillRegState(isKill))
871 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
873 llvm_unreachable("Unknown reg class!");
876 if (ARM::DPRRegClass.hasSubClassEq(RC)) {
877 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTRD))
878 .addReg(SrcReg, getKillRegState(isKill))
879 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
880 } else if (ARM::GPRPairRegClass.hasSubClassEq(RC)) {
881 if (Subtarget.hasV5TEOps()) {
882 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(ARM::STRD));
883 AddDReg(MIB, SrcReg, ARM::gsub_0, getKillRegState(isKill), TRI);
884 AddDReg(MIB, SrcReg, ARM::gsub_1, 0, TRI);
885 MIB.addFrameIndex(FI).addReg(0).addImm(0).addMemOperand(MMO);
889 // Fallback to STM instruction, which has existed since the dawn of
891 MachineInstrBuilder MIB =
892 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::STMIA))
893 .addFrameIndex(FI).addMemOperand(MMO));
894 AddDReg(MIB, SrcReg, ARM::gsub_0, getKillRegState(isKill), TRI);
895 AddDReg(MIB, SrcReg, ARM::gsub_1, 0, TRI);
898 llvm_unreachable("Unknown reg class!");
901 if (ARM::DPairRegClass.hasSubClassEq(RC)) {
902 // Use aligned spills if the stack can be realigned.
903 if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) {
904 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VST1q64))
905 .addFrameIndex(FI).addImm(16)
906 .addReg(SrcReg, getKillRegState(isKill))
907 .addMemOperand(MMO));
909 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTMQIA))
910 .addReg(SrcReg, getKillRegState(isKill))
912 .addMemOperand(MMO));
915 llvm_unreachable("Unknown reg class!");
918 if (ARM::DTripleRegClass.hasSubClassEq(RC)) {
919 // Use aligned spills if the stack can be realigned.
920 if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) {
921 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VST1d64TPseudo))
922 .addFrameIndex(FI).addImm(16)
923 .addReg(SrcReg, getKillRegState(isKill))
924 .addMemOperand(MMO));
926 MachineInstrBuilder MIB =
927 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTMDIA))
930 MIB = AddDReg(MIB, SrcReg, ARM::dsub_0, getKillRegState(isKill), TRI);
931 MIB = AddDReg(MIB, SrcReg, ARM::dsub_1, 0, TRI);
932 AddDReg(MIB, SrcReg, ARM::dsub_2, 0, TRI);
935 llvm_unreachable("Unknown reg class!");
938 if (ARM::QQPRRegClass.hasSubClassEq(RC) || ARM::DQuadRegClass.hasSubClassEq(RC)) {
939 if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) {
940 // FIXME: It's possible to only store part of the QQ register if the
941 // spilled def has a sub-register index.
942 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VST1d64QPseudo))
943 .addFrameIndex(FI).addImm(16)
944 .addReg(SrcReg, getKillRegState(isKill))
945 .addMemOperand(MMO));
947 MachineInstrBuilder MIB =
948 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTMDIA))
951 MIB = AddDReg(MIB, SrcReg, ARM::dsub_0, getKillRegState(isKill), TRI);
952 MIB = AddDReg(MIB, SrcReg, ARM::dsub_1, 0, TRI);
953 MIB = AddDReg(MIB, SrcReg, ARM::dsub_2, 0, TRI);
954 AddDReg(MIB, SrcReg, ARM::dsub_3, 0, TRI);
957 llvm_unreachable("Unknown reg class!");
960 if (ARM::QQQQPRRegClass.hasSubClassEq(RC)) {
961 MachineInstrBuilder MIB =
962 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTMDIA))
965 MIB = AddDReg(MIB, SrcReg, ARM::dsub_0, getKillRegState(isKill), TRI);
966 MIB = AddDReg(MIB, SrcReg, ARM::dsub_1, 0, TRI);
967 MIB = AddDReg(MIB, SrcReg, ARM::dsub_2, 0, TRI);
968 MIB = AddDReg(MIB, SrcReg, ARM::dsub_3, 0, TRI);
969 MIB = AddDReg(MIB, SrcReg, ARM::dsub_4, 0, TRI);
970 MIB = AddDReg(MIB, SrcReg, ARM::dsub_5, 0, TRI);
971 MIB = AddDReg(MIB, SrcReg, ARM::dsub_6, 0, TRI);
972 AddDReg(MIB, SrcReg, ARM::dsub_7, 0, TRI);
974 llvm_unreachable("Unknown reg class!");
977 llvm_unreachable("Unknown reg class!");
982 ARMBaseInstrInfo::isStoreToStackSlot(const MachineInstr *MI,
983 int &FrameIndex) const {
984 switch (MI->getOpcode()) {
987 case ARM::t2STRs: // FIXME: don't use t2STRs to access frame.
988 if (MI->getOperand(1).isFI() &&
989 MI->getOperand(2).isReg() &&
990 MI->getOperand(3).isImm() &&
991 MI->getOperand(2).getReg() == 0 &&
992 MI->getOperand(3).getImm() == 0) {
993 FrameIndex = MI->getOperand(1).getIndex();
994 return MI->getOperand(0).getReg();
1002 if (MI->getOperand(1).isFI() &&
1003 MI->getOperand(2).isImm() &&
1004 MI->getOperand(2).getImm() == 0) {
1005 FrameIndex = MI->getOperand(1).getIndex();
1006 return MI->getOperand(0).getReg();
1010 case ARM::VST1d64TPseudo:
1011 case ARM::VST1d64QPseudo:
1012 if (MI->getOperand(0).isFI() &&
1013 MI->getOperand(2).getSubReg() == 0) {
1014 FrameIndex = MI->getOperand(0).getIndex();
1015 return MI->getOperand(2).getReg();
1019 if (MI->getOperand(1).isFI() &&
1020 MI->getOperand(0).getSubReg() == 0) {
1021 FrameIndex = MI->getOperand(1).getIndex();
1022 return MI->getOperand(0).getReg();
1030 unsigned ARMBaseInstrInfo::isStoreToStackSlotPostFE(const MachineInstr *MI,
1031 int &FrameIndex) const {
1032 const MachineMemOperand *Dummy;
1033 return MI->mayStore() && hasStoreToStackSlot(MI, Dummy, FrameIndex);
1036 void ARMBaseInstrInfo::
1037 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
1038 unsigned DestReg, int FI,
1039 const TargetRegisterClass *RC,
1040 const TargetRegisterInfo *TRI) const {
1042 if (I != MBB.end()) DL = I->getDebugLoc();
1043 MachineFunction &MF = *MBB.getParent();
1044 MachineFrameInfo &MFI = *MF.getFrameInfo();
1045 unsigned Align = MFI.getObjectAlignment(FI);
1046 MachineMemOperand *MMO =
1047 MF.getMachineMemOperand(
1048 MachinePointerInfo::getFixedStack(FI),
1049 MachineMemOperand::MOLoad,
1050 MFI.getObjectSize(FI),
1053 switch (RC->getSize()) {
1055 if (ARM::GPRRegClass.hasSubClassEq(RC)) {
1056 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::LDRi12), DestReg)
1057 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
1059 } else if (ARM::SPRRegClass.hasSubClassEq(RC)) {
1060 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDRS), DestReg)
1061 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
1063 llvm_unreachable("Unknown reg class!");
1066 if (ARM::DPRRegClass.hasSubClassEq(RC)) {
1067 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDRD), DestReg)
1068 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
1069 } else if (ARM::GPRPairRegClass.hasSubClassEq(RC)) {
1070 MachineInstrBuilder MIB;
1072 if (Subtarget.hasV5TEOps()) {
1073 MIB = BuildMI(MBB, I, DL, get(ARM::LDRD));
1074 AddDReg(MIB, DestReg, ARM::gsub_0, RegState::DefineNoRead, TRI);
1075 AddDReg(MIB, DestReg, ARM::gsub_1, RegState::DefineNoRead, TRI);
1076 MIB.addFrameIndex(FI).addReg(0).addImm(0).addMemOperand(MMO);
1078 AddDefaultPred(MIB);
1080 // Fallback to LDM instruction, which has existed since the dawn of
1082 MIB = AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::LDMIA))
1083 .addFrameIndex(FI).addMemOperand(MMO));
1084 MIB = AddDReg(MIB, DestReg, ARM::gsub_0, RegState::DefineNoRead, TRI);
1085 MIB = AddDReg(MIB, DestReg, ARM::gsub_1, RegState::DefineNoRead, TRI);
1088 if (TargetRegisterInfo::isPhysicalRegister(DestReg))
1089 MIB.addReg(DestReg, RegState::ImplicitDefine);
1091 llvm_unreachable("Unknown reg class!");
1094 if (ARM::DPairRegClass.hasSubClassEq(RC)) {
1095 if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) {
1096 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLD1q64), DestReg)
1097 .addFrameIndex(FI).addImm(16)
1098 .addMemOperand(MMO));
1100 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDMQIA), DestReg)
1102 .addMemOperand(MMO));
1105 llvm_unreachable("Unknown reg class!");
1108 if (ARM::DTripleRegClass.hasSubClassEq(RC)) {
1109 if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) {
1110 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLD1d64TPseudo), DestReg)
1111 .addFrameIndex(FI).addImm(16)
1112 .addMemOperand(MMO));
1114 MachineInstrBuilder MIB =
1115 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDMDIA))
1117 .addMemOperand(MMO));
1118 MIB = AddDReg(MIB, DestReg, ARM::dsub_0, RegState::DefineNoRead, TRI);
1119 MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::DefineNoRead, TRI);
1120 MIB = AddDReg(MIB, DestReg, ARM::dsub_2, RegState::DefineNoRead, TRI);
1121 if (TargetRegisterInfo::isPhysicalRegister(DestReg))
1122 MIB.addReg(DestReg, RegState::ImplicitDefine);
1125 llvm_unreachable("Unknown reg class!");
1128 if (ARM::QQPRRegClass.hasSubClassEq(RC) || ARM::DQuadRegClass.hasSubClassEq(RC)) {
1129 if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) {
1130 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLD1d64QPseudo), DestReg)
1131 .addFrameIndex(FI).addImm(16)
1132 .addMemOperand(MMO));
1134 MachineInstrBuilder MIB =
1135 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDMDIA))
1137 .addMemOperand(MMO);
1138 MIB = AddDReg(MIB, DestReg, ARM::dsub_0, RegState::DefineNoRead, TRI);
1139 MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::DefineNoRead, TRI);
1140 MIB = AddDReg(MIB, DestReg, ARM::dsub_2, RegState::DefineNoRead, TRI);
1141 MIB = AddDReg(MIB, DestReg, ARM::dsub_3, RegState::DefineNoRead, TRI);
1142 if (TargetRegisterInfo::isPhysicalRegister(DestReg))
1143 MIB.addReg(DestReg, RegState::ImplicitDefine);
1146 llvm_unreachable("Unknown reg class!");
1149 if (ARM::QQQQPRRegClass.hasSubClassEq(RC)) {
1150 MachineInstrBuilder MIB =
1151 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDMDIA))
1153 .addMemOperand(MMO);
1154 MIB = AddDReg(MIB, DestReg, ARM::dsub_0, RegState::DefineNoRead, TRI);
1155 MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::DefineNoRead, TRI);
1156 MIB = AddDReg(MIB, DestReg, ARM::dsub_2, RegState::DefineNoRead, TRI);
1157 MIB = AddDReg(MIB, DestReg, ARM::dsub_3, RegState::DefineNoRead, TRI);
1158 MIB = AddDReg(MIB, DestReg, ARM::dsub_4, RegState::DefineNoRead, TRI);
1159 MIB = AddDReg(MIB, DestReg, ARM::dsub_5, RegState::DefineNoRead, TRI);
1160 MIB = AddDReg(MIB, DestReg, ARM::dsub_6, RegState::DefineNoRead, TRI);
1161 MIB = AddDReg(MIB, DestReg, ARM::dsub_7, RegState::DefineNoRead, TRI);
1162 if (TargetRegisterInfo::isPhysicalRegister(DestReg))
1163 MIB.addReg(DestReg, RegState::ImplicitDefine);
1165 llvm_unreachable("Unknown reg class!");
1168 llvm_unreachable("Unknown regclass!");
1173 ARMBaseInstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
1174 int &FrameIndex) const {
1175 switch (MI->getOpcode()) {
1178 case ARM::t2LDRs: // FIXME: don't use t2LDRs to access frame.
1179 if (MI->getOperand(1).isFI() &&
1180 MI->getOperand(2).isReg() &&
1181 MI->getOperand(3).isImm() &&
1182 MI->getOperand(2).getReg() == 0 &&
1183 MI->getOperand(3).getImm() == 0) {
1184 FrameIndex = MI->getOperand(1).getIndex();
1185 return MI->getOperand(0).getReg();
1193 if (MI->getOperand(1).isFI() &&
1194 MI->getOperand(2).isImm() &&
1195 MI->getOperand(2).getImm() == 0) {
1196 FrameIndex = MI->getOperand(1).getIndex();
1197 return MI->getOperand(0).getReg();
1201 case ARM::VLD1d64TPseudo:
1202 case ARM::VLD1d64QPseudo:
1203 if (MI->getOperand(1).isFI() &&
1204 MI->getOperand(0).getSubReg() == 0) {
1205 FrameIndex = MI->getOperand(1).getIndex();
1206 return MI->getOperand(0).getReg();
1210 if (MI->getOperand(1).isFI() &&
1211 MI->getOperand(0).getSubReg() == 0) {
1212 FrameIndex = MI->getOperand(1).getIndex();
1213 return MI->getOperand(0).getReg();
1221 unsigned ARMBaseInstrInfo::isLoadFromStackSlotPostFE(const MachineInstr *MI,
1222 int &FrameIndex) const {
1223 const MachineMemOperand *Dummy;
1224 return MI->mayLoad() && hasLoadFromStackSlot(MI, Dummy, FrameIndex);
1228 ARMBaseInstrInfo::expandPostRAPseudo(MachineBasicBlock::iterator MI) const {
1229 MachineFunction &MF = *MI->getParent()->getParent();
1230 Reloc::Model RM = MF.getTarget().getRelocationModel();
1232 if (MI->getOpcode() == TargetOpcode::LOAD_STACK_GUARD) {
1233 assert(getSubtarget().getTargetTriple().isOSBinFormatMachO() &&
1234 "LOAD_STACK_GUARD currently supported only for MachO.");
1235 expandLoadStackGuard(MI, RM);
1236 MI->getParent()->erase(MI);
1240 // This hook gets to expand COPY instructions before they become
1241 // copyPhysReg() calls. Look for VMOVS instructions that can legally be
1242 // widened to VMOVD. We prefer the VMOVD when possible because it may be
1243 // changed into a VORR that can go down the NEON pipeline.
1244 if (!WidenVMOVS || !MI->isCopy() || Subtarget.isCortexA15() ||
1245 Subtarget.isFPOnlySP())
1248 // Look for a copy between even S-registers. That is where we keep floats
1249 // when using NEON v2f32 instructions for f32 arithmetic.
1250 unsigned DstRegS = MI->getOperand(0).getReg();
1251 unsigned SrcRegS = MI->getOperand(1).getReg();
1252 if (!ARM::SPRRegClass.contains(DstRegS, SrcRegS))
1255 const TargetRegisterInfo *TRI = &getRegisterInfo();
1256 unsigned DstRegD = TRI->getMatchingSuperReg(DstRegS, ARM::ssub_0,
1258 unsigned SrcRegD = TRI->getMatchingSuperReg(SrcRegS, ARM::ssub_0,
1260 if (!DstRegD || !SrcRegD)
1263 // We want to widen this into a DstRegD = VMOVD SrcRegD copy. This is only
1264 // legal if the COPY already defines the full DstRegD, and it isn't a
1265 // sub-register insertion.
1266 if (!MI->definesRegister(DstRegD, TRI) || MI->readsRegister(DstRegD, TRI))
1269 // A dead copy shouldn't show up here, but reject it just in case.
1270 if (MI->getOperand(0).isDead())
1273 // All clear, widen the COPY.
1274 DEBUG(dbgs() << "widening: " << *MI);
1275 MachineInstrBuilder MIB(*MI->getParent()->getParent(), MI);
1277 // Get rid of the old <imp-def> of DstRegD. Leave it if it defines a Q-reg
1278 // or some other super-register.
1279 int ImpDefIdx = MI->findRegisterDefOperandIdx(DstRegD);
1280 if (ImpDefIdx != -1)
1281 MI->RemoveOperand(ImpDefIdx);
1283 // Change the opcode and operands.
1284 MI->setDesc(get(ARM::VMOVD));
1285 MI->getOperand(0).setReg(DstRegD);
1286 MI->getOperand(1).setReg(SrcRegD);
1287 AddDefaultPred(MIB);
1289 // We are now reading SrcRegD instead of SrcRegS. This may upset the
1290 // register scavenger and machine verifier, so we need to indicate that we
1291 // are reading an undefined value from SrcRegD, but a proper value from
1293 MI->getOperand(1).setIsUndef();
1294 MIB.addReg(SrcRegS, RegState::Implicit);
1296 // SrcRegD may actually contain an unrelated value in the ssub_1
1297 // sub-register. Don't kill it. Only kill the ssub_0 sub-register.
1298 if (MI->getOperand(1).isKill()) {
1299 MI->getOperand(1).setIsKill(false);
1300 MI->addRegisterKilled(SrcRegS, TRI, true);
1303 DEBUG(dbgs() << "replaced by: " << *MI);
1307 /// Create a copy of a const pool value. Update CPI to the new index and return
1309 static unsigned duplicateCPV(MachineFunction &MF, unsigned &CPI) {
1310 MachineConstantPool *MCP = MF.getConstantPool();
1311 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1313 const MachineConstantPoolEntry &MCPE = MCP->getConstants()[CPI];
1314 assert(MCPE.isMachineConstantPoolEntry() &&
1315 "Expecting a machine constantpool entry!");
1316 ARMConstantPoolValue *ACPV =
1317 static_cast<ARMConstantPoolValue*>(MCPE.Val.MachineCPVal);
1319 unsigned PCLabelId = AFI->createPICLabelUId();
1320 ARMConstantPoolValue *NewCPV = nullptr;
1322 // FIXME: The below assumes PIC relocation model and that the function
1323 // is Thumb mode (t1 or t2). PCAdjustment would be 8 for ARM mode PIC, and
1324 // zero for non-PIC in ARM or Thumb. The callers are all of thumb LDR
1325 // instructions, so that's probably OK, but is PIC always correct when
1327 if (ACPV->isGlobalValue())
1328 NewCPV = ARMConstantPoolConstant::
1329 Create(cast<ARMConstantPoolConstant>(ACPV)->getGV(), PCLabelId,
1331 else if (ACPV->isExtSymbol())
1332 NewCPV = ARMConstantPoolSymbol::
1333 Create(MF.getFunction()->getContext(),
1334 cast<ARMConstantPoolSymbol>(ACPV)->getSymbol(), PCLabelId, 4);
1335 else if (ACPV->isBlockAddress())
1336 NewCPV = ARMConstantPoolConstant::
1337 Create(cast<ARMConstantPoolConstant>(ACPV)->getBlockAddress(), PCLabelId,
1338 ARMCP::CPBlockAddress, 4);
1339 else if (ACPV->isLSDA())
1340 NewCPV = ARMConstantPoolConstant::Create(MF.getFunction(), PCLabelId,
1342 else if (ACPV->isMachineBasicBlock())
1343 NewCPV = ARMConstantPoolMBB::
1344 Create(MF.getFunction()->getContext(),
1345 cast<ARMConstantPoolMBB>(ACPV)->getMBB(), PCLabelId, 4);
1347 llvm_unreachable("Unexpected ARM constantpool value type!!");
1348 CPI = MCP->getConstantPoolIndex(NewCPV, MCPE.getAlignment());
1352 void ARMBaseInstrInfo::
1353 reMaterialize(MachineBasicBlock &MBB,
1354 MachineBasicBlock::iterator I,
1355 unsigned DestReg, unsigned SubIdx,
1356 const MachineInstr *Orig,
1357 const TargetRegisterInfo &TRI) const {
1358 unsigned Opcode = Orig->getOpcode();
1361 MachineInstr *MI = MBB.getParent()->CloneMachineInstr(Orig);
1362 MI->substituteRegister(Orig->getOperand(0).getReg(), DestReg, SubIdx, TRI);
1366 case ARM::tLDRpci_pic:
1367 case ARM::t2LDRpci_pic: {
1368 MachineFunction &MF = *MBB.getParent();
1369 unsigned CPI = Orig->getOperand(1).getIndex();
1370 unsigned PCLabelId = duplicateCPV(MF, CPI);
1371 MachineInstrBuilder MIB = BuildMI(MBB, I, Orig->getDebugLoc(), get(Opcode),
1373 .addConstantPoolIndex(CPI).addImm(PCLabelId);
1374 MIB->setMemRefs(Orig->memoperands_begin(), Orig->memoperands_end());
1381 ARMBaseInstrInfo::duplicate(MachineInstr *Orig, MachineFunction &MF) const {
1382 MachineInstr *MI = TargetInstrInfo::duplicate(Orig, MF);
1383 switch(Orig->getOpcode()) {
1384 case ARM::tLDRpci_pic:
1385 case ARM::t2LDRpci_pic: {
1386 unsigned CPI = Orig->getOperand(1).getIndex();
1387 unsigned PCLabelId = duplicateCPV(MF, CPI);
1388 Orig->getOperand(1).setIndex(CPI);
1389 Orig->getOperand(2).setImm(PCLabelId);
1396 bool ARMBaseInstrInfo::produceSameValue(const MachineInstr *MI0,
1397 const MachineInstr *MI1,
1398 const MachineRegisterInfo *MRI) const {
1399 unsigned Opcode = MI0->getOpcode();
1400 if (Opcode == ARM::t2LDRpci ||
1401 Opcode == ARM::t2LDRpci_pic ||
1402 Opcode == ARM::tLDRpci ||
1403 Opcode == ARM::tLDRpci_pic ||
1404 Opcode == ARM::LDRLIT_ga_pcrel ||
1405 Opcode == ARM::LDRLIT_ga_pcrel_ldr ||
1406 Opcode == ARM::tLDRLIT_ga_pcrel ||
1407 Opcode == ARM::MOV_ga_pcrel ||
1408 Opcode == ARM::MOV_ga_pcrel_ldr ||
1409 Opcode == ARM::t2MOV_ga_pcrel) {
1410 if (MI1->getOpcode() != Opcode)
1412 if (MI0->getNumOperands() != MI1->getNumOperands())
1415 const MachineOperand &MO0 = MI0->getOperand(1);
1416 const MachineOperand &MO1 = MI1->getOperand(1);
1417 if (MO0.getOffset() != MO1.getOffset())
1420 if (Opcode == ARM::LDRLIT_ga_pcrel ||
1421 Opcode == ARM::LDRLIT_ga_pcrel_ldr ||
1422 Opcode == ARM::tLDRLIT_ga_pcrel ||
1423 Opcode == ARM::MOV_ga_pcrel ||
1424 Opcode == ARM::MOV_ga_pcrel_ldr ||
1425 Opcode == ARM::t2MOV_ga_pcrel)
1426 // Ignore the PC labels.
1427 return MO0.getGlobal() == MO1.getGlobal();
1429 const MachineFunction *MF = MI0->getParent()->getParent();
1430 const MachineConstantPool *MCP = MF->getConstantPool();
1431 int CPI0 = MO0.getIndex();
1432 int CPI1 = MO1.getIndex();
1433 const MachineConstantPoolEntry &MCPE0 = MCP->getConstants()[CPI0];
1434 const MachineConstantPoolEntry &MCPE1 = MCP->getConstants()[CPI1];
1435 bool isARMCP0 = MCPE0.isMachineConstantPoolEntry();
1436 bool isARMCP1 = MCPE1.isMachineConstantPoolEntry();
1437 if (isARMCP0 && isARMCP1) {
1438 ARMConstantPoolValue *ACPV0 =
1439 static_cast<ARMConstantPoolValue*>(MCPE0.Val.MachineCPVal);
1440 ARMConstantPoolValue *ACPV1 =
1441 static_cast<ARMConstantPoolValue*>(MCPE1.Val.MachineCPVal);
1442 return ACPV0->hasSameValue(ACPV1);
1443 } else if (!isARMCP0 && !isARMCP1) {
1444 return MCPE0.Val.ConstVal == MCPE1.Val.ConstVal;
1447 } else if (Opcode == ARM::PICLDR) {
1448 if (MI1->getOpcode() != Opcode)
1450 if (MI0->getNumOperands() != MI1->getNumOperands())
1453 unsigned Addr0 = MI0->getOperand(1).getReg();
1454 unsigned Addr1 = MI1->getOperand(1).getReg();
1455 if (Addr0 != Addr1) {
1457 !TargetRegisterInfo::isVirtualRegister(Addr0) ||
1458 !TargetRegisterInfo::isVirtualRegister(Addr1))
1461 // This assumes SSA form.
1462 MachineInstr *Def0 = MRI->getVRegDef(Addr0);
1463 MachineInstr *Def1 = MRI->getVRegDef(Addr1);
1464 // Check if the loaded value, e.g. a constantpool of a global address, are
1466 if (!produceSameValue(Def0, Def1, MRI))
1470 for (unsigned i = 3, e = MI0->getNumOperands(); i != e; ++i) {
1471 // %vreg12<def> = PICLDR %vreg11, 0, pred:14, pred:%noreg
1472 const MachineOperand &MO0 = MI0->getOperand(i);
1473 const MachineOperand &MO1 = MI1->getOperand(i);
1474 if (!MO0.isIdenticalTo(MO1))
1480 return MI0->isIdenticalTo(MI1, MachineInstr::IgnoreVRegDefs);
1483 /// areLoadsFromSameBasePtr - This is used by the pre-regalloc scheduler to
1484 /// determine if two loads are loading from the same base address. It should
1485 /// only return true if the base pointers are the same and the only differences
1486 /// between the two addresses is the offset. It also returns the offsets by
1489 /// FIXME: remove this in favor of the MachineInstr interface once pre-RA-sched
1490 /// is permanently disabled.
1491 bool ARMBaseInstrInfo::areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2,
1493 int64_t &Offset2) const {
1494 // Don't worry about Thumb: just ARM and Thumb2.
1495 if (Subtarget.isThumb1Only()) return false;
1497 if (!Load1->isMachineOpcode() || !Load2->isMachineOpcode())
1500 switch (Load1->getMachineOpcode()) {
1514 case ARM::t2LDRSHi8:
1516 case ARM::t2LDRBi12:
1517 case ARM::t2LDRSHi12:
1521 switch (Load2->getMachineOpcode()) {
1534 case ARM::t2LDRSHi8:
1536 case ARM::t2LDRBi12:
1537 case ARM::t2LDRSHi12:
1541 // Check if base addresses and chain operands match.
1542 if (Load1->getOperand(0) != Load2->getOperand(0) ||
1543 Load1->getOperand(4) != Load2->getOperand(4))
1546 // Index should be Reg0.
1547 if (Load1->getOperand(3) != Load2->getOperand(3))
1550 // Determine the offsets.
1551 if (isa<ConstantSDNode>(Load1->getOperand(1)) &&
1552 isa<ConstantSDNode>(Load2->getOperand(1))) {
1553 Offset1 = cast<ConstantSDNode>(Load1->getOperand(1))->getSExtValue();
1554 Offset2 = cast<ConstantSDNode>(Load2->getOperand(1))->getSExtValue();
1561 /// shouldScheduleLoadsNear - This is a used by the pre-regalloc scheduler to
1562 /// determine (in conjunction with areLoadsFromSameBasePtr) if two loads should
1563 /// be scheduled togther. On some targets if two loads are loading from
1564 /// addresses in the same cache line, it's better if they are scheduled
1565 /// together. This function takes two integers that represent the load offsets
1566 /// from the common base address. It returns true if it decides it's desirable
1567 /// to schedule the two loads together. "NumLoads" is the number of loads that
1568 /// have already been scheduled after Load1.
1570 /// FIXME: remove this in favor of the MachineInstr interface once pre-RA-sched
1571 /// is permanently disabled.
1572 bool ARMBaseInstrInfo::shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,
1573 int64_t Offset1, int64_t Offset2,
1574 unsigned NumLoads) const {
1575 // Don't worry about Thumb: just ARM and Thumb2.
1576 if (Subtarget.isThumb1Only()) return false;
1578 assert(Offset2 > Offset1);
1580 if ((Offset2 - Offset1) / 8 > 64)
1583 // Check if the machine opcodes are different. If they are different
1584 // then we consider them to not be of the same base address,
1585 // EXCEPT in the case of Thumb2 byte loads where one is LDRBi8 and the other LDRBi12.
1586 // In this case, they are considered to be the same because they are different
1587 // encoding forms of the same basic instruction.
1588 if ((Load1->getMachineOpcode() != Load2->getMachineOpcode()) &&
1589 !((Load1->getMachineOpcode() == ARM::t2LDRBi8 &&
1590 Load2->getMachineOpcode() == ARM::t2LDRBi12) ||
1591 (Load1->getMachineOpcode() == ARM::t2LDRBi12 &&
1592 Load2->getMachineOpcode() == ARM::t2LDRBi8)))
1593 return false; // FIXME: overly conservative?
1595 // Four loads in a row should be sufficient.
1602 bool ARMBaseInstrInfo::isSchedulingBoundary(const MachineInstr *MI,
1603 const MachineBasicBlock *MBB,
1604 const MachineFunction &MF) const {
1605 // Debug info is never a scheduling boundary. It's necessary to be explicit
1606 // due to the special treatment of IT instructions below, otherwise a
1607 // dbg_value followed by an IT will result in the IT instruction being
1608 // considered a scheduling hazard, which is wrong. It should be the actual
1609 // instruction preceding the dbg_value instruction(s), just like it is
1610 // when debug info is not present.
1611 if (MI->isDebugValue())
1614 // Terminators and labels can't be scheduled around.
1615 if (MI->isTerminator() || MI->isPosition())
1618 // Treat the start of the IT block as a scheduling boundary, but schedule
1619 // t2IT along with all instructions following it.
1620 // FIXME: This is a big hammer. But the alternative is to add all potential
1621 // true and anti dependencies to IT block instructions as implicit operands
1622 // to the t2IT instruction. The added compile time and complexity does not
1624 MachineBasicBlock::const_iterator I = MI;
1625 // Make sure to skip any dbg_value instructions
1626 while (++I != MBB->end() && I->isDebugValue())
1628 if (I != MBB->end() && I->getOpcode() == ARM::t2IT)
1631 // Don't attempt to schedule around any instruction that defines
1632 // a stack-oriented pointer, as it's unlikely to be profitable. This
1633 // saves compile time, because it doesn't require every single
1634 // stack slot reference to depend on the instruction that does the
1636 // Calls don't actually change the stack pointer, even if they have imp-defs.
1637 // No ARM calling conventions change the stack pointer. (X86 calling
1638 // conventions sometimes do).
1639 if (!MI->isCall() && MI->definesRegister(ARM::SP))
1645 bool ARMBaseInstrInfo::
1646 isProfitableToIfCvt(MachineBasicBlock &MBB,
1647 unsigned NumCycles, unsigned ExtraPredCycles,
1648 const BranchProbability &Probability) const {
1652 // If we are optimizing for size, see if the branch in the predecessor can be
1653 // lowered to cbn?z by the constant island lowering pass, and return false if
1654 // so. This results in a shorter instruction sequence.
1655 if (MBB.getParent()->getFunction()->optForSize()) {
1656 MachineBasicBlock *Pred = *MBB.pred_begin();
1657 if (!Pred->empty()) {
1658 MachineInstr *LastMI = &*Pred->rbegin();
1659 if (LastMI->getOpcode() == ARM::t2Bcc) {
1660 MachineBasicBlock::iterator CmpMI = LastMI;
1661 if (CmpMI != Pred->begin()) {
1663 if (CmpMI->getOpcode() == ARM::tCMPi8 ||
1664 CmpMI->getOpcode() == ARM::t2CMPri) {
1665 unsigned Reg = CmpMI->getOperand(0).getReg();
1666 unsigned PredReg = 0;
1667 ARMCC::CondCodes P = getInstrPredicate(CmpMI, PredReg);
1668 if (P == ARMCC::AL && CmpMI->getOperand(1).getImm() == 0 &&
1669 isARMLowRegister(Reg))
1677 // Attempt to estimate the relative costs of predication versus branching.
1678 unsigned UnpredCost = Probability.getNumerator() * NumCycles;
1679 UnpredCost /= Probability.getDenominator();
1680 UnpredCost += 1; // The branch itself
1681 UnpredCost += Subtarget.getMispredictionPenalty() / 10;
1683 return (NumCycles + ExtraPredCycles) <= UnpredCost;
1686 bool ARMBaseInstrInfo::
1687 isProfitableToIfCvt(MachineBasicBlock &TMBB,
1688 unsigned TCycles, unsigned TExtra,
1689 MachineBasicBlock &FMBB,
1690 unsigned FCycles, unsigned FExtra,
1691 const BranchProbability &Probability) const {
1692 if (!TCycles || !FCycles)
1695 // Attempt to estimate the relative costs of predication versus branching.
1696 unsigned TUnpredCost = Probability.getNumerator() * TCycles;
1697 TUnpredCost /= Probability.getDenominator();
1699 uint32_t Comp = Probability.getDenominator() - Probability.getNumerator();
1700 unsigned FUnpredCost = Comp * FCycles;
1701 FUnpredCost /= Probability.getDenominator();
1703 unsigned UnpredCost = TUnpredCost + FUnpredCost;
1704 UnpredCost += 1; // The branch itself
1705 UnpredCost += Subtarget.getMispredictionPenalty() / 10;
1707 return (TCycles + FCycles + TExtra + FExtra) <= UnpredCost;
1711 ARMBaseInstrInfo::isProfitableToUnpredicate(MachineBasicBlock &TMBB,
1712 MachineBasicBlock &FMBB) const {
1713 // Reduce false anti-dependencies to let Swift's out-of-order execution
1714 // engine do its thing.
1715 return Subtarget.isSwift();
1718 /// getInstrPredicate - If instruction is predicated, returns its predicate
1719 /// condition, otherwise returns AL. It also returns the condition code
1720 /// register by reference.
1722 llvm::getInstrPredicate(const MachineInstr *MI, unsigned &PredReg) {
1723 int PIdx = MI->findFirstPredOperandIdx();
1729 PredReg = MI->getOperand(PIdx+1).getReg();
1730 return (ARMCC::CondCodes)MI->getOperand(PIdx).getImm();
1734 unsigned llvm::getMatchingCondBranchOpcode(unsigned Opc) {
1739 if (Opc == ARM::t2B)
1742 llvm_unreachable("Unknown unconditional branch opcode!");
1745 /// commuteInstruction - Handle commutable instructions.
1747 ARMBaseInstrInfo::commuteInstruction(MachineInstr *MI, bool NewMI) const {
1748 switch (MI->getOpcode()) {
1750 case ARM::t2MOVCCr: {
1751 // MOVCC can be commuted by inverting the condition.
1752 unsigned PredReg = 0;
1753 ARMCC::CondCodes CC = getInstrPredicate(MI, PredReg);
1754 // MOVCC AL can't be inverted. Shouldn't happen.
1755 if (CC == ARMCC::AL || PredReg != ARM::CPSR)
1757 MI = TargetInstrInfo::commuteInstruction(MI, NewMI);
1760 // After swapping the MOVCC operands, also invert the condition.
1761 MI->getOperand(MI->findFirstPredOperandIdx())
1762 .setImm(ARMCC::getOppositeCondition(CC));
1766 return TargetInstrInfo::commuteInstruction(MI, NewMI);
1769 /// Identify instructions that can be folded into a MOVCC instruction, and
1770 /// return the defining instruction.
1771 static MachineInstr *canFoldIntoMOVCC(unsigned Reg,
1772 const MachineRegisterInfo &MRI,
1773 const TargetInstrInfo *TII) {
1774 if (!TargetRegisterInfo::isVirtualRegister(Reg))
1776 if (!MRI.hasOneNonDBGUse(Reg))
1778 MachineInstr *MI = MRI.getVRegDef(Reg);
1781 // MI is folded into the MOVCC by predicating it.
1782 if (!MI->isPredicable())
1784 // Check if MI has any non-dead defs or physreg uses. This also detects
1785 // predicated instructions which will be reading CPSR.
1786 for (unsigned i = 1, e = MI->getNumOperands(); i != e; ++i) {
1787 const MachineOperand &MO = MI->getOperand(i);
1788 // Reject frame index operands, PEI can't handle the predicated pseudos.
1789 if (MO.isFI() || MO.isCPI() || MO.isJTI())
1793 // MI can't have any tied operands, that would conflict with predication.
1796 if (TargetRegisterInfo::isPhysicalRegister(MO.getReg()))
1798 if (MO.isDef() && !MO.isDead())
1801 bool DontMoveAcrossStores = true;
1802 if (!MI->isSafeToMove(/* AliasAnalysis = */ nullptr, DontMoveAcrossStores))
1807 bool ARMBaseInstrInfo::analyzeSelect(const MachineInstr *MI,
1808 SmallVectorImpl<MachineOperand> &Cond,
1809 unsigned &TrueOp, unsigned &FalseOp,
1810 bool &Optimizable) const {
1811 assert((MI->getOpcode() == ARM::MOVCCr || MI->getOpcode() == ARM::t2MOVCCr) &&
1812 "Unknown select instruction");
1817 // 3: Condition code.
1821 Cond.push_back(MI->getOperand(3));
1822 Cond.push_back(MI->getOperand(4));
1823 // We can always fold a def.
1829 ARMBaseInstrInfo::optimizeSelect(MachineInstr *MI,
1830 SmallPtrSetImpl<MachineInstr *> &SeenMIs,
1831 bool PreferFalse) const {
1832 assert((MI->getOpcode() == ARM::MOVCCr || MI->getOpcode() == ARM::t2MOVCCr) &&
1833 "Unknown select instruction");
1834 MachineRegisterInfo &MRI = MI->getParent()->getParent()->getRegInfo();
1835 MachineInstr *DefMI = canFoldIntoMOVCC(MI->getOperand(2).getReg(), MRI, this);
1836 bool Invert = !DefMI;
1838 DefMI = canFoldIntoMOVCC(MI->getOperand(1).getReg(), MRI, this);
1842 // Find new register class to use.
1843 MachineOperand FalseReg = MI->getOperand(Invert ? 2 : 1);
1844 unsigned DestReg = MI->getOperand(0).getReg();
1845 const TargetRegisterClass *PreviousClass = MRI.getRegClass(FalseReg.getReg());
1846 if (!MRI.constrainRegClass(DestReg, PreviousClass))
1849 // Create a new predicated version of DefMI.
1850 // Rfalse is the first use.
1851 MachineInstrBuilder NewMI = BuildMI(*MI->getParent(), MI, MI->getDebugLoc(),
1852 DefMI->getDesc(), DestReg);
1854 // Copy all the DefMI operands, excluding its (null) predicate.
1855 const MCInstrDesc &DefDesc = DefMI->getDesc();
1856 for (unsigned i = 1, e = DefDesc.getNumOperands();
1857 i != e && !DefDesc.OpInfo[i].isPredicate(); ++i)
1858 NewMI.addOperand(DefMI->getOperand(i));
1860 unsigned CondCode = MI->getOperand(3).getImm();
1862 NewMI.addImm(ARMCC::getOppositeCondition(ARMCC::CondCodes(CondCode)));
1864 NewMI.addImm(CondCode);
1865 NewMI.addOperand(MI->getOperand(4));
1867 // DefMI is not the -S version that sets CPSR, so add an optional %noreg.
1868 if (NewMI->hasOptionalDef())
1869 AddDefaultCC(NewMI);
1871 // The output register value when the predicate is false is an implicit
1872 // register operand tied to the first def.
1873 // The tie makes the register allocator ensure the FalseReg is allocated the
1874 // same register as operand 0.
1875 FalseReg.setImplicit();
1876 NewMI.addOperand(FalseReg);
1877 NewMI->tieOperands(0, NewMI->getNumOperands() - 1);
1879 // Update SeenMIs set: register newly created MI and erase removed DefMI.
1880 SeenMIs.insert(NewMI);
1881 SeenMIs.erase(DefMI);
1883 // If MI is inside a loop, and DefMI is outside the loop, then kill flags on
1884 // DefMI would be invalid when tranferred inside the loop. Checking for a
1885 // loop is expensive, but at least remove kill flags if they are in different
1887 if (DefMI->getParent() != MI->getParent())
1888 NewMI->clearKillInfo();
1890 // The caller will erase MI, but not DefMI.
1891 DefMI->eraseFromParent();
1895 /// Map pseudo instructions that imply an 'S' bit onto real opcodes. Whether the
1896 /// instruction is encoded with an 'S' bit is determined by the optional CPSR
1899 /// This will go away once we can teach tblgen how to set the optional CPSR def
1901 struct AddSubFlagsOpcodePair {
1903 uint16_t MachineOpc;
1906 static const AddSubFlagsOpcodePair AddSubFlagsOpcodeMap[] = {
1907 {ARM::ADDSri, ARM::ADDri},
1908 {ARM::ADDSrr, ARM::ADDrr},
1909 {ARM::ADDSrsi, ARM::ADDrsi},
1910 {ARM::ADDSrsr, ARM::ADDrsr},
1912 {ARM::SUBSri, ARM::SUBri},
1913 {ARM::SUBSrr, ARM::SUBrr},
1914 {ARM::SUBSrsi, ARM::SUBrsi},
1915 {ARM::SUBSrsr, ARM::SUBrsr},
1917 {ARM::RSBSri, ARM::RSBri},
1918 {ARM::RSBSrsi, ARM::RSBrsi},
1919 {ARM::RSBSrsr, ARM::RSBrsr},
1921 {ARM::t2ADDSri, ARM::t2ADDri},
1922 {ARM::t2ADDSrr, ARM::t2ADDrr},
1923 {ARM::t2ADDSrs, ARM::t2ADDrs},
1925 {ARM::t2SUBSri, ARM::t2SUBri},
1926 {ARM::t2SUBSrr, ARM::t2SUBrr},
1927 {ARM::t2SUBSrs, ARM::t2SUBrs},
1929 {ARM::t2RSBSri, ARM::t2RSBri},
1930 {ARM::t2RSBSrs, ARM::t2RSBrs},
1933 unsigned llvm::convertAddSubFlagsOpcode(unsigned OldOpc) {
1934 for (unsigned i = 0, e = array_lengthof(AddSubFlagsOpcodeMap); i != e; ++i)
1935 if (OldOpc == AddSubFlagsOpcodeMap[i].PseudoOpc)
1936 return AddSubFlagsOpcodeMap[i].MachineOpc;
1940 void llvm::emitARMRegPlusImmediate(MachineBasicBlock &MBB,
1941 MachineBasicBlock::iterator &MBBI, DebugLoc dl,
1942 unsigned DestReg, unsigned BaseReg, int NumBytes,
1943 ARMCC::CondCodes Pred, unsigned PredReg,
1944 const ARMBaseInstrInfo &TII, unsigned MIFlags) {
1945 if (NumBytes == 0 && DestReg != BaseReg) {
1946 BuildMI(MBB, MBBI, dl, TII.get(ARM::MOVr), DestReg)
1947 .addReg(BaseReg, RegState::Kill)
1948 .addImm((unsigned)Pred).addReg(PredReg).addReg(0)
1949 .setMIFlags(MIFlags);
1953 bool isSub = NumBytes < 0;
1954 if (isSub) NumBytes = -NumBytes;
1957 unsigned RotAmt = ARM_AM::getSOImmValRotate(NumBytes);
1958 unsigned ThisVal = NumBytes & ARM_AM::rotr32(0xFF, RotAmt);
1959 assert(ThisVal && "Didn't extract field correctly");
1961 // We will handle these bits from offset, clear them.
1962 NumBytes &= ~ThisVal;
1964 assert(ARM_AM::getSOImmVal(ThisVal) != -1 && "Bit extraction didn't work?");
1966 // Build the new ADD / SUB.
1967 unsigned Opc = isSub ? ARM::SUBri : ARM::ADDri;
1968 BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg)
1969 .addReg(BaseReg, RegState::Kill).addImm(ThisVal)
1970 .addImm((unsigned)Pred).addReg(PredReg).addReg(0)
1971 .setMIFlags(MIFlags);
1976 static bool isAnySubRegLive(unsigned Reg, const TargetRegisterInfo *TRI,
1978 for (MCSubRegIterator Subreg(Reg, TRI, /* IncludeSelf */ true);
1979 Subreg.isValid(); ++Subreg)
1980 if (MI->getParent()->computeRegisterLiveness(TRI, *Subreg, MI) !=
1981 MachineBasicBlock::LQR_Dead)
1985 bool llvm::tryFoldSPUpdateIntoPushPop(const ARMSubtarget &Subtarget,
1986 MachineFunction &MF, MachineInstr *MI,
1987 unsigned NumBytes) {
1988 // This optimisation potentially adds lots of load and store
1989 // micro-operations, it's only really a great benefit to code-size.
1990 if (!MF.getFunction()->optForMinSize())
1993 // If only one register is pushed/popped, LLVM can use an LDR/STR
1994 // instead. We can't modify those so make sure we're dealing with an
1995 // instruction we understand.
1996 bool IsPop = isPopOpcode(MI->getOpcode());
1997 bool IsPush = isPushOpcode(MI->getOpcode());
1998 if (!IsPush && !IsPop)
2001 bool IsVFPPushPop = MI->getOpcode() == ARM::VSTMDDB_UPD ||
2002 MI->getOpcode() == ARM::VLDMDIA_UPD;
2003 bool IsT1PushPop = MI->getOpcode() == ARM::tPUSH ||
2004 MI->getOpcode() == ARM::tPOP ||
2005 MI->getOpcode() == ARM::tPOP_RET;
2007 assert((IsT1PushPop || (MI->getOperand(0).getReg() == ARM::SP &&
2008 MI->getOperand(1).getReg() == ARM::SP)) &&
2009 "trying to fold sp update into non-sp-updating push/pop");
2011 // The VFP push & pop act on D-registers, so we can only fold an adjustment
2012 // by a multiple of 8 bytes in correctly. Similarly rN is 4-bytes. Don't try
2013 // if this is violated.
2014 if (NumBytes % (IsVFPPushPop ? 8 : 4) != 0)
2017 // ARM and Thumb2 push/pop insts have explicit "sp, sp" operands (+
2018 // pred) so the list starts at 4. Thumb1 starts after the predicate.
2019 int RegListIdx = IsT1PushPop ? 2 : 4;
2021 // Calculate the space we'll need in terms of registers.
2022 unsigned FirstReg = MI->getOperand(RegListIdx).getReg();
2023 unsigned RD0Reg, RegsNeeded;
2026 RegsNeeded = NumBytes / 8;
2029 RegsNeeded = NumBytes / 4;
2032 // We're going to have to strip all list operands off before
2033 // re-adding them since the order matters, so save the existing ones
2035 SmallVector<MachineOperand, 4> RegList;
2036 for (int i = MI->getNumOperands() - 1; i >= RegListIdx; --i)
2037 RegList.push_back(MI->getOperand(i));
2039 const TargetRegisterInfo *TRI = MF.getRegInfo().getTargetRegisterInfo();
2040 const MCPhysReg *CSRegs = TRI->getCalleeSavedRegs(&MF);
2042 // Now try to find enough space in the reglist to allocate NumBytes.
2043 for (unsigned CurReg = FirstReg - 1; CurReg >= RD0Reg && RegsNeeded;
2046 // Pushing any register is completely harmless, mark the
2047 // register involved as undef since we don't care about it in
2049 RegList.push_back(MachineOperand::CreateReg(CurReg, false, false,
2050 false, false, true));
2055 // However, we can only pop an extra register if it's not live. For
2056 // registers live within the function we might clobber a return value
2057 // register; the other way a register can be live here is if it's
2059 // TODO: Currently, computeRegisterLiveness() does not report "live" if a
2060 // sub reg is live. When computeRegisterLiveness() works for sub reg, it
2061 // can replace isAnySubRegLive().
2062 if (isCalleeSavedRegister(CurReg, CSRegs) ||
2063 isAnySubRegLive(CurReg, TRI, MI)) {
2064 // VFP pops don't allow holes in the register list, so any skip is fatal
2065 // for our transformation. GPR pops do, so we should just keep looking.
2072 // Mark the unimportant registers as <def,dead> in the POP.
2073 RegList.push_back(MachineOperand::CreateReg(CurReg, true, false, false,
2081 // Finally we know we can profitably perform the optimisation so go
2082 // ahead: strip all existing registers off and add them back again
2083 // in the right order.
2084 for (int i = MI->getNumOperands() - 1; i >= RegListIdx; --i)
2085 MI->RemoveOperand(i);
2087 // Add the complete list back in.
2088 MachineInstrBuilder MIB(MF, &*MI);
2089 for (int i = RegList.size() - 1; i >= 0; --i)
2090 MIB.addOperand(RegList[i]);
2095 bool llvm::rewriteARMFrameIndex(MachineInstr &MI, unsigned FrameRegIdx,
2096 unsigned FrameReg, int &Offset,
2097 const ARMBaseInstrInfo &TII) {
2098 unsigned Opcode = MI.getOpcode();
2099 const MCInstrDesc &Desc = MI.getDesc();
2100 unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
2103 // Memory operands in inline assembly always use AddrMode2.
2104 if (Opcode == ARM::INLINEASM)
2105 AddrMode = ARMII::AddrMode2;
2107 if (Opcode == ARM::ADDri) {
2108 Offset += MI.getOperand(FrameRegIdx+1).getImm();
2110 // Turn it into a move.
2111 MI.setDesc(TII.get(ARM::MOVr));
2112 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
2113 MI.RemoveOperand(FrameRegIdx+1);
2116 } else if (Offset < 0) {
2119 MI.setDesc(TII.get(ARM::SUBri));
2122 // Common case: small offset, fits into instruction.
2123 if (ARM_AM::getSOImmVal(Offset) != -1) {
2124 // Replace the FrameIndex with sp / fp
2125 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
2126 MI.getOperand(FrameRegIdx+1).ChangeToImmediate(Offset);
2131 // Otherwise, pull as much of the immedidate into this ADDri/SUBri
2133 unsigned RotAmt = ARM_AM::getSOImmValRotate(Offset);
2134 unsigned ThisImmVal = Offset & ARM_AM::rotr32(0xFF, RotAmt);
2136 // We will handle these bits from offset, clear them.
2137 Offset &= ~ThisImmVal;
2139 // Get the properly encoded SOImmVal field.
2140 assert(ARM_AM::getSOImmVal(ThisImmVal) != -1 &&
2141 "Bit extraction didn't work?");
2142 MI.getOperand(FrameRegIdx+1).ChangeToImmediate(ThisImmVal);
2144 unsigned ImmIdx = 0;
2146 unsigned NumBits = 0;
2149 case ARMII::AddrMode_i12: {
2150 ImmIdx = FrameRegIdx + 1;
2151 InstrOffs = MI.getOperand(ImmIdx).getImm();
2155 case ARMII::AddrMode2: {
2156 ImmIdx = FrameRegIdx+2;
2157 InstrOffs = ARM_AM::getAM2Offset(MI.getOperand(ImmIdx).getImm());
2158 if (ARM_AM::getAM2Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub)
2163 case ARMII::AddrMode3: {
2164 ImmIdx = FrameRegIdx+2;
2165 InstrOffs = ARM_AM::getAM3Offset(MI.getOperand(ImmIdx).getImm());
2166 if (ARM_AM::getAM3Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub)
2171 case ARMII::AddrMode4:
2172 case ARMII::AddrMode6:
2173 // Can't fold any offset even if it's zero.
2175 case ARMII::AddrMode5: {
2176 ImmIdx = FrameRegIdx+1;
2177 InstrOffs = ARM_AM::getAM5Offset(MI.getOperand(ImmIdx).getImm());
2178 if (ARM_AM::getAM5Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub)
2185 llvm_unreachable("Unsupported addressing mode!");
2188 Offset += InstrOffs * Scale;
2189 assert((Offset & (Scale-1)) == 0 && "Can't encode this offset!");
2195 // Attempt to fold address comp. if opcode has offset bits
2197 // Common case: small offset, fits into instruction.
2198 MachineOperand &ImmOp = MI.getOperand(ImmIdx);
2199 int ImmedOffset = Offset / Scale;
2200 unsigned Mask = (1 << NumBits) - 1;
2201 if ((unsigned)Offset <= Mask * Scale) {
2202 // Replace the FrameIndex with sp
2203 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
2204 // FIXME: When addrmode2 goes away, this will simplify (like the
2205 // T2 version), as the LDR.i12 versions don't need the encoding
2206 // tricks for the offset value.
2208 if (AddrMode == ARMII::AddrMode_i12)
2209 ImmedOffset = -ImmedOffset;
2211 ImmedOffset |= 1 << NumBits;
2213 ImmOp.ChangeToImmediate(ImmedOffset);
2218 // Otherwise, it didn't fit. Pull in what we can to simplify the immed.
2219 ImmedOffset = ImmedOffset & Mask;
2221 if (AddrMode == ARMII::AddrMode_i12)
2222 ImmedOffset = -ImmedOffset;
2224 ImmedOffset |= 1 << NumBits;
2226 ImmOp.ChangeToImmediate(ImmedOffset);
2227 Offset &= ~(Mask*Scale);
2231 Offset = (isSub) ? -Offset : Offset;
2235 /// analyzeCompare - For a comparison instruction, return the source registers
2236 /// in SrcReg and SrcReg2 if having two register operands, and the value it
2237 /// compares against in CmpValue. Return true if the comparison instruction
2238 /// can be analyzed.
2239 bool ARMBaseInstrInfo::
2240 analyzeCompare(const MachineInstr *MI, unsigned &SrcReg, unsigned &SrcReg2,
2241 int &CmpMask, int &CmpValue) const {
2242 switch (MI->getOpcode()) {
2246 SrcReg = MI->getOperand(0).getReg();
2249 CmpValue = MI->getOperand(1).getImm();
2253 SrcReg = MI->getOperand(0).getReg();
2254 SrcReg2 = MI->getOperand(1).getReg();
2260 SrcReg = MI->getOperand(0).getReg();
2262 CmpMask = MI->getOperand(1).getImm();
2270 /// isSuitableForMask - Identify a suitable 'and' instruction that
2271 /// operates on the given source register and applies the same mask
2272 /// as a 'tst' instruction. Provide a limited look-through for copies.
2273 /// When successful, MI will hold the found instruction.
2274 static bool isSuitableForMask(MachineInstr *&MI, unsigned SrcReg,
2275 int CmpMask, bool CommonUse) {
2276 switch (MI->getOpcode()) {
2279 if (CmpMask != MI->getOperand(2).getImm())
2281 if (SrcReg == MI->getOperand(CommonUse ? 1 : 0).getReg())
2289 /// getSwappedCondition - assume the flags are set by MI(a,b), return
2290 /// the condition code if we modify the instructions such that flags are
2292 inline static ARMCC::CondCodes getSwappedCondition(ARMCC::CondCodes CC) {
2294 default: return ARMCC::AL;
2295 case ARMCC::EQ: return ARMCC::EQ;
2296 case ARMCC::NE: return ARMCC::NE;
2297 case ARMCC::HS: return ARMCC::LS;
2298 case ARMCC::LO: return ARMCC::HI;
2299 case ARMCC::HI: return ARMCC::LO;
2300 case ARMCC::LS: return ARMCC::HS;
2301 case ARMCC::GE: return ARMCC::LE;
2302 case ARMCC::LT: return ARMCC::GT;
2303 case ARMCC::GT: return ARMCC::LT;
2304 case ARMCC::LE: return ARMCC::GE;
2308 /// isRedundantFlagInstr - check whether the first instruction, whose only
2309 /// purpose is to update flags, can be made redundant.
2310 /// CMPrr can be made redundant by SUBrr if the operands are the same.
2311 /// CMPri can be made redundant by SUBri if the operands are the same.
2312 /// This function can be extended later on.
2313 inline static bool isRedundantFlagInstr(MachineInstr *CmpI, unsigned SrcReg,
2314 unsigned SrcReg2, int ImmValue,
2316 if ((CmpI->getOpcode() == ARM::CMPrr ||
2317 CmpI->getOpcode() == ARM::t2CMPrr) &&
2318 (OI->getOpcode() == ARM::SUBrr ||
2319 OI->getOpcode() == ARM::t2SUBrr) &&
2320 ((OI->getOperand(1).getReg() == SrcReg &&
2321 OI->getOperand(2).getReg() == SrcReg2) ||
2322 (OI->getOperand(1).getReg() == SrcReg2 &&
2323 OI->getOperand(2).getReg() == SrcReg)))
2326 if ((CmpI->getOpcode() == ARM::CMPri ||
2327 CmpI->getOpcode() == ARM::t2CMPri) &&
2328 (OI->getOpcode() == ARM::SUBri ||
2329 OI->getOpcode() == ARM::t2SUBri) &&
2330 OI->getOperand(1).getReg() == SrcReg &&
2331 OI->getOperand(2).getImm() == ImmValue)
2336 /// optimizeCompareInstr - Convert the instruction supplying the argument to the
2337 /// comparison into one that sets the zero bit in the flags register;
2338 /// Remove a redundant Compare instruction if an earlier instruction can set the
2339 /// flags in the same way as Compare.
2340 /// E.g. SUBrr(r1,r2) and CMPrr(r1,r2). We also handle the case where two
2341 /// operands are swapped: SUBrr(r1,r2) and CMPrr(r2,r1), by updating the
2342 /// condition code of instructions which use the flags.
2343 bool ARMBaseInstrInfo::
2344 optimizeCompareInstr(MachineInstr *CmpInstr, unsigned SrcReg, unsigned SrcReg2,
2345 int CmpMask, int CmpValue,
2346 const MachineRegisterInfo *MRI) const {
2347 // Get the unique definition of SrcReg.
2348 MachineInstr *MI = MRI->getUniqueVRegDef(SrcReg);
2349 if (!MI) return false;
2351 // Masked compares sometimes use the same register as the corresponding 'and'.
2352 if (CmpMask != ~0) {
2353 if (!isSuitableForMask(MI, SrcReg, CmpMask, false) || isPredicated(MI)) {
2355 for (MachineRegisterInfo::use_instr_iterator
2356 UI = MRI->use_instr_begin(SrcReg), UE = MRI->use_instr_end();
2358 if (UI->getParent() != CmpInstr->getParent()) continue;
2359 MachineInstr *PotentialAND = &*UI;
2360 if (!isSuitableForMask(PotentialAND, SrcReg, CmpMask, true) ||
2361 isPredicated(PotentialAND))
2366 if (!MI) return false;
2370 // Get ready to iterate backward from CmpInstr.
2371 MachineBasicBlock::iterator I = CmpInstr, E = MI,
2372 B = CmpInstr->getParent()->begin();
2374 // Early exit if CmpInstr is at the beginning of the BB.
2375 if (I == B) return false;
2377 // There are two possible candidates which can be changed to set CPSR:
2378 // One is MI, the other is a SUB instruction.
2379 // For CMPrr(r1,r2), we are looking for SUB(r1,r2) or SUB(r2,r1).
2380 // For CMPri(r1, CmpValue), we are looking for SUBri(r1, CmpValue).
2381 MachineInstr *Sub = nullptr;
2383 // MI is not a candidate for CMPrr.
2385 else if (MI->getParent() != CmpInstr->getParent() || CmpValue != 0) {
2386 // Conservatively refuse to convert an instruction which isn't in the same
2387 // BB as the comparison.
2388 // For CMPri w/ CmpValue != 0, a Sub may still be a candidate.
2389 // Thus we cannot return here.
2390 if (CmpInstr->getOpcode() == ARM::CMPri ||
2391 CmpInstr->getOpcode() == ARM::t2CMPri)
2397 // Check that CPSR isn't set between the comparison instruction and the one we
2398 // want to change. At the same time, search for Sub.
2399 const TargetRegisterInfo *TRI = &getRegisterInfo();
2401 for (; I != E; --I) {
2402 const MachineInstr &Instr = *I;
2404 if (Instr.modifiesRegister(ARM::CPSR, TRI) ||
2405 Instr.readsRegister(ARM::CPSR, TRI))
2406 // This instruction modifies or uses CPSR after the one we want to
2407 // change. We can't do this transformation.
2410 // Check whether CmpInstr can be made redundant by the current instruction.
2411 if (isRedundantFlagInstr(CmpInstr, SrcReg, SrcReg2, CmpValue, &*I)) {
2417 // The 'and' is below the comparison instruction.
2421 // Return false if no candidates exist.
2425 // The single candidate is called MI.
2428 // We can't use a predicated instruction - it doesn't always write the flags.
2429 if (isPredicated(MI))
2432 switch (MI->getOpcode()) {
2466 case ARM::t2EORri: {
2467 // Scan forward for the use of CPSR
2468 // When checking against MI: if it's a conditional code that requires
2469 // checking of the V bit or C bit, then this is not safe to do.
2470 // It is safe to remove CmpInstr if CPSR is redefined or killed.
2471 // If we are done with the basic block, we need to check whether CPSR is
2473 SmallVector<std::pair<MachineOperand*, ARMCC::CondCodes>, 4>
2475 bool isSafe = false;
2477 E = CmpInstr->getParent()->end();
2478 while (!isSafe && ++I != E) {
2479 const MachineInstr &Instr = *I;
2480 for (unsigned IO = 0, EO = Instr.getNumOperands();
2481 !isSafe && IO != EO; ++IO) {
2482 const MachineOperand &MO = Instr.getOperand(IO);
2483 if (MO.isRegMask() && MO.clobbersPhysReg(ARM::CPSR)) {
2487 if (!MO.isReg() || MO.getReg() != ARM::CPSR)
2493 // Condition code is after the operand before CPSR except for VSELs.
2494 ARMCC::CondCodes CC;
2495 bool IsInstrVSel = true;
2496 switch (Instr.getOpcode()) {
2498 IsInstrVSel = false;
2499 CC = (ARMCC::CondCodes)Instr.getOperand(IO - 1).getImm();
2520 ARMCC::CondCodes NewCC = getSwappedCondition(CC);
2521 if (NewCC == ARMCC::AL)
2523 // If we have SUB(r1, r2) and CMP(r2, r1), the condition code based
2524 // on CMP needs to be updated to be based on SUB.
2525 // Push the condition code operands to OperandsToUpdate.
2526 // If it is safe to remove CmpInstr, the condition code of these
2527 // operands will be modified.
2528 if (SrcReg2 != 0 && Sub->getOperand(1).getReg() == SrcReg2 &&
2529 Sub->getOperand(2).getReg() == SrcReg) {
2530 // VSel doesn't support condition code update.
2533 OperandsToUpdate.push_back(
2534 std::make_pair(&((*I).getOperand(IO - 1)), NewCC));
2537 // No Sub, so this is x = <op> y, z; cmp x, 0.
2539 case ARMCC::EQ: // Z
2540 case ARMCC::NE: // Z
2541 case ARMCC::MI: // N
2542 case ARMCC::PL: // N
2543 case ARMCC::AL: // none
2544 // CPSR can be used multiple times, we should continue.
2546 case ARMCC::HS: // C
2547 case ARMCC::LO: // C
2548 case ARMCC::VS: // V
2549 case ARMCC::VC: // V
2550 case ARMCC::HI: // C Z
2551 case ARMCC::LS: // C Z
2552 case ARMCC::GE: // N V
2553 case ARMCC::LT: // N V
2554 case ARMCC::GT: // Z N V
2555 case ARMCC::LE: // Z N V
2556 // The instruction uses the V bit or C bit which is not safe.
2563 // If CPSR is not killed nor re-defined, we should check whether it is
2564 // live-out. If it is live-out, do not optimize.
2566 MachineBasicBlock *MBB = CmpInstr->getParent();
2567 for (MachineBasicBlock::succ_iterator SI = MBB->succ_begin(),
2568 SE = MBB->succ_end(); SI != SE; ++SI)
2569 if ((*SI)->isLiveIn(ARM::CPSR))
2573 // Toggle the optional operand to CPSR.
2574 MI->getOperand(5).setReg(ARM::CPSR);
2575 MI->getOperand(5).setIsDef(true);
2576 assert(!isPredicated(MI) && "Can't use flags from predicated instruction");
2577 CmpInstr->eraseFromParent();
2579 // Modify the condition code of operands in OperandsToUpdate.
2580 // Since we have SUB(r1, r2) and CMP(r2, r1), the condition code needs to
2581 // be changed from r2 > r1 to r1 < r2, from r2 < r1 to r1 > r2, etc.
2582 for (unsigned i = 0, e = OperandsToUpdate.size(); i < e; i++)
2583 OperandsToUpdate[i].first->setImm(OperandsToUpdate[i].second);
2591 bool ARMBaseInstrInfo::FoldImmediate(MachineInstr *UseMI,
2592 MachineInstr *DefMI, unsigned Reg,
2593 MachineRegisterInfo *MRI) const {
2594 // Fold large immediates into add, sub, or, xor.
2595 unsigned DefOpc = DefMI->getOpcode();
2596 if (DefOpc != ARM::t2MOVi32imm && DefOpc != ARM::MOVi32imm)
2598 if (!DefMI->getOperand(1).isImm())
2599 // Could be t2MOVi32imm <ga:xx>
2602 if (!MRI->hasOneNonDBGUse(Reg))
2605 const MCInstrDesc &DefMCID = DefMI->getDesc();
2606 if (DefMCID.hasOptionalDef()) {
2607 unsigned NumOps = DefMCID.getNumOperands();
2608 const MachineOperand &MO = DefMI->getOperand(NumOps-1);
2609 if (MO.getReg() == ARM::CPSR && !MO.isDead())
2610 // If DefMI defines CPSR and it is not dead, it's obviously not safe
2615 const MCInstrDesc &UseMCID = UseMI->getDesc();
2616 if (UseMCID.hasOptionalDef()) {
2617 unsigned NumOps = UseMCID.getNumOperands();
2618 if (UseMI->getOperand(NumOps-1).getReg() == ARM::CPSR)
2619 // If the instruction sets the flag, do not attempt this optimization
2620 // since it may change the semantics of the code.
2624 unsigned UseOpc = UseMI->getOpcode();
2625 unsigned NewUseOpc = 0;
2626 uint32_t ImmVal = (uint32_t)DefMI->getOperand(1).getImm();
2627 uint32_t SOImmValV1 = 0, SOImmValV2 = 0;
2628 bool Commute = false;
2630 default: return false;
2638 case ARM::t2EORrr: {
2639 Commute = UseMI->getOperand(2).getReg() != Reg;
2646 NewUseOpc = ARM::SUBri;
2652 if (!ARM_AM::isSOImmTwoPartVal(ImmVal))
2654 SOImmValV1 = (uint32_t)ARM_AM::getSOImmTwoPartFirst(ImmVal);
2655 SOImmValV2 = (uint32_t)ARM_AM::getSOImmTwoPartSecond(ImmVal);
2658 case ARM::ADDrr: NewUseOpc = ARM::ADDri; break;
2659 case ARM::ORRrr: NewUseOpc = ARM::ORRri; break;
2660 case ARM::EORrr: NewUseOpc = ARM::EORri; break;
2664 case ARM::t2SUBrr: {
2668 NewUseOpc = ARM::t2SUBri;
2673 case ARM::t2EORrr: {
2674 if (!ARM_AM::isT2SOImmTwoPartVal(ImmVal))
2676 SOImmValV1 = (uint32_t)ARM_AM::getT2SOImmTwoPartFirst(ImmVal);
2677 SOImmValV2 = (uint32_t)ARM_AM::getT2SOImmTwoPartSecond(ImmVal);
2680 case ARM::t2ADDrr: NewUseOpc = ARM::t2ADDri; break;
2681 case ARM::t2ORRrr: NewUseOpc = ARM::t2ORRri; break;
2682 case ARM::t2EORrr: NewUseOpc = ARM::t2EORri; break;
2690 unsigned OpIdx = Commute ? 2 : 1;
2691 unsigned Reg1 = UseMI->getOperand(OpIdx).getReg();
2692 bool isKill = UseMI->getOperand(OpIdx).isKill();
2693 unsigned NewReg = MRI->createVirtualRegister(MRI->getRegClass(Reg));
2694 AddDefaultCC(AddDefaultPred(BuildMI(*UseMI->getParent(),
2695 UseMI, UseMI->getDebugLoc(),
2696 get(NewUseOpc), NewReg)
2697 .addReg(Reg1, getKillRegState(isKill))
2698 .addImm(SOImmValV1)));
2699 UseMI->setDesc(get(NewUseOpc));
2700 UseMI->getOperand(1).setReg(NewReg);
2701 UseMI->getOperand(1).setIsKill();
2702 UseMI->getOperand(2).ChangeToImmediate(SOImmValV2);
2703 DefMI->eraseFromParent();
2707 static unsigned getNumMicroOpsSwiftLdSt(const InstrItineraryData *ItinData,
2708 const MachineInstr *MI) {
2709 switch (MI->getOpcode()) {
2711 const MCInstrDesc &Desc = MI->getDesc();
2712 int UOps = ItinData->getNumMicroOps(Desc.getSchedClass());
2713 assert(UOps >= 0 && "bad # UOps");
2721 unsigned ShOpVal = MI->getOperand(3).getImm();
2722 bool isSub = ARM_AM::getAM2Op(ShOpVal) == ARM_AM::sub;
2723 unsigned ShImm = ARM_AM::getAM2Offset(ShOpVal);
2726 ((ShImm == 1 || ShImm == 2 || ShImm == 3) &&
2727 ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl)))
2734 if (!MI->getOperand(2).getReg())
2737 unsigned ShOpVal = MI->getOperand(3).getImm();
2738 bool isSub = ARM_AM::getAM2Op(ShOpVal) == ARM_AM::sub;
2739 unsigned ShImm = ARM_AM::getAM2Offset(ShOpVal);
2742 ((ShImm == 1 || ShImm == 2 || ShImm == 3) &&
2743 ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl)))
2750 return (ARM_AM::getAM3Op(MI->getOperand(3).getImm()) == ARM_AM::sub) ? 3:2;
2752 case ARM::LDRSB_POST:
2753 case ARM::LDRSH_POST: {
2754 unsigned Rt = MI->getOperand(0).getReg();
2755 unsigned Rm = MI->getOperand(3).getReg();
2756 return (Rt == Rm) ? 4 : 3;
2759 case ARM::LDR_PRE_REG:
2760 case ARM::LDRB_PRE_REG: {
2761 unsigned Rt = MI->getOperand(0).getReg();
2762 unsigned Rm = MI->getOperand(3).getReg();
2765 unsigned ShOpVal = MI->getOperand(4).getImm();
2766 bool isSub = ARM_AM::getAM2Op(ShOpVal) == ARM_AM::sub;
2767 unsigned ShImm = ARM_AM::getAM2Offset(ShOpVal);
2770 ((ShImm == 1 || ShImm == 2 || ShImm == 3) &&
2771 ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl)))
2776 case ARM::STR_PRE_REG:
2777 case ARM::STRB_PRE_REG: {
2778 unsigned ShOpVal = MI->getOperand(4).getImm();
2779 bool isSub = ARM_AM::getAM2Op(ShOpVal) == ARM_AM::sub;
2780 unsigned ShImm = ARM_AM::getAM2Offset(ShOpVal);
2783 ((ShImm == 1 || ShImm == 2 || ShImm == 3) &&
2784 ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl)))
2790 case ARM::STRH_PRE: {
2791 unsigned Rt = MI->getOperand(0).getReg();
2792 unsigned Rm = MI->getOperand(3).getReg();
2797 return (ARM_AM::getAM3Op(MI->getOperand(4).getImm()) == ARM_AM::sub)
2801 case ARM::LDR_POST_REG:
2802 case ARM::LDRB_POST_REG:
2803 case ARM::LDRH_POST: {
2804 unsigned Rt = MI->getOperand(0).getReg();
2805 unsigned Rm = MI->getOperand(3).getReg();
2806 return (Rt == Rm) ? 3 : 2;
2809 case ARM::LDR_PRE_IMM:
2810 case ARM::LDRB_PRE_IMM:
2811 case ARM::LDR_POST_IMM:
2812 case ARM::LDRB_POST_IMM:
2813 case ARM::STRB_POST_IMM:
2814 case ARM::STRB_POST_REG:
2815 case ARM::STRB_PRE_IMM:
2816 case ARM::STRH_POST:
2817 case ARM::STR_POST_IMM:
2818 case ARM::STR_POST_REG:
2819 case ARM::STR_PRE_IMM:
2822 case ARM::LDRSB_PRE:
2823 case ARM::LDRSH_PRE: {
2824 unsigned Rm = MI->getOperand(3).getReg();
2827 unsigned Rt = MI->getOperand(0).getReg();
2830 unsigned ShOpVal = MI->getOperand(4).getImm();
2831 bool isSub = ARM_AM::getAM2Op(ShOpVal) == ARM_AM::sub;
2832 unsigned ShImm = ARM_AM::getAM2Offset(ShOpVal);
2835 ((ShImm == 1 || ShImm == 2 || ShImm == 3) &&
2836 ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl)))
2842 unsigned Rt = MI->getOperand(0).getReg();
2843 unsigned Rn = MI->getOperand(2).getReg();
2844 unsigned Rm = MI->getOperand(3).getReg();
2846 return (ARM_AM::getAM3Op(MI->getOperand(4).getImm()) == ARM_AM::sub) ?4:3;
2847 return (Rt == Rn) ? 3 : 2;
2851 unsigned Rm = MI->getOperand(3).getReg();
2853 return (ARM_AM::getAM3Op(MI->getOperand(4).getImm()) == ARM_AM::sub) ?4:3;
2857 case ARM::LDRD_POST:
2858 case ARM::t2LDRD_POST:
2861 case ARM::STRD_POST:
2862 case ARM::t2STRD_POST:
2865 case ARM::LDRD_PRE: {
2866 unsigned Rt = MI->getOperand(0).getReg();
2867 unsigned Rn = MI->getOperand(3).getReg();
2868 unsigned Rm = MI->getOperand(4).getReg();
2870 return (ARM_AM::getAM3Op(MI->getOperand(5).getImm()) == ARM_AM::sub) ?5:4;
2871 return (Rt == Rn) ? 4 : 3;
2874 case ARM::t2LDRD_PRE: {
2875 unsigned Rt = MI->getOperand(0).getReg();
2876 unsigned Rn = MI->getOperand(3).getReg();
2877 return (Rt == Rn) ? 4 : 3;
2880 case ARM::STRD_PRE: {
2881 unsigned Rm = MI->getOperand(4).getReg();
2883 return (ARM_AM::getAM3Op(MI->getOperand(5).getImm()) == ARM_AM::sub) ?5:4;
2887 case ARM::t2STRD_PRE:
2890 case ARM::t2LDR_POST:
2891 case ARM::t2LDRB_POST:
2892 case ARM::t2LDRB_PRE:
2893 case ARM::t2LDRSBi12:
2894 case ARM::t2LDRSBi8:
2895 case ARM::t2LDRSBpci:
2897 case ARM::t2LDRH_POST:
2898 case ARM::t2LDRH_PRE:
2900 case ARM::t2LDRSB_POST:
2901 case ARM::t2LDRSB_PRE:
2902 case ARM::t2LDRSH_POST:
2903 case ARM::t2LDRSH_PRE:
2904 case ARM::t2LDRSHi12:
2905 case ARM::t2LDRSHi8:
2906 case ARM::t2LDRSHpci:
2910 case ARM::t2LDRDi8: {
2911 unsigned Rt = MI->getOperand(0).getReg();
2912 unsigned Rn = MI->getOperand(2).getReg();
2913 return (Rt == Rn) ? 3 : 2;
2916 case ARM::t2STRB_POST:
2917 case ARM::t2STRB_PRE:
2920 case ARM::t2STRH_POST:
2921 case ARM::t2STRH_PRE:
2923 case ARM::t2STR_POST:
2924 case ARM::t2STR_PRE:
2930 // Return the number of 32-bit words loaded by LDM or stored by STM. If this
2931 // can't be easily determined return 0 (missing MachineMemOperand).
2933 // FIXME: The current MachineInstr design does not support relying on machine
2934 // mem operands to determine the width of a memory access. Instead, we expect
2935 // the target to provide this information based on the instruction opcode and
2936 // operands. However, using MachineMemOperand is the best solution now for
2939 // 1) getNumMicroOps tries to infer LDM memory width from the total number of MI
2940 // operands. This is much more dangerous than using the MachineMemOperand
2941 // sizes because CodeGen passes can insert/remove optional machine operands. In
2942 // fact, it's totally incorrect for preRA passes and appears to be wrong for
2943 // postRA passes as well.
2945 // 2) getNumLDMAddresses is only used by the scheduling machine model and any
2946 // machine model that calls this should handle the unknown (zero size) case.
2948 // Long term, we should require a target hook that verifies MachineMemOperand
2949 // sizes during MC lowering. That target hook should be local to MC lowering
2950 // because we can't ensure that it is aware of other MI forms. Doing this will
2951 // ensure that MachineMemOperands are correctly propagated through all passes.
2952 unsigned ARMBaseInstrInfo::getNumLDMAddresses(const MachineInstr *MI) const {
2954 for (MachineInstr::mmo_iterator I = MI->memoperands_begin(),
2955 E = MI->memoperands_end(); I != E; ++I) {
2956 Size += (*I)->getSize();
2962 ARMBaseInstrInfo::getNumMicroOps(const InstrItineraryData *ItinData,
2963 const MachineInstr *MI) const {
2964 if (!ItinData || ItinData->isEmpty())
2967 const MCInstrDesc &Desc = MI->getDesc();
2968 unsigned Class = Desc.getSchedClass();
2969 int ItinUOps = ItinData->getNumMicroOps(Class);
2970 if (ItinUOps >= 0) {
2971 if (Subtarget.isSwift() && (Desc.mayLoad() || Desc.mayStore()))
2972 return getNumMicroOpsSwiftLdSt(ItinData, MI);
2977 unsigned Opc = MI->getOpcode();
2980 llvm_unreachable("Unexpected multi-uops instruction!");
2985 // The number of uOps for load / store multiple are determined by the number
2988 // On Cortex-A8, each pair of register loads / stores can be scheduled on the
2989 // same cycle. The scheduling for the first load / store must be done
2990 // separately by assuming the address is not 64-bit aligned.
2992 // On Cortex-A9, the formula is simply (#reg / 2) + (#reg % 2). If the address
2993 // is not 64-bit aligned, then AGU would take an extra cycle. For VFP / NEON
2994 // load / store multiple, the formula is (#reg / 2) + (#reg % 2) + 1.
2996 case ARM::VLDMDIA_UPD:
2997 case ARM::VLDMDDB_UPD:
2999 case ARM::VLDMSIA_UPD:
3000 case ARM::VLDMSDB_UPD:
3002 case ARM::VSTMDIA_UPD:
3003 case ARM::VSTMDDB_UPD:
3005 case ARM::VSTMSIA_UPD:
3006 case ARM::VSTMSDB_UPD: {
3007 unsigned NumRegs = MI->getNumOperands() - Desc.getNumOperands();
3008 return (NumRegs / 2) + (NumRegs % 2) + 1;
3011 case ARM::LDMIA_RET:
3016 case ARM::LDMIA_UPD:
3017 case ARM::LDMDA_UPD:
3018 case ARM::LDMDB_UPD:
3019 case ARM::LDMIB_UPD:
3024 case ARM::STMIA_UPD:
3025 case ARM::STMDA_UPD:
3026 case ARM::STMDB_UPD:
3027 case ARM::STMIB_UPD:
3029 case ARM::tLDMIA_UPD:
3030 case ARM::tSTMIA_UPD:
3034 case ARM::t2LDMIA_RET:
3037 case ARM::t2LDMIA_UPD:
3038 case ARM::t2LDMDB_UPD:
3041 case ARM::t2STMIA_UPD:
3042 case ARM::t2STMDB_UPD: {
3043 unsigned NumRegs = MI->getNumOperands() - Desc.getNumOperands() + 1;
3044 if (Subtarget.isSwift()) {
3045 int UOps = 1 + NumRegs; // One for address computation, one for each ld / st.
3048 case ARM::VLDMDIA_UPD:
3049 case ARM::VLDMDDB_UPD:
3050 case ARM::VLDMSIA_UPD:
3051 case ARM::VLDMSDB_UPD:
3052 case ARM::VSTMDIA_UPD:
3053 case ARM::VSTMDDB_UPD:
3054 case ARM::VSTMSIA_UPD:
3055 case ARM::VSTMSDB_UPD:
3056 case ARM::LDMIA_UPD:
3057 case ARM::LDMDA_UPD:
3058 case ARM::LDMDB_UPD:
3059 case ARM::LDMIB_UPD:
3060 case ARM::STMIA_UPD:
3061 case ARM::STMDA_UPD:
3062 case ARM::STMDB_UPD:
3063 case ARM::STMIB_UPD:
3064 case ARM::tLDMIA_UPD:
3065 case ARM::tSTMIA_UPD:
3066 case ARM::t2LDMIA_UPD:
3067 case ARM::t2LDMDB_UPD:
3068 case ARM::t2STMIA_UPD:
3069 case ARM::t2STMDB_UPD:
3070 ++UOps; // One for base register writeback.
3072 case ARM::LDMIA_RET:
3074 case ARM::t2LDMIA_RET:
3075 UOps += 2; // One for base reg wb, one for write to pc.
3079 } else if (Subtarget.isCortexA8() || Subtarget.isCortexA7()) {
3082 // 4 registers would be issued: 2, 2.
3083 // 5 registers would be issued: 2, 2, 1.
3084 int A8UOps = (NumRegs / 2);
3088 } else if (Subtarget.isLikeA9() || Subtarget.isSwift()) {
3089 int A9UOps = (NumRegs / 2);
3090 // If there are odd number of registers or if it's not 64-bit aligned,
3091 // then it takes an extra AGU (Address Generation Unit) cycle.
3092 if ((NumRegs % 2) ||
3093 !MI->hasOneMemOperand() ||
3094 (*MI->memoperands_begin())->getAlignment() < 8)
3098 // Assume the worst.
3106 ARMBaseInstrInfo::getVLDMDefCycle(const InstrItineraryData *ItinData,
3107 const MCInstrDesc &DefMCID,
3109 unsigned DefIdx, unsigned DefAlign) const {
3110 int RegNo = (int)(DefIdx+1) - DefMCID.getNumOperands() + 1;
3112 // Def is the address writeback.
3113 return ItinData->getOperandCycle(DefClass, DefIdx);
3116 if (Subtarget.isCortexA8() || Subtarget.isCortexA7()) {
3117 // (regno / 2) + (regno % 2) + 1
3118 DefCycle = RegNo / 2 + 1;
3121 } else if (Subtarget.isLikeA9() || Subtarget.isSwift()) {
3123 bool isSLoad = false;
3125 switch (DefMCID.getOpcode()) {
3128 case ARM::VLDMSIA_UPD:
3129 case ARM::VLDMSDB_UPD:
3134 // If there are odd number of 'S' registers or if it's not 64-bit aligned,
3135 // then it takes an extra cycle.
3136 if ((isSLoad && (RegNo % 2)) || DefAlign < 8)
3139 // Assume the worst.
3140 DefCycle = RegNo + 2;
3147 ARMBaseInstrInfo::getLDMDefCycle(const InstrItineraryData *ItinData,
3148 const MCInstrDesc &DefMCID,
3150 unsigned DefIdx, unsigned DefAlign) const {
3151 int RegNo = (int)(DefIdx+1) - DefMCID.getNumOperands() + 1;
3153 // Def is the address writeback.
3154 return ItinData->getOperandCycle(DefClass, DefIdx);
3157 if (Subtarget.isCortexA8() || Subtarget.isCortexA7()) {
3158 // 4 registers would be issued: 1, 2, 1.
3159 // 5 registers would be issued: 1, 2, 2.
3160 DefCycle = RegNo / 2;
3163 // Result latency is issue cycle + 2: E2.
3165 } else if (Subtarget.isLikeA9() || Subtarget.isSwift()) {
3166 DefCycle = (RegNo / 2);
3167 // If there are odd number of registers or if it's not 64-bit aligned,
3168 // then it takes an extra AGU (Address Generation Unit) cycle.
3169 if ((RegNo % 2) || DefAlign < 8)
3171 // Result latency is AGU cycles + 2.
3174 // Assume the worst.
3175 DefCycle = RegNo + 2;
3182 ARMBaseInstrInfo::getVSTMUseCycle(const InstrItineraryData *ItinData,
3183 const MCInstrDesc &UseMCID,
3185 unsigned UseIdx, unsigned UseAlign) const {
3186 int RegNo = (int)(UseIdx+1) - UseMCID.getNumOperands() + 1;
3188 return ItinData->getOperandCycle(UseClass, UseIdx);
3191 if (Subtarget.isCortexA8() || Subtarget.isCortexA7()) {
3192 // (regno / 2) + (regno % 2) + 1
3193 UseCycle = RegNo / 2 + 1;
3196 } else if (Subtarget.isLikeA9() || Subtarget.isSwift()) {
3198 bool isSStore = false;
3200 switch (UseMCID.getOpcode()) {
3203 case ARM::VSTMSIA_UPD:
3204 case ARM::VSTMSDB_UPD:
3209 // If there are odd number of 'S' registers or if it's not 64-bit aligned,
3210 // then it takes an extra cycle.
3211 if ((isSStore && (RegNo % 2)) || UseAlign < 8)
3214 // Assume the worst.
3215 UseCycle = RegNo + 2;
3222 ARMBaseInstrInfo::getSTMUseCycle(const InstrItineraryData *ItinData,
3223 const MCInstrDesc &UseMCID,
3225 unsigned UseIdx, unsigned UseAlign) const {
3226 int RegNo = (int)(UseIdx+1) - UseMCID.getNumOperands() + 1;
3228 return ItinData->getOperandCycle(UseClass, UseIdx);
3231 if (Subtarget.isCortexA8() || Subtarget.isCortexA7()) {
3232 UseCycle = RegNo / 2;
3237 } else if (Subtarget.isLikeA9() || Subtarget.isSwift()) {
3238 UseCycle = (RegNo / 2);
3239 // If there are odd number of registers or if it's not 64-bit aligned,
3240 // then it takes an extra AGU (Address Generation Unit) cycle.
3241 if ((RegNo % 2) || UseAlign < 8)
3244 // Assume the worst.
3251 ARMBaseInstrInfo::getOperandLatency(const InstrItineraryData *ItinData,
3252 const MCInstrDesc &DefMCID,
3253 unsigned DefIdx, unsigned DefAlign,
3254 const MCInstrDesc &UseMCID,
3255 unsigned UseIdx, unsigned UseAlign) const {
3256 unsigned DefClass = DefMCID.getSchedClass();
3257 unsigned UseClass = UseMCID.getSchedClass();
3259 if (DefIdx < DefMCID.getNumDefs() && UseIdx < UseMCID.getNumOperands())
3260 return ItinData->getOperandLatency(DefClass, DefIdx, UseClass, UseIdx);
3262 // This may be a def / use of a variable_ops instruction, the operand
3263 // latency might be determinable dynamically. Let the target try to
3266 bool LdmBypass = false;
3267 switch (DefMCID.getOpcode()) {
3269 DefCycle = ItinData->getOperandCycle(DefClass, DefIdx);
3273 case ARM::VLDMDIA_UPD:
3274 case ARM::VLDMDDB_UPD:
3276 case ARM::VLDMSIA_UPD:
3277 case ARM::VLDMSDB_UPD:
3278 DefCycle = getVLDMDefCycle(ItinData, DefMCID, DefClass, DefIdx, DefAlign);
3281 case ARM::LDMIA_RET:
3286 case ARM::LDMIA_UPD:
3287 case ARM::LDMDA_UPD:
3288 case ARM::LDMDB_UPD:
3289 case ARM::LDMIB_UPD:
3291 case ARM::tLDMIA_UPD:
3293 case ARM::t2LDMIA_RET:
3296 case ARM::t2LDMIA_UPD:
3297 case ARM::t2LDMDB_UPD:
3299 DefCycle = getLDMDefCycle(ItinData, DefMCID, DefClass, DefIdx, DefAlign);
3304 // We can't seem to determine the result latency of the def, assume it's 2.
3308 switch (UseMCID.getOpcode()) {
3310 UseCycle = ItinData->getOperandCycle(UseClass, UseIdx);
3314 case ARM::VSTMDIA_UPD:
3315 case ARM::VSTMDDB_UPD:
3317 case ARM::VSTMSIA_UPD:
3318 case ARM::VSTMSDB_UPD:
3319 UseCycle = getVSTMUseCycle(ItinData, UseMCID, UseClass, UseIdx, UseAlign);
3326 case ARM::STMIA_UPD:
3327 case ARM::STMDA_UPD:
3328 case ARM::STMDB_UPD:
3329 case ARM::STMIB_UPD:
3330 case ARM::tSTMIA_UPD:
3335 case ARM::t2STMIA_UPD:
3336 case ARM::t2STMDB_UPD:
3337 UseCycle = getSTMUseCycle(ItinData, UseMCID, UseClass, UseIdx, UseAlign);
3342 // Assume it's read in the first stage.
3345 UseCycle = DefCycle - UseCycle + 1;
3348 // It's a variable_ops instruction so we can't use DefIdx here. Just use
3349 // first def operand.
3350 if (ItinData->hasPipelineForwarding(DefClass, DefMCID.getNumOperands()-1,
3353 } else if (ItinData->hasPipelineForwarding(DefClass, DefIdx,
3354 UseClass, UseIdx)) {
3362 static const MachineInstr *getBundledDefMI(const TargetRegisterInfo *TRI,
3363 const MachineInstr *MI, unsigned Reg,
3364 unsigned &DefIdx, unsigned &Dist) {
3367 MachineBasicBlock::const_iterator I = MI; ++I;
3368 MachineBasicBlock::const_instr_iterator II = std::prev(I.getInstrIterator());
3369 assert(II->isInsideBundle() && "Empty bundle?");
3372 while (II->isInsideBundle()) {
3373 Idx = II->findRegisterDefOperandIdx(Reg, false, true, TRI);
3380 assert(Idx != -1 && "Cannot find bundled definition!");
3385 static const MachineInstr *getBundledUseMI(const TargetRegisterInfo *TRI,
3386 const MachineInstr *MI, unsigned Reg,
3387 unsigned &UseIdx, unsigned &Dist) {
3390 MachineBasicBlock::const_instr_iterator II = MI; ++II;
3391 assert(II->isInsideBundle() && "Empty bundle?");
3392 MachineBasicBlock::const_instr_iterator E = MI->getParent()->instr_end();
3394 // FIXME: This doesn't properly handle multiple uses.
3396 while (II != E && II->isInsideBundle()) {
3397 Idx = II->findRegisterUseOperandIdx(Reg, false, TRI);
3400 if (II->getOpcode() != ARM::t2IT)
3414 /// Return the number of cycles to add to (or subtract from) the static
3415 /// itinerary based on the def opcode and alignment. The caller will ensure that
3416 /// adjusted latency is at least one cycle.
3417 static int adjustDefLatency(const ARMSubtarget &Subtarget,
3418 const MachineInstr *DefMI,
3419 const MCInstrDesc *DefMCID, unsigned DefAlign) {
3421 if (Subtarget.isCortexA8() || Subtarget.isLikeA9() || Subtarget.isCortexA7()) {
3422 // FIXME: Shifter op hack: no shift (i.e. [r +/- r]) or [r + r << 2]
3423 // variants are one cycle cheaper.
3424 switch (DefMCID->getOpcode()) {
3428 unsigned ShOpVal = DefMI->getOperand(3).getImm();
3429 unsigned ShImm = ARM_AM::getAM2Offset(ShOpVal);
3431 (ShImm == 2 && ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl))
3438 case ARM::t2LDRSHs: {
3439 // Thumb2 mode: lsl only.
3440 unsigned ShAmt = DefMI->getOperand(3).getImm();
3441 if (ShAmt == 0 || ShAmt == 2)
3446 } else if (Subtarget.isSwift()) {
3447 // FIXME: Properly handle all of the latency adjustments for address
3449 switch (DefMCID->getOpcode()) {
3453 unsigned ShOpVal = DefMI->getOperand(3).getImm();
3454 bool isSub = ARM_AM::getAM2Op(ShOpVal) == ARM_AM::sub;
3455 unsigned ShImm = ARM_AM::getAM2Offset(ShOpVal);
3458 ((ShImm == 1 || ShImm == 2 || ShImm == 3) &&
3459 ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl)))
3462 ShImm == 1 && ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsr)
3469 case ARM::t2LDRSHs: {
3470 // Thumb2 mode: lsl only.
3471 unsigned ShAmt = DefMI->getOperand(3).getImm();
3472 if (ShAmt == 0 || ShAmt == 1 || ShAmt == 2 || ShAmt == 3)
3479 if (DefAlign < 8 && Subtarget.isLikeA9()) {
3480 switch (DefMCID->getOpcode()) {
3486 case ARM::VLD1q8wb_fixed:
3487 case ARM::VLD1q16wb_fixed:
3488 case ARM::VLD1q32wb_fixed:
3489 case ARM::VLD1q64wb_fixed:
3490 case ARM::VLD1q8wb_register:
3491 case ARM::VLD1q16wb_register:
3492 case ARM::VLD1q32wb_register:
3493 case ARM::VLD1q64wb_register:
3500 case ARM::VLD2d8wb_fixed:
3501 case ARM::VLD2d16wb_fixed:
3502 case ARM::VLD2d32wb_fixed:
3503 case ARM::VLD2q8wb_fixed:
3504 case ARM::VLD2q16wb_fixed:
3505 case ARM::VLD2q32wb_fixed:
3506 case ARM::VLD2d8wb_register:
3507 case ARM::VLD2d16wb_register:
3508 case ARM::VLD2d32wb_register:
3509 case ARM::VLD2q8wb_register:
3510 case ARM::VLD2q16wb_register:
3511 case ARM::VLD2q32wb_register:
3516 case ARM::VLD3d8_UPD:
3517 case ARM::VLD3d16_UPD:
3518 case ARM::VLD3d32_UPD:
3519 case ARM::VLD1d64Twb_fixed:
3520 case ARM::VLD1d64Twb_register:
3521 case ARM::VLD3q8_UPD:
3522 case ARM::VLD3q16_UPD:
3523 case ARM::VLD3q32_UPD:
3528 case ARM::VLD4d8_UPD:
3529 case ARM::VLD4d16_UPD:
3530 case ARM::VLD4d32_UPD:
3531 case ARM::VLD1d64Qwb_fixed:
3532 case ARM::VLD1d64Qwb_register:
3533 case ARM::VLD4q8_UPD:
3534 case ARM::VLD4q16_UPD:
3535 case ARM::VLD4q32_UPD:
3536 case ARM::VLD1DUPq8:
3537 case ARM::VLD1DUPq16:
3538 case ARM::VLD1DUPq32:
3539 case ARM::VLD1DUPq8wb_fixed:
3540 case ARM::VLD1DUPq16wb_fixed:
3541 case ARM::VLD1DUPq32wb_fixed:
3542 case ARM::VLD1DUPq8wb_register:
3543 case ARM::VLD1DUPq16wb_register:
3544 case ARM::VLD1DUPq32wb_register:
3545 case ARM::VLD2DUPd8:
3546 case ARM::VLD2DUPd16:
3547 case ARM::VLD2DUPd32:
3548 case ARM::VLD2DUPd8wb_fixed:
3549 case ARM::VLD2DUPd16wb_fixed:
3550 case ARM::VLD2DUPd32wb_fixed:
3551 case ARM::VLD2DUPd8wb_register:
3552 case ARM::VLD2DUPd16wb_register:
3553 case ARM::VLD2DUPd32wb_register:
3554 case ARM::VLD4DUPd8:
3555 case ARM::VLD4DUPd16:
3556 case ARM::VLD4DUPd32:
3557 case ARM::VLD4DUPd8_UPD:
3558 case ARM::VLD4DUPd16_UPD:
3559 case ARM::VLD4DUPd32_UPD:
3561 case ARM::VLD1LNd16:
3562 case ARM::VLD1LNd32:
3563 case ARM::VLD1LNd8_UPD:
3564 case ARM::VLD1LNd16_UPD:
3565 case ARM::VLD1LNd32_UPD:
3567 case ARM::VLD2LNd16:
3568 case ARM::VLD2LNd32:
3569 case ARM::VLD2LNq16:
3570 case ARM::VLD2LNq32:
3571 case ARM::VLD2LNd8_UPD:
3572 case ARM::VLD2LNd16_UPD:
3573 case ARM::VLD2LNd32_UPD:
3574 case ARM::VLD2LNq16_UPD:
3575 case ARM::VLD2LNq32_UPD:
3577 case ARM::VLD4LNd16:
3578 case ARM::VLD4LNd32:
3579 case ARM::VLD4LNq16:
3580 case ARM::VLD4LNq32:
3581 case ARM::VLD4LNd8_UPD:
3582 case ARM::VLD4LNd16_UPD:
3583 case ARM::VLD4LNd32_UPD:
3584 case ARM::VLD4LNq16_UPD:
3585 case ARM::VLD4LNq32_UPD:
3586 // If the address is not 64-bit aligned, the latencies of these
3587 // instructions increases by one.
3598 ARMBaseInstrInfo::getOperandLatency(const InstrItineraryData *ItinData,
3599 const MachineInstr *DefMI, unsigned DefIdx,
3600 const MachineInstr *UseMI,
3601 unsigned UseIdx) const {
3602 // No operand latency. The caller may fall back to getInstrLatency.
3603 if (!ItinData || ItinData->isEmpty())
3606 const MachineOperand &DefMO = DefMI->getOperand(DefIdx);
3607 unsigned Reg = DefMO.getReg();
3608 const MCInstrDesc *DefMCID = &DefMI->getDesc();
3609 const MCInstrDesc *UseMCID = &UseMI->getDesc();
3611 unsigned DefAdj = 0;
3612 if (DefMI->isBundle()) {
3613 DefMI = getBundledDefMI(&getRegisterInfo(), DefMI, Reg, DefIdx, DefAdj);
3614 DefMCID = &DefMI->getDesc();
3616 if (DefMI->isCopyLike() || DefMI->isInsertSubreg() ||
3617 DefMI->isRegSequence() || DefMI->isImplicitDef()) {
3621 unsigned UseAdj = 0;
3622 if (UseMI->isBundle()) {
3624 const MachineInstr *NewUseMI = getBundledUseMI(&getRegisterInfo(), UseMI,
3625 Reg, NewUseIdx, UseAdj);
3631 UseMCID = &UseMI->getDesc();
3634 if (Reg == ARM::CPSR) {
3635 if (DefMI->getOpcode() == ARM::FMSTAT) {
3636 // fpscr -> cpsr stalls over 20 cycles on A8 (and earlier?)
3637 return Subtarget.isLikeA9() ? 1 : 20;
3640 // CPSR set and branch can be paired in the same cycle.
3641 if (UseMI->isBranch())
3644 // Otherwise it takes the instruction latency (generally one).
3645 unsigned Latency = getInstrLatency(ItinData, DefMI);
3647 // For Thumb2 and -Os, prefer scheduling CPSR setting instruction close to
3648 // its uses. Instructions which are otherwise scheduled between them may
3649 // incur a code size penalty (not able to use the CPSR setting 16-bit
3651 if (Latency > 0 && Subtarget.isThumb2()) {
3652 const MachineFunction *MF = DefMI->getParent()->getParent();
3653 // FIXME: Use Function::optForSize().
3654 if (MF->getFunction()->hasFnAttribute(Attribute::OptimizeForSize))
3660 if (DefMO.isImplicit() || UseMI->getOperand(UseIdx).isImplicit())
3663 unsigned DefAlign = DefMI->hasOneMemOperand()
3664 ? (*DefMI->memoperands_begin())->getAlignment() : 0;
3665 unsigned UseAlign = UseMI->hasOneMemOperand()
3666 ? (*UseMI->memoperands_begin())->getAlignment() : 0;
3668 // Get the itinerary's latency if possible, and handle variable_ops.
3669 int Latency = getOperandLatency(ItinData, *DefMCID, DefIdx, DefAlign,
3670 *UseMCID, UseIdx, UseAlign);
3671 // Unable to find operand latency. The caller may resort to getInstrLatency.
3675 // Adjust for IT block position.
3676 int Adj = DefAdj + UseAdj;
3678 // Adjust for dynamic def-side opcode variants not captured by the itinerary.
3679 Adj += adjustDefLatency(Subtarget, DefMI, DefMCID, DefAlign);
3680 if (Adj >= 0 || (int)Latency > -Adj) {
3681 return Latency + Adj;
3683 // Return the itinerary latency, which may be zero but not less than zero.
3688 ARMBaseInstrInfo::getOperandLatency(const InstrItineraryData *ItinData,
3689 SDNode *DefNode, unsigned DefIdx,
3690 SDNode *UseNode, unsigned UseIdx) const {
3691 if (!DefNode->isMachineOpcode())
3694 const MCInstrDesc &DefMCID = get(DefNode->getMachineOpcode());
3696 if (isZeroCost(DefMCID.Opcode))
3699 if (!ItinData || ItinData->isEmpty())
3700 return DefMCID.mayLoad() ? 3 : 1;
3702 if (!UseNode->isMachineOpcode()) {
3703 int Latency = ItinData->getOperandCycle(DefMCID.getSchedClass(), DefIdx);
3704 if (Subtarget.isLikeA9() || Subtarget.isSwift())
3705 return Latency <= 2 ? 1 : Latency - 1;
3707 return Latency <= 3 ? 1 : Latency - 2;
3710 const MCInstrDesc &UseMCID = get(UseNode->getMachineOpcode());
3711 const MachineSDNode *DefMN = dyn_cast<MachineSDNode>(DefNode);
3712 unsigned DefAlign = !DefMN->memoperands_empty()
3713 ? (*DefMN->memoperands_begin())->getAlignment() : 0;
3714 const MachineSDNode *UseMN = dyn_cast<MachineSDNode>(UseNode);
3715 unsigned UseAlign = !UseMN->memoperands_empty()
3716 ? (*UseMN->memoperands_begin())->getAlignment() : 0;
3717 int Latency = getOperandLatency(ItinData, DefMCID, DefIdx, DefAlign,
3718 UseMCID, UseIdx, UseAlign);
3721 (Subtarget.isCortexA8() || Subtarget.isLikeA9() ||
3722 Subtarget.isCortexA7())) {
3723 // FIXME: Shifter op hack: no shift (i.e. [r +/- r]) or [r + r << 2]
3724 // variants are one cycle cheaper.
3725 switch (DefMCID.getOpcode()) {
3730 cast<ConstantSDNode>(DefNode->getOperand(2))->getZExtValue();
3731 unsigned ShImm = ARM_AM::getAM2Offset(ShOpVal);
3733 (ShImm == 2 && ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl))
3740 case ARM::t2LDRSHs: {
3741 // Thumb2 mode: lsl only.
3743 cast<ConstantSDNode>(DefNode->getOperand(2))->getZExtValue();
3744 if (ShAmt == 0 || ShAmt == 2)
3749 } else if (DefIdx == 0 && Latency > 2 && Subtarget.isSwift()) {
3750 // FIXME: Properly handle all of the latency adjustments for address
3752 switch (DefMCID.getOpcode()) {
3757 cast<ConstantSDNode>(DefNode->getOperand(2))->getZExtValue();
3758 unsigned ShImm = ARM_AM::getAM2Offset(ShOpVal);
3760 ((ShImm == 1 || ShImm == 2 || ShImm == 3) &&
3761 ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl))
3763 else if (ShImm == 1 && ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsr)
3770 case ARM::t2LDRSHs: {
3771 // Thumb2 mode: lsl 0-3 only.
3778 if (DefAlign < 8 && Subtarget.isLikeA9())
3779 switch (DefMCID.getOpcode()) {
3785 case ARM::VLD1q8wb_register:
3786 case ARM::VLD1q16wb_register:
3787 case ARM::VLD1q32wb_register:
3788 case ARM::VLD1q64wb_register:
3789 case ARM::VLD1q8wb_fixed:
3790 case ARM::VLD1q16wb_fixed:
3791 case ARM::VLD1q32wb_fixed:
3792 case ARM::VLD1q64wb_fixed:
3796 case ARM::VLD2q8Pseudo:
3797 case ARM::VLD2q16Pseudo:
3798 case ARM::VLD2q32Pseudo:
3799 case ARM::VLD2d8wb_fixed:
3800 case ARM::VLD2d16wb_fixed:
3801 case ARM::VLD2d32wb_fixed:
3802 case ARM::VLD2q8PseudoWB_fixed:
3803 case ARM::VLD2q16PseudoWB_fixed:
3804 case ARM::VLD2q32PseudoWB_fixed:
3805 case ARM::VLD2d8wb_register:
3806 case ARM::VLD2d16wb_register:
3807 case ARM::VLD2d32wb_register:
3808 case ARM::VLD2q8PseudoWB_register:
3809 case ARM::VLD2q16PseudoWB_register:
3810 case ARM::VLD2q32PseudoWB_register:
3811 case ARM::VLD3d8Pseudo:
3812 case ARM::VLD3d16Pseudo:
3813 case ARM::VLD3d32Pseudo:
3814 case ARM::VLD1d64TPseudo:
3815 case ARM::VLD1d64TPseudoWB_fixed:
3816 case ARM::VLD3d8Pseudo_UPD:
3817 case ARM::VLD3d16Pseudo_UPD:
3818 case ARM::VLD3d32Pseudo_UPD:
3819 case ARM::VLD3q8Pseudo_UPD:
3820 case ARM::VLD3q16Pseudo_UPD:
3821 case ARM::VLD3q32Pseudo_UPD:
3822 case ARM::VLD3q8oddPseudo:
3823 case ARM::VLD3q16oddPseudo:
3824 case ARM::VLD3q32oddPseudo:
3825 case ARM::VLD3q8oddPseudo_UPD:
3826 case ARM::VLD3q16oddPseudo_UPD:
3827 case ARM::VLD3q32oddPseudo_UPD:
3828 case ARM::VLD4d8Pseudo:
3829 case ARM::VLD4d16Pseudo:
3830 case ARM::VLD4d32Pseudo:
3831 case ARM::VLD1d64QPseudo:
3832 case ARM::VLD1d64QPseudoWB_fixed:
3833 case ARM::VLD4d8Pseudo_UPD:
3834 case ARM::VLD4d16Pseudo_UPD:
3835 case ARM::VLD4d32Pseudo_UPD:
3836 case ARM::VLD4q8Pseudo_UPD:
3837 case ARM::VLD4q16Pseudo_UPD:
3838 case ARM::VLD4q32Pseudo_UPD:
3839 case ARM::VLD4q8oddPseudo:
3840 case ARM::VLD4q16oddPseudo:
3841 case ARM::VLD4q32oddPseudo:
3842 case ARM::VLD4q8oddPseudo_UPD:
3843 case ARM::VLD4q16oddPseudo_UPD:
3844 case ARM::VLD4q32oddPseudo_UPD:
3845 case ARM::VLD1DUPq8:
3846 case ARM::VLD1DUPq16:
3847 case ARM::VLD1DUPq32:
3848 case ARM::VLD1DUPq8wb_fixed:
3849 case ARM::VLD1DUPq16wb_fixed:
3850 case ARM::VLD1DUPq32wb_fixed:
3851 case ARM::VLD1DUPq8wb_register:
3852 case ARM::VLD1DUPq16wb_register:
3853 case ARM::VLD1DUPq32wb_register:
3854 case ARM::VLD2DUPd8:
3855 case ARM::VLD2DUPd16:
3856 case ARM::VLD2DUPd32:
3857 case ARM::VLD2DUPd8wb_fixed:
3858 case ARM::VLD2DUPd16wb_fixed:
3859 case ARM::VLD2DUPd32wb_fixed:
3860 case ARM::VLD2DUPd8wb_register:
3861 case ARM::VLD2DUPd16wb_register:
3862 case ARM::VLD2DUPd32wb_register:
3863 case ARM::VLD4DUPd8Pseudo:
3864 case ARM::VLD4DUPd16Pseudo:
3865 case ARM::VLD4DUPd32Pseudo:
3866 case ARM::VLD4DUPd8Pseudo_UPD:
3867 case ARM::VLD4DUPd16Pseudo_UPD:
3868 case ARM::VLD4DUPd32Pseudo_UPD:
3869 case ARM::VLD1LNq8Pseudo:
3870 case ARM::VLD1LNq16Pseudo:
3871 case ARM::VLD1LNq32Pseudo:
3872 case ARM::VLD1LNq8Pseudo_UPD:
3873 case ARM::VLD1LNq16Pseudo_UPD:
3874 case ARM::VLD1LNq32Pseudo_UPD:
3875 case ARM::VLD2LNd8Pseudo:
3876 case ARM::VLD2LNd16Pseudo:
3877 case ARM::VLD2LNd32Pseudo:
3878 case ARM::VLD2LNq16Pseudo:
3879 case ARM::VLD2LNq32Pseudo:
3880 case ARM::VLD2LNd8Pseudo_UPD:
3881 case ARM::VLD2LNd16Pseudo_UPD:
3882 case ARM::VLD2LNd32Pseudo_UPD:
3883 case ARM::VLD2LNq16Pseudo_UPD:
3884 case ARM::VLD2LNq32Pseudo_UPD:
3885 case ARM::VLD4LNd8Pseudo:
3886 case ARM::VLD4LNd16Pseudo:
3887 case ARM::VLD4LNd32Pseudo:
3888 case ARM::VLD4LNq16Pseudo:
3889 case ARM::VLD4LNq32Pseudo:
3890 case ARM::VLD4LNd8Pseudo_UPD:
3891 case ARM::VLD4LNd16Pseudo_UPD:
3892 case ARM::VLD4LNd32Pseudo_UPD:
3893 case ARM::VLD4LNq16Pseudo_UPD:
3894 case ARM::VLD4LNq32Pseudo_UPD:
3895 // If the address is not 64-bit aligned, the latencies of these
3896 // instructions increases by one.
3904 unsigned ARMBaseInstrInfo::getPredicationCost(const MachineInstr *MI) const {
3905 if (MI->isCopyLike() || MI->isInsertSubreg() ||
3906 MI->isRegSequence() || MI->isImplicitDef())
3912 const MCInstrDesc &MCID = MI->getDesc();
3914 if (MCID.isCall() || MCID.hasImplicitDefOfPhysReg(ARM::CPSR)) {
3915 // When predicated, CPSR is an additional source operand for CPSR updating
3916 // instructions, this apparently increases their latencies.
3922 unsigned ARMBaseInstrInfo::getInstrLatency(const InstrItineraryData *ItinData,
3923 const MachineInstr *MI,
3924 unsigned *PredCost) const {
3925 if (MI->isCopyLike() || MI->isInsertSubreg() ||
3926 MI->isRegSequence() || MI->isImplicitDef())
3929 // An instruction scheduler typically runs on unbundled instructions, however
3930 // other passes may query the latency of a bundled instruction.
3931 if (MI->isBundle()) {
3932 unsigned Latency = 0;
3933 MachineBasicBlock::const_instr_iterator I = MI;
3934 MachineBasicBlock::const_instr_iterator E = MI->getParent()->instr_end();
3935 while (++I != E && I->isInsideBundle()) {
3936 if (I->getOpcode() != ARM::t2IT)
3937 Latency += getInstrLatency(ItinData, I, PredCost);
3942 const MCInstrDesc &MCID = MI->getDesc();
3943 if (PredCost && (MCID.isCall() || MCID.hasImplicitDefOfPhysReg(ARM::CPSR))) {
3944 // When predicated, CPSR is an additional source operand for CPSR updating
3945 // instructions, this apparently increases their latencies.
3948 // Be sure to call getStageLatency for an empty itinerary in case it has a
3949 // valid MinLatency property.
3951 return MI->mayLoad() ? 3 : 1;
3953 unsigned Class = MCID.getSchedClass();
3955 // For instructions with variable uops, use uops as latency.
3956 if (!ItinData->isEmpty() && ItinData->getNumMicroOps(Class) < 0)
3957 return getNumMicroOps(ItinData, MI);
3959 // For the common case, fall back on the itinerary's latency.
3960 unsigned Latency = ItinData->getStageLatency(Class);
3962 // Adjust for dynamic def-side opcode variants not captured by the itinerary.
3963 unsigned DefAlign = MI->hasOneMemOperand()
3964 ? (*MI->memoperands_begin())->getAlignment() : 0;
3965 int Adj = adjustDefLatency(Subtarget, MI, &MCID, DefAlign);
3966 if (Adj >= 0 || (int)Latency > -Adj) {
3967 return Latency + Adj;
3972 int ARMBaseInstrInfo::getInstrLatency(const InstrItineraryData *ItinData,
3973 SDNode *Node) const {
3974 if (!Node->isMachineOpcode())
3977 if (!ItinData || ItinData->isEmpty())
3980 unsigned Opcode = Node->getMachineOpcode();
3983 return ItinData->getStageLatency(get(Opcode).getSchedClass());
3990 bool ARMBaseInstrInfo::
3991 hasHighOperandLatency(const TargetSchedModel &SchedModel,
3992 const MachineRegisterInfo *MRI,
3993 const MachineInstr *DefMI, unsigned DefIdx,
3994 const MachineInstr *UseMI, unsigned UseIdx) const {
3995 unsigned DDomain = DefMI->getDesc().TSFlags & ARMII::DomainMask;
3996 unsigned UDomain = UseMI->getDesc().TSFlags & ARMII::DomainMask;
3997 if (Subtarget.isCortexA8() &&
3998 (DDomain == ARMII::DomainVFP || UDomain == ARMII::DomainVFP))
3999 // CortexA8 VFP instructions are not pipelined.
4002 // Hoist VFP / NEON instructions with 4 or higher latency.
4004 = SchedModel.computeOperandLatency(DefMI, DefIdx, UseMI, UseIdx);
4007 return DDomain == ARMII::DomainVFP || DDomain == ARMII::DomainNEON ||
4008 UDomain == ARMII::DomainVFP || UDomain == ARMII::DomainNEON;
4011 bool ARMBaseInstrInfo::
4012 hasLowDefLatency(const TargetSchedModel &SchedModel,
4013 const MachineInstr *DefMI, unsigned DefIdx) const {
4014 const InstrItineraryData *ItinData = SchedModel.getInstrItineraries();
4015 if (!ItinData || ItinData->isEmpty())
4018 unsigned DDomain = DefMI->getDesc().TSFlags & ARMII::DomainMask;
4019 if (DDomain == ARMII::DomainGeneral) {
4020 unsigned DefClass = DefMI->getDesc().getSchedClass();
4021 int DefCycle = ItinData->getOperandCycle(DefClass, DefIdx);
4022 return (DefCycle != -1 && DefCycle <= 2);
4027 bool ARMBaseInstrInfo::verifyInstruction(const MachineInstr *MI,
4028 StringRef &ErrInfo) const {
4029 if (convertAddSubFlagsOpcode(MI->getOpcode())) {
4030 ErrInfo = "Pseudo flag setting opcodes only exist in Selection DAG";
4036 // LoadStackGuard has so far only been implemented for MachO. Different code
4037 // sequence is needed for other targets.
4038 void ARMBaseInstrInfo::expandLoadStackGuardBase(MachineBasicBlock::iterator MI,
4039 unsigned LoadImmOpc,
4041 Reloc::Model RM) const {
4042 MachineBasicBlock &MBB = *MI->getParent();
4043 DebugLoc DL = MI->getDebugLoc();
4044 unsigned Reg = MI->getOperand(0).getReg();
4045 const GlobalValue *GV =
4046 cast<GlobalValue>((*MI->memoperands_begin())->getValue());
4047 MachineInstrBuilder MIB;
4049 BuildMI(MBB, MI, DL, get(LoadImmOpc), Reg)
4050 .addGlobalAddress(GV, 0, ARMII::MO_NONLAZY);
4052 if (Subtarget.GVIsIndirectSymbol(GV, RM)) {
4053 MIB = BuildMI(MBB, MI, DL, get(LoadOpc), Reg);
4054 MIB.addReg(Reg, RegState::Kill).addImm(0);
4055 unsigned Flag = MachineMemOperand::MOLoad | MachineMemOperand::MOInvariant;
4056 MachineMemOperand *MMO = MBB.getParent()->
4057 getMachineMemOperand(MachinePointerInfo::getGOT(), Flag, 4, 4);
4058 MIB.addMemOperand(MMO);
4059 AddDefaultPred(MIB);
4062 MIB = BuildMI(MBB, MI, DL, get(LoadOpc), Reg);
4063 MIB.addReg(Reg, RegState::Kill).addImm(0);
4064 MIB.setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
4065 AddDefaultPred(MIB);
4069 ARMBaseInstrInfo::isFpMLxInstruction(unsigned Opcode, unsigned &MulOpc,
4070 unsigned &AddSubOpc,
4071 bool &NegAcc, bool &HasLane) const {
4072 DenseMap<unsigned, unsigned>::const_iterator I = MLxEntryMap.find(Opcode);
4073 if (I == MLxEntryMap.end())
4076 const ARM_MLxEntry &Entry = ARM_MLxTable[I->second];
4077 MulOpc = Entry.MulOpc;
4078 AddSubOpc = Entry.AddSubOpc;
4079 NegAcc = Entry.NegAcc;
4080 HasLane = Entry.HasLane;
4084 //===----------------------------------------------------------------------===//
4085 // Execution domains.
4086 //===----------------------------------------------------------------------===//
4088 // Some instructions go down the NEON pipeline, some go down the VFP pipeline,
4089 // and some can go down both. The vmov instructions go down the VFP pipeline,
4090 // but they can be changed to vorr equivalents that are executed by the NEON
4093 // We use the following execution domain numbering:
4101 // Also see ARMInstrFormats.td and Domain* enums in ARMBaseInfo.h
4103 std::pair<uint16_t, uint16_t>
4104 ARMBaseInstrInfo::getExecutionDomain(const MachineInstr *MI) const {
4105 // If we don't have access to NEON instructions then we won't be able
4106 // to swizzle anything to the NEON domain. Check to make sure.
4107 if (Subtarget.hasNEON()) {
4108 // VMOVD, VMOVRS and VMOVSR are VFP instructions, but can be changed to NEON
4109 // if they are not predicated.
4110 if (MI->getOpcode() == ARM::VMOVD && !isPredicated(MI))
4111 return std::make_pair(ExeVFP, (1 << ExeVFP) | (1 << ExeNEON));
4113 // CortexA9 is particularly picky about mixing the two and wants these
4115 if (Subtarget.isCortexA9() && !isPredicated(MI) &&
4116 (MI->getOpcode() == ARM::VMOVRS || MI->getOpcode() == ARM::VMOVSR ||
4117 MI->getOpcode() == ARM::VMOVS))
4118 return std::make_pair(ExeVFP, (1 << ExeVFP) | (1 << ExeNEON));
4120 // No other instructions can be swizzled, so just determine their domain.
4121 unsigned Domain = MI->getDesc().TSFlags & ARMII::DomainMask;
4123 if (Domain & ARMII::DomainNEON)
4124 return std::make_pair(ExeNEON, 0);
4126 // Certain instructions can go either way on Cortex-A8.
4127 // Treat them as NEON instructions.
4128 if ((Domain & ARMII::DomainNEONA8) && Subtarget.isCortexA8())
4129 return std::make_pair(ExeNEON, 0);
4131 if (Domain & ARMII::DomainVFP)
4132 return std::make_pair(ExeVFP, 0);
4134 return std::make_pair(ExeGeneric, 0);
4137 static unsigned getCorrespondingDRegAndLane(const TargetRegisterInfo *TRI,
4138 unsigned SReg, unsigned &Lane) {
4139 unsigned DReg = TRI->getMatchingSuperReg(SReg, ARM::ssub_0, &ARM::DPRRegClass);
4142 if (DReg != ARM::NoRegister)
4146 DReg = TRI->getMatchingSuperReg(SReg, ARM::ssub_1, &ARM::DPRRegClass);
4148 assert(DReg && "S-register with no D super-register?");
4152 /// getImplicitSPRUseForDPRUse - Given a use of a DPR register and lane,
4153 /// set ImplicitSReg to a register number that must be marked as implicit-use or
4154 /// zero if no register needs to be defined as implicit-use.
4156 /// If the function cannot determine if an SPR should be marked implicit use or
4157 /// not, it returns false.
4159 /// This function handles cases where an instruction is being modified from taking
4160 /// an SPR to a DPR[Lane]. A use of the DPR is being added, which may conflict
4161 /// with an earlier def of an SPR corresponding to DPR[Lane^1] (i.e. the other
4162 /// lane of the DPR).
4164 /// If the other SPR is defined, an implicit-use of it should be added. Else,
4165 /// (including the case where the DPR itself is defined), it should not.
4167 static bool getImplicitSPRUseForDPRUse(const TargetRegisterInfo *TRI,
4169 unsigned DReg, unsigned Lane,
4170 unsigned &ImplicitSReg) {
4171 // If the DPR is defined or used already, the other SPR lane will be chained
4172 // correctly, so there is nothing to be done.
4173 if (MI->definesRegister(DReg, TRI) || MI->readsRegister(DReg, TRI)) {
4178 // Otherwise we need to go searching to see if the SPR is set explicitly.
4179 ImplicitSReg = TRI->getSubReg(DReg,
4180 (Lane & 1) ? ARM::ssub_0 : ARM::ssub_1);
4181 MachineBasicBlock::LivenessQueryResult LQR =
4182 MI->getParent()->computeRegisterLiveness(TRI, ImplicitSReg, MI);
4184 if (LQR == MachineBasicBlock::LQR_Live)
4186 else if (LQR == MachineBasicBlock::LQR_Unknown)
4189 // If the register is known not to be live, there is no need to add an
4196 ARMBaseInstrInfo::setExecutionDomain(MachineInstr *MI, unsigned Domain) const {
4197 unsigned DstReg, SrcReg, DReg;
4199 MachineInstrBuilder MIB(*MI->getParent()->getParent(), MI);
4200 const TargetRegisterInfo *TRI = &getRegisterInfo();
4201 switch (MI->getOpcode()) {
4203 llvm_unreachable("cannot handle opcode!");
4206 if (Domain != ExeNEON)
4209 // Zap the predicate operands.
4210 assert(!isPredicated(MI) && "Cannot predicate a VORRd");
4212 // Make sure we've got NEON instructions.
4213 assert(Subtarget.hasNEON() && "VORRd requires NEON");
4215 // Source instruction is %DDst = VMOVD %DSrc, 14, %noreg (; implicits)
4216 DstReg = MI->getOperand(0).getReg();
4217 SrcReg = MI->getOperand(1).getReg();
4219 for (unsigned i = MI->getDesc().getNumOperands(); i; --i)
4220 MI->RemoveOperand(i-1);
4222 // Change to a %DDst = VORRd %DSrc, %DSrc, 14, %noreg (; implicits)
4223 MI->setDesc(get(ARM::VORRd));
4224 AddDefaultPred(MIB.addReg(DstReg, RegState::Define)
4229 if (Domain != ExeNEON)
4231 assert(!isPredicated(MI) && "Cannot predicate a VGETLN");
4233 // Source instruction is %RDst = VMOVRS %SSrc, 14, %noreg (; implicits)
4234 DstReg = MI->getOperand(0).getReg();
4235 SrcReg = MI->getOperand(1).getReg();
4237 for (unsigned i = MI->getDesc().getNumOperands(); i; --i)
4238 MI->RemoveOperand(i-1);
4240 DReg = getCorrespondingDRegAndLane(TRI, SrcReg, Lane);
4242 // Convert to %RDst = VGETLNi32 %DSrc, Lane, 14, %noreg (; imps)
4243 // Note that DSrc has been widened and the other lane may be undef, which
4244 // contaminates the entire register.
4245 MI->setDesc(get(ARM::VGETLNi32));
4246 AddDefaultPred(MIB.addReg(DstReg, RegState::Define)
4247 .addReg(DReg, RegState::Undef)
4250 // The old source should be an implicit use, otherwise we might think it
4251 // was dead before here.
4252 MIB.addReg(SrcReg, RegState::Implicit);
4255 if (Domain != ExeNEON)
4257 assert(!isPredicated(MI) && "Cannot predicate a VSETLN");
4259 // Source instruction is %SDst = VMOVSR %RSrc, 14, %noreg (; implicits)
4260 DstReg = MI->getOperand(0).getReg();
4261 SrcReg = MI->getOperand(1).getReg();
4263 DReg = getCorrespondingDRegAndLane(TRI, DstReg, Lane);
4265 unsigned ImplicitSReg;
4266 if (!getImplicitSPRUseForDPRUse(TRI, MI, DReg, Lane, ImplicitSReg))
4269 for (unsigned i = MI->getDesc().getNumOperands(); i; --i)
4270 MI->RemoveOperand(i-1);
4272 // Convert to %DDst = VSETLNi32 %DDst, %RSrc, Lane, 14, %noreg (; imps)
4273 // Again DDst may be undefined at the beginning of this instruction.
4274 MI->setDesc(get(ARM::VSETLNi32));
4275 MIB.addReg(DReg, RegState::Define)
4276 .addReg(DReg, getUndefRegState(!MI->readsRegister(DReg, TRI)))
4279 AddDefaultPred(MIB);
4281 // The narrower destination must be marked as set to keep previous chains
4283 MIB.addReg(DstReg, RegState::Define | RegState::Implicit);
4284 if (ImplicitSReg != 0)
4285 MIB.addReg(ImplicitSReg, RegState::Implicit);
4289 if (Domain != ExeNEON)
4292 // Source instruction is %SDst = VMOVS %SSrc, 14, %noreg (; implicits)
4293 DstReg = MI->getOperand(0).getReg();
4294 SrcReg = MI->getOperand(1).getReg();
4296 unsigned DstLane = 0, SrcLane = 0, DDst, DSrc;
4297 DDst = getCorrespondingDRegAndLane(TRI, DstReg, DstLane);
4298 DSrc = getCorrespondingDRegAndLane(TRI, SrcReg, SrcLane);
4300 unsigned ImplicitSReg;
4301 if (!getImplicitSPRUseForDPRUse(TRI, MI, DSrc, SrcLane, ImplicitSReg))
4304 for (unsigned i = MI->getDesc().getNumOperands(); i; --i)
4305 MI->RemoveOperand(i-1);
4308 // Destination can be:
4309 // %DDst = VDUPLN32d %DDst, Lane, 14, %noreg (; implicits)
4310 MI->setDesc(get(ARM::VDUPLN32d));
4311 MIB.addReg(DDst, RegState::Define)
4312 .addReg(DDst, getUndefRegState(!MI->readsRegister(DDst, TRI)))
4314 AddDefaultPred(MIB);
4316 // Neither the source or the destination are naturally represented any
4317 // more, so add them in manually.
4318 MIB.addReg(DstReg, RegState::Implicit | RegState::Define);
4319 MIB.addReg(SrcReg, RegState::Implicit);
4320 if (ImplicitSReg != 0)
4321 MIB.addReg(ImplicitSReg, RegState::Implicit);
4325 // In general there's no single instruction that can perform an S <-> S
4326 // move in NEON space, but a pair of VEXT instructions *can* do the
4327 // job. It turns out that the VEXTs needed will only use DSrc once, with
4328 // the position based purely on the combination of lane-0 and lane-1
4329 // involved. For example
4330 // vmov s0, s2 -> vext.32 d0, d0, d1, #1 vext.32 d0, d0, d0, #1
4331 // vmov s1, s3 -> vext.32 d0, d1, d0, #1 vext.32 d0, d0, d0, #1
4332 // vmov s0, s3 -> vext.32 d0, d0, d0, #1 vext.32 d0, d1, d0, #1
4333 // vmov s1, s2 -> vext.32 d0, d0, d0, #1 vext.32 d0, d0, d1, #1
4335 // Pattern of the MachineInstrs is:
4336 // %DDst = VEXTd32 %DSrc1, %DSrc2, Lane, 14, %noreg (;implicits)
4337 MachineInstrBuilder NewMIB;
4338 NewMIB = BuildMI(*MI->getParent(), MI, MI->getDebugLoc(),
4339 get(ARM::VEXTd32), DDst);
4341 // On the first instruction, both DSrc and DDst may be <undef> if present.
4342 // Specifically when the original instruction didn't have them as an
4344 unsigned CurReg = SrcLane == 1 && DstLane == 1 ? DSrc : DDst;
4345 bool CurUndef = !MI->readsRegister(CurReg, TRI);
4346 NewMIB.addReg(CurReg, getUndefRegState(CurUndef));
4348 CurReg = SrcLane == 0 && DstLane == 0 ? DSrc : DDst;
4349 CurUndef = !MI->readsRegister(CurReg, TRI);
4350 NewMIB.addReg(CurReg, getUndefRegState(CurUndef));
4353 AddDefaultPred(NewMIB);
4355 if (SrcLane == DstLane)
4356 NewMIB.addReg(SrcReg, RegState::Implicit);
4358 MI->setDesc(get(ARM::VEXTd32));
4359 MIB.addReg(DDst, RegState::Define);
4361 // On the second instruction, DDst has definitely been defined above, so
4362 // it is not <undef>. DSrc, if present, can be <undef> as above.
4363 CurReg = SrcLane == 1 && DstLane == 0 ? DSrc : DDst;
4364 CurUndef = CurReg == DSrc && !MI->readsRegister(CurReg, TRI);
4365 MIB.addReg(CurReg, getUndefRegState(CurUndef));
4367 CurReg = SrcLane == 0 && DstLane == 1 ? DSrc : DDst;
4368 CurUndef = CurReg == DSrc && !MI->readsRegister(CurReg, TRI);
4369 MIB.addReg(CurReg, getUndefRegState(CurUndef));
4372 AddDefaultPred(MIB);
4374 if (SrcLane != DstLane)
4375 MIB.addReg(SrcReg, RegState::Implicit);
4377 // As before, the original destination is no longer represented, add it
4379 MIB.addReg(DstReg, RegState::Define | RegState::Implicit);
4380 if (ImplicitSReg != 0)
4381 MIB.addReg(ImplicitSReg, RegState::Implicit);
4388 //===----------------------------------------------------------------------===//
4389 // Partial register updates
4390 //===----------------------------------------------------------------------===//
4392 // Swift renames NEON registers with 64-bit granularity. That means any
4393 // instruction writing an S-reg implicitly reads the containing D-reg. The
4394 // problem is mostly avoided by translating f32 operations to v2f32 operations
4395 // on D-registers, but f32 loads are still a problem.
4397 // These instructions can load an f32 into a NEON register:
4399 // VLDRS - Only writes S, partial D update.
4400 // VLD1LNd32 - Writes all D-regs, explicit partial D update, 2 uops.
4401 // VLD1DUPd32 - Writes all D-regs, no partial reg update, 2 uops.
4403 // FCONSTD can be used as a dependency-breaking instruction.
4404 unsigned ARMBaseInstrInfo::
4405 getPartialRegUpdateClearance(const MachineInstr *MI,
4407 const TargetRegisterInfo *TRI) const {
4408 if (!SwiftPartialUpdateClearance ||
4409 !(Subtarget.isSwift() || Subtarget.isCortexA15()))
4412 assert(TRI && "Need TRI instance");
4414 const MachineOperand &MO = MI->getOperand(OpNum);
4417 unsigned Reg = MO.getReg();
4420 switch(MI->getOpcode()) {
4421 // Normal instructions writing only an S-register.
4426 case ARM::VMOVv4i16:
4427 case ARM::VMOVv2i32:
4428 case ARM::VMOVv2f32:
4429 case ARM::VMOVv1i64:
4430 UseOp = MI->findRegisterUseOperandIdx(Reg, false, TRI);
4433 // Explicitly reads the dependency.
4434 case ARM::VLD1LNd32:
4441 // If this instruction actually reads a value from Reg, there is no unwanted
4443 if (UseOp != -1 && MI->getOperand(UseOp).readsReg())
4446 // We must be able to clobber the whole D-reg.
4447 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
4448 // Virtual register must be a foo:ssub_0<def,undef> operand.
4449 if (!MO.getSubReg() || MI->readsVirtualRegister(Reg))
4451 } else if (ARM::SPRRegClass.contains(Reg)) {
4452 // Physical register: MI must define the full D-reg.
4453 unsigned DReg = TRI->getMatchingSuperReg(Reg, ARM::ssub_0,
4455 if (!DReg || !MI->definesRegister(DReg, TRI))
4459 // MI has an unwanted D-register dependency.
4460 // Avoid defs in the previous N instructrions.
4461 return SwiftPartialUpdateClearance;
4464 // Break a partial register dependency after getPartialRegUpdateClearance
4465 // returned non-zero.
4466 void ARMBaseInstrInfo::
4467 breakPartialRegDependency(MachineBasicBlock::iterator MI,
4469 const TargetRegisterInfo *TRI) const {
4470 assert(MI && OpNum < MI->getDesc().getNumDefs() && "OpNum is not a def");
4471 assert(TRI && "Need TRI instance");
4473 const MachineOperand &MO = MI->getOperand(OpNum);
4474 unsigned Reg = MO.getReg();
4475 assert(TargetRegisterInfo::isPhysicalRegister(Reg) &&
4476 "Can't break virtual register dependencies.");
4477 unsigned DReg = Reg;
4479 // If MI defines an S-reg, find the corresponding D super-register.
4480 if (ARM::SPRRegClass.contains(Reg)) {
4481 DReg = ARM::D0 + (Reg - ARM::S0) / 2;
4482 assert(TRI->isSuperRegister(Reg, DReg) && "Register enums broken");
4485 assert(ARM::DPRRegClass.contains(DReg) && "Can only break D-reg deps");
4486 assert(MI->definesRegister(DReg, TRI) && "MI doesn't clobber full D-reg");
4488 // FIXME: In some cases, VLDRS can be changed to a VLD1DUPd32 which defines
4489 // the full D-register by loading the same value to both lanes. The
4490 // instruction is micro-coded with 2 uops, so don't do this until we can
4491 // properly schedule micro-coded instructions. The dispatcher stalls cause
4492 // too big regressions.
4494 // Insert the dependency-breaking FCONSTD before MI.
4495 // 96 is the encoding of 0.5, but the actual value doesn't matter here.
4496 AddDefaultPred(BuildMI(*MI->getParent(), MI, MI->getDebugLoc(),
4497 get(ARM::FCONSTD), DReg).addImm(96));
4498 MI->addRegisterKilled(DReg, TRI, true);
4501 bool ARMBaseInstrInfo::hasNOP() const {
4502 return Subtarget.getFeatureBits()[ARM::HasV6KOps];
4505 bool ARMBaseInstrInfo::isSwiftFastImmShift(const MachineInstr *MI) const {
4506 if (MI->getNumOperands() < 4)
4508 unsigned ShOpVal = MI->getOperand(3).getImm();
4509 unsigned ShImm = ARM_AM::getSORegOffset(ShOpVal);
4510 // Swift supports faster shifts for: lsl 2, lsl 1, and lsr 1.
4511 if ((ShImm == 1 && ARM_AM::getSORegShOp(ShOpVal) == ARM_AM::lsr) ||
4512 ((ShImm == 1 || ShImm == 2) &&
4513 ARM_AM::getSORegShOp(ShOpVal) == ARM_AM::lsl))
4519 bool ARMBaseInstrInfo::getRegSequenceLikeInputs(
4520 const MachineInstr &MI, unsigned DefIdx,
4521 SmallVectorImpl<RegSubRegPairAndIdx> &InputRegs) const {
4522 assert(DefIdx < MI.getDesc().getNumDefs() && "Invalid definition index");
4523 assert(MI.isRegSequenceLike() && "Invalid kind of instruction");
4525 switch (MI.getOpcode()) {
4527 // dX = VMOVDRR rY, rZ
4529 // dX = REG_SEQUENCE rY, ssub_0, rZ, ssub_1
4530 // Populate the InputRegs accordingly.
4532 const MachineOperand *MOReg = &MI.getOperand(1);
4533 InputRegs.push_back(
4534 RegSubRegPairAndIdx(MOReg->getReg(), MOReg->getSubReg(), ARM::ssub_0));
4536 MOReg = &MI.getOperand(2);
4537 InputRegs.push_back(
4538 RegSubRegPairAndIdx(MOReg->getReg(), MOReg->getSubReg(), ARM::ssub_1));
4541 llvm_unreachable("Target dependent opcode missing");
4544 bool ARMBaseInstrInfo::getExtractSubregLikeInputs(
4545 const MachineInstr &MI, unsigned DefIdx,
4546 RegSubRegPairAndIdx &InputReg) const {
4547 assert(DefIdx < MI.getDesc().getNumDefs() && "Invalid definition index");
4548 assert(MI.isExtractSubregLike() && "Invalid kind of instruction");
4550 switch (MI.getOpcode()) {
4552 // rX, rY = VMOVRRD dZ
4554 // rX = EXTRACT_SUBREG dZ, ssub_0
4555 // rY = EXTRACT_SUBREG dZ, ssub_1
4556 const MachineOperand &MOReg = MI.getOperand(2);
4557 InputReg.Reg = MOReg.getReg();
4558 InputReg.SubReg = MOReg.getSubReg();
4559 InputReg.SubIdx = DefIdx == 0 ? ARM::ssub_0 : ARM::ssub_1;
4562 llvm_unreachable("Target dependent opcode missing");
4565 bool ARMBaseInstrInfo::getInsertSubregLikeInputs(
4566 const MachineInstr &MI, unsigned DefIdx, RegSubRegPair &BaseReg,
4567 RegSubRegPairAndIdx &InsertedReg) const {
4568 assert(DefIdx < MI.getDesc().getNumDefs() && "Invalid definition index");
4569 assert(MI.isInsertSubregLike() && "Invalid kind of instruction");
4571 switch (MI.getOpcode()) {
4572 case ARM::VSETLNi32:
4573 // dX = VSETLNi32 dY, rZ, imm
4574 const MachineOperand &MOBaseReg = MI.getOperand(1);
4575 const MachineOperand &MOInsertedReg = MI.getOperand(2);
4576 const MachineOperand &MOIndex = MI.getOperand(3);
4577 BaseReg.Reg = MOBaseReg.getReg();
4578 BaseReg.SubReg = MOBaseReg.getSubReg();
4580 InsertedReg.Reg = MOInsertedReg.getReg();
4581 InsertedReg.SubReg = MOInsertedReg.getSubReg();
4582 InsertedReg.SubIdx = MOIndex.getImm() == 0 ? ARM::ssub_0 : ARM::ssub_1;
4585 llvm_unreachable("Target dependent opcode missing");