1 //===-- ARMBaseInstrInfo.cpp - ARM Instruction Information ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Base ARM implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "ARMBaseInstrInfo.h"
16 #include "ARMConstantPoolValue.h"
17 #include "ARMHazardRecognizer.h"
18 #include "ARMMachineFunctionInfo.h"
19 #include "ARMRegisterInfo.h"
20 #include "MCTargetDesc/ARMAddressingModes.h"
21 #include "llvm/Constants.h"
22 #include "llvm/Function.h"
23 #include "llvm/GlobalValue.h"
24 #include "llvm/CodeGen/LiveVariables.h"
25 #include "llvm/CodeGen/MachineConstantPool.h"
26 #include "llvm/CodeGen/MachineFrameInfo.h"
27 #include "llvm/CodeGen/MachineInstrBuilder.h"
28 #include "llvm/CodeGen/MachineJumpTableInfo.h"
29 #include "llvm/CodeGen/MachineMemOperand.h"
30 #include "llvm/CodeGen/MachineRegisterInfo.h"
31 #include "llvm/CodeGen/SelectionDAGNodes.h"
32 #include "llvm/MC/MCAsmInfo.h"
33 #include "llvm/Support/BranchProbability.h"
34 #include "llvm/Support/CommandLine.h"
35 #include "llvm/Support/Debug.h"
36 #include "llvm/Support/ErrorHandling.h"
37 #include "llvm/ADT/STLExtras.h"
39 #define GET_INSTRINFO_CTOR
40 #include "ARMGenInstrInfo.inc"
45 EnableARM3Addr("enable-arm-3-addr-conv", cl::Hidden,
46 cl::desc("Enable ARM 2-addr to 3-addr conv"));
49 WidenVMOVS("widen-vmovs", cl::Hidden, cl::init(true),
50 cl::desc("Widen ARM vmovs to vmovd when possible"));
52 /// ARM_MLxEntry - Record information about MLA / MLS instructions.
54 unsigned MLxOpc; // MLA / MLS opcode
55 unsigned MulOpc; // Expanded multiplication opcode
56 unsigned AddSubOpc; // Expanded add / sub opcode
57 bool NegAcc; // True if the acc is negated before the add / sub.
58 bool HasLane; // True if instruction has an extra "lane" operand.
61 static const ARM_MLxEntry ARM_MLxTable[] = {
62 // MLxOpc, MulOpc, AddSubOpc, NegAcc, HasLane
64 { ARM::VMLAS, ARM::VMULS, ARM::VADDS, false, false },
65 { ARM::VMLSS, ARM::VMULS, ARM::VSUBS, false, false },
66 { ARM::VMLAD, ARM::VMULD, ARM::VADDD, false, false },
67 { ARM::VMLSD, ARM::VMULD, ARM::VSUBD, false, false },
68 { ARM::VNMLAS, ARM::VNMULS, ARM::VSUBS, true, false },
69 { ARM::VNMLSS, ARM::VMULS, ARM::VSUBS, true, false },
70 { ARM::VNMLAD, ARM::VNMULD, ARM::VSUBD, true, false },
71 { ARM::VNMLSD, ARM::VMULD, ARM::VSUBD, true, false },
74 { ARM::VMLAfd, ARM::VMULfd, ARM::VADDfd, false, false },
75 { ARM::VMLSfd, ARM::VMULfd, ARM::VSUBfd, false, false },
76 { ARM::VMLAfq, ARM::VMULfq, ARM::VADDfq, false, false },
77 { ARM::VMLSfq, ARM::VMULfq, ARM::VSUBfq, false, false },
78 { ARM::VMLAslfd, ARM::VMULslfd, ARM::VADDfd, false, true },
79 { ARM::VMLSslfd, ARM::VMULslfd, ARM::VSUBfd, false, true },
80 { ARM::VMLAslfq, ARM::VMULslfq, ARM::VADDfq, false, true },
81 { ARM::VMLSslfq, ARM::VMULslfq, ARM::VSUBfq, false, true },
84 ARMBaseInstrInfo::ARMBaseInstrInfo(const ARMSubtarget& STI)
85 : ARMGenInstrInfo(ARM::ADJCALLSTACKDOWN, ARM::ADJCALLSTACKUP),
87 for (unsigned i = 0, e = array_lengthof(ARM_MLxTable); i != e; ++i) {
88 if (!MLxEntryMap.insert(std::make_pair(ARM_MLxTable[i].MLxOpc, i)).second)
89 assert(false && "Duplicated entries?");
90 MLxHazardOpcodes.insert(ARM_MLxTable[i].AddSubOpc);
91 MLxHazardOpcodes.insert(ARM_MLxTable[i].MulOpc);
95 // Use a ScoreboardHazardRecognizer for prepass ARM scheduling. TargetInstrImpl
96 // currently defaults to no prepass hazard recognizer.
97 ScheduleHazardRecognizer *ARMBaseInstrInfo::
98 CreateTargetHazardRecognizer(const TargetMachine *TM,
99 const ScheduleDAG *DAG) const {
100 if (usePreRAHazardRecognizer()) {
101 const InstrItineraryData *II = TM->getInstrItineraryData();
102 return new ScoreboardHazardRecognizer(II, DAG, "pre-RA-sched");
104 return TargetInstrInfoImpl::CreateTargetHazardRecognizer(TM, DAG);
107 ScheduleHazardRecognizer *ARMBaseInstrInfo::
108 CreateTargetPostRAHazardRecognizer(const InstrItineraryData *II,
109 const ScheduleDAG *DAG) const {
110 if (Subtarget.isThumb2() || Subtarget.hasVFP2())
111 return (ScheduleHazardRecognizer *)
112 new ARMHazardRecognizer(II, *this, getRegisterInfo(), Subtarget, DAG);
113 return TargetInstrInfoImpl::CreateTargetPostRAHazardRecognizer(II, DAG);
117 ARMBaseInstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
118 MachineBasicBlock::iterator &MBBI,
119 LiveVariables *LV) const {
120 // FIXME: Thumb2 support.
125 MachineInstr *MI = MBBI;
126 MachineFunction &MF = *MI->getParent()->getParent();
127 uint64_t TSFlags = MI->getDesc().TSFlags;
129 switch ((TSFlags & ARMII::IndexModeMask) >> ARMII::IndexModeShift) {
130 default: return NULL;
131 case ARMII::IndexModePre:
134 case ARMII::IndexModePost:
138 // Try splitting an indexed load/store to an un-indexed one plus an add/sub
140 unsigned MemOpc = getUnindexedOpcode(MI->getOpcode());
144 MachineInstr *UpdateMI = NULL;
145 MachineInstr *MemMI = NULL;
146 unsigned AddrMode = (TSFlags & ARMII::AddrModeMask);
147 const MCInstrDesc &MCID = MI->getDesc();
148 unsigned NumOps = MCID.getNumOperands();
149 bool isLoad = !MI->mayStore();
150 const MachineOperand &WB = isLoad ? MI->getOperand(1) : MI->getOperand(0);
151 const MachineOperand &Base = MI->getOperand(2);
152 const MachineOperand &Offset = MI->getOperand(NumOps-3);
153 unsigned WBReg = WB.getReg();
154 unsigned BaseReg = Base.getReg();
155 unsigned OffReg = Offset.getReg();
156 unsigned OffImm = MI->getOperand(NumOps-2).getImm();
157 ARMCC::CondCodes Pred = (ARMCC::CondCodes)MI->getOperand(NumOps-1).getImm();
159 default: llvm_unreachable("Unknown indexed op!");
160 case ARMII::AddrMode2: {
161 bool isSub = ARM_AM::getAM2Op(OffImm) == ARM_AM::sub;
162 unsigned Amt = ARM_AM::getAM2Offset(OffImm);
164 if (ARM_AM::getSOImmVal(Amt) == -1)
165 // Can't encode it in a so_imm operand. This transformation will
166 // add more than 1 instruction. Abandon!
168 UpdateMI = BuildMI(MF, MI->getDebugLoc(),
169 get(isSub ? ARM::SUBri : ARM::ADDri), WBReg)
170 .addReg(BaseReg).addImm(Amt)
171 .addImm(Pred).addReg(0).addReg(0);
172 } else if (Amt != 0) {
173 ARM_AM::ShiftOpc ShOpc = ARM_AM::getAM2ShiftOpc(OffImm);
174 unsigned SOOpc = ARM_AM::getSORegOpc(ShOpc, Amt);
175 UpdateMI = BuildMI(MF, MI->getDebugLoc(),
176 get(isSub ? ARM::SUBrsi : ARM::ADDrsi), WBReg)
177 .addReg(BaseReg).addReg(OffReg).addReg(0).addImm(SOOpc)
178 .addImm(Pred).addReg(0).addReg(0);
180 UpdateMI = BuildMI(MF, MI->getDebugLoc(),
181 get(isSub ? ARM::SUBrr : ARM::ADDrr), WBReg)
182 .addReg(BaseReg).addReg(OffReg)
183 .addImm(Pred).addReg(0).addReg(0);
186 case ARMII::AddrMode3 : {
187 bool isSub = ARM_AM::getAM3Op(OffImm) == ARM_AM::sub;
188 unsigned Amt = ARM_AM::getAM3Offset(OffImm);
190 // Immediate is 8-bits. It's guaranteed to fit in a so_imm operand.
191 UpdateMI = BuildMI(MF, MI->getDebugLoc(),
192 get(isSub ? ARM::SUBri : ARM::ADDri), WBReg)
193 .addReg(BaseReg).addImm(Amt)
194 .addImm(Pred).addReg(0).addReg(0);
196 UpdateMI = BuildMI(MF, MI->getDebugLoc(),
197 get(isSub ? ARM::SUBrr : ARM::ADDrr), WBReg)
198 .addReg(BaseReg).addReg(OffReg)
199 .addImm(Pred).addReg(0).addReg(0);
204 std::vector<MachineInstr*> NewMIs;
207 MemMI = BuildMI(MF, MI->getDebugLoc(),
208 get(MemOpc), MI->getOperand(0).getReg())
209 .addReg(WBReg).addImm(0).addImm(Pred);
211 MemMI = BuildMI(MF, MI->getDebugLoc(),
212 get(MemOpc)).addReg(MI->getOperand(1).getReg())
213 .addReg(WBReg).addReg(0).addImm(0).addImm(Pred);
214 NewMIs.push_back(MemMI);
215 NewMIs.push_back(UpdateMI);
218 MemMI = BuildMI(MF, MI->getDebugLoc(),
219 get(MemOpc), MI->getOperand(0).getReg())
220 .addReg(BaseReg).addImm(0).addImm(Pred);
222 MemMI = BuildMI(MF, MI->getDebugLoc(),
223 get(MemOpc)).addReg(MI->getOperand(1).getReg())
224 .addReg(BaseReg).addReg(0).addImm(0).addImm(Pred);
226 UpdateMI->getOperand(0).setIsDead();
227 NewMIs.push_back(UpdateMI);
228 NewMIs.push_back(MemMI);
231 // Transfer LiveVariables states, kill / dead info.
233 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
234 MachineOperand &MO = MI->getOperand(i);
235 if (MO.isReg() && TargetRegisterInfo::isVirtualRegister(MO.getReg())) {
236 unsigned Reg = MO.getReg();
238 LiveVariables::VarInfo &VI = LV->getVarInfo(Reg);
240 MachineInstr *NewMI = (Reg == WBReg) ? UpdateMI : MemMI;
242 LV->addVirtualRegisterDead(Reg, NewMI);
244 if (MO.isUse() && MO.isKill()) {
245 for (unsigned j = 0; j < 2; ++j) {
246 // Look at the two new MI's in reverse order.
247 MachineInstr *NewMI = NewMIs[j];
248 if (!NewMI->readsRegister(Reg))
250 LV->addVirtualRegisterKilled(Reg, NewMI);
251 if (VI.removeKill(MI))
252 VI.Kills.push_back(NewMI);
260 MFI->insert(MBBI, NewMIs[1]);
261 MFI->insert(MBBI, NewMIs[0]);
267 ARMBaseInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB,
268 MachineBasicBlock *&FBB,
269 SmallVectorImpl<MachineOperand> &Cond,
270 bool AllowModify) const {
271 // If the block has no terminators, it just falls into the block after it.
272 MachineBasicBlock::iterator I = MBB.end();
273 if (I == MBB.begin())
276 while (I->isDebugValue()) {
277 if (I == MBB.begin())
281 if (!isUnpredicatedTerminator(I))
284 // Get the last instruction in the block.
285 MachineInstr *LastInst = I;
287 // If there is only one terminator instruction, process it.
288 unsigned LastOpc = LastInst->getOpcode();
289 if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) {
290 if (isUncondBranchOpcode(LastOpc)) {
291 TBB = LastInst->getOperand(0).getMBB();
294 if (isCondBranchOpcode(LastOpc)) {
295 // Block ends with fall-through condbranch.
296 TBB = LastInst->getOperand(0).getMBB();
297 Cond.push_back(LastInst->getOperand(1));
298 Cond.push_back(LastInst->getOperand(2));
301 return true; // Can't handle indirect branch.
304 // Get the instruction before it if it is a terminator.
305 MachineInstr *SecondLastInst = I;
306 unsigned SecondLastOpc = SecondLastInst->getOpcode();
308 // If AllowModify is true and the block ends with two or more unconditional
309 // branches, delete all but the first unconditional branch.
310 if (AllowModify && isUncondBranchOpcode(LastOpc)) {
311 while (isUncondBranchOpcode(SecondLastOpc)) {
312 LastInst->eraseFromParent();
313 LastInst = SecondLastInst;
314 LastOpc = LastInst->getOpcode();
315 if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) {
316 // Return now the only terminator is an unconditional branch.
317 TBB = LastInst->getOperand(0).getMBB();
321 SecondLastOpc = SecondLastInst->getOpcode();
326 // If there are three terminators, we don't know what sort of block this is.
327 if (SecondLastInst && I != MBB.begin() && isUnpredicatedTerminator(--I))
330 // If the block ends with a B and a Bcc, handle it.
331 if (isCondBranchOpcode(SecondLastOpc) && isUncondBranchOpcode(LastOpc)) {
332 TBB = SecondLastInst->getOperand(0).getMBB();
333 Cond.push_back(SecondLastInst->getOperand(1));
334 Cond.push_back(SecondLastInst->getOperand(2));
335 FBB = LastInst->getOperand(0).getMBB();
339 // If the block ends with two unconditional branches, handle it. The second
340 // one is not executed, so remove it.
341 if (isUncondBranchOpcode(SecondLastOpc) && isUncondBranchOpcode(LastOpc)) {
342 TBB = SecondLastInst->getOperand(0).getMBB();
345 I->eraseFromParent();
349 // ...likewise if it ends with a branch table followed by an unconditional
350 // branch. The branch folder can create these, and we must get rid of them for
351 // correctness of Thumb constant islands.
352 if ((isJumpTableBranchOpcode(SecondLastOpc) ||
353 isIndirectBranchOpcode(SecondLastOpc)) &&
354 isUncondBranchOpcode(LastOpc)) {
357 I->eraseFromParent();
361 // Otherwise, can't handle this.
366 unsigned ARMBaseInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
367 MachineBasicBlock::iterator I = MBB.end();
368 if (I == MBB.begin()) return 0;
370 while (I->isDebugValue()) {
371 if (I == MBB.begin())
375 if (!isUncondBranchOpcode(I->getOpcode()) &&
376 !isCondBranchOpcode(I->getOpcode()))
379 // Remove the branch.
380 I->eraseFromParent();
384 if (I == MBB.begin()) return 1;
386 if (!isCondBranchOpcode(I->getOpcode()))
389 // Remove the branch.
390 I->eraseFromParent();
395 ARMBaseInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
396 MachineBasicBlock *FBB,
397 const SmallVectorImpl<MachineOperand> &Cond,
399 ARMFunctionInfo *AFI = MBB.getParent()->getInfo<ARMFunctionInfo>();
400 int BOpc = !AFI->isThumbFunction()
401 ? ARM::B : (AFI->isThumb2Function() ? ARM::t2B : ARM::tB);
402 int BccOpc = !AFI->isThumbFunction()
403 ? ARM::Bcc : (AFI->isThumb2Function() ? ARM::t2Bcc : ARM::tBcc);
404 bool isThumb = AFI->isThumbFunction() || AFI->isThumb2Function();
406 // Shouldn't be a fall through.
407 assert(TBB && "InsertBranch must not be told to insert a fallthrough");
408 assert((Cond.size() == 2 || Cond.size() == 0) &&
409 "ARM branch conditions have two components!");
412 if (Cond.empty()) { // Unconditional branch?
414 BuildMI(&MBB, DL, get(BOpc)).addMBB(TBB).addImm(ARMCC::AL).addReg(0);
416 BuildMI(&MBB, DL, get(BOpc)).addMBB(TBB);
418 BuildMI(&MBB, DL, get(BccOpc)).addMBB(TBB)
419 .addImm(Cond[0].getImm()).addReg(Cond[1].getReg());
423 // Two-way conditional branch.
424 BuildMI(&MBB, DL, get(BccOpc)).addMBB(TBB)
425 .addImm(Cond[0].getImm()).addReg(Cond[1].getReg());
427 BuildMI(&MBB, DL, get(BOpc)).addMBB(FBB).addImm(ARMCC::AL).addReg(0);
429 BuildMI(&MBB, DL, get(BOpc)).addMBB(FBB);
433 bool ARMBaseInstrInfo::
434 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
435 ARMCC::CondCodes CC = (ARMCC::CondCodes)(int)Cond[0].getImm();
436 Cond[0].setImm(ARMCC::getOppositeCondition(CC));
440 bool ARMBaseInstrInfo::isPredicated(const MachineInstr *MI) const {
441 if (MI->isBundle()) {
442 MachineBasicBlock::const_instr_iterator I = MI;
443 MachineBasicBlock::const_instr_iterator E = MI->getParent()->instr_end();
444 while (++I != E && I->isInsideBundle()) {
445 int PIdx = I->findFirstPredOperandIdx();
446 if (PIdx != -1 && I->getOperand(PIdx).getImm() != ARMCC::AL)
452 int PIdx = MI->findFirstPredOperandIdx();
453 return PIdx != -1 && MI->getOperand(PIdx).getImm() != ARMCC::AL;
456 bool ARMBaseInstrInfo::
457 PredicateInstruction(MachineInstr *MI,
458 const SmallVectorImpl<MachineOperand> &Pred) const {
459 unsigned Opc = MI->getOpcode();
460 if (isUncondBranchOpcode(Opc)) {
461 MI->setDesc(get(getMatchingCondBranchOpcode(Opc)));
462 MI->addOperand(MachineOperand::CreateImm(Pred[0].getImm()));
463 MI->addOperand(MachineOperand::CreateReg(Pred[1].getReg(), false));
467 int PIdx = MI->findFirstPredOperandIdx();
469 MachineOperand &PMO = MI->getOperand(PIdx);
470 PMO.setImm(Pred[0].getImm());
471 MI->getOperand(PIdx+1).setReg(Pred[1].getReg());
477 bool ARMBaseInstrInfo::
478 SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1,
479 const SmallVectorImpl<MachineOperand> &Pred2) const {
480 if (Pred1.size() > 2 || Pred2.size() > 2)
483 ARMCC::CondCodes CC1 = (ARMCC::CondCodes)Pred1[0].getImm();
484 ARMCC::CondCodes CC2 = (ARMCC::CondCodes)Pred2[0].getImm();
494 return CC2 == ARMCC::HI;
496 return CC2 == ARMCC::LO || CC2 == ARMCC::EQ;
498 return CC2 == ARMCC::GT;
500 return CC2 == ARMCC::LT;
504 bool ARMBaseInstrInfo::DefinesPredicate(MachineInstr *MI,
505 std::vector<MachineOperand> &Pred) const {
507 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
508 const MachineOperand &MO = MI->getOperand(i);
509 if ((MO.isRegMask() && MO.clobbersPhysReg(ARM::CPSR)) ||
510 (MO.isReg() && MO.isDef() && MO.getReg() == ARM::CPSR)) {
519 /// isPredicable - Return true if the specified instruction can be predicated.
520 /// By default, this returns true for every instruction with a
521 /// PredicateOperand.
522 bool ARMBaseInstrInfo::isPredicable(MachineInstr *MI) const {
523 if (!MI->isPredicable())
526 if ((MI->getDesc().TSFlags & ARMII::DomainMask) == ARMII::DomainNEON) {
527 ARMFunctionInfo *AFI =
528 MI->getParent()->getParent()->getInfo<ARMFunctionInfo>();
529 return AFI->isThumb2Function();
534 /// FIXME: Works around a gcc miscompilation with -fstrict-aliasing.
535 LLVM_ATTRIBUTE_NOINLINE
536 static unsigned getNumJTEntries(const std::vector<MachineJumpTableEntry> &JT,
538 static unsigned getNumJTEntries(const std::vector<MachineJumpTableEntry> &JT,
540 assert(JTI < JT.size());
541 return JT[JTI].MBBs.size();
544 /// GetInstSize - Return the size of the specified MachineInstr.
546 unsigned ARMBaseInstrInfo::GetInstSizeInBytes(const MachineInstr *MI) const {
547 const MachineBasicBlock &MBB = *MI->getParent();
548 const MachineFunction *MF = MBB.getParent();
549 const MCAsmInfo *MAI = MF->getTarget().getMCAsmInfo();
551 const MCInstrDesc &MCID = MI->getDesc();
553 return MCID.getSize();
555 // If this machine instr is an inline asm, measure it.
556 if (MI->getOpcode() == ARM::INLINEASM)
557 return getInlineAsmLength(MI->getOperand(0).getSymbolName(), *MAI);
560 unsigned Opc = MI->getOpcode();
562 case TargetOpcode::IMPLICIT_DEF:
563 case TargetOpcode::KILL:
564 case TargetOpcode::PROLOG_LABEL:
565 case TargetOpcode::EH_LABEL:
566 case TargetOpcode::DBG_VALUE:
568 case TargetOpcode::BUNDLE:
569 return getInstBundleLength(MI);
570 case ARM::MOVi16_ga_pcrel:
571 case ARM::MOVTi16_ga_pcrel:
572 case ARM::t2MOVi16_ga_pcrel:
573 case ARM::t2MOVTi16_ga_pcrel:
576 case ARM::t2MOVi32imm:
578 case ARM::CONSTPOOL_ENTRY:
579 // If this machine instr is a constant pool entry, its size is recorded as
581 return MI->getOperand(2).getImm();
582 case ARM::Int_eh_sjlj_longjmp:
584 case ARM::tInt_eh_sjlj_longjmp:
586 case ARM::Int_eh_sjlj_setjmp:
587 case ARM::Int_eh_sjlj_setjmp_nofp:
589 case ARM::tInt_eh_sjlj_setjmp:
590 case ARM::t2Int_eh_sjlj_setjmp:
591 case ARM::t2Int_eh_sjlj_setjmp_nofp:
599 case ARM::t2TBH_JT: {
600 // These are jumptable branches, i.e. a branch followed by an inlined
601 // jumptable. The size is 4 + 4 * number of entries. For TBB, each
602 // entry is one byte; TBH two byte each.
603 unsigned EntrySize = (Opc == ARM::t2TBB_JT)
604 ? 1 : ((Opc == ARM::t2TBH_JT) ? 2 : 4);
605 unsigned NumOps = MCID.getNumOperands();
606 MachineOperand JTOP =
607 MI->getOperand(NumOps - (MI->isPredicable() ? 3 : 2));
608 unsigned JTI = JTOP.getIndex();
609 const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
611 const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
612 assert(JTI < JT.size());
613 // Thumb instructions are 2 byte aligned, but JT entries are 4 byte
614 // 4 aligned. The assembler / linker may add 2 byte padding just before
615 // the JT entries. The size does not include this padding; the
616 // constant islands pass does separate bookkeeping for it.
617 // FIXME: If we know the size of the function is less than (1 << 16) *2
618 // bytes, we can use 16-bit entries instead. Then there won't be an
620 unsigned InstSize = (Opc == ARM::tBR_JTr || Opc == ARM::t2BR_JT) ? 2 : 4;
621 unsigned NumEntries = getNumJTEntries(JT, JTI);
622 if (Opc == ARM::t2TBB_JT && (NumEntries & 1))
623 // Make sure the instruction that follows TBB is 2-byte aligned.
624 // FIXME: Constant island pass should insert an "ALIGN" instruction
627 return NumEntries * EntrySize + InstSize;
630 // Otherwise, pseudo-instruction sizes are zero.
635 unsigned ARMBaseInstrInfo::getInstBundleLength(const MachineInstr *MI) const {
637 MachineBasicBlock::const_instr_iterator I = MI;
638 MachineBasicBlock::const_instr_iterator E = MI->getParent()->instr_end();
639 while (++I != E && I->isInsideBundle()) {
640 assert(!I->isBundle() && "No nested bundle!");
641 Size += GetInstSizeInBytes(&*I);
646 void ARMBaseInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
647 MachineBasicBlock::iterator I, DebugLoc DL,
648 unsigned DestReg, unsigned SrcReg,
649 bool KillSrc) const {
650 bool GPRDest = ARM::GPRRegClass.contains(DestReg);
651 bool GPRSrc = ARM::GPRRegClass.contains(SrcReg);
653 if (GPRDest && GPRSrc) {
654 AddDefaultCC(AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::MOVr), DestReg)
655 .addReg(SrcReg, getKillRegState(KillSrc))));
659 bool SPRDest = ARM::SPRRegClass.contains(DestReg);
660 bool SPRSrc = ARM::SPRRegClass.contains(SrcReg);
663 if (SPRDest && SPRSrc)
665 else if (GPRDest && SPRSrc)
667 else if (SPRDest && GPRSrc)
669 else if (ARM::DPRRegClass.contains(DestReg, SrcReg))
671 else if (ARM::QPRRegClass.contains(DestReg, SrcReg))
675 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(Opc), DestReg);
676 MIB.addReg(SrcReg, getKillRegState(KillSrc));
677 if (Opc == ARM::VORRq)
678 MIB.addReg(SrcReg, getKillRegState(KillSrc));
683 // Generate instructions for VMOVQQ and VMOVQQQQ pseudos in place.
684 if (ARM::QQPRRegClass.contains(DestReg, SrcReg) ||
685 ARM::QQQQPRRegClass.contains(DestReg, SrcReg)) {
686 const TargetRegisterInfo *TRI = &getRegisterInfo();
687 assert(ARM::qsub_0 + 3 == ARM::qsub_3 && "Expected contiguous enum.");
688 unsigned EndSubReg = ARM::QQPRRegClass.contains(DestReg, SrcReg) ?
689 ARM::qsub_1 : ARM::qsub_3;
690 for (unsigned i = ARM::qsub_0, e = EndSubReg + 1; i != e; ++i) {
691 unsigned Dst = TRI->getSubReg(DestReg, i);
692 unsigned Src = TRI->getSubReg(SrcReg, i);
693 MachineInstrBuilder Mov =
694 AddDefaultPred(BuildMI(MBB, I, I->getDebugLoc(), get(ARM::VORRq))
695 .addReg(Dst, RegState::Define)
696 .addReg(Src, getKillRegState(KillSrc))
697 .addReg(Src, getKillRegState(KillSrc)));
698 if (i == EndSubReg) {
699 Mov->addRegisterDefined(DestReg, TRI);
701 Mov->addRegisterKilled(SrcReg, TRI);
706 llvm_unreachable("Impossible reg-to-reg copy");
710 MachineInstrBuilder &AddDReg(MachineInstrBuilder &MIB,
711 unsigned Reg, unsigned SubIdx, unsigned State,
712 const TargetRegisterInfo *TRI) {
714 return MIB.addReg(Reg, State);
716 if (TargetRegisterInfo::isPhysicalRegister(Reg))
717 return MIB.addReg(TRI->getSubReg(Reg, SubIdx), State);
718 return MIB.addReg(Reg, State, SubIdx);
721 void ARMBaseInstrInfo::
722 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
723 unsigned SrcReg, bool isKill, int FI,
724 const TargetRegisterClass *RC,
725 const TargetRegisterInfo *TRI) const {
727 if (I != MBB.end()) DL = I->getDebugLoc();
728 MachineFunction &MF = *MBB.getParent();
729 MachineFrameInfo &MFI = *MF.getFrameInfo();
730 unsigned Align = MFI.getObjectAlignment(FI);
732 MachineMemOperand *MMO =
733 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(FI),
734 MachineMemOperand::MOStore,
735 MFI.getObjectSize(FI),
738 switch (RC->getSize()) {
740 if (ARM::GPRRegClass.hasSubClassEq(RC)) {
741 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::STRi12))
742 .addReg(SrcReg, getKillRegState(isKill))
743 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
744 } else if (ARM::SPRRegClass.hasSubClassEq(RC)) {
745 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTRS))
746 .addReg(SrcReg, getKillRegState(isKill))
747 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
749 llvm_unreachable("Unknown reg class!");
752 if (ARM::DPRRegClass.hasSubClassEq(RC)) {
753 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTRD))
754 .addReg(SrcReg, getKillRegState(isKill))
755 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
757 llvm_unreachable("Unknown reg class!");
760 if (ARM::QPRRegClass.hasSubClassEq(RC)) {
761 // Use aligned spills if the stack can be realigned.
762 if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) {
763 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VST1q64))
764 .addFrameIndex(FI).addImm(16)
765 .addReg(SrcReg, getKillRegState(isKill))
766 .addMemOperand(MMO));
768 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTMQIA))
769 .addReg(SrcReg, getKillRegState(isKill))
771 .addMemOperand(MMO));
774 llvm_unreachable("Unknown reg class!");
777 if (ARM::QQPRRegClass.hasSubClassEq(RC)) {
778 if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) {
779 // FIXME: It's possible to only store part of the QQ register if the
780 // spilled def has a sub-register index.
781 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VST1d64QPseudo))
782 .addFrameIndex(FI).addImm(16)
783 .addReg(SrcReg, getKillRegState(isKill))
784 .addMemOperand(MMO));
786 MachineInstrBuilder MIB =
787 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTMDIA))
790 MIB = AddDReg(MIB, SrcReg, ARM::dsub_0, getKillRegState(isKill), TRI);
791 MIB = AddDReg(MIB, SrcReg, ARM::dsub_1, 0, TRI);
792 MIB = AddDReg(MIB, SrcReg, ARM::dsub_2, 0, TRI);
793 AddDReg(MIB, SrcReg, ARM::dsub_3, 0, TRI);
796 llvm_unreachable("Unknown reg class!");
799 if (ARM::QQQQPRRegClass.hasSubClassEq(RC)) {
800 MachineInstrBuilder MIB =
801 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTMDIA))
804 MIB = AddDReg(MIB, SrcReg, ARM::dsub_0, getKillRegState(isKill), TRI);
805 MIB = AddDReg(MIB, SrcReg, ARM::dsub_1, 0, TRI);
806 MIB = AddDReg(MIB, SrcReg, ARM::dsub_2, 0, TRI);
807 MIB = AddDReg(MIB, SrcReg, ARM::dsub_3, 0, TRI);
808 MIB = AddDReg(MIB, SrcReg, ARM::dsub_4, 0, TRI);
809 MIB = AddDReg(MIB, SrcReg, ARM::dsub_5, 0, TRI);
810 MIB = AddDReg(MIB, SrcReg, ARM::dsub_6, 0, TRI);
811 AddDReg(MIB, SrcReg, ARM::dsub_7, 0, TRI);
813 llvm_unreachable("Unknown reg class!");
816 llvm_unreachable("Unknown reg class!");
821 ARMBaseInstrInfo::isStoreToStackSlot(const MachineInstr *MI,
822 int &FrameIndex) const {
823 switch (MI->getOpcode()) {
826 case ARM::t2STRs: // FIXME: don't use t2STRs to access frame.
827 if (MI->getOperand(1).isFI() &&
828 MI->getOperand(2).isReg() &&
829 MI->getOperand(3).isImm() &&
830 MI->getOperand(2).getReg() == 0 &&
831 MI->getOperand(3).getImm() == 0) {
832 FrameIndex = MI->getOperand(1).getIndex();
833 return MI->getOperand(0).getReg();
841 if (MI->getOperand(1).isFI() &&
842 MI->getOperand(2).isImm() &&
843 MI->getOperand(2).getImm() == 0) {
844 FrameIndex = MI->getOperand(1).getIndex();
845 return MI->getOperand(0).getReg();
849 if (MI->getOperand(0).isFI() &&
850 MI->getOperand(2).getSubReg() == 0) {
851 FrameIndex = MI->getOperand(0).getIndex();
852 return MI->getOperand(2).getReg();
856 if (MI->getOperand(1).isFI() &&
857 MI->getOperand(0).getSubReg() == 0) {
858 FrameIndex = MI->getOperand(1).getIndex();
859 return MI->getOperand(0).getReg();
867 unsigned ARMBaseInstrInfo::isStoreToStackSlotPostFE(const MachineInstr *MI,
868 int &FrameIndex) const {
869 const MachineMemOperand *Dummy;
870 return MI->mayStore() && hasStoreToStackSlot(MI, Dummy, FrameIndex);
873 void ARMBaseInstrInfo::
874 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
875 unsigned DestReg, int FI,
876 const TargetRegisterClass *RC,
877 const TargetRegisterInfo *TRI) const {
879 if (I != MBB.end()) DL = I->getDebugLoc();
880 MachineFunction &MF = *MBB.getParent();
881 MachineFrameInfo &MFI = *MF.getFrameInfo();
882 unsigned Align = MFI.getObjectAlignment(FI);
883 MachineMemOperand *MMO =
884 MF.getMachineMemOperand(
885 MachinePointerInfo::getFixedStack(FI),
886 MachineMemOperand::MOLoad,
887 MFI.getObjectSize(FI),
890 switch (RC->getSize()) {
892 if (ARM::GPRRegClass.hasSubClassEq(RC)) {
893 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::LDRi12), DestReg)
894 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
896 } else if (ARM::SPRRegClass.hasSubClassEq(RC)) {
897 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDRS), DestReg)
898 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
900 llvm_unreachable("Unknown reg class!");
903 if (ARM::DPRRegClass.hasSubClassEq(RC)) {
904 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDRD), DestReg)
905 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
907 llvm_unreachable("Unknown reg class!");
910 if (ARM::QPRRegClass.hasSubClassEq(RC)) {
911 if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) {
912 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLD1q64), DestReg)
913 .addFrameIndex(FI).addImm(16)
914 .addMemOperand(MMO));
916 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDMQIA), DestReg)
918 .addMemOperand(MMO));
921 llvm_unreachable("Unknown reg class!");
924 if (ARM::QQPRRegClass.hasSubClassEq(RC)) {
925 if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) {
926 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLD1d64QPseudo), DestReg)
927 .addFrameIndex(FI).addImm(16)
928 .addMemOperand(MMO));
930 MachineInstrBuilder MIB =
931 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDMDIA))
934 MIB = AddDReg(MIB, DestReg, ARM::dsub_0, RegState::DefineNoRead, TRI);
935 MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::DefineNoRead, TRI);
936 MIB = AddDReg(MIB, DestReg, ARM::dsub_2, RegState::DefineNoRead, TRI);
937 MIB = AddDReg(MIB, DestReg, ARM::dsub_3, RegState::DefineNoRead, TRI);
938 if (TargetRegisterInfo::isPhysicalRegister(DestReg))
939 MIB.addReg(DestReg, RegState::ImplicitDefine);
942 llvm_unreachable("Unknown reg class!");
945 if (ARM::QQQQPRRegClass.hasSubClassEq(RC)) {
946 MachineInstrBuilder MIB =
947 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDMDIA))
950 MIB = AddDReg(MIB, DestReg, ARM::dsub_0, RegState::DefineNoRead, TRI);
951 MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::DefineNoRead, TRI);
952 MIB = AddDReg(MIB, DestReg, ARM::dsub_2, RegState::DefineNoRead, TRI);
953 MIB = AddDReg(MIB, DestReg, ARM::dsub_3, RegState::DefineNoRead, TRI);
954 MIB = AddDReg(MIB, DestReg, ARM::dsub_4, RegState::DefineNoRead, TRI);
955 MIB = AddDReg(MIB, DestReg, ARM::dsub_5, RegState::DefineNoRead, TRI);
956 MIB = AddDReg(MIB, DestReg, ARM::dsub_6, RegState::DefineNoRead, TRI);
957 MIB = AddDReg(MIB, DestReg, ARM::dsub_7, RegState::DefineNoRead, TRI);
958 if (TargetRegisterInfo::isPhysicalRegister(DestReg))
959 MIB.addReg(DestReg, RegState::ImplicitDefine);
961 llvm_unreachable("Unknown reg class!");
964 llvm_unreachable("Unknown regclass!");
969 ARMBaseInstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
970 int &FrameIndex) const {
971 switch (MI->getOpcode()) {
974 case ARM::t2LDRs: // FIXME: don't use t2LDRs to access frame.
975 if (MI->getOperand(1).isFI() &&
976 MI->getOperand(2).isReg() &&
977 MI->getOperand(3).isImm() &&
978 MI->getOperand(2).getReg() == 0 &&
979 MI->getOperand(3).getImm() == 0) {
980 FrameIndex = MI->getOperand(1).getIndex();
981 return MI->getOperand(0).getReg();
989 if (MI->getOperand(1).isFI() &&
990 MI->getOperand(2).isImm() &&
991 MI->getOperand(2).getImm() == 0) {
992 FrameIndex = MI->getOperand(1).getIndex();
993 return MI->getOperand(0).getReg();
997 if (MI->getOperand(1).isFI() &&
998 MI->getOperand(0).getSubReg() == 0) {
999 FrameIndex = MI->getOperand(1).getIndex();
1000 return MI->getOperand(0).getReg();
1004 if (MI->getOperand(1).isFI() &&
1005 MI->getOperand(0).getSubReg() == 0) {
1006 FrameIndex = MI->getOperand(1).getIndex();
1007 return MI->getOperand(0).getReg();
1015 unsigned ARMBaseInstrInfo::isLoadFromStackSlotPostFE(const MachineInstr *MI,
1016 int &FrameIndex) const {
1017 const MachineMemOperand *Dummy;
1018 return MI->mayLoad() && hasLoadFromStackSlot(MI, Dummy, FrameIndex);
1021 bool ARMBaseInstrInfo::expandPostRAPseudo(MachineBasicBlock::iterator MI) const{
1022 // This hook gets to expand COPY instructions before they become
1023 // copyPhysReg() calls. Look for VMOVS instructions that can legally be
1024 // widened to VMOVD. We prefer the VMOVD when possible because it may be
1025 // changed into a VORR that can go down the NEON pipeline.
1026 if (!WidenVMOVS || !MI->isCopy())
1029 // Look for a copy between even S-registers. That is where we keep floats
1030 // when using NEON v2f32 instructions for f32 arithmetic.
1031 unsigned DstRegS = MI->getOperand(0).getReg();
1032 unsigned SrcRegS = MI->getOperand(1).getReg();
1033 if (!ARM::SPRRegClass.contains(DstRegS, SrcRegS))
1036 const TargetRegisterInfo *TRI = &getRegisterInfo();
1037 unsigned DstRegD = TRI->getMatchingSuperReg(DstRegS, ARM::ssub_0,
1039 unsigned SrcRegD = TRI->getMatchingSuperReg(SrcRegS, ARM::ssub_0,
1041 if (!DstRegD || !SrcRegD)
1044 // We want to widen this into a DstRegD = VMOVD SrcRegD copy. This is only
1045 // legal if the COPY already defines the full DstRegD, and it isn't a
1046 // sub-register insertion.
1047 if (!MI->definesRegister(DstRegD, TRI) || MI->readsRegister(DstRegD, TRI))
1050 // A dead copy shouldn't show up here, but reject it just in case.
1051 if (MI->getOperand(0).isDead())
1054 // All clear, widen the COPY.
1055 DEBUG(dbgs() << "widening: " << *MI);
1057 // Get rid of the old <imp-def> of DstRegD. Leave it if it defines a Q-reg
1058 // or some other super-register.
1059 int ImpDefIdx = MI->findRegisterDefOperandIdx(DstRegD);
1060 if (ImpDefIdx != -1)
1061 MI->RemoveOperand(ImpDefIdx);
1063 // Change the opcode and operands.
1064 MI->setDesc(get(ARM::VMOVD));
1065 MI->getOperand(0).setReg(DstRegD);
1066 MI->getOperand(1).setReg(SrcRegD);
1067 AddDefaultPred(MachineInstrBuilder(MI));
1069 // We are now reading SrcRegD instead of SrcRegS. This may upset the
1070 // register scavenger and machine verifier, so we need to indicate that we
1071 // are reading an undefined value from SrcRegD, but a proper value from
1073 MI->getOperand(1).setIsUndef();
1074 MachineInstrBuilder(MI).addReg(SrcRegS, RegState::Implicit);
1076 // SrcRegD may actually contain an unrelated value in the ssub_1
1077 // sub-register. Don't kill it. Only kill the ssub_0 sub-register.
1078 if (MI->getOperand(1).isKill()) {
1079 MI->getOperand(1).setIsKill(false);
1080 MI->addRegisterKilled(SrcRegS, TRI, true);
1083 DEBUG(dbgs() << "replaced by: " << *MI);
1088 ARMBaseInstrInfo::emitFrameIndexDebugValue(MachineFunction &MF,
1089 int FrameIx, uint64_t Offset,
1090 const MDNode *MDPtr,
1091 DebugLoc DL) const {
1092 MachineInstrBuilder MIB = BuildMI(MF, DL, get(ARM::DBG_VALUE))
1093 .addFrameIndex(FrameIx).addImm(0).addImm(Offset).addMetadata(MDPtr);
1097 /// Create a copy of a const pool value. Update CPI to the new index and return
1099 static unsigned duplicateCPV(MachineFunction &MF, unsigned &CPI) {
1100 MachineConstantPool *MCP = MF.getConstantPool();
1101 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1103 const MachineConstantPoolEntry &MCPE = MCP->getConstants()[CPI];
1104 assert(MCPE.isMachineConstantPoolEntry() &&
1105 "Expecting a machine constantpool entry!");
1106 ARMConstantPoolValue *ACPV =
1107 static_cast<ARMConstantPoolValue*>(MCPE.Val.MachineCPVal);
1109 unsigned PCLabelId = AFI->createPICLabelUId();
1110 ARMConstantPoolValue *NewCPV = 0;
1111 // FIXME: The below assumes PIC relocation model and that the function
1112 // is Thumb mode (t1 or t2). PCAdjustment would be 8 for ARM mode PIC, and
1113 // zero for non-PIC in ARM or Thumb. The callers are all of thumb LDR
1114 // instructions, so that's probably OK, but is PIC always correct when
1116 if (ACPV->isGlobalValue())
1117 NewCPV = ARMConstantPoolConstant::
1118 Create(cast<ARMConstantPoolConstant>(ACPV)->getGV(), PCLabelId,
1120 else if (ACPV->isExtSymbol())
1121 NewCPV = ARMConstantPoolSymbol::
1122 Create(MF.getFunction()->getContext(),
1123 cast<ARMConstantPoolSymbol>(ACPV)->getSymbol(), PCLabelId, 4);
1124 else if (ACPV->isBlockAddress())
1125 NewCPV = ARMConstantPoolConstant::
1126 Create(cast<ARMConstantPoolConstant>(ACPV)->getBlockAddress(), PCLabelId,
1127 ARMCP::CPBlockAddress, 4);
1128 else if (ACPV->isLSDA())
1129 NewCPV = ARMConstantPoolConstant::Create(MF.getFunction(), PCLabelId,
1131 else if (ACPV->isMachineBasicBlock())
1132 NewCPV = ARMConstantPoolMBB::
1133 Create(MF.getFunction()->getContext(),
1134 cast<ARMConstantPoolMBB>(ACPV)->getMBB(), PCLabelId, 4);
1136 llvm_unreachable("Unexpected ARM constantpool value type!!");
1137 CPI = MCP->getConstantPoolIndex(NewCPV, MCPE.getAlignment());
1141 void ARMBaseInstrInfo::
1142 reMaterialize(MachineBasicBlock &MBB,
1143 MachineBasicBlock::iterator I,
1144 unsigned DestReg, unsigned SubIdx,
1145 const MachineInstr *Orig,
1146 const TargetRegisterInfo &TRI) const {
1147 unsigned Opcode = Orig->getOpcode();
1150 MachineInstr *MI = MBB.getParent()->CloneMachineInstr(Orig);
1151 MI->substituteRegister(Orig->getOperand(0).getReg(), DestReg, SubIdx, TRI);
1155 case ARM::tLDRpci_pic:
1156 case ARM::t2LDRpci_pic: {
1157 MachineFunction &MF = *MBB.getParent();
1158 unsigned CPI = Orig->getOperand(1).getIndex();
1159 unsigned PCLabelId = duplicateCPV(MF, CPI);
1160 MachineInstrBuilder MIB = BuildMI(MBB, I, Orig->getDebugLoc(), get(Opcode),
1162 .addConstantPoolIndex(CPI).addImm(PCLabelId);
1163 MIB->setMemRefs(Orig->memoperands_begin(), Orig->memoperands_end());
1170 ARMBaseInstrInfo::duplicate(MachineInstr *Orig, MachineFunction &MF) const {
1171 MachineInstr *MI = TargetInstrInfoImpl::duplicate(Orig, MF);
1172 switch(Orig->getOpcode()) {
1173 case ARM::tLDRpci_pic:
1174 case ARM::t2LDRpci_pic: {
1175 unsigned CPI = Orig->getOperand(1).getIndex();
1176 unsigned PCLabelId = duplicateCPV(MF, CPI);
1177 Orig->getOperand(1).setIndex(CPI);
1178 Orig->getOperand(2).setImm(PCLabelId);
1185 bool ARMBaseInstrInfo::produceSameValue(const MachineInstr *MI0,
1186 const MachineInstr *MI1,
1187 const MachineRegisterInfo *MRI) const {
1188 int Opcode = MI0->getOpcode();
1189 if (Opcode == ARM::t2LDRpci ||
1190 Opcode == ARM::t2LDRpci_pic ||
1191 Opcode == ARM::tLDRpci ||
1192 Opcode == ARM::tLDRpci_pic ||
1193 Opcode == ARM::MOV_ga_dyn ||
1194 Opcode == ARM::MOV_ga_pcrel ||
1195 Opcode == ARM::MOV_ga_pcrel_ldr ||
1196 Opcode == ARM::t2MOV_ga_dyn ||
1197 Opcode == ARM::t2MOV_ga_pcrel) {
1198 if (MI1->getOpcode() != Opcode)
1200 if (MI0->getNumOperands() != MI1->getNumOperands())
1203 const MachineOperand &MO0 = MI0->getOperand(1);
1204 const MachineOperand &MO1 = MI1->getOperand(1);
1205 if (MO0.getOffset() != MO1.getOffset())
1208 if (Opcode == ARM::MOV_ga_dyn ||
1209 Opcode == ARM::MOV_ga_pcrel ||
1210 Opcode == ARM::MOV_ga_pcrel_ldr ||
1211 Opcode == ARM::t2MOV_ga_dyn ||
1212 Opcode == ARM::t2MOV_ga_pcrel)
1213 // Ignore the PC labels.
1214 return MO0.getGlobal() == MO1.getGlobal();
1216 const MachineFunction *MF = MI0->getParent()->getParent();
1217 const MachineConstantPool *MCP = MF->getConstantPool();
1218 int CPI0 = MO0.getIndex();
1219 int CPI1 = MO1.getIndex();
1220 const MachineConstantPoolEntry &MCPE0 = MCP->getConstants()[CPI0];
1221 const MachineConstantPoolEntry &MCPE1 = MCP->getConstants()[CPI1];
1222 bool isARMCP0 = MCPE0.isMachineConstantPoolEntry();
1223 bool isARMCP1 = MCPE1.isMachineConstantPoolEntry();
1224 if (isARMCP0 && isARMCP1) {
1225 ARMConstantPoolValue *ACPV0 =
1226 static_cast<ARMConstantPoolValue*>(MCPE0.Val.MachineCPVal);
1227 ARMConstantPoolValue *ACPV1 =
1228 static_cast<ARMConstantPoolValue*>(MCPE1.Val.MachineCPVal);
1229 return ACPV0->hasSameValue(ACPV1);
1230 } else if (!isARMCP0 && !isARMCP1) {
1231 return MCPE0.Val.ConstVal == MCPE1.Val.ConstVal;
1234 } else if (Opcode == ARM::PICLDR) {
1235 if (MI1->getOpcode() != Opcode)
1237 if (MI0->getNumOperands() != MI1->getNumOperands())
1240 unsigned Addr0 = MI0->getOperand(1).getReg();
1241 unsigned Addr1 = MI1->getOperand(1).getReg();
1242 if (Addr0 != Addr1) {
1244 !TargetRegisterInfo::isVirtualRegister(Addr0) ||
1245 !TargetRegisterInfo::isVirtualRegister(Addr1))
1248 // This assumes SSA form.
1249 MachineInstr *Def0 = MRI->getVRegDef(Addr0);
1250 MachineInstr *Def1 = MRI->getVRegDef(Addr1);
1251 // Check if the loaded value, e.g. a constantpool of a global address, are
1253 if (!produceSameValue(Def0, Def1, MRI))
1257 for (unsigned i = 3, e = MI0->getNumOperands(); i != e; ++i) {
1258 // %vreg12<def> = PICLDR %vreg11, 0, pred:14, pred:%noreg
1259 const MachineOperand &MO0 = MI0->getOperand(i);
1260 const MachineOperand &MO1 = MI1->getOperand(i);
1261 if (!MO0.isIdenticalTo(MO1))
1267 return MI0->isIdenticalTo(MI1, MachineInstr::IgnoreVRegDefs);
1270 /// areLoadsFromSameBasePtr - This is used by the pre-regalloc scheduler to
1271 /// determine if two loads are loading from the same base address. It should
1272 /// only return true if the base pointers are the same and the only differences
1273 /// between the two addresses is the offset. It also returns the offsets by
1275 bool ARMBaseInstrInfo::areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2,
1277 int64_t &Offset2) const {
1278 // Don't worry about Thumb: just ARM and Thumb2.
1279 if (Subtarget.isThumb1Only()) return false;
1281 if (!Load1->isMachineOpcode() || !Load2->isMachineOpcode())
1284 switch (Load1->getMachineOpcode()) {
1297 case ARM::t2LDRSHi8:
1299 case ARM::t2LDRSHi12:
1303 switch (Load2->getMachineOpcode()) {
1316 case ARM::t2LDRSHi8:
1318 case ARM::t2LDRSHi12:
1322 // Check if base addresses and chain operands match.
1323 if (Load1->getOperand(0) != Load2->getOperand(0) ||
1324 Load1->getOperand(4) != Load2->getOperand(4))
1327 // Index should be Reg0.
1328 if (Load1->getOperand(3) != Load2->getOperand(3))
1331 // Determine the offsets.
1332 if (isa<ConstantSDNode>(Load1->getOperand(1)) &&
1333 isa<ConstantSDNode>(Load2->getOperand(1))) {
1334 Offset1 = cast<ConstantSDNode>(Load1->getOperand(1))->getSExtValue();
1335 Offset2 = cast<ConstantSDNode>(Load2->getOperand(1))->getSExtValue();
1342 /// shouldScheduleLoadsNear - This is a used by the pre-regalloc scheduler to
1343 /// determine (in conjunction with areLoadsFromSameBasePtr) if two loads should
1344 /// be scheduled togther. On some targets if two loads are loading from
1345 /// addresses in the same cache line, it's better if they are scheduled
1346 /// together. This function takes two integers that represent the load offsets
1347 /// from the common base address. It returns true if it decides it's desirable
1348 /// to schedule the two loads together. "NumLoads" is the number of loads that
1349 /// have already been scheduled after Load1.
1350 bool ARMBaseInstrInfo::shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,
1351 int64_t Offset1, int64_t Offset2,
1352 unsigned NumLoads) const {
1353 // Don't worry about Thumb: just ARM and Thumb2.
1354 if (Subtarget.isThumb1Only()) return false;
1356 assert(Offset2 > Offset1);
1358 if ((Offset2 - Offset1) / 8 > 64)
1361 if (Load1->getMachineOpcode() != Load2->getMachineOpcode())
1362 return false; // FIXME: overly conservative?
1364 // Four loads in a row should be sufficient.
1371 bool ARMBaseInstrInfo::isSchedulingBoundary(const MachineInstr *MI,
1372 const MachineBasicBlock *MBB,
1373 const MachineFunction &MF) const {
1374 // Debug info is never a scheduling boundary. It's necessary to be explicit
1375 // due to the special treatment of IT instructions below, otherwise a
1376 // dbg_value followed by an IT will result in the IT instruction being
1377 // considered a scheduling hazard, which is wrong. It should be the actual
1378 // instruction preceding the dbg_value instruction(s), just like it is
1379 // when debug info is not present.
1380 if (MI->isDebugValue())
1383 // Terminators and labels can't be scheduled around.
1384 if (MI->isTerminator() || MI->isLabel())
1387 // Treat the start of the IT block as a scheduling boundary, but schedule
1388 // t2IT along with all instructions following it.
1389 // FIXME: This is a big hammer. But the alternative is to add all potential
1390 // true and anti dependencies to IT block instructions as implicit operands
1391 // to the t2IT instruction. The added compile time and complexity does not
1393 MachineBasicBlock::const_iterator I = MI;
1394 // Make sure to skip any dbg_value instructions
1395 while (++I != MBB->end() && I->isDebugValue())
1397 if (I != MBB->end() && I->getOpcode() == ARM::t2IT)
1400 // Don't attempt to schedule around any instruction that defines
1401 // a stack-oriented pointer, as it's unlikely to be profitable. This
1402 // saves compile time, because it doesn't require every single
1403 // stack slot reference to depend on the instruction that does the
1405 // Calls don't actually change the stack pointer, even if they have imp-defs.
1406 // No ARM calling conventions change the stack pointer. (X86 calling
1407 // conventions sometimes do).
1408 if (!MI->isCall() && MI->definesRegister(ARM::SP))
1414 bool ARMBaseInstrInfo::
1415 isProfitableToIfCvt(MachineBasicBlock &MBB,
1416 unsigned NumCycles, unsigned ExtraPredCycles,
1417 const BranchProbability &Probability) const {
1421 // Attempt to estimate the relative costs of predication versus branching.
1422 unsigned UnpredCost = Probability.getNumerator() * NumCycles;
1423 UnpredCost /= Probability.getDenominator();
1424 UnpredCost += 1; // The branch itself
1425 UnpredCost += Subtarget.getMispredictionPenalty() / 10;
1427 return (NumCycles + ExtraPredCycles) <= UnpredCost;
1430 bool ARMBaseInstrInfo::
1431 isProfitableToIfCvt(MachineBasicBlock &TMBB,
1432 unsigned TCycles, unsigned TExtra,
1433 MachineBasicBlock &FMBB,
1434 unsigned FCycles, unsigned FExtra,
1435 const BranchProbability &Probability) const {
1436 if (!TCycles || !FCycles)
1439 // Attempt to estimate the relative costs of predication versus branching.
1440 unsigned TUnpredCost = Probability.getNumerator() * TCycles;
1441 TUnpredCost /= Probability.getDenominator();
1443 uint32_t Comp = Probability.getDenominator() - Probability.getNumerator();
1444 unsigned FUnpredCost = Comp * FCycles;
1445 FUnpredCost /= Probability.getDenominator();
1447 unsigned UnpredCost = TUnpredCost + FUnpredCost;
1448 UnpredCost += 1; // The branch itself
1449 UnpredCost += Subtarget.getMispredictionPenalty() / 10;
1451 return (TCycles + FCycles + TExtra + FExtra) <= UnpredCost;
1454 /// getInstrPredicate - If instruction is predicated, returns its predicate
1455 /// condition, otherwise returns AL. It also returns the condition code
1456 /// register by reference.
1458 llvm::getInstrPredicate(const MachineInstr *MI, unsigned &PredReg) {
1459 int PIdx = MI->findFirstPredOperandIdx();
1465 PredReg = MI->getOperand(PIdx+1).getReg();
1466 return (ARMCC::CondCodes)MI->getOperand(PIdx).getImm();
1470 int llvm::getMatchingCondBranchOpcode(int Opc) {
1475 if (Opc == ARM::t2B)
1478 llvm_unreachable("Unknown unconditional branch opcode!");
1482 /// Map pseudo instructions that imply an 'S' bit onto real opcodes. Whether the
1483 /// instruction is encoded with an 'S' bit is determined by the optional CPSR
1486 /// This will go away once we can teach tblgen how to set the optional CPSR def
1488 struct AddSubFlagsOpcodePair {
1490 unsigned MachineOpc;
1493 static AddSubFlagsOpcodePair AddSubFlagsOpcodeMap[] = {
1494 {ARM::ADDSri, ARM::ADDri},
1495 {ARM::ADDSrr, ARM::ADDrr},
1496 {ARM::ADDSrsi, ARM::ADDrsi},
1497 {ARM::ADDSrsr, ARM::ADDrsr},
1499 {ARM::SUBSri, ARM::SUBri},
1500 {ARM::SUBSrr, ARM::SUBrr},
1501 {ARM::SUBSrsi, ARM::SUBrsi},
1502 {ARM::SUBSrsr, ARM::SUBrsr},
1504 {ARM::RSBSri, ARM::RSBri},
1505 {ARM::RSBSrsi, ARM::RSBrsi},
1506 {ARM::RSBSrsr, ARM::RSBrsr},
1508 {ARM::t2ADDSri, ARM::t2ADDri},
1509 {ARM::t2ADDSrr, ARM::t2ADDrr},
1510 {ARM::t2ADDSrs, ARM::t2ADDrs},
1512 {ARM::t2SUBSri, ARM::t2SUBri},
1513 {ARM::t2SUBSrr, ARM::t2SUBrr},
1514 {ARM::t2SUBSrs, ARM::t2SUBrs},
1516 {ARM::t2RSBSri, ARM::t2RSBri},
1517 {ARM::t2RSBSrs, ARM::t2RSBrs},
1520 unsigned llvm::convertAddSubFlagsOpcode(unsigned OldOpc) {
1521 static const int NPairs =
1522 sizeof(AddSubFlagsOpcodeMap) / sizeof(AddSubFlagsOpcodePair);
1523 for (AddSubFlagsOpcodePair *OpcPair = &AddSubFlagsOpcodeMap[0],
1524 *End = &AddSubFlagsOpcodeMap[NPairs]; OpcPair != End; ++OpcPair) {
1525 if (OldOpc == OpcPair->PseudoOpc) {
1526 return OpcPair->MachineOpc;
1532 void llvm::emitARMRegPlusImmediate(MachineBasicBlock &MBB,
1533 MachineBasicBlock::iterator &MBBI, DebugLoc dl,
1534 unsigned DestReg, unsigned BaseReg, int NumBytes,
1535 ARMCC::CondCodes Pred, unsigned PredReg,
1536 const ARMBaseInstrInfo &TII, unsigned MIFlags) {
1537 bool isSub = NumBytes < 0;
1538 if (isSub) NumBytes = -NumBytes;
1541 unsigned RotAmt = ARM_AM::getSOImmValRotate(NumBytes);
1542 unsigned ThisVal = NumBytes & ARM_AM::rotr32(0xFF, RotAmt);
1543 assert(ThisVal && "Didn't extract field correctly");
1545 // We will handle these bits from offset, clear them.
1546 NumBytes &= ~ThisVal;
1548 assert(ARM_AM::getSOImmVal(ThisVal) != -1 && "Bit extraction didn't work?");
1550 // Build the new ADD / SUB.
1551 unsigned Opc = isSub ? ARM::SUBri : ARM::ADDri;
1552 BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg)
1553 .addReg(BaseReg, RegState::Kill).addImm(ThisVal)
1554 .addImm((unsigned)Pred).addReg(PredReg).addReg(0)
1555 .setMIFlags(MIFlags);
1560 bool llvm::rewriteARMFrameIndex(MachineInstr &MI, unsigned FrameRegIdx,
1561 unsigned FrameReg, int &Offset,
1562 const ARMBaseInstrInfo &TII) {
1563 unsigned Opcode = MI.getOpcode();
1564 const MCInstrDesc &Desc = MI.getDesc();
1565 unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
1568 // Memory operands in inline assembly always use AddrMode2.
1569 if (Opcode == ARM::INLINEASM)
1570 AddrMode = ARMII::AddrMode2;
1572 if (Opcode == ARM::ADDri) {
1573 Offset += MI.getOperand(FrameRegIdx+1).getImm();
1575 // Turn it into a move.
1576 MI.setDesc(TII.get(ARM::MOVr));
1577 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
1578 MI.RemoveOperand(FrameRegIdx+1);
1581 } else if (Offset < 0) {
1584 MI.setDesc(TII.get(ARM::SUBri));
1587 // Common case: small offset, fits into instruction.
1588 if (ARM_AM::getSOImmVal(Offset) != -1) {
1589 // Replace the FrameIndex with sp / fp
1590 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
1591 MI.getOperand(FrameRegIdx+1).ChangeToImmediate(Offset);
1596 // Otherwise, pull as much of the immedidate into this ADDri/SUBri
1598 unsigned RotAmt = ARM_AM::getSOImmValRotate(Offset);
1599 unsigned ThisImmVal = Offset & ARM_AM::rotr32(0xFF, RotAmt);
1601 // We will handle these bits from offset, clear them.
1602 Offset &= ~ThisImmVal;
1604 // Get the properly encoded SOImmVal field.
1605 assert(ARM_AM::getSOImmVal(ThisImmVal) != -1 &&
1606 "Bit extraction didn't work?");
1607 MI.getOperand(FrameRegIdx+1).ChangeToImmediate(ThisImmVal);
1609 unsigned ImmIdx = 0;
1611 unsigned NumBits = 0;
1614 case ARMII::AddrMode_i12: {
1615 ImmIdx = FrameRegIdx + 1;
1616 InstrOffs = MI.getOperand(ImmIdx).getImm();
1620 case ARMII::AddrMode2: {
1621 ImmIdx = FrameRegIdx+2;
1622 InstrOffs = ARM_AM::getAM2Offset(MI.getOperand(ImmIdx).getImm());
1623 if (ARM_AM::getAM2Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub)
1628 case ARMII::AddrMode3: {
1629 ImmIdx = FrameRegIdx+2;
1630 InstrOffs = ARM_AM::getAM3Offset(MI.getOperand(ImmIdx).getImm());
1631 if (ARM_AM::getAM3Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub)
1636 case ARMII::AddrMode4:
1637 case ARMII::AddrMode6:
1638 // Can't fold any offset even if it's zero.
1640 case ARMII::AddrMode5: {
1641 ImmIdx = FrameRegIdx+1;
1642 InstrOffs = ARM_AM::getAM5Offset(MI.getOperand(ImmIdx).getImm());
1643 if (ARM_AM::getAM5Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub)
1650 llvm_unreachable("Unsupported addressing mode!");
1653 Offset += InstrOffs * Scale;
1654 assert((Offset & (Scale-1)) == 0 && "Can't encode this offset!");
1660 // Attempt to fold address comp. if opcode has offset bits
1662 // Common case: small offset, fits into instruction.
1663 MachineOperand &ImmOp = MI.getOperand(ImmIdx);
1664 int ImmedOffset = Offset / Scale;
1665 unsigned Mask = (1 << NumBits) - 1;
1666 if ((unsigned)Offset <= Mask * Scale) {
1667 // Replace the FrameIndex with sp
1668 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
1669 // FIXME: When addrmode2 goes away, this will simplify (like the
1670 // T2 version), as the LDR.i12 versions don't need the encoding
1671 // tricks for the offset value.
1673 if (AddrMode == ARMII::AddrMode_i12)
1674 ImmedOffset = -ImmedOffset;
1676 ImmedOffset |= 1 << NumBits;
1678 ImmOp.ChangeToImmediate(ImmedOffset);
1683 // Otherwise, it didn't fit. Pull in what we can to simplify the immed.
1684 ImmedOffset = ImmedOffset & Mask;
1686 if (AddrMode == ARMII::AddrMode_i12)
1687 ImmedOffset = -ImmedOffset;
1689 ImmedOffset |= 1 << NumBits;
1691 ImmOp.ChangeToImmediate(ImmedOffset);
1692 Offset &= ~(Mask*Scale);
1696 Offset = (isSub) ? -Offset : Offset;
1700 bool ARMBaseInstrInfo::
1701 AnalyzeCompare(const MachineInstr *MI, unsigned &SrcReg, int &CmpMask,
1702 int &CmpValue) const {
1703 switch (MI->getOpcode()) {
1707 SrcReg = MI->getOperand(0).getReg();
1709 CmpValue = MI->getOperand(1).getImm();
1713 SrcReg = MI->getOperand(0).getReg();
1714 CmpMask = MI->getOperand(1).getImm();
1722 /// isSuitableForMask - Identify a suitable 'and' instruction that
1723 /// operates on the given source register and applies the same mask
1724 /// as a 'tst' instruction. Provide a limited look-through for copies.
1725 /// When successful, MI will hold the found instruction.
1726 static bool isSuitableForMask(MachineInstr *&MI, unsigned SrcReg,
1727 int CmpMask, bool CommonUse) {
1728 switch (MI->getOpcode()) {
1731 if (CmpMask != MI->getOperand(2).getImm())
1733 if (SrcReg == MI->getOperand(CommonUse ? 1 : 0).getReg())
1737 // Walk down one instruction which is potentially an 'and'.
1738 const MachineInstr &Copy = *MI;
1739 MachineBasicBlock::iterator AND(
1740 llvm::next(MachineBasicBlock::iterator(MI)));
1741 if (AND == MI->getParent()->end()) return false;
1743 return isSuitableForMask(MI, Copy.getOperand(0).getReg(),
1751 /// OptimizeCompareInstr - Convert the instruction supplying the argument to the
1752 /// comparison into one that sets the zero bit in the flags register.
1753 bool ARMBaseInstrInfo::
1754 OptimizeCompareInstr(MachineInstr *CmpInstr, unsigned SrcReg, int CmpMask,
1755 int CmpValue, const MachineRegisterInfo *MRI) const {
1759 MachineRegisterInfo::def_iterator DI = MRI->def_begin(SrcReg);
1760 if (llvm::next(DI) != MRI->def_end())
1761 // Only support one definition.
1764 MachineInstr *MI = &*DI;
1766 // Masked compares sometimes use the same register as the corresponding 'and'.
1767 if (CmpMask != ~0) {
1768 if (!isSuitableForMask(MI, SrcReg, CmpMask, false)) {
1770 for (MachineRegisterInfo::use_iterator UI = MRI->use_begin(SrcReg),
1771 UE = MRI->use_end(); UI != UE; ++UI) {
1772 if (UI->getParent() != CmpInstr->getParent()) continue;
1773 MachineInstr *PotentialAND = &*UI;
1774 if (!isSuitableForMask(PotentialAND, SrcReg, CmpMask, true))
1779 if (!MI) return false;
1783 // Conservatively refuse to convert an instruction which isn't in the same BB
1784 // as the comparison.
1785 if (MI->getParent() != CmpInstr->getParent())
1788 // Check that CPSR isn't set between the comparison instruction and the one we
1790 MachineBasicBlock::iterator I = CmpInstr,E = MI, B = MI->getParent()->begin();
1792 // Early exit if CmpInstr is at the beginning of the BB.
1793 if (I == B) return false;
1796 for (; I != E; --I) {
1797 const MachineInstr &Instr = *I;
1799 for (unsigned IO = 0, EO = Instr.getNumOperands(); IO != EO; ++IO) {
1800 const MachineOperand &MO = Instr.getOperand(IO);
1801 if (MO.isRegMask() && MO.clobbersPhysReg(ARM::CPSR))
1803 if (!MO.isReg()) continue;
1805 // This instruction modifies or uses CPSR after the one we want to
1806 // change. We can't do this transformation.
1807 if (MO.getReg() == ARM::CPSR)
1812 // The 'and' is below the comparison instruction.
1816 // Set the "zero" bit in CPSR.
1817 switch (MI->getOpcode()) {
1851 case ARM::t2EORri: {
1852 // Scan forward for the use of CPSR, if it's a conditional code requires
1853 // checking of V bit, then this is not safe to do. If we can't find the
1854 // CPSR use (i.e. used in another block), then it's not safe to perform
1855 // the optimization.
1856 bool isSafe = false;
1858 E = MI->getParent()->end();
1859 while (!isSafe && ++I != E) {
1860 const MachineInstr &Instr = *I;
1861 for (unsigned IO = 0, EO = Instr.getNumOperands();
1862 !isSafe && IO != EO; ++IO) {
1863 const MachineOperand &MO = Instr.getOperand(IO);
1864 if (MO.isRegMask() && MO.clobbersPhysReg(ARM::CPSR)) {
1868 if (!MO.isReg() || MO.getReg() != ARM::CPSR)
1874 // Condition code is after the operand before CPSR.
1875 ARMCC::CondCodes CC = (ARMCC::CondCodes)Instr.getOperand(IO-1).getImm();
1894 // Toggle the optional operand to CPSR.
1895 MI->getOperand(5).setReg(ARM::CPSR);
1896 MI->getOperand(5).setIsDef(true);
1897 CmpInstr->eraseFromParent();
1905 bool ARMBaseInstrInfo::FoldImmediate(MachineInstr *UseMI,
1906 MachineInstr *DefMI, unsigned Reg,
1907 MachineRegisterInfo *MRI) const {
1908 // Fold large immediates into add, sub, or, xor.
1909 unsigned DefOpc = DefMI->getOpcode();
1910 if (DefOpc != ARM::t2MOVi32imm && DefOpc != ARM::MOVi32imm)
1912 if (!DefMI->getOperand(1).isImm())
1913 // Could be t2MOVi32imm <ga:xx>
1916 if (!MRI->hasOneNonDBGUse(Reg))
1919 unsigned UseOpc = UseMI->getOpcode();
1920 unsigned NewUseOpc = 0;
1921 uint32_t ImmVal = (uint32_t)DefMI->getOperand(1).getImm();
1922 uint32_t SOImmValV1 = 0, SOImmValV2 = 0;
1923 bool Commute = false;
1925 default: return false;
1933 case ARM::t2EORrr: {
1934 Commute = UseMI->getOperand(2).getReg() != Reg;
1941 NewUseOpc = ARM::SUBri;
1947 if (!ARM_AM::isSOImmTwoPartVal(ImmVal))
1949 SOImmValV1 = (uint32_t)ARM_AM::getSOImmTwoPartFirst(ImmVal);
1950 SOImmValV2 = (uint32_t)ARM_AM::getSOImmTwoPartSecond(ImmVal);
1953 case ARM::ADDrr: NewUseOpc = ARM::ADDri; break;
1954 case ARM::ORRrr: NewUseOpc = ARM::ORRri; break;
1955 case ARM::EORrr: NewUseOpc = ARM::EORri; break;
1959 case ARM::t2SUBrr: {
1963 NewUseOpc = ARM::t2SUBri;
1968 case ARM::t2EORrr: {
1969 if (!ARM_AM::isT2SOImmTwoPartVal(ImmVal))
1971 SOImmValV1 = (uint32_t)ARM_AM::getT2SOImmTwoPartFirst(ImmVal);
1972 SOImmValV2 = (uint32_t)ARM_AM::getT2SOImmTwoPartSecond(ImmVal);
1975 case ARM::t2ADDrr: NewUseOpc = ARM::t2ADDri; break;
1976 case ARM::t2ORRrr: NewUseOpc = ARM::t2ORRri; break;
1977 case ARM::t2EORrr: NewUseOpc = ARM::t2EORri; break;
1985 unsigned OpIdx = Commute ? 2 : 1;
1986 unsigned Reg1 = UseMI->getOperand(OpIdx).getReg();
1987 bool isKill = UseMI->getOperand(OpIdx).isKill();
1988 unsigned NewReg = MRI->createVirtualRegister(MRI->getRegClass(Reg));
1989 AddDefaultCC(AddDefaultPred(BuildMI(*UseMI->getParent(),
1990 UseMI, UseMI->getDebugLoc(),
1991 get(NewUseOpc), NewReg)
1992 .addReg(Reg1, getKillRegState(isKill))
1993 .addImm(SOImmValV1)));
1994 UseMI->setDesc(get(NewUseOpc));
1995 UseMI->getOperand(1).setReg(NewReg);
1996 UseMI->getOperand(1).setIsKill();
1997 UseMI->getOperand(2).ChangeToImmediate(SOImmValV2);
1998 DefMI->eraseFromParent();
2003 ARMBaseInstrInfo::getNumMicroOps(const InstrItineraryData *ItinData,
2004 const MachineInstr *MI) const {
2005 if (!ItinData || ItinData->isEmpty())
2008 const MCInstrDesc &Desc = MI->getDesc();
2009 unsigned Class = Desc.getSchedClass();
2010 unsigned UOps = ItinData->Itineraries[Class].NumMicroOps;
2014 unsigned Opc = MI->getOpcode();
2017 llvm_unreachable("Unexpected multi-uops instruction!");
2022 // The number of uOps for load / store multiple are determined by the number
2025 // On Cortex-A8, each pair of register loads / stores can be scheduled on the
2026 // same cycle. The scheduling for the first load / store must be done
2027 // separately by assuming the the address is not 64-bit aligned.
2029 // On Cortex-A9, the formula is simply (#reg / 2) + (#reg % 2). If the address
2030 // is not 64-bit aligned, then AGU would take an extra cycle. For VFP / NEON
2031 // load / store multiple, the formula is (#reg / 2) + (#reg % 2) + 1.
2033 case ARM::VLDMDIA_UPD:
2034 case ARM::VLDMDDB_UPD:
2036 case ARM::VLDMSIA_UPD:
2037 case ARM::VLDMSDB_UPD:
2039 case ARM::VSTMDIA_UPD:
2040 case ARM::VSTMDDB_UPD:
2042 case ARM::VSTMSIA_UPD:
2043 case ARM::VSTMSDB_UPD: {
2044 unsigned NumRegs = MI->getNumOperands() - Desc.getNumOperands();
2045 return (NumRegs / 2) + (NumRegs % 2) + 1;
2048 case ARM::LDMIA_RET:
2053 case ARM::LDMIA_UPD:
2054 case ARM::LDMDA_UPD:
2055 case ARM::LDMDB_UPD:
2056 case ARM::LDMIB_UPD:
2061 case ARM::STMIA_UPD:
2062 case ARM::STMDA_UPD:
2063 case ARM::STMDB_UPD:
2064 case ARM::STMIB_UPD:
2066 case ARM::tLDMIA_UPD:
2067 case ARM::tSTMIA_UPD:
2071 case ARM::t2LDMIA_RET:
2074 case ARM::t2LDMIA_UPD:
2075 case ARM::t2LDMDB_UPD:
2078 case ARM::t2STMIA_UPD:
2079 case ARM::t2STMDB_UPD: {
2080 unsigned NumRegs = MI->getNumOperands() - Desc.getNumOperands() + 1;
2081 if (Subtarget.isCortexA8()) {
2084 // 4 registers would be issued: 2, 2.
2085 // 5 registers would be issued: 2, 2, 1.
2086 UOps = (NumRegs / 2);
2090 } else if (Subtarget.isCortexA9()) {
2091 UOps = (NumRegs / 2);
2092 // If there are odd number of registers or if it's not 64-bit aligned,
2093 // then it takes an extra AGU (Address Generation Unit) cycle.
2094 if ((NumRegs % 2) ||
2095 !MI->hasOneMemOperand() ||
2096 (*MI->memoperands_begin())->getAlignment() < 8)
2100 // Assume the worst.
2108 ARMBaseInstrInfo::getVLDMDefCycle(const InstrItineraryData *ItinData,
2109 const MCInstrDesc &DefMCID,
2111 unsigned DefIdx, unsigned DefAlign) const {
2112 int RegNo = (int)(DefIdx+1) - DefMCID.getNumOperands() + 1;
2114 // Def is the address writeback.
2115 return ItinData->getOperandCycle(DefClass, DefIdx);
2118 if (Subtarget.isCortexA8()) {
2119 // (regno / 2) + (regno % 2) + 1
2120 DefCycle = RegNo / 2 + 1;
2123 } else if (Subtarget.isCortexA9()) {
2125 bool isSLoad = false;
2127 switch (DefMCID.getOpcode()) {
2130 case ARM::VLDMSIA_UPD:
2131 case ARM::VLDMSDB_UPD:
2136 // If there are odd number of 'S' registers or if it's not 64-bit aligned,
2137 // then it takes an extra cycle.
2138 if ((isSLoad && (RegNo % 2)) || DefAlign < 8)
2141 // Assume the worst.
2142 DefCycle = RegNo + 2;
2149 ARMBaseInstrInfo::getLDMDefCycle(const InstrItineraryData *ItinData,
2150 const MCInstrDesc &DefMCID,
2152 unsigned DefIdx, unsigned DefAlign) const {
2153 int RegNo = (int)(DefIdx+1) - DefMCID.getNumOperands() + 1;
2155 // Def is the address writeback.
2156 return ItinData->getOperandCycle(DefClass, DefIdx);
2159 if (Subtarget.isCortexA8()) {
2160 // 4 registers would be issued: 1, 2, 1.
2161 // 5 registers would be issued: 1, 2, 2.
2162 DefCycle = RegNo / 2;
2165 // Result latency is issue cycle + 2: E2.
2167 } else if (Subtarget.isCortexA9()) {
2168 DefCycle = (RegNo / 2);
2169 // If there are odd number of registers or if it's not 64-bit aligned,
2170 // then it takes an extra AGU (Address Generation Unit) cycle.
2171 if ((RegNo % 2) || DefAlign < 8)
2173 // Result latency is AGU cycles + 2.
2176 // Assume the worst.
2177 DefCycle = RegNo + 2;
2184 ARMBaseInstrInfo::getVSTMUseCycle(const InstrItineraryData *ItinData,
2185 const MCInstrDesc &UseMCID,
2187 unsigned UseIdx, unsigned UseAlign) const {
2188 int RegNo = (int)(UseIdx+1) - UseMCID.getNumOperands() + 1;
2190 return ItinData->getOperandCycle(UseClass, UseIdx);
2193 if (Subtarget.isCortexA8()) {
2194 // (regno / 2) + (regno % 2) + 1
2195 UseCycle = RegNo / 2 + 1;
2198 } else if (Subtarget.isCortexA9()) {
2200 bool isSStore = false;
2202 switch (UseMCID.getOpcode()) {
2205 case ARM::VSTMSIA_UPD:
2206 case ARM::VSTMSDB_UPD:
2211 // If there are odd number of 'S' registers or if it's not 64-bit aligned,
2212 // then it takes an extra cycle.
2213 if ((isSStore && (RegNo % 2)) || UseAlign < 8)
2216 // Assume the worst.
2217 UseCycle = RegNo + 2;
2224 ARMBaseInstrInfo::getSTMUseCycle(const InstrItineraryData *ItinData,
2225 const MCInstrDesc &UseMCID,
2227 unsigned UseIdx, unsigned UseAlign) const {
2228 int RegNo = (int)(UseIdx+1) - UseMCID.getNumOperands() + 1;
2230 return ItinData->getOperandCycle(UseClass, UseIdx);
2233 if (Subtarget.isCortexA8()) {
2234 UseCycle = RegNo / 2;
2239 } else if (Subtarget.isCortexA9()) {
2240 UseCycle = (RegNo / 2);
2241 // If there are odd number of registers or if it's not 64-bit aligned,
2242 // then it takes an extra AGU (Address Generation Unit) cycle.
2243 if ((RegNo % 2) || UseAlign < 8)
2246 // Assume the worst.
2253 ARMBaseInstrInfo::getOperandLatency(const InstrItineraryData *ItinData,
2254 const MCInstrDesc &DefMCID,
2255 unsigned DefIdx, unsigned DefAlign,
2256 const MCInstrDesc &UseMCID,
2257 unsigned UseIdx, unsigned UseAlign) const {
2258 unsigned DefClass = DefMCID.getSchedClass();
2259 unsigned UseClass = UseMCID.getSchedClass();
2261 if (DefIdx < DefMCID.getNumDefs() && UseIdx < UseMCID.getNumOperands())
2262 return ItinData->getOperandLatency(DefClass, DefIdx, UseClass, UseIdx);
2264 // This may be a def / use of a variable_ops instruction, the operand
2265 // latency might be determinable dynamically. Let the target try to
2268 bool LdmBypass = false;
2269 switch (DefMCID.getOpcode()) {
2271 DefCycle = ItinData->getOperandCycle(DefClass, DefIdx);
2275 case ARM::VLDMDIA_UPD:
2276 case ARM::VLDMDDB_UPD:
2278 case ARM::VLDMSIA_UPD:
2279 case ARM::VLDMSDB_UPD:
2280 DefCycle = getVLDMDefCycle(ItinData, DefMCID, DefClass, DefIdx, DefAlign);
2283 case ARM::LDMIA_RET:
2288 case ARM::LDMIA_UPD:
2289 case ARM::LDMDA_UPD:
2290 case ARM::LDMDB_UPD:
2291 case ARM::LDMIB_UPD:
2293 case ARM::tLDMIA_UPD:
2295 case ARM::t2LDMIA_RET:
2298 case ARM::t2LDMIA_UPD:
2299 case ARM::t2LDMDB_UPD:
2301 DefCycle = getLDMDefCycle(ItinData, DefMCID, DefClass, DefIdx, DefAlign);
2306 // We can't seem to determine the result latency of the def, assume it's 2.
2310 switch (UseMCID.getOpcode()) {
2312 UseCycle = ItinData->getOperandCycle(UseClass, UseIdx);
2316 case ARM::VSTMDIA_UPD:
2317 case ARM::VSTMDDB_UPD:
2319 case ARM::VSTMSIA_UPD:
2320 case ARM::VSTMSDB_UPD:
2321 UseCycle = getVSTMUseCycle(ItinData, UseMCID, UseClass, UseIdx, UseAlign);
2328 case ARM::STMIA_UPD:
2329 case ARM::STMDA_UPD:
2330 case ARM::STMDB_UPD:
2331 case ARM::STMIB_UPD:
2332 case ARM::tSTMIA_UPD:
2337 case ARM::t2STMIA_UPD:
2338 case ARM::t2STMDB_UPD:
2339 UseCycle = getSTMUseCycle(ItinData, UseMCID, UseClass, UseIdx, UseAlign);
2344 // Assume it's read in the first stage.
2347 UseCycle = DefCycle - UseCycle + 1;
2350 // It's a variable_ops instruction so we can't use DefIdx here. Just use
2351 // first def operand.
2352 if (ItinData->hasPipelineForwarding(DefClass, DefMCID.getNumOperands()-1,
2355 } else if (ItinData->hasPipelineForwarding(DefClass, DefIdx,
2356 UseClass, UseIdx)) {
2364 static const MachineInstr *getBundledDefMI(const TargetRegisterInfo *TRI,
2365 const MachineInstr *MI, unsigned Reg,
2366 unsigned &DefIdx, unsigned &Dist) {
2369 MachineBasicBlock::const_iterator I = MI; ++I;
2370 MachineBasicBlock::const_instr_iterator II =
2371 llvm::prior(I.getInstrIterator());
2372 assert(II->isInsideBundle() && "Empty bundle?");
2375 while (II->isInsideBundle()) {
2376 Idx = II->findRegisterDefOperandIdx(Reg, false, true, TRI);
2383 assert(Idx != -1 && "Cannot find bundled definition!");
2388 static const MachineInstr *getBundledUseMI(const TargetRegisterInfo *TRI,
2389 const MachineInstr *MI, unsigned Reg,
2390 unsigned &UseIdx, unsigned &Dist) {
2393 MachineBasicBlock::const_instr_iterator II = MI; ++II;
2394 assert(II->isInsideBundle() && "Empty bundle?");
2395 MachineBasicBlock::const_instr_iterator E = MI->getParent()->instr_end();
2397 // FIXME: This doesn't properly handle multiple uses.
2399 while (II != E && II->isInsideBundle()) {
2400 Idx = II->findRegisterUseOperandIdx(Reg, false, TRI);
2403 if (II->getOpcode() != ARM::t2IT)
2418 ARMBaseInstrInfo::getOperandLatency(const InstrItineraryData *ItinData,
2419 const MachineInstr *DefMI, unsigned DefIdx,
2420 const MachineInstr *UseMI, unsigned UseIdx) const {
2421 if (DefMI->isCopyLike() || DefMI->isInsertSubreg() ||
2422 DefMI->isRegSequence() || DefMI->isImplicitDef())
2425 if (!ItinData || ItinData->isEmpty())
2426 return DefMI->mayLoad() ? 3 : 1;
2428 const MCInstrDesc *DefMCID = &DefMI->getDesc();
2429 const MCInstrDesc *UseMCID = &UseMI->getDesc();
2430 const MachineOperand &DefMO = DefMI->getOperand(DefIdx);
2431 unsigned Reg = DefMO.getReg();
2432 if (Reg == ARM::CPSR) {
2433 if (DefMI->getOpcode() == ARM::FMSTAT) {
2434 // fpscr -> cpsr stalls over 20 cycles on A8 (and earlier?)
2435 return Subtarget.isCortexA9() ? 1 : 20;
2438 // CPSR set and branch can be paired in the same cycle.
2439 if (UseMI->isBranch())
2442 // Otherwise it takes the instruction latency (generally one).
2443 int Latency = getInstrLatency(ItinData, DefMI);
2445 // For Thumb2 and -Os, prefer scheduling CPSR setting instruction close to
2446 // its uses. Instructions which are otherwise scheduled between them may
2447 // incur a code size penalty (not able to use the CPSR setting 16-bit
2449 if (Latency > 0 && Subtarget.isThumb2()) {
2450 const MachineFunction *MF = DefMI->getParent()->getParent();
2451 if (MF->getFunction()->hasFnAttr(Attribute::OptimizeForSize))
2457 unsigned DefAlign = DefMI->hasOneMemOperand()
2458 ? (*DefMI->memoperands_begin())->getAlignment() : 0;
2459 unsigned UseAlign = UseMI->hasOneMemOperand()
2460 ? (*UseMI->memoperands_begin())->getAlignment() : 0;
2462 unsigned DefAdj = 0;
2463 if (DefMI->isBundle()) {
2464 DefMI = getBundledDefMI(&getRegisterInfo(), DefMI, Reg, DefIdx, DefAdj);
2465 if (DefMI->isCopyLike() || DefMI->isInsertSubreg() ||
2466 DefMI->isRegSequence() || DefMI->isImplicitDef())
2468 DefMCID = &DefMI->getDesc();
2470 unsigned UseAdj = 0;
2471 if (UseMI->isBundle()) {
2473 const MachineInstr *NewUseMI = getBundledUseMI(&getRegisterInfo(), UseMI,
2474 Reg, NewUseIdx, UseAdj);
2478 UseMCID = &UseMI->getDesc();
2482 int Latency = getOperandLatency(ItinData, *DefMCID, DefIdx, DefAlign,
2483 *UseMCID, UseIdx, UseAlign);
2484 int Adj = DefAdj + UseAdj;
2486 Latency -= (int)(DefAdj + UseAdj);
2492 (Subtarget.isCortexA8() || Subtarget.isCortexA9())) {
2493 // FIXME: Shifter op hack: no shift (i.e. [r +/- r]) or [r + r << 2]
2494 // variants are one cycle cheaper.
2495 switch (DefMCID->getOpcode()) {
2499 unsigned ShOpVal = DefMI->getOperand(3).getImm();
2500 unsigned ShImm = ARM_AM::getAM2Offset(ShOpVal);
2502 (ShImm == 2 && ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl))
2509 case ARM::t2LDRSHs: {
2510 // Thumb2 mode: lsl only.
2511 unsigned ShAmt = DefMI->getOperand(3).getImm();
2512 if (ShAmt == 0 || ShAmt == 2)
2519 if (DefAlign < 8 && Subtarget.isCortexA9())
2520 switch (DefMCID->getOpcode()) {
2526 case ARM::VLD1q8wb_fixed:
2527 case ARM::VLD1q16wb_fixed:
2528 case ARM::VLD1q32wb_fixed:
2529 case ARM::VLD1q64wb_fixed:
2530 case ARM::VLD1q8wb_register:
2531 case ARM::VLD1q16wb_register:
2532 case ARM::VLD1q32wb_register:
2533 case ARM::VLD1q64wb_register:
2540 case ARM::VLD2d8wb_fixed:
2541 case ARM::VLD2d16wb_fixed:
2542 case ARM::VLD2d32wb_fixed:
2543 case ARM::VLD2q8wb_fixed:
2544 case ARM::VLD2q16wb_fixed:
2545 case ARM::VLD2q32wb_fixed:
2546 case ARM::VLD2d8wb_register:
2547 case ARM::VLD2d16wb_register:
2548 case ARM::VLD2d32wb_register:
2549 case ARM::VLD2q8wb_register:
2550 case ARM::VLD2q16wb_register:
2551 case ARM::VLD2q32wb_register:
2556 case ARM::VLD3d8_UPD:
2557 case ARM::VLD3d16_UPD:
2558 case ARM::VLD3d32_UPD:
2559 case ARM::VLD1d64Twb_fixed:
2560 case ARM::VLD1d64Twb_register:
2561 case ARM::VLD3q8_UPD:
2562 case ARM::VLD3q16_UPD:
2563 case ARM::VLD3q32_UPD:
2568 case ARM::VLD4d8_UPD:
2569 case ARM::VLD4d16_UPD:
2570 case ARM::VLD4d32_UPD:
2571 case ARM::VLD1d64Qwb_fixed:
2572 case ARM::VLD1d64Qwb_register:
2573 case ARM::VLD4q8_UPD:
2574 case ARM::VLD4q16_UPD:
2575 case ARM::VLD4q32_UPD:
2576 case ARM::VLD1DUPq8:
2577 case ARM::VLD1DUPq16:
2578 case ARM::VLD1DUPq32:
2579 case ARM::VLD1DUPq8wb_fixed:
2580 case ARM::VLD1DUPq16wb_fixed:
2581 case ARM::VLD1DUPq32wb_fixed:
2582 case ARM::VLD1DUPq8wb_register:
2583 case ARM::VLD1DUPq16wb_register:
2584 case ARM::VLD1DUPq32wb_register:
2585 case ARM::VLD2DUPd8:
2586 case ARM::VLD2DUPd16:
2587 case ARM::VLD2DUPd32:
2588 case ARM::VLD2DUPd8wb_fixed:
2589 case ARM::VLD2DUPd16wb_fixed:
2590 case ARM::VLD2DUPd32wb_fixed:
2591 case ARM::VLD2DUPd8wb_register:
2592 case ARM::VLD2DUPd16wb_register:
2593 case ARM::VLD2DUPd32wb_register:
2594 case ARM::VLD4DUPd8:
2595 case ARM::VLD4DUPd16:
2596 case ARM::VLD4DUPd32:
2597 case ARM::VLD4DUPd8_UPD:
2598 case ARM::VLD4DUPd16_UPD:
2599 case ARM::VLD4DUPd32_UPD:
2601 case ARM::VLD1LNd16:
2602 case ARM::VLD1LNd32:
2603 case ARM::VLD1LNd8_UPD:
2604 case ARM::VLD1LNd16_UPD:
2605 case ARM::VLD1LNd32_UPD:
2607 case ARM::VLD2LNd16:
2608 case ARM::VLD2LNd32:
2609 case ARM::VLD2LNq16:
2610 case ARM::VLD2LNq32:
2611 case ARM::VLD2LNd8_UPD:
2612 case ARM::VLD2LNd16_UPD:
2613 case ARM::VLD2LNd32_UPD:
2614 case ARM::VLD2LNq16_UPD:
2615 case ARM::VLD2LNq32_UPD:
2617 case ARM::VLD4LNd16:
2618 case ARM::VLD4LNd32:
2619 case ARM::VLD4LNq16:
2620 case ARM::VLD4LNq32:
2621 case ARM::VLD4LNd8_UPD:
2622 case ARM::VLD4LNd16_UPD:
2623 case ARM::VLD4LNd32_UPD:
2624 case ARM::VLD4LNq16_UPD:
2625 case ARM::VLD4LNq32_UPD:
2626 // If the address is not 64-bit aligned, the latencies of these
2627 // instructions increases by one.
2636 ARMBaseInstrInfo::getOperandLatency(const InstrItineraryData *ItinData,
2637 SDNode *DefNode, unsigned DefIdx,
2638 SDNode *UseNode, unsigned UseIdx) const {
2639 if (!DefNode->isMachineOpcode())
2642 const MCInstrDesc &DefMCID = get(DefNode->getMachineOpcode());
2644 if (isZeroCost(DefMCID.Opcode))
2647 if (!ItinData || ItinData->isEmpty())
2648 return DefMCID.mayLoad() ? 3 : 1;
2650 if (!UseNode->isMachineOpcode()) {
2651 int Latency = ItinData->getOperandCycle(DefMCID.getSchedClass(), DefIdx);
2652 if (Subtarget.isCortexA9())
2653 return Latency <= 2 ? 1 : Latency - 1;
2655 return Latency <= 3 ? 1 : Latency - 2;
2658 const MCInstrDesc &UseMCID = get(UseNode->getMachineOpcode());
2659 const MachineSDNode *DefMN = dyn_cast<MachineSDNode>(DefNode);
2660 unsigned DefAlign = !DefMN->memoperands_empty()
2661 ? (*DefMN->memoperands_begin())->getAlignment() : 0;
2662 const MachineSDNode *UseMN = dyn_cast<MachineSDNode>(UseNode);
2663 unsigned UseAlign = !UseMN->memoperands_empty()
2664 ? (*UseMN->memoperands_begin())->getAlignment() : 0;
2665 int Latency = getOperandLatency(ItinData, DefMCID, DefIdx, DefAlign,
2666 UseMCID, UseIdx, UseAlign);
2669 (Subtarget.isCortexA8() || Subtarget.isCortexA9())) {
2670 // FIXME: Shifter op hack: no shift (i.e. [r +/- r]) or [r + r << 2]
2671 // variants are one cycle cheaper.
2672 switch (DefMCID.getOpcode()) {
2677 cast<ConstantSDNode>(DefNode->getOperand(2))->getZExtValue();
2678 unsigned ShImm = ARM_AM::getAM2Offset(ShOpVal);
2680 (ShImm == 2 && ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl))
2687 case ARM::t2LDRSHs: {
2688 // Thumb2 mode: lsl only.
2690 cast<ConstantSDNode>(DefNode->getOperand(2))->getZExtValue();
2691 if (ShAmt == 0 || ShAmt == 2)
2698 if (DefAlign < 8 && Subtarget.isCortexA9())
2699 switch (DefMCID.getOpcode()) {
2705 case ARM::VLD1q8wb_register:
2706 case ARM::VLD1q16wb_register:
2707 case ARM::VLD1q32wb_register:
2708 case ARM::VLD1q64wb_register:
2709 case ARM::VLD1q8wb_fixed:
2710 case ARM::VLD1q16wb_fixed:
2711 case ARM::VLD1q32wb_fixed:
2712 case ARM::VLD1q64wb_fixed:
2716 case ARM::VLD2q8Pseudo:
2717 case ARM::VLD2q16Pseudo:
2718 case ARM::VLD2q32Pseudo:
2719 case ARM::VLD2d8wb_fixed:
2720 case ARM::VLD2d16wb_fixed:
2721 case ARM::VLD2d32wb_fixed:
2722 case ARM::VLD2q8PseudoWB_fixed:
2723 case ARM::VLD2q16PseudoWB_fixed:
2724 case ARM::VLD2q32PseudoWB_fixed:
2725 case ARM::VLD2d8wb_register:
2726 case ARM::VLD2d16wb_register:
2727 case ARM::VLD2d32wb_register:
2728 case ARM::VLD2q8PseudoWB_register:
2729 case ARM::VLD2q16PseudoWB_register:
2730 case ARM::VLD2q32PseudoWB_register:
2731 case ARM::VLD3d8Pseudo:
2732 case ARM::VLD3d16Pseudo:
2733 case ARM::VLD3d32Pseudo:
2734 case ARM::VLD1d64TPseudo:
2735 case ARM::VLD3d8Pseudo_UPD:
2736 case ARM::VLD3d16Pseudo_UPD:
2737 case ARM::VLD3d32Pseudo_UPD:
2738 case ARM::VLD3q8Pseudo_UPD:
2739 case ARM::VLD3q16Pseudo_UPD:
2740 case ARM::VLD3q32Pseudo_UPD:
2741 case ARM::VLD3q8oddPseudo:
2742 case ARM::VLD3q16oddPseudo:
2743 case ARM::VLD3q32oddPseudo:
2744 case ARM::VLD3q8oddPseudo_UPD:
2745 case ARM::VLD3q16oddPseudo_UPD:
2746 case ARM::VLD3q32oddPseudo_UPD:
2747 case ARM::VLD4d8Pseudo:
2748 case ARM::VLD4d16Pseudo:
2749 case ARM::VLD4d32Pseudo:
2750 case ARM::VLD1d64QPseudo:
2751 case ARM::VLD4d8Pseudo_UPD:
2752 case ARM::VLD4d16Pseudo_UPD:
2753 case ARM::VLD4d32Pseudo_UPD:
2754 case ARM::VLD4q8Pseudo_UPD:
2755 case ARM::VLD4q16Pseudo_UPD:
2756 case ARM::VLD4q32Pseudo_UPD:
2757 case ARM::VLD4q8oddPseudo:
2758 case ARM::VLD4q16oddPseudo:
2759 case ARM::VLD4q32oddPseudo:
2760 case ARM::VLD4q8oddPseudo_UPD:
2761 case ARM::VLD4q16oddPseudo_UPD:
2762 case ARM::VLD4q32oddPseudo_UPD:
2763 case ARM::VLD1DUPq8:
2764 case ARM::VLD1DUPq16:
2765 case ARM::VLD1DUPq32:
2766 case ARM::VLD1DUPq8wb_fixed:
2767 case ARM::VLD1DUPq16wb_fixed:
2768 case ARM::VLD1DUPq32wb_fixed:
2769 case ARM::VLD1DUPq8wb_register:
2770 case ARM::VLD1DUPq16wb_register:
2771 case ARM::VLD1DUPq32wb_register:
2772 case ARM::VLD2DUPd8:
2773 case ARM::VLD2DUPd16:
2774 case ARM::VLD2DUPd32:
2775 case ARM::VLD2DUPd8wb_fixed:
2776 case ARM::VLD2DUPd16wb_fixed:
2777 case ARM::VLD2DUPd32wb_fixed:
2778 case ARM::VLD2DUPd8wb_register:
2779 case ARM::VLD2DUPd16wb_register:
2780 case ARM::VLD2DUPd32wb_register:
2781 case ARM::VLD4DUPd8Pseudo:
2782 case ARM::VLD4DUPd16Pseudo:
2783 case ARM::VLD4DUPd32Pseudo:
2784 case ARM::VLD4DUPd8Pseudo_UPD:
2785 case ARM::VLD4DUPd16Pseudo_UPD:
2786 case ARM::VLD4DUPd32Pseudo_UPD:
2787 case ARM::VLD1LNq8Pseudo:
2788 case ARM::VLD1LNq16Pseudo:
2789 case ARM::VLD1LNq32Pseudo:
2790 case ARM::VLD1LNq8Pseudo_UPD:
2791 case ARM::VLD1LNq16Pseudo_UPD:
2792 case ARM::VLD1LNq32Pseudo_UPD:
2793 case ARM::VLD2LNd8Pseudo:
2794 case ARM::VLD2LNd16Pseudo:
2795 case ARM::VLD2LNd32Pseudo:
2796 case ARM::VLD2LNq16Pseudo:
2797 case ARM::VLD2LNq32Pseudo:
2798 case ARM::VLD2LNd8Pseudo_UPD:
2799 case ARM::VLD2LNd16Pseudo_UPD:
2800 case ARM::VLD2LNd32Pseudo_UPD:
2801 case ARM::VLD2LNq16Pseudo_UPD:
2802 case ARM::VLD2LNq32Pseudo_UPD:
2803 case ARM::VLD4LNd8Pseudo:
2804 case ARM::VLD4LNd16Pseudo:
2805 case ARM::VLD4LNd32Pseudo:
2806 case ARM::VLD4LNq16Pseudo:
2807 case ARM::VLD4LNq32Pseudo:
2808 case ARM::VLD4LNd8Pseudo_UPD:
2809 case ARM::VLD4LNd16Pseudo_UPD:
2810 case ARM::VLD4LNd32Pseudo_UPD:
2811 case ARM::VLD4LNq16Pseudo_UPD:
2812 case ARM::VLD4LNq32Pseudo_UPD:
2813 // If the address is not 64-bit aligned, the latencies of these
2814 // instructions increases by one.
2823 ARMBaseInstrInfo::getOutputLatency(const InstrItineraryData *ItinData,
2824 const MachineInstr *DefMI, unsigned DefIdx,
2825 const MachineInstr *DepMI) const {
2826 unsigned Reg = DefMI->getOperand(DefIdx).getReg();
2827 if (DepMI->readsRegister(Reg, &getRegisterInfo()) || !isPredicated(DepMI))
2830 // If the second MI is predicated, then there is an implicit use dependency.
2831 return getOperandLatency(ItinData, DefMI, DefIdx, DepMI,
2832 DepMI->getNumOperands());
2835 int ARMBaseInstrInfo::getInstrLatency(const InstrItineraryData *ItinData,
2836 const MachineInstr *MI,
2837 unsigned *PredCost) const {
2838 if (MI->isCopyLike() || MI->isInsertSubreg() ||
2839 MI->isRegSequence() || MI->isImplicitDef())
2842 if (!ItinData || ItinData->isEmpty())
2845 if (MI->isBundle()) {
2847 MachineBasicBlock::const_instr_iterator I = MI;
2848 MachineBasicBlock::const_instr_iterator E = MI->getParent()->instr_end();
2849 while (++I != E && I->isInsideBundle()) {
2850 if (I->getOpcode() != ARM::t2IT)
2851 Latency += getInstrLatency(ItinData, I, PredCost);
2856 const MCInstrDesc &MCID = MI->getDesc();
2857 unsigned Class = MCID.getSchedClass();
2858 unsigned UOps = ItinData->Itineraries[Class].NumMicroOps;
2859 if (PredCost && (MCID.isCall() || MCID.hasImplicitDefOfPhysReg(ARM::CPSR)))
2860 // When predicated, CPSR is an additional source operand for CPSR updating
2861 // instructions, this apparently increases their latencies.
2864 return ItinData->getStageLatency(Class);
2865 return getNumMicroOps(ItinData, MI);
2868 int ARMBaseInstrInfo::getInstrLatency(const InstrItineraryData *ItinData,
2869 SDNode *Node) const {
2870 if (!Node->isMachineOpcode())
2873 if (!ItinData || ItinData->isEmpty())
2876 unsigned Opcode = Node->getMachineOpcode();
2879 return ItinData->getStageLatency(get(Opcode).getSchedClass());
2886 bool ARMBaseInstrInfo::
2887 hasHighOperandLatency(const InstrItineraryData *ItinData,
2888 const MachineRegisterInfo *MRI,
2889 const MachineInstr *DefMI, unsigned DefIdx,
2890 const MachineInstr *UseMI, unsigned UseIdx) const {
2891 unsigned DDomain = DefMI->getDesc().TSFlags & ARMII::DomainMask;
2892 unsigned UDomain = UseMI->getDesc().TSFlags & ARMII::DomainMask;
2893 if (Subtarget.isCortexA8() &&
2894 (DDomain == ARMII::DomainVFP || UDomain == ARMII::DomainVFP))
2895 // CortexA8 VFP instructions are not pipelined.
2898 // Hoist VFP / NEON instructions with 4 or higher latency.
2899 int Latency = getOperandLatency(ItinData, DefMI, DefIdx, UseMI, UseIdx);
2902 return DDomain == ARMII::DomainVFP || DDomain == ARMII::DomainNEON ||
2903 UDomain == ARMII::DomainVFP || UDomain == ARMII::DomainNEON;
2906 bool ARMBaseInstrInfo::
2907 hasLowDefLatency(const InstrItineraryData *ItinData,
2908 const MachineInstr *DefMI, unsigned DefIdx) const {
2909 if (!ItinData || ItinData->isEmpty())
2912 unsigned DDomain = DefMI->getDesc().TSFlags & ARMII::DomainMask;
2913 if (DDomain == ARMII::DomainGeneral) {
2914 unsigned DefClass = DefMI->getDesc().getSchedClass();
2915 int DefCycle = ItinData->getOperandCycle(DefClass, DefIdx);
2916 return (DefCycle != -1 && DefCycle <= 2);
2921 bool ARMBaseInstrInfo::verifyInstruction(const MachineInstr *MI,
2922 StringRef &ErrInfo) const {
2923 if (convertAddSubFlagsOpcode(MI->getOpcode())) {
2924 ErrInfo = "Pseudo flag setting opcodes only exist in Selection DAG";
2931 ARMBaseInstrInfo::isFpMLxInstruction(unsigned Opcode, unsigned &MulOpc,
2932 unsigned &AddSubOpc,
2933 bool &NegAcc, bool &HasLane) const {
2934 DenseMap<unsigned, unsigned>::const_iterator I = MLxEntryMap.find(Opcode);
2935 if (I == MLxEntryMap.end())
2938 const ARM_MLxEntry &Entry = ARM_MLxTable[I->second];
2939 MulOpc = Entry.MulOpc;
2940 AddSubOpc = Entry.AddSubOpc;
2941 NegAcc = Entry.NegAcc;
2942 HasLane = Entry.HasLane;
2946 //===----------------------------------------------------------------------===//
2947 // Execution domains.
2948 //===----------------------------------------------------------------------===//
2950 // Some instructions go down the NEON pipeline, some go down the VFP pipeline,
2951 // and some can go down both. The vmov instructions go down the VFP pipeline,
2952 // but they can be changed to vorr equivalents that are executed by the NEON
2955 // We use the following execution domain numbering:
2963 // Also see ARMInstrFormats.td and Domain* enums in ARMBaseInfo.h
2965 std::pair<uint16_t, uint16_t>
2966 ARMBaseInstrInfo::getExecutionDomain(const MachineInstr *MI) const {
2967 // VMOVD is a VFP instruction, but can be changed to NEON if it isn't
2969 if (MI->getOpcode() == ARM::VMOVD && !isPredicated(MI))
2970 return std::make_pair(ExeVFP, (1<<ExeVFP) | (1<<ExeNEON));
2972 // No other instructions can be swizzled, so just determine their domain.
2973 unsigned Domain = MI->getDesc().TSFlags & ARMII::DomainMask;
2975 if (Domain & ARMII::DomainNEON)
2976 return std::make_pair(ExeNEON, 0);
2978 // Certain instructions can go either way on Cortex-A8.
2979 // Treat them as NEON instructions.
2980 if ((Domain & ARMII::DomainNEONA8) && Subtarget.isCortexA8())
2981 return std::make_pair(ExeNEON, 0);
2983 if (Domain & ARMII::DomainVFP)
2984 return std::make_pair(ExeVFP, 0);
2986 return std::make_pair(ExeGeneric, 0);
2990 ARMBaseInstrInfo::setExecutionDomain(MachineInstr *MI, unsigned Domain) const {
2991 // We only know how to change VMOVD into VORR.
2992 assert(MI->getOpcode() == ARM::VMOVD && "Can only swizzle VMOVD");
2993 if (Domain != ExeNEON)
2996 // Zap the predicate operands.
2997 assert(!isPredicated(MI) && "Cannot predicate a VORRd");
2998 MI->RemoveOperand(3);
2999 MI->RemoveOperand(2);
3001 // Change to a VORRd which requires two identical use operands.
3002 MI->setDesc(get(ARM::VORRd));
3004 // Add the extra source operand and new predicates.
3005 // This will go before any implicit ops.
3006 AddDefaultPred(MachineInstrBuilder(MI).addOperand(MI->getOperand(1)));
3009 bool ARMBaseInstrInfo::hasNOP() const {
3010 return (Subtarget.getFeatureBits() & ARM::HasV6T2Ops) != 0;