1 //===- ARMBaseInstrInfo.cpp - ARM Instruction Information -------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Base ARM implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "ARMBaseInstrInfo.h"
16 #include "ARMAddressingModes.h"
17 #include "ARMConstantPoolValue.h"
18 #include "ARMMachineFunctionInfo.h"
19 #include "ARMRegisterInfo.h"
20 #include "ARMGenInstrInfo.inc"
21 #include "llvm/Constants.h"
22 #include "llvm/Function.h"
23 #include "llvm/GlobalValue.h"
24 #include "llvm/ADT/STLExtras.h"
25 #include "llvm/CodeGen/LiveVariables.h"
26 #include "llvm/CodeGen/MachineConstantPool.h"
27 #include "llvm/CodeGen/MachineFrameInfo.h"
28 #include "llvm/CodeGen/MachineInstrBuilder.h"
29 #include "llvm/CodeGen/MachineJumpTableInfo.h"
30 #include "llvm/CodeGen/MachineMemOperand.h"
31 #include "llvm/CodeGen/MachineRegisterInfo.h"
32 #include "llvm/CodeGen/PseudoSourceValue.h"
33 #include "llvm/MC/MCAsmInfo.h"
34 #include "llvm/Support/CommandLine.h"
35 #include "llvm/Support/Debug.h"
36 #include "llvm/Support/ErrorHandling.h"
40 EnableARM3Addr("enable-arm-3-addr-conv", cl::Hidden,
41 cl::desc("Enable ARM 2-addr to 3-addr conv"));
43 ARMBaseInstrInfo::ARMBaseInstrInfo(const ARMSubtarget& STI)
44 : TargetInstrInfoImpl(ARMInsts, array_lengthof(ARMInsts)),
49 ARMBaseInstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
50 MachineBasicBlock::iterator &MBBI,
51 LiveVariables *LV) const {
52 // FIXME: Thumb2 support.
57 MachineInstr *MI = MBBI;
58 MachineFunction &MF = *MI->getParent()->getParent();
59 uint64_t TSFlags = MI->getDesc().TSFlags;
61 switch ((TSFlags & ARMII::IndexModeMask) >> ARMII::IndexModeShift) {
63 case ARMII::IndexModePre:
66 case ARMII::IndexModePost:
70 // Try splitting an indexed load/store to an un-indexed one plus an add/sub
72 unsigned MemOpc = getUnindexedOpcode(MI->getOpcode());
76 MachineInstr *UpdateMI = NULL;
77 MachineInstr *MemMI = NULL;
78 unsigned AddrMode = (TSFlags & ARMII::AddrModeMask);
79 const TargetInstrDesc &TID = MI->getDesc();
80 unsigned NumOps = TID.getNumOperands();
81 bool isLoad = !TID.mayStore();
82 const MachineOperand &WB = isLoad ? MI->getOperand(1) : MI->getOperand(0);
83 const MachineOperand &Base = MI->getOperand(2);
84 const MachineOperand &Offset = MI->getOperand(NumOps-3);
85 unsigned WBReg = WB.getReg();
86 unsigned BaseReg = Base.getReg();
87 unsigned OffReg = Offset.getReg();
88 unsigned OffImm = MI->getOperand(NumOps-2).getImm();
89 ARMCC::CondCodes Pred = (ARMCC::CondCodes)MI->getOperand(NumOps-1).getImm();
92 assert(false && "Unknown indexed op!");
94 case ARMII::AddrMode2: {
95 bool isSub = ARM_AM::getAM2Op(OffImm) == ARM_AM::sub;
96 unsigned Amt = ARM_AM::getAM2Offset(OffImm);
98 if (ARM_AM::getSOImmVal(Amt) == -1)
99 // Can't encode it in a so_imm operand. This transformation will
100 // add more than 1 instruction. Abandon!
102 UpdateMI = BuildMI(MF, MI->getDebugLoc(),
103 get(isSub ? ARM::SUBri : ARM::ADDri), WBReg)
104 .addReg(BaseReg).addImm(Amt)
105 .addImm(Pred).addReg(0).addReg(0);
106 } else if (Amt != 0) {
107 ARM_AM::ShiftOpc ShOpc = ARM_AM::getAM2ShiftOpc(OffImm);
108 unsigned SOOpc = ARM_AM::getSORegOpc(ShOpc, Amt);
109 UpdateMI = BuildMI(MF, MI->getDebugLoc(),
110 get(isSub ? ARM::SUBrs : ARM::ADDrs), WBReg)
111 .addReg(BaseReg).addReg(OffReg).addReg(0).addImm(SOOpc)
112 .addImm(Pred).addReg(0).addReg(0);
114 UpdateMI = BuildMI(MF, MI->getDebugLoc(),
115 get(isSub ? ARM::SUBrr : ARM::ADDrr), WBReg)
116 .addReg(BaseReg).addReg(OffReg)
117 .addImm(Pred).addReg(0).addReg(0);
120 case ARMII::AddrMode3 : {
121 bool isSub = ARM_AM::getAM3Op(OffImm) == ARM_AM::sub;
122 unsigned Amt = ARM_AM::getAM3Offset(OffImm);
124 // Immediate is 8-bits. It's guaranteed to fit in a so_imm operand.
125 UpdateMI = BuildMI(MF, MI->getDebugLoc(),
126 get(isSub ? ARM::SUBri : ARM::ADDri), WBReg)
127 .addReg(BaseReg).addImm(Amt)
128 .addImm(Pred).addReg(0).addReg(0);
130 UpdateMI = BuildMI(MF, MI->getDebugLoc(),
131 get(isSub ? ARM::SUBrr : ARM::ADDrr), WBReg)
132 .addReg(BaseReg).addReg(OffReg)
133 .addImm(Pred).addReg(0).addReg(0);
138 std::vector<MachineInstr*> NewMIs;
141 MemMI = BuildMI(MF, MI->getDebugLoc(),
142 get(MemOpc), MI->getOperand(0).getReg())
143 .addReg(WBReg).addReg(0).addImm(0).addImm(Pred);
145 MemMI = BuildMI(MF, MI->getDebugLoc(),
146 get(MemOpc)).addReg(MI->getOperand(1).getReg())
147 .addReg(WBReg).addReg(0).addImm(0).addImm(Pred);
148 NewMIs.push_back(MemMI);
149 NewMIs.push_back(UpdateMI);
152 MemMI = BuildMI(MF, MI->getDebugLoc(),
153 get(MemOpc), MI->getOperand(0).getReg())
154 .addReg(BaseReg).addReg(0).addImm(0).addImm(Pred);
156 MemMI = BuildMI(MF, MI->getDebugLoc(),
157 get(MemOpc)).addReg(MI->getOperand(1).getReg())
158 .addReg(BaseReg).addReg(0).addImm(0).addImm(Pred);
160 UpdateMI->getOperand(0).setIsDead();
161 NewMIs.push_back(UpdateMI);
162 NewMIs.push_back(MemMI);
165 // Transfer LiveVariables states, kill / dead info.
167 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
168 MachineOperand &MO = MI->getOperand(i);
169 if (MO.isReg() && MO.getReg() &&
170 TargetRegisterInfo::isVirtualRegister(MO.getReg())) {
171 unsigned Reg = MO.getReg();
173 LiveVariables::VarInfo &VI = LV->getVarInfo(Reg);
175 MachineInstr *NewMI = (Reg == WBReg) ? UpdateMI : MemMI;
177 LV->addVirtualRegisterDead(Reg, NewMI);
179 if (MO.isUse() && MO.isKill()) {
180 for (unsigned j = 0; j < 2; ++j) {
181 // Look at the two new MI's in reverse order.
182 MachineInstr *NewMI = NewMIs[j];
183 if (!NewMI->readsRegister(Reg))
185 LV->addVirtualRegisterKilled(Reg, NewMI);
186 if (VI.removeKill(MI))
187 VI.Kills.push_back(NewMI);
195 MFI->insert(MBBI, NewMIs[1]);
196 MFI->insert(MBBI, NewMIs[0]);
201 ARMBaseInstrInfo::spillCalleeSavedRegisters(MachineBasicBlock &MBB,
202 MachineBasicBlock::iterator MI,
203 const std::vector<CalleeSavedInfo> &CSI,
204 const TargetRegisterInfo *TRI) const {
209 if (MI != MBB.end()) DL = MI->getDebugLoc();
211 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
212 unsigned Reg = CSI[i].getReg();
215 // Add the callee-saved register as live-in unless it's LR and
216 // @llvm.returnaddress is called. If LR is returned for @llvm.returnaddress
217 // then it's already added to the function and entry block live-in sets.
218 if (Reg == ARM::LR) {
219 MachineFunction &MF = *MBB.getParent();
220 if (MF.getFrameInfo()->isReturnAddressTaken() &&
221 MF.getRegInfo().isLiveIn(Reg))
228 // Insert the spill to the stack frame. The register is killed at the spill
230 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
231 storeRegToStackSlot(MBB, MI, Reg, isKill,
232 CSI[i].getFrameIdx(), RC, TRI);
239 ARMBaseInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB,
240 MachineBasicBlock *&FBB,
241 SmallVectorImpl<MachineOperand> &Cond,
242 bool AllowModify) const {
243 // If the block has no terminators, it just falls into the block after it.
244 MachineBasicBlock::iterator I = MBB.end();
245 if (I == MBB.begin())
248 while (I->isDebugValue()) {
249 if (I == MBB.begin())
253 if (!isUnpredicatedTerminator(I))
256 // Get the last instruction in the block.
257 MachineInstr *LastInst = I;
259 // If there is only one terminator instruction, process it.
260 unsigned LastOpc = LastInst->getOpcode();
261 if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) {
262 if (isUncondBranchOpcode(LastOpc)) {
263 TBB = LastInst->getOperand(0).getMBB();
266 if (isCondBranchOpcode(LastOpc)) {
267 // Block ends with fall-through condbranch.
268 TBB = LastInst->getOperand(0).getMBB();
269 Cond.push_back(LastInst->getOperand(1));
270 Cond.push_back(LastInst->getOperand(2));
273 return true; // Can't handle indirect branch.
276 // Get the instruction before it if it is a terminator.
277 MachineInstr *SecondLastInst = I;
278 unsigned SecondLastOpc = SecondLastInst->getOpcode();
280 // If AllowModify is true and the block ends with two or more unconditional
281 // branches, delete all but the first unconditional branch.
282 if (AllowModify && isUncondBranchOpcode(LastOpc)) {
283 while (isUncondBranchOpcode(SecondLastOpc)) {
284 LastInst->eraseFromParent();
285 LastInst = SecondLastInst;
286 LastOpc = LastInst->getOpcode();
287 if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) {
288 // Return now the only terminator is an unconditional branch.
289 TBB = LastInst->getOperand(0).getMBB();
293 SecondLastOpc = SecondLastInst->getOpcode();
298 // If there are three terminators, we don't know what sort of block this is.
299 if (SecondLastInst && I != MBB.begin() && isUnpredicatedTerminator(--I))
302 // If the block ends with a B and a Bcc, handle it.
303 if (isCondBranchOpcode(SecondLastOpc) && isUncondBranchOpcode(LastOpc)) {
304 TBB = SecondLastInst->getOperand(0).getMBB();
305 Cond.push_back(SecondLastInst->getOperand(1));
306 Cond.push_back(SecondLastInst->getOperand(2));
307 FBB = LastInst->getOperand(0).getMBB();
311 // If the block ends with two unconditional branches, handle it. The second
312 // one is not executed, so remove it.
313 if (isUncondBranchOpcode(SecondLastOpc) && isUncondBranchOpcode(LastOpc)) {
314 TBB = SecondLastInst->getOperand(0).getMBB();
317 I->eraseFromParent();
321 // ...likewise if it ends with a branch table followed by an unconditional
322 // branch. The branch folder can create these, and we must get rid of them for
323 // correctness of Thumb constant islands.
324 if ((isJumpTableBranchOpcode(SecondLastOpc) ||
325 isIndirectBranchOpcode(SecondLastOpc)) &&
326 isUncondBranchOpcode(LastOpc)) {
329 I->eraseFromParent();
333 // Otherwise, can't handle this.
338 unsigned ARMBaseInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
339 MachineBasicBlock::iterator I = MBB.end();
340 if (I == MBB.begin()) return 0;
342 while (I->isDebugValue()) {
343 if (I == MBB.begin())
347 if (!isUncondBranchOpcode(I->getOpcode()) &&
348 !isCondBranchOpcode(I->getOpcode()))
351 // Remove the branch.
352 I->eraseFromParent();
356 if (I == MBB.begin()) return 1;
358 if (!isCondBranchOpcode(I->getOpcode()))
361 // Remove the branch.
362 I->eraseFromParent();
367 ARMBaseInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
368 MachineBasicBlock *FBB,
369 const SmallVectorImpl<MachineOperand> &Cond,
371 ARMFunctionInfo *AFI = MBB.getParent()->getInfo<ARMFunctionInfo>();
372 int BOpc = !AFI->isThumbFunction()
373 ? ARM::B : (AFI->isThumb2Function() ? ARM::t2B : ARM::tB);
374 int BccOpc = !AFI->isThumbFunction()
375 ? ARM::Bcc : (AFI->isThumb2Function() ? ARM::t2Bcc : ARM::tBcc);
377 // Shouldn't be a fall through.
378 assert(TBB && "InsertBranch must not be told to insert a fallthrough");
379 assert((Cond.size() == 2 || Cond.size() == 0) &&
380 "ARM branch conditions have two components!");
383 if (Cond.empty()) // Unconditional branch?
384 BuildMI(&MBB, DL, get(BOpc)).addMBB(TBB);
386 BuildMI(&MBB, DL, get(BccOpc)).addMBB(TBB)
387 .addImm(Cond[0].getImm()).addReg(Cond[1].getReg());
391 // Two-way conditional branch.
392 BuildMI(&MBB, DL, get(BccOpc)).addMBB(TBB)
393 .addImm(Cond[0].getImm()).addReg(Cond[1].getReg());
394 BuildMI(&MBB, DL, get(BOpc)).addMBB(FBB);
398 bool ARMBaseInstrInfo::
399 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
400 ARMCC::CondCodes CC = (ARMCC::CondCodes)(int)Cond[0].getImm();
401 Cond[0].setImm(ARMCC::getOppositeCondition(CC));
405 bool ARMBaseInstrInfo::
406 PredicateInstruction(MachineInstr *MI,
407 const SmallVectorImpl<MachineOperand> &Pred) const {
408 unsigned Opc = MI->getOpcode();
409 if (isUncondBranchOpcode(Opc)) {
410 MI->setDesc(get(getMatchingCondBranchOpcode(Opc)));
411 MI->addOperand(MachineOperand::CreateImm(Pred[0].getImm()));
412 MI->addOperand(MachineOperand::CreateReg(Pred[1].getReg(), false));
416 int PIdx = MI->findFirstPredOperandIdx();
418 MachineOperand &PMO = MI->getOperand(PIdx);
419 PMO.setImm(Pred[0].getImm());
420 MI->getOperand(PIdx+1).setReg(Pred[1].getReg());
426 bool ARMBaseInstrInfo::
427 SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1,
428 const SmallVectorImpl<MachineOperand> &Pred2) const {
429 if (Pred1.size() > 2 || Pred2.size() > 2)
432 ARMCC::CondCodes CC1 = (ARMCC::CondCodes)Pred1[0].getImm();
433 ARMCC::CondCodes CC2 = (ARMCC::CondCodes)Pred2[0].getImm();
443 return CC2 == ARMCC::HI;
445 return CC2 == ARMCC::LO || CC2 == ARMCC::EQ;
447 return CC2 == ARMCC::GT;
449 return CC2 == ARMCC::LT;
453 bool ARMBaseInstrInfo::DefinesPredicate(MachineInstr *MI,
454 std::vector<MachineOperand> &Pred) const {
455 // FIXME: This confuses implicit_def with optional CPSR def.
456 const TargetInstrDesc &TID = MI->getDesc();
457 if (!TID.getImplicitDefs() && !TID.hasOptionalDef())
461 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
462 const MachineOperand &MO = MI->getOperand(i);
463 if (MO.isReg() && MO.getReg() == ARM::CPSR) {
472 /// isPredicable - Return true if the specified instruction can be predicated.
473 /// By default, this returns true for every instruction with a
474 /// PredicateOperand.
475 bool ARMBaseInstrInfo::isPredicable(MachineInstr *MI) const {
476 const TargetInstrDesc &TID = MI->getDesc();
477 if (!TID.isPredicable())
480 if ((TID.TSFlags & ARMII::DomainMask) == ARMII::DomainNEON) {
481 ARMFunctionInfo *AFI =
482 MI->getParent()->getParent()->getInfo<ARMFunctionInfo>();
483 return AFI->isThumb2Function();
488 /// FIXME: Works around a gcc miscompilation with -fstrict-aliasing.
490 static unsigned getNumJTEntries(const std::vector<MachineJumpTableEntry> &JT,
492 static unsigned getNumJTEntries(const std::vector<MachineJumpTableEntry> &JT,
494 assert(JTI < JT.size());
495 return JT[JTI].MBBs.size();
498 /// GetInstSize - Return the size of the specified MachineInstr.
500 unsigned ARMBaseInstrInfo::GetInstSizeInBytes(const MachineInstr *MI) const {
501 const MachineBasicBlock &MBB = *MI->getParent();
502 const MachineFunction *MF = MBB.getParent();
503 const MCAsmInfo *MAI = MF->getTarget().getMCAsmInfo();
505 // Basic size info comes from the TSFlags field.
506 const TargetInstrDesc &TID = MI->getDesc();
507 uint64_t TSFlags = TID.TSFlags;
509 unsigned Opc = MI->getOpcode();
510 switch ((TSFlags & ARMII::SizeMask) >> ARMII::SizeShift) {
512 // If this machine instr is an inline asm, measure it.
513 if (MI->getOpcode() == ARM::INLINEASM)
514 return getInlineAsmLength(MI->getOperand(0).getSymbolName(), *MAI);
519 llvm_unreachable("Unknown or unset size field for instr!");
520 case TargetOpcode::IMPLICIT_DEF:
521 case TargetOpcode::KILL:
522 case TargetOpcode::PROLOG_LABEL:
523 case TargetOpcode::EH_LABEL:
524 case TargetOpcode::DBG_VALUE:
529 case ARMII::Size8Bytes: return 8; // ARM instruction x 2.
530 case ARMII::Size4Bytes: return 4; // ARM / Thumb2 instruction.
531 case ARMII::Size2Bytes: return 2; // Thumb1 instruction.
532 case ARMII::SizeSpecial: {
534 case ARM::CONSTPOOL_ENTRY:
535 // If this machine instr is a constant pool entry, its size is recorded as
537 return MI->getOperand(2).getImm();
538 case ARM::Int_eh_sjlj_longjmp:
540 case ARM::tInt_eh_sjlj_longjmp:
542 case ARM::Int_eh_sjlj_setjmp:
543 case ARM::Int_eh_sjlj_setjmp_nofp:
545 case ARM::tInt_eh_sjlj_setjmp:
546 case ARM::t2Int_eh_sjlj_setjmp:
547 case ARM::t2Int_eh_sjlj_setjmp_nofp:
556 // These are jumptable branches, i.e. a branch followed by an inlined
557 // jumptable. The size is 4 + 4 * number of entries. For TBB, each
558 // entry is one byte; TBH two byte each.
559 unsigned EntrySize = (Opc == ARM::t2TBB)
560 ? 1 : ((Opc == ARM::t2TBH) ? 2 : 4);
561 unsigned NumOps = TID.getNumOperands();
562 MachineOperand JTOP =
563 MI->getOperand(NumOps - (TID.isPredicable() ? 3 : 2));
564 unsigned JTI = JTOP.getIndex();
565 const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
567 const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
568 assert(JTI < JT.size());
569 // Thumb instructions are 2 byte aligned, but JT entries are 4 byte
570 // 4 aligned. The assembler / linker may add 2 byte padding just before
571 // the JT entries. The size does not include this padding; the
572 // constant islands pass does separate bookkeeping for it.
573 // FIXME: If we know the size of the function is less than (1 << 16) *2
574 // bytes, we can use 16-bit entries instead. Then there won't be an
576 unsigned InstSize = (Opc == ARM::tBR_JTr || Opc == ARM::t2BR_JT) ? 2 : 4;
577 unsigned NumEntries = getNumJTEntries(JT, JTI);
578 if (Opc == ARM::t2TBB && (NumEntries & 1))
579 // Make sure the instruction that follows TBB is 2-byte aligned.
580 // FIXME: Constant island pass should insert an "ALIGN" instruction
583 return NumEntries * EntrySize + InstSize;
586 // Otherwise, pseudo-instruction sizes are zero.
591 return 0; // Not reached
594 void ARMBaseInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
595 MachineBasicBlock::iterator I, DebugLoc DL,
596 unsigned DestReg, unsigned SrcReg,
597 bool KillSrc) const {
598 bool GPRDest = ARM::GPRRegClass.contains(DestReg);
599 bool GPRSrc = ARM::GPRRegClass.contains(SrcReg);
601 if (GPRDest && GPRSrc) {
602 AddDefaultCC(AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::MOVr), DestReg)
603 .addReg(SrcReg, getKillRegState(KillSrc))));
607 bool SPRDest = ARM::SPRRegClass.contains(DestReg);
608 bool SPRSrc = ARM::SPRRegClass.contains(SrcReg);
611 if (SPRDest && SPRSrc)
613 else if (GPRDest && SPRSrc)
615 else if (SPRDest && GPRSrc)
617 else if (ARM::DPRRegClass.contains(DestReg, SrcReg))
619 else if (ARM::QPRRegClass.contains(DestReg, SrcReg))
621 else if (ARM::QQPRRegClass.contains(DestReg, SrcReg))
623 else if (ARM::QQQQPRRegClass.contains(DestReg, SrcReg))
626 llvm_unreachable("Impossible reg-to-reg copy");
628 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(Opc), DestReg);
629 MIB.addReg(SrcReg, getKillRegState(KillSrc));
630 if (Opc != ARM::VMOVQQ && Opc != ARM::VMOVQQQQ)
635 MachineInstrBuilder &AddDReg(MachineInstrBuilder &MIB,
636 unsigned Reg, unsigned SubIdx, unsigned State,
637 const TargetRegisterInfo *TRI) {
639 return MIB.addReg(Reg, State);
641 if (TargetRegisterInfo::isPhysicalRegister(Reg))
642 return MIB.addReg(TRI->getSubReg(Reg, SubIdx), State);
643 return MIB.addReg(Reg, State, SubIdx);
646 void ARMBaseInstrInfo::
647 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
648 unsigned SrcReg, bool isKill, int FI,
649 const TargetRegisterClass *RC,
650 const TargetRegisterInfo *TRI) const {
652 if (I != MBB.end()) DL = I->getDebugLoc();
653 MachineFunction &MF = *MBB.getParent();
654 MachineFrameInfo &MFI = *MF.getFrameInfo();
655 unsigned Align = MFI.getObjectAlignment(FI);
657 MachineMemOperand *MMO =
658 MF.getMachineMemOperand(MachinePointerInfo(
659 PseudoSourceValue::getFixedStack(FI)),
660 MachineMemOperand::MOStore,
661 MFI.getObjectSize(FI),
664 // tGPR is used sometimes in ARM instructions that need to avoid using
665 // certain registers. Just treat it as GPR here. Likewise, rGPR.
666 if (RC == ARM::tGPRRegisterClass || RC == ARM::tcGPRRegisterClass
667 || RC == ARM::rGPRRegisterClass)
668 RC = ARM::GPRRegisterClass;
670 switch (RC->getID()) {
671 case ARM::GPRRegClassID:
672 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::STR))
673 .addReg(SrcReg, getKillRegState(isKill))
674 .addFrameIndex(FI).addReg(0).addImm(0).addMemOperand(MMO));
676 case ARM::SPRRegClassID:
677 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTRS))
678 .addReg(SrcReg, getKillRegState(isKill))
679 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
681 case ARM::DPRRegClassID:
682 case ARM::DPR_VFP2RegClassID:
683 case ARM::DPR_8RegClassID:
684 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTRD))
685 .addReg(SrcReg, getKillRegState(isKill))
686 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
688 case ARM::QPRRegClassID:
689 case ARM::QPR_VFP2RegClassID:
690 case ARM::QPR_8RegClassID:
691 if (Align >= 16 && getRegisterInfo().needsStackRealignment(MF)) {
692 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VST1q64Pseudo))
693 .addFrameIndex(FI).addImm(16)
694 .addReg(SrcReg, getKillRegState(isKill))
695 .addMemOperand(MMO));
697 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTMQ))
698 .addReg(SrcReg, getKillRegState(isKill))
700 .addImm(ARM_AM::getAM4ModeImm(ARM_AM::ia))
701 .addMemOperand(MMO));
704 case ARM::QQPRRegClassID:
705 case ARM::QQPR_VFP2RegClassID:
706 if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) {
707 // FIXME: It's possible to only store part of the QQ register if the
708 // spilled def has a sub-register index.
709 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VST1d64QPseudo))
710 .addFrameIndex(FI).addImm(16)
711 .addReg(SrcReg, getKillRegState(isKill))
712 .addMemOperand(MMO));
714 MachineInstrBuilder MIB =
715 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTMD))
717 .addImm(ARM_AM::getAM4ModeImm(ARM_AM::ia)))
719 MIB = AddDReg(MIB, SrcReg, ARM::dsub_0, getKillRegState(isKill), TRI);
720 MIB = AddDReg(MIB, SrcReg, ARM::dsub_1, 0, TRI);
721 MIB = AddDReg(MIB, SrcReg, ARM::dsub_2, 0, TRI);
722 AddDReg(MIB, SrcReg, ARM::dsub_3, 0, TRI);
725 case ARM::QQQQPRRegClassID: {
726 MachineInstrBuilder MIB =
727 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTMD))
729 .addImm(ARM_AM::getAM4ModeImm(ARM_AM::ia)))
731 MIB = AddDReg(MIB, SrcReg, ARM::dsub_0, getKillRegState(isKill), TRI);
732 MIB = AddDReg(MIB, SrcReg, ARM::dsub_1, 0, TRI);
733 MIB = AddDReg(MIB, SrcReg, ARM::dsub_2, 0, TRI);
734 MIB = AddDReg(MIB, SrcReg, ARM::dsub_3, 0, TRI);
735 MIB = AddDReg(MIB, SrcReg, ARM::dsub_4, 0, TRI);
736 MIB = AddDReg(MIB, SrcReg, ARM::dsub_5, 0, TRI);
737 MIB = AddDReg(MIB, SrcReg, ARM::dsub_6, 0, TRI);
738 AddDReg(MIB, SrcReg, ARM::dsub_7, 0, TRI);
742 llvm_unreachable("Unknown regclass!");
747 ARMBaseInstrInfo::isStoreToStackSlot(const MachineInstr *MI,
748 int &FrameIndex) const {
749 switch (MI->getOpcode()) {
752 case ARM::t2STRs: // FIXME: don't use t2STRs to access frame.
753 if (MI->getOperand(1).isFI() &&
754 MI->getOperand(2).isReg() &&
755 MI->getOperand(3).isImm() &&
756 MI->getOperand(2).getReg() == 0 &&
757 MI->getOperand(3).getImm() == 0) {
758 FrameIndex = MI->getOperand(1).getIndex();
759 return MI->getOperand(0).getReg();
766 if (MI->getOperand(1).isFI() &&
767 MI->getOperand(2).isImm() &&
768 MI->getOperand(2).getImm() == 0) {
769 FrameIndex = MI->getOperand(1).getIndex();
770 return MI->getOperand(0).getReg();
773 case ARM::VST1q64Pseudo:
774 if (MI->getOperand(0).isFI() &&
775 MI->getOperand(2).getSubReg() == 0) {
776 FrameIndex = MI->getOperand(0).getIndex();
777 return MI->getOperand(2).getReg();
781 if (MI->getOperand(1).isFI() &&
782 MI->getOperand(2).isImm() &&
783 MI->getOperand(2).getImm() == ARM_AM::getAM4ModeImm(ARM_AM::ia) &&
784 MI->getOperand(0).getSubReg() == 0) {
785 FrameIndex = MI->getOperand(1).getIndex();
786 return MI->getOperand(0).getReg();
794 void ARMBaseInstrInfo::
795 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
796 unsigned DestReg, int FI,
797 const TargetRegisterClass *RC,
798 const TargetRegisterInfo *TRI) const {
800 if (I != MBB.end()) DL = I->getDebugLoc();
801 MachineFunction &MF = *MBB.getParent();
802 MachineFrameInfo &MFI = *MF.getFrameInfo();
803 unsigned Align = MFI.getObjectAlignment(FI);
804 MachineMemOperand *MMO =
805 MF.getMachineMemOperand(
806 MachinePointerInfo(PseudoSourceValue::getFixedStack(FI)),
807 MachineMemOperand::MOLoad,
808 MFI.getObjectSize(FI),
811 // tGPR is used sometimes in ARM instructions that need to avoid using
812 // certain registers. Just treat it as GPR here.
813 if (RC == ARM::tGPRRegisterClass || RC == ARM::tcGPRRegisterClass
814 || RC == ARM::rGPRRegisterClass)
815 RC = ARM::GPRRegisterClass;
817 switch (RC->getID()) {
818 case ARM::GPRRegClassID:
819 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::LDR), DestReg)
820 .addFrameIndex(FI).addReg(0).addImm(0).addMemOperand(MMO));
822 case ARM::SPRRegClassID:
823 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDRS), DestReg)
824 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
826 case ARM::DPRRegClassID:
827 case ARM::DPR_VFP2RegClassID:
828 case ARM::DPR_8RegClassID:
829 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDRD), DestReg)
830 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
832 case ARM::QPRRegClassID:
833 case ARM::QPR_VFP2RegClassID:
834 case ARM::QPR_8RegClassID:
835 if (Align >= 16 && getRegisterInfo().needsStackRealignment(MF)) {
836 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLD1q64Pseudo), DestReg)
837 .addFrameIndex(FI).addImm(16)
838 .addMemOperand(MMO));
840 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDMQ), DestReg)
842 .addImm(ARM_AM::getAM4ModeImm(ARM_AM::ia))
843 .addMemOperand(MMO));
846 case ARM::QQPRRegClassID:
847 case ARM::QQPR_VFP2RegClassID:
848 if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) {
849 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLD1d64QPseudo), DestReg)
850 .addFrameIndex(FI).addImm(16)
851 .addMemOperand(MMO));
853 MachineInstrBuilder MIB =
854 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDMD))
856 .addImm(ARM_AM::getAM4ModeImm(ARM_AM::ia)))
858 MIB = AddDReg(MIB, DestReg, ARM::dsub_0, RegState::Define, TRI);
859 MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::Define, TRI);
860 MIB = AddDReg(MIB, DestReg, ARM::dsub_2, RegState::Define, TRI);
861 AddDReg(MIB, DestReg, ARM::dsub_3, RegState::Define, TRI);
864 case ARM::QQQQPRRegClassID: {
865 MachineInstrBuilder MIB =
866 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDMD))
868 .addImm(ARM_AM::getAM4ModeImm(ARM_AM::ia)))
870 MIB = AddDReg(MIB, DestReg, ARM::dsub_0, RegState::Define, TRI);
871 MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::Define, TRI);
872 MIB = AddDReg(MIB, DestReg, ARM::dsub_2, RegState::Define, TRI);
873 MIB = AddDReg(MIB, DestReg, ARM::dsub_3, RegState::Define, TRI);
874 MIB = AddDReg(MIB, DestReg, ARM::dsub_4, RegState::Define, TRI);
875 MIB = AddDReg(MIB, DestReg, ARM::dsub_5, RegState::Define, TRI);
876 MIB = AddDReg(MIB, DestReg, ARM::dsub_6, RegState::Define, TRI);
877 AddDReg(MIB, DestReg, ARM::dsub_7, RegState::Define, TRI);
881 llvm_unreachable("Unknown regclass!");
886 ARMBaseInstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
887 int &FrameIndex) const {
888 switch (MI->getOpcode()) {
891 case ARM::t2LDRs: // FIXME: don't use t2LDRs to access frame.
892 if (MI->getOperand(1).isFI() &&
893 MI->getOperand(2).isReg() &&
894 MI->getOperand(3).isImm() &&
895 MI->getOperand(2).getReg() == 0 &&
896 MI->getOperand(3).getImm() == 0) {
897 FrameIndex = MI->getOperand(1).getIndex();
898 return MI->getOperand(0).getReg();
905 if (MI->getOperand(1).isFI() &&
906 MI->getOperand(2).isImm() &&
907 MI->getOperand(2).getImm() == 0) {
908 FrameIndex = MI->getOperand(1).getIndex();
909 return MI->getOperand(0).getReg();
912 case ARM::VLD1q64Pseudo:
913 if (MI->getOperand(1).isFI() &&
914 MI->getOperand(0).getSubReg() == 0) {
915 FrameIndex = MI->getOperand(1).getIndex();
916 return MI->getOperand(0).getReg();
920 if (MI->getOperand(1).isFI() &&
921 MI->getOperand(2).isImm() &&
922 MI->getOperand(2).getImm() == ARM_AM::getAM4ModeImm(ARM_AM::ia) &&
923 MI->getOperand(0).getSubReg() == 0) {
924 FrameIndex = MI->getOperand(1).getIndex();
925 return MI->getOperand(0).getReg();
934 ARMBaseInstrInfo::emitFrameIndexDebugValue(MachineFunction &MF,
935 int FrameIx, uint64_t Offset,
938 MachineInstrBuilder MIB = BuildMI(MF, DL, get(ARM::DBG_VALUE))
939 .addFrameIndex(FrameIx).addImm(0).addImm(Offset).addMetadata(MDPtr);
943 /// Create a copy of a const pool value. Update CPI to the new index and return
945 static unsigned duplicateCPV(MachineFunction &MF, unsigned &CPI) {
946 MachineConstantPool *MCP = MF.getConstantPool();
947 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
949 const MachineConstantPoolEntry &MCPE = MCP->getConstants()[CPI];
950 assert(MCPE.isMachineConstantPoolEntry() &&
951 "Expecting a machine constantpool entry!");
952 ARMConstantPoolValue *ACPV =
953 static_cast<ARMConstantPoolValue*>(MCPE.Val.MachineCPVal);
955 unsigned PCLabelId = AFI->createConstPoolEntryUId();
956 ARMConstantPoolValue *NewCPV = 0;
957 // FIXME: The below assumes PIC relocation model and that the function
958 // is Thumb mode (t1 or t2). PCAdjustment would be 8 for ARM mode PIC, and
959 // zero for non-PIC in ARM or Thumb. The callers are all of thumb LDR
960 // instructions, so that's probably OK, but is PIC always correct when
962 if (ACPV->isGlobalValue())
963 NewCPV = new ARMConstantPoolValue(ACPV->getGV(), PCLabelId,
965 else if (ACPV->isExtSymbol())
966 NewCPV = new ARMConstantPoolValue(MF.getFunction()->getContext(),
967 ACPV->getSymbol(), PCLabelId, 4);
968 else if (ACPV->isBlockAddress())
969 NewCPV = new ARMConstantPoolValue(ACPV->getBlockAddress(), PCLabelId,
970 ARMCP::CPBlockAddress, 4);
971 else if (ACPV->isLSDA())
972 NewCPV = new ARMConstantPoolValue(MF.getFunction(), PCLabelId,
975 llvm_unreachable("Unexpected ARM constantpool value type!!");
976 CPI = MCP->getConstantPoolIndex(NewCPV, MCPE.getAlignment());
980 void ARMBaseInstrInfo::
981 reMaterialize(MachineBasicBlock &MBB,
982 MachineBasicBlock::iterator I,
983 unsigned DestReg, unsigned SubIdx,
984 const MachineInstr *Orig,
985 const TargetRegisterInfo &TRI) const {
986 unsigned Opcode = Orig->getOpcode();
989 MachineInstr *MI = MBB.getParent()->CloneMachineInstr(Orig);
990 MI->substituteRegister(Orig->getOperand(0).getReg(), DestReg, SubIdx, TRI);
994 case ARM::tLDRpci_pic:
995 case ARM::t2LDRpci_pic: {
996 MachineFunction &MF = *MBB.getParent();
997 unsigned CPI = Orig->getOperand(1).getIndex();
998 unsigned PCLabelId = duplicateCPV(MF, CPI);
999 MachineInstrBuilder MIB = BuildMI(MBB, I, Orig->getDebugLoc(), get(Opcode),
1001 .addConstantPoolIndex(CPI).addImm(PCLabelId);
1002 (*MIB).setMemRefs(Orig->memoperands_begin(), Orig->memoperands_end());
1009 ARMBaseInstrInfo::duplicate(MachineInstr *Orig, MachineFunction &MF) const {
1010 MachineInstr *MI = TargetInstrInfoImpl::duplicate(Orig, MF);
1011 switch(Orig->getOpcode()) {
1012 case ARM::tLDRpci_pic:
1013 case ARM::t2LDRpci_pic: {
1014 unsigned CPI = Orig->getOperand(1).getIndex();
1015 unsigned PCLabelId = duplicateCPV(MF, CPI);
1016 Orig->getOperand(1).setIndex(CPI);
1017 Orig->getOperand(2).setImm(PCLabelId);
1024 bool ARMBaseInstrInfo::produceSameValue(const MachineInstr *MI0,
1025 const MachineInstr *MI1) const {
1026 int Opcode = MI0->getOpcode();
1027 if (Opcode == ARM::t2LDRpci ||
1028 Opcode == ARM::t2LDRpci_pic ||
1029 Opcode == ARM::tLDRpci ||
1030 Opcode == ARM::tLDRpci_pic) {
1031 if (MI1->getOpcode() != Opcode)
1033 if (MI0->getNumOperands() != MI1->getNumOperands())
1036 const MachineOperand &MO0 = MI0->getOperand(1);
1037 const MachineOperand &MO1 = MI1->getOperand(1);
1038 if (MO0.getOffset() != MO1.getOffset())
1041 const MachineFunction *MF = MI0->getParent()->getParent();
1042 const MachineConstantPool *MCP = MF->getConstantPool();
1043 int CPI0 = MO0.getIndex();
1044 int CPI1 = MO1.getIndex();
1045 const MachineConstantPoolEntry &MCPE0 = MCP->getConstants()[CPI0];
1046 const MachineConstantPoolEntry &MCPE1 = MCP->getConstants()[CPI1];
1047 ARMConstantPoolValue *ACPV0 =
1048 static_cast<ARMConstantPoolValue*>(MCPE0.Val.MachineCPVal);
1049 ARMConstantPoolValue *ACPV1 =
1050 static_cast<ARMConstantPoolValue*>(MCPE1.Val.MachineCPVal);
1051 return ACPV0->hasSameValue(ACPV1);
1054 return MI0->isIdenticalTo(MI1, MachineInstr::IgnoreVRegDefs);
1057 /// areLoadsFromSameBasePtr - This is used by the pre-regalloc scheduler to
1058 /// determine if two loads are loading from the same base address. It should
1059 /// only return true if the base pointers are the same and the only differences
1060 /// between the two addresses is the offset. It also returns the offsets by
1062 bool ARMBaseInstrInfo::areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2,
1064 int64_t &Offset2) const {
1065 // Don't worry about Thumb: just ARM and Thumb2.
1066 if (Subtarget.isThumb1Only()) return false;
1068 if (!Load1->isMachineOpcode() || !Load2->isMachineOpcode())
1071 switch (Load1->getMachineOpcode()) {
1084 case ARM::t2LDRSHi8:
1086 case ARM::t2LDRSHi12:
1090 switch (Load2->getMachineOpcode()) {
1103 case ARM::t2LDRSHi8:
1105 case ARM::t2LDRSHi12:
1109 // Check if base addresses and chain operands match.
1110 if (Load1->getOperand(0) != Load2->getOperand(0) ||
1111 Load1->getOperand(4) != Load2->getOperand(4))
1114 // Index should be Reg0.
1115 if (Load1->getOperand(3) != Load2->getOperand(3))
1118 // Determine the offsets.
1119 if (isa<ConstantSDNode>(Load1->getOperand(1)) &&
1120 isa<ConstantSDNode>(Load2->getOperand(1))) {
1121 Offset1 = cast<ConstantSDNode>(Load1->getOperand(1))->getSExtValue();
1122 Offset2 = cast<ConstantSDNode>(Load2->getOperand(1))->getSExtValue();
1129 /// shouldScheduleLoadsNear - This is a used by the pre-regalloc scheduler to
1130 /// determine (in conjuction with areLoadsFromSameBasePtr) if two loads should
1131 /// be scheduled togther. On some targets if two loads are loading from
1132 /// addresses in the same cache line, it's better if they are scheduled
1133 /// together. This function takes two integers that represent the load offsets
1134 /// from the common base address. It returns true if it decides it's desirable
1135 /// to schedule the two loads together. "NumLoads" is the number of loads that
1136 /// have already been scheduled after Load1.
1137 bool ARMBaseInstrInfo::shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,
1138 int64_t Offset1, int64_t Offset2,
1139 unsigned NumLoads) const {
1140 // Don't worry about Thumb: just ARM and Thumb2.
1141 if (Subtarget.isThumb1Only()) return false;
1143 assert(Offset2 > Offset1);
1145 if ((Offset2 - Offset1) / 8 > 64)
1148 if (Load1->getMachineOpcode() != Load2->getMachineOpcode())
1149 return false; // FIXME: overly conservative?
1151 // Four loads in a row should be sufficient.
1158 bool ARMBaseInstrInfo::isSchedulingBoundary(const MachineInstr *MI,
1159 const MachineBasicBlock *MBB,
1160 const MachineFunction &MF) const {
1161 // Debug info is never a scheduling boundary. It's necessary to be explicit
1162 // due to the special treatment of IT instructions below, otherwise a
1163 // dbg_value followed by an IT will result in the IT instruction being
1164 // considered a scheduling hazard, which is wrong. It should be the actual
1165 // instruction preceding the dbg_value instruction(s), just like it is
1166 // when debug info is not present.
1167 if (MI->isDebugValue())
1170 // Terminators and labels can't be scheduled around.
1171 if (MI->getDesc().isTerminator() || MI->isLabel())
1174 // Treat the start of the IT block as a scheduling boundary, but schedule
1175 // t2IT along with all instructions following it.
1176 // FIXME: This is a big hammer. But the alternative is to add all potential
1177 // true and anti dependencies to IT block instructions as implicit operands
1178 // to the t2IT instruction. The added compile time and complexity does not
1180 MachineBasicBlock::const_iterator I = MI;
1181 // Make sure to skip any dbg_value instructions
1182 while (++I != MBB->end() && I->isDebugValue())
1184 if (I != MBB->end() && I->getOpcode() == ARM::t2IT)
1187 // Don't attempt to schedule around any instruction that defines
1188 // a stack-oriented pointer, as it's unlikely to be profitable. This
1189 // saves compile time, because it doesn't require every single
1190 // stack slot reference to depend on the instruction that does the
1192 if (MI->definesRegister(ARM::SP))
1198 bool ARMBaseInstrInfo::isProfitableToIfCvt(MachineBasicBlock &MBB,
1200 float Probability) const {
1204 // Attempt to estimate the relative costs of predication versus branching.
1205 float UnpredCost = Probability * NumInstrs;
1206 UnpredCost += 1.0; // The branch itself
1207 UnpredCost += 0.1 * Subtarget.getMispredictionPenalty();
1209 float PredCost = NumInstrs;
1211 return PredCost < UnpredCost;
1215 bool ARMBaseInstrInfo::
1216 isProfitableToIfCvt(MachineBasicBlock &TMBB, unsigned NumT,
1217 MachineBasicBlock &FMBB, unsigned NumF,
1218 float Probability) const {
1222 // Attempt to estimate the relative costs of predication versus branching.
1223 float UnpredCost = Probability * NumT + (1.0 - Probability) * NumF;
1224 UnpredCost += 1.0; // The branch itself
1225 UnpredCost += 0.1 * Subtarget.getMispredictionPenalty();
1227 float PredCost = NumT + NumF;
1229 return PredCost < UnpredCost;
1232 /// getInstrPredicate - If instruction is predicated, returns its predicate
1233 /// condition, otherwise returns AL. It also returns the condition code
1234 /// register by reference.
1236 llvm::getInstrPredicate(const MachineInstr *MI, unsigned &PredReg) {
1237 int PIdx = MI->findFirstPredOperandIdx();
1243 PredReg = MI->getOperand(PIdx+1).getReg();
1244 return (ARMCC::CondCodes)MI->getOperand(PIdx).getImm();
1248 int llvm::getMatchingCondBranchOpcode(int Opc) {
1251 else if (Opc == ARM::tB)
1253 else if (Opc == ARM::t2B)
1256 llvm_unreachable("Unknown unconditional branch opcode!");
1261 void llvm::emitARMRegPlusImmediate(MachineBasicBlock &MBB,
1262 MachineBasicBlock::iterator &MBBI, DebugLoc dl,
1263 unsigned DestReg, unsigned BaseReg, int NumBytes,
1264 ARMCC::CondCodes Pred, unsigned PredReg,
1265 const ARMBaseInstrInfo &TII) {
1266 bool isSub = NumBytes < 0;
1267 if (isSub) NumBytes = -NumBytes;
1270 unsigned RotAmt = ARM_AM::getSOImmValRotate(NumBytes);
1271 unsigned ThisVal = NumBytes & ARM_AM::rotr32(0xFF, RotAmt);
1272 assert(ThisVal && "Didn't extract field correctly");
1274 // We will handle these bits from offset, clear them.
1275 NumBytes &= ~ThisVal;
1277 assert(ARM_AM::getSOImmVal(ThisVal) != -1 && "Bit extraction didn't work?");
1279 // Build the new ADD / SUB.
1280 unsigned Opc = isSub ? ARM::SUBri : ARM::ADDri;
1281 BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg)
1282 .addReg(BaseReg, RegState::Kill).addImm(ThisVal)
1283 .addImm((unsigned)Pred).addReg(PredReg).addReg(0);
1288 bool llvm::rewriteARMFrameIndex(MachineInstr &MI, unsigned FrameRegIdx,
1289 unsigned FrameReg, int &Offset,
1290 const ARMBaseInstrInfo &TII) {
1291 unsigned Opcode = MI.getOpcode();
1292 const TargetInstrDesc &Desc = MI.getDesc();
1293 unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
1296 // Memory operands in inline assembly always use AddrMode2.
1297 if (Opcode == ARM::INLINEASM)
1298 AddrMode = ARMII::AddrMode2;
1300 if (Opcode == ARM::ADDri) {
1301 Offset += MI.getOperand(FrameRegIdx+1).getImm();
1303 // Turn it into a move.
1304 MI.setDesc(TII.get(ARM::MOVr));
1305 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
1306 MI.RemoveOperand(FrameRegIdx+1);
1309 } else if (Offset < 0) {
1312 MI.setDesc(TII.get(ARM::SUBri));
1315 // Common case: small offset, fits into instruction.
1316 if (ARM_AM::getSOImmVal(Offset) != -1) {
1317 // Replace the FrameIndex with sp / fp
1318 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
1319 MI.getOperand(FrameRegIdx+1).ChangeToImmediate(Offset);
1324 // Otherwise, pull as much of the immedidate into this ADDri/SUBri
1326 unsigned RotAmt = ARM_AM::getSOImmValRotate(Offset);
1327 unsigned ThisImmVal = Offset & ARM_AM::rotr32(0xFF, RotAmt);
1329 // We will handle these bits from offset, clear them.
1330 Offset &= ~ThisImmVal;
1332 // Get the properly encoded SOImmVal field.
1333 assert(ARM_AM::getSOImmVal(ThisImmVal) != -1 &&
1334 "Bit extraction didn't work?");
1335 MI.getOperand(FrameRegIdx+1).ChangeToImmediate(ThisImmVal);
1337 unsigned ImmIdx = 0;
1339 unsigned NumBits = 0;
1342 case ARMII::AddrMode2: {
1343 ImmIdx = FrameRegIdx+2;
1344 InstrOffs = ARM_AM::getAM2Offset(MI.getOperand(ImmIdx).getImm());
1345 if (ARM_AM::getAM2Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub)
1350 case ARMII::AddrMode3: {
1351 ImmIdx = FrameRegIdx+2;
1352 InstrOffs = ARM_AM::getAM3Offset(MI.getOperand(ImmIdx).getImm());
1353 if (ARM_AM::getAM3Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub)
1358 case ARMII::AddrMode4:
1359 case ARMII::AddrMode6:
1360 // Can't fold any offset even if it's zero.
1362 case ARMII::AddrMode5: {
1363 ImmIdx = FrameRegIdx+1;
1364 InstrOffs = ARM_AM::getAM5Offset(MI.getOperand(ImmIdx).getImm());
1365 if (ARM_AM::getAM5Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub)
1372 llvm_unreachable("Unsupported addressing mode!");
1376 Offset += InstrOffs * Scale;
1377 assert((Offset & (Scale-1)) == 0 && "Can't encode this offset!");
1383 // Attempt to fold address comp. if opcode has offset bits
1385 // Common case: small offset, fits into instruction.
1386 MachineOperand &ImmOp = MI.getOperand(ImmIdx);
1387 int ImmedOffset = Offset / Scale;
1388 unsigned Mask = (1 << NumBits) - 1;
1389 if ((unsigned)Offset <= Mask * Scale) {
1390 // Replace the FrameIndex with sp
1391 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
1393 ImmedOffset |= 1 << NumBits;
1394 ImmOp.ChangeToImmediate(ImmedOffset);
1399 // Otherwise, it didn't fit. Pull in what we can to simplify the immed.
1400 ImmedOffset = ImmedOffset & Mask;
1402 ImmedOffset |= 1 << NumBits;
1403 ImmOp.ChangeToImmediate(ImmedOffset);
1404 Offset &= ~(Mask*Scale);
1408 Offset = (isSub) ? -Offset : Offset;
1412 bool ARMBaseInstrInfo::
1413 AnalyzeCompare(const MachineInstr *MI, unsigned &SrcReg, int &CmpMask,
1414 int &CmpValue) const {
1415 switch (MI->getOpcode()) {
1421 SrcReg = MI->getOperand(0).getReg();
1423 CmpValue = MI->getOperand(1).getImm();
1427 SrcReg = MI->getOperand(0).getReg();
1428 CmpMask = MI->getOperand(1).getImm();
1436 /// isSuitableForMask - Identify a suitable 'and' instruction that
1437 /// operates on the given source register and applies the same mask
1438 /// as a 'tst' instruction. Provide a limited look-through for copies.
1439 /// When successful, MI will hold the found instruction.
1440 static bool isSuitableForMask(MachineInstr *&MI, unsigned SrcReg,
1441 int CmpMask, bool CommonUse) {
1442 switch (MI->getOpcode()) {
1445 if (CmpMask != MI->getOperand(2).getImm())
1447 if (SrcReg == MI->getOperand(CommonUse ? 1 : 0).getReg())
1451 // Walk down one instruction which is potentially an 'and'.
1452 const MachineInstr &Copy = *MI;
1453 MachineBasicBlock::iterator AND(next(MachineBasicBlock::iterator(MI)));
1454 if (AND == MI->getParent()->end()) return false;
1456 return isSuitableForMask(MI, Copy.getOperand(0).getReg(),
1464 /// OptimizeCompareInstr - Convert the instruction supplying the argument to the
1465 /// comparison into one that sets the zero bit in the flags register. Update the
1466 /// iterator *only* if a transformation took place.
1467 bool ARMBaseInstrInfo::
1468 OptimizeCompareInstr(MachineInstr *CmpInstr, unsigned SrcReg, int CmpMask,
1469 int CmpValue, MachineBasicBlock::iterator &MII) const {
1473 MachineRegisterInfo &MRI = CmpInstr->getParent()->getParent()->getRegInfo();
1474 MachineRegisterInfo::def_iterator DI = MRI.def_begin(SrcReg);
1475 if (llvm::next(DI) != MRI.def_end())
1476 // Only support one definition.
1479 MachineInstr *MI = &*DI;
1481 // Masked compares sometimes use the same register as the corresponding 'and'.
1482 if (CmpMask != ~0) {
1483 if (!isSuitableForMask(MI, SrcReg, CmpMask, false)) {
1485 for (MachineRegisterInfo::use_iterator UI = MRI.use_begin(SrcReg),
1486 UE = MRI.use_end(); UI != UE; ++UI) {
1487 if (UI->getParent() != CmpInstr->getParent()) continue;
1488 MachineInstr *PotentialAND = &*UI;
1489 if (!isSuitableForMask(PotentialAND, SrcReg, CmpMask, true))
1494 if (!MI) return false;
1498 // Conservatively refuse to convert an instruction which isn't in the same BB
1499 // as the comparison.
1500 if (MI->getParent() != CmpInstr->getParent())
1503 // Check that CPSR isn't set between the comparison instruction and the one we
1505 MachineBasicBlock::const_iterator I = CmpInstr, E = MI,
1506 B = MI->getParent()->begin();
1508 for (; I != E; --I) {
1509 const MachineInstr &Instr = *I;
1511 for (unsigned IO = 0, EO = Instr.getNumOperands(); IO != EO; ++IO) {
1512 const MachineOperand &MO = Instr.getOperand(IO);
1513 if (!MO.isReg() || !MO.isDef()) continue;
1515 // This instruction modifies CPSR before the one we want to change. We
1516 // can't do this transformation.
1517 if (MO.getReg() == ARM::CPSR)
1522 // The 'and' is below the comparison instruction.
1526 // Set the "zero" bit in CPSR.
1527 switch (MI->getOpcode()) {
1535 MI->RemoveOperand(5);
1536 MachineInstrBuilder(MI)
1537 .addReg(ARM::CPSR, RegState::Define | RegState::Implicit);
1538 MII = llvm::next(MachineBasicBlock::iterator(CmpInstr));
1539 CmpInstr->eraseFromParent();
1547 ARMBaseInstrInfo::getNumMicroOps(const MachineInstr *MI,
1548 const InstrItineraryData *ItinData) const {
1549 if (!ItinData || ItinData->isEmpty())
1552 const TargetInstrDesc &Desc = MI->getDesc();
1553 unsigned Class = Desc.getSchedClass();
1554 unsigned UOps = ItinData->Itineraries[Class].NumMicroOps;
1558 unsigned Opc = MI->getOpcode();
1561 llvm_unreachable("Unexpected multi-uops instruction!");
1567 // The number of uOps for load / store multiple are determined by the number
1569 // On Cortex-A8, each pair of register loads / stores can be scheduled on the
1570 // same cycle. The scheduling for the first load / store must be done
1571 // separately by assuming the the address is not 64-bit aligned.
1572 // On Cortex-A9, the formula is simply (#reg / 2) + (#reg % 2). If the address
1573 // is not 64-bit aligned, then AGU would take an extra cycle.
1574 // For VFP / NEON load / store multiple, the formula is
1575 // (#reg / 2) + (#reg % 2) + 1.
1578 case ARM::VLDMD_UPD:
1579 case ARM::VLDMS_UPD:
1582 case ARM::VSTMD_UPD:
1583 case ARM::VSTMS_UPD: {
1584 unsigned NumRegs = MI->getNumOperands() - Desc.getNumOperands();
1585 return (NumRegs / 2) + (NumRegs % 2) + 1;
1598 case ARM::t2LDM_RET:
1600 case ARM::t2LDM_UPD:
1602 case ARM::t2STM_UPD: {
1603 unsigned NumRegs = MI->getNumOperands() - Desc.getNumOperands() + 1;
1604 if (Subtarget.isCortexA8()) {
1605 // 4 registers would be issued: 1, 2, 1.
1606 // 5 registers would be issued: 1, 2, 2.
1607 return 1 + (NumRegs / 2);
1608 } else if (Subtarget.isCortexA9()) {
1609 UOps = (NumRegs / 2);
1610 // If there are odd number of registers or if it's not 64-bit aligned,
1611 // then it takes an extra AGU (Address Generation Unit) cycle.
1612 if ((NumRegs % 2) ||
1613 !MI->hasOneMemOperand() ||
1614 (*MI->memoperands_begin())->getAlignment() < 8)
1618 // Assume the worst.