1 //===- ARMBaseInstrInfo.cpp - ARM Instruction Information -------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Base ARM implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "ARMBaseInstrInfo.h"
16 #include "ARMConstantPoolValue.h"
17 #include "ARMHazardRecognizer.h"
18 #include "ARMMachineFunctionInfo.h"
19 #include "ARMRegisterInfo.h"
20 #include "MCTargetDesc/ARMAddressingModes.h"
21 #include "llvm/Constants.h"
22 #include "llvm/Function.h"
23 #include "llvm/GlobalValue.h"
24 #include "llvm/CodeGen/LiveVariables.h"
25 #include "llvm/CodeGen/MachineConstantPool.h"
26 #include "llvm/CodeGen/MachineFrameInfo.h"
27 #include "llvm/CodeGen/MachineInstrBuilder.h"
28 #include "llvm/CodeGen/MachineJumpTableInfo.h"
29 #include "llvm/CodeGen/MachineMemOperand.h"
30 #include "llvm/CodeGen/MachineRegisterInfo.h"
31 #include "llvm/CodeGen/PseudoSourceValue.h"
32 #include "llvm/CodeGen/SelectionDAGNodes.h"
33 #include "llvm/MC/MCAsmInfo.h"
34 #include "llvm/Support/BranchProbability.h"
35 #include "llvm/Support/CommandLine.h"
36 #include "llvm/Support/Debug.h"
37 #include "llvm/Support/ErrorHandling.h"
38 #include "llvm/ADT/STLExtras.h"
40 #define GET_INSTRINFO_CTOR
41 #include "ARMGenInstrInfo.inc"
46 EnableARM3Addr("enable-arm-3-addr-conv", cl::Hidden,
47 cl::desc("Enable ARM 2-addr to 3-addr conv"));
50 WidenVMOVS("widen-vmovs", cl::Hidden,
51 cl::desc("Widen ARM vmovs to vmovd when possible"));
53 /// ARM_MLxEntry - Record information about MLA / MLS instructions.
55 unsigned MLxOpc; // MLA / MLS opcode
56 unsigned MulOpc; // Expanded multiplication opcode
57 unsigned AddSubOpc; // Expanded add / sub opcode
58 bool NegAcc; // True if the acc is negated before the add / sub.
59 bool HasLane; // True if instruction has an extra "lane" operand.
62 static const ARM_MLxEntry ARM_MLxTable[] = {
63 // MLxOpc, MulOpc, AddSubOpc, NegAcc, HasLane
65 { ARM::VMLAS, ARM::VMULS, ARM::VADDS, false, false },
66 { ARM::VMLSS, ARM::VMULS, ARM::VSUBS, false, false },
67 { ARM::VMLAD, ARM::VMULD, ARM::VADDD, false, false },
68 { ARM::VMLSD, ARM::VMULD, ARM::VSUBD, false, false },
69 { ARM::VNMLAS, ARM::VNMULS, ARM::VSUBS, true, false },
70 { ARM::VNMLSS, ARM::VMULS, ARM::VSUBS, true, false },
71 { ARM::VNMLAD, ARM::VNMULD, ARM::VSUBD, true, false },
72 { ARM::VNMLSD, ARM::VMULD, ARM::VSUBD, true, false },
75 { ARM::VMLAfd, ARM::VMULfd, ARM::VADDfd, false, false },
76 { ARM::VMLSfd, ARM::VMULfd, ARM::VSUBfd, false, false },
77 { ARM::VMLAfq, ARM::VMULfq, ARM::VADDfq, false, false },
78 { ARM::VMLSfq, ARM::VMULfq, ARM::VSUBfq, false, false },
79 { ARM::VMLAslfd, ARM::VMULslfd, ARM::VADDfd, false, true },
80 { ARM::VMLSslfd, ARM::VMULslfd, ARM::VSUBfd, false, true },
81 { ARM::VMLAslfq, ARM::VMULslfq, ARM::VADDfq, false, true },
82 { ARM::VMLSslfq, ARM::VMULslfq, ARM::VSUBfq, false, true },
85 ARMBaseInstrInfo::ARMBaseInstrInfo(const ARMSubtarget& STI)
86 : ARMGenInstrInfo(ARM::ADJCALLSTACKDOWN, ARM::ADJCALLSTACKUP),
88 for (unsigned i = 0, e = array_lengthof(ARM_MLxTable); i != e; ++i) {
89 if (!MLxEntryMap.insert(std::make_pair(ARM_MLxTable[i].MLxOpc, i)).second)
90 assert(false && "Duplicated entries?");
91 MLxHazardOpcodes.insert(ARM_MLxTable[i].AddSubOpc);
92 MLxHazardOpcodes.insert(ARM_MLxTable[i].MulOpc);
96 // Use a ScoreboardHazardRecognizer for prepass ARM scheduling. TargetInstrImpl
97 // currently defaults to no prepass hazard recognizer.
98 ScheduleHazardRecognizer *ARMBaseInstrInfo::
99 CreateTargetHazardRecognizer(const TargetMachine *TM,
100 const ScheduleDAG *DAG) const {
101 if (usePreRAHazardRecognizer()) {
102 const InstrItineraryData *II = TM->getInstrItineraryData();
103 return new ScoreboardHazardRecognizer(II, DAG, "pre-RA-sched");
105 return TargetInstrInfoImpl::CreateTargetHazardRecognizer(TM, DAG);
108 ScheduleHazardRecognizer *ARMBaseInstrInfo::
109 CreateTargetPostRAHazardRecognizer(const InstrItineraryData *II,
110 const ScheduleDAG *DAG) const {
111 if (Subtarget.isThumb2() || Subtarget.hasVFP2())
112 return (ScheduleHazardRecognizer *)
113 new ARMHazardRecognizer(II, *this, getRegisterInfo(), Subtarget, DAG);
114 return TargetInstrInfoImpl::CreateTargetPostRAHazardRecognizer(II, DAG);
118 ARMBaseInstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
119 MachineBasicBlock::iterator &MBBI,
120 LiveVariables *LV) const {
121 // FIXME: Thumb2 support.
126 MachineInstr *MI = MBBI;
127 MachineFunction &MF = *MI->getParent()->getParent();
128 uint64_t TSFlags = MI->getDesc().TSFlags;
130 switch ((TSFlags & ARMII::IndexModeMask) >> ARMII::IndexModeShift) {
131 default: return NULL;
132 case ARMII::IndexModePre:
135 case ARMII::IndexModePost:
139 // Try splitting an indexed load/store to an un-indexed one plus an add/sub
141 unsigned MemOpc = getUnindexedOpcode(MI->getOpcode());
145 MachineInstr *UpdateMI = NULL;
146 MachineInstr *MemMI = NULL;
147 unsigned AddrMode = (TSFlags & ARMII::AddrModeMask);
148 const MCInstrDesc &MCID = MI->getDesc();
149 unsigned NumOps = MCID.getNumOperands();
150 bool isLoad = !MCID.mayStore();
151 const MachineOperand &WB = isLoad ? MI->getOperand(1) : MI->getOperand(0);
152 const MachineOperand &Base = MI->getOperand(2);
153 const MachineOperand &Offset = MI->getOperand(NumOps-3);
154 unsigned WBReg = WB.getReg();
155 unsigned BaseReg = Base.getReg();
156 unsigned OffReg = Offset.getReg();
157 unsigned OffImm = MI->getOperand(NumOps-2).getImm();
158 ARMCC::CondCodes Pred = (ARMCC::CondCodes)MI->getOperand(NumOps-1).getImm();
161 assert(false && "Unknown indexed op!");
163 case ARMII::AddrMode2: {
164 bool isSub = ARM_AM::getAM2Op(OffImm) == ARM_AM::sub;
165 unsigned Amt = ARM_AM::getAM2Offset(OffImm);
167 if (ARM_AM::getSOImmVal(Amt) == -1)
168 // Can't encode it in a so_imm operand. This transformation will
169 // add more than 1 instruction. Abandon!
171 UpdateMI = BuildMI(MF, MI->getDebugLoc(),
172 get(isSub ? ARM::SUBri : ARM::ADDri), WBReg)
173 .addReg(BaseReg).addImm(Amt)
174 .addImm(Pred).addReg(0).addReg(0);
175 } else if (Amt != 0) {
176 ARM_AM::ShiftOpc ShOpc = ARM_AM::getAM2ShiftOpc(OffImm);
177 unsigned SOOpc = ARM_AM::getSORegOpc(ShOpc, Amt);
178 UpdateMI = BuildMI(MF, MI->getDebugLoc(),
179 get(isSub ? ARM::SUBrsi : ARM::ADDrsi), WBReg)
180 .addReg(BaseReg).addReg(OffReg).addReg(0).addImm(SOOpc)
181 .addImm(Pred).addReg(0).addReg(0);
183 UpdateMI = BuildMI(MF, MI->getDebugLoc(),
184 get(isSub ? ARM::SUBrr : ARM::ADDrr), WBReg)
185 .addReg(BaseReg).addReg(OffReg)
186 .addImm(Pred).addReg(0).addReg(0);
189 case ARMII::AddrMode3 : {
190 bool isSub = ARM_AM::getAM3Op(OffImm) == ARM_AM::sub;
191 unsigned Amt = ARM_AM::getAM3Offset(OffImm);
193 // Immediate is 8-bits. It's guaranteed to fit in a so_imm operand.
194 UpdateMI = BuildMI(MF, MI->getDebugLoc(),
195 get(isSub ? ARM::SUBri : ARM::ADDri), WBReg)
196 .addReg(BaseReg).addImm(Amt)
197 .addImm(Pred).addReg(0).addReg(0);
199 UpdateMI = BuildMI(MF, MI->getDebugLoc(),
200 get(isSub ? ARM::SUBrr : ARM::ADDrr), WBReg)
201 .addReg(BaseReg).addReg(OffReg)
202 .addImm(Pred).addReg(0).addReg(0);
207 std::vector<MachineInstr*> NewMIs;
210 MemMI = BuildMI(MF, MI->getDebugLoc(),
211 get(MemOpc), MI->getOperand(0).getReg())
212 .addReg(WBReg).addImm(0).addImm(Pred);
214 MemMI = BuildMI(MF, MI->getDebugLoc(),
215 get(MemOpc)).addReg(MI->getOperand(1).getReg())
216 .addReg(WBReg).addReg(0).addImm(0).addImm(Pred);
217 NewMIs.push_back(MemMI);
218 NewMIs.push_back(UpdateMI);
221 MemMI = BuildMI(MF, MI->getDebugLoc(),
222 get(MemOpc), MI->getOperand(0).getReg())
223 .addReg(BaseReg).addImm(0).addImm(Pred);
225 MemMI = BuildMI(MF, MI->getDebugLoc(),
226 get(MemOpc)).addReg(MI->getOperand(1).getReg())
227 .addReg(BaseReg).addReg(0).addImm(0).addImm(Pred);
229 UpdateMI->getOperand(0).setIsDead();
230 NewMIs.push_back(UpdateMI);
231 NewMIs.push_back(MemMI);
234 // Transfer LiveVariables states, kill / dead info.
236 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
237 MachineOperand &MO = MI->getOperand(i);
238 if (MO.isReg() && TargetRegisterInfo::isVirtualRegister(MO.getReg())) {
239 unsigned Reg = MO.getReg();
241 LiveVariables::VarInfo &VI = LV->getVarInfo(Reg);
243 MachineInstr *NewMI = (Reg == WBReg) ? UpdateMI : MemMI;
245 LV->addVirtualRegisterDead(Reg, NewMI);
247 if (MO.isUse() && MO.isKill()) {
248 for (unsigned j = 0; j < 2; ++j) {
249 // Look at the two new MI's in reverse order.
250 MachineInstr *NewMI = NewMIs[j];
251 if (!NewMI->readsRegister(Reg))
253 LV->addVirtualRegisterKilled(Reg, NewMI);
254 if (VI.removeKill(MI))
255 VI.Kills.push_back(NewMI);
263 MFI->insert(MBBI, NewMIs[1]);
264 MFI->insert(MBBI, NewMIs[0]);
270 ARMBaseInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB,
271 MachineBasicBlock *&FBB,
272 SmallVectorImpl<MachineOperand> &Cond,
273 bool AllowModify) const {
274 // If the block has no terminators, it just falls into the block after it.
275 MachineBasicBlock::iterator I = MBB.end();
276 if (I == MBB.begin())
279 while (I->isDebugValue()) {
280 if (I == MBB.begin())
284 if (!isUnpredicatedTerminator(I))
287 // Get the last instruction in the block.
288 MachineInstr *LastInst = I;
290 // If there is only one terminator instruction, process it.
291 unsigned LastOpc = LastInst->getOpcode();
292 if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) {
293 if (isUncondBranchOpcode(LastOpc)) {
294 TBB = LastInst->getOperand(0).getMBB();
297 if (isCondBranchOpcode(LastOpc)) {
298 // Block ends with fall-through condbranch.
299 TBB = LastInst->getOperand(0).getMBB();
300 Cond.push_back(LastInst->getOperand(1));
301 Cond.push_back(LastInst->getOperand(2));
304 return true; // Can't handle indirect branch.
307 // Get the instruction before it if it is a terminator.
308 MachineInstr *SecondLastInst = I;
309 unsigned SecondLastOpc = SecondLastInst->getOpcode();
311 // If AllowModify is true and the block ends with two or more unconditional
312 // branches, delete all but the first unconditional branch.
313 if (AllowModify && isUncondBranchOpcode(LastOpc)) {
314 while (isUncondBranchOpcode(SecondLastOpc)) {
315 LastInst->eraseFromParent();
316 LastInst = SecondLastInst;
317 LastOpc = LastInst->getOpcode();
318 if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) {
319 // Return now the only terminator is an unconditional branch.
320 TBB = LastInst->getOperand(0).getMBB();
324 SecondLastOpc = SecondLastInst->getOpcode();
329 // If there are three terminators, we don't know what sort of block this is.
330 if (SecondLastInst && I != MBB.begin() && isUnpredicatedTerminator(--I))
333 // If the block ends with a B and a Bcc, handle it.
334 if (isCondBranchOpcode(SecondLastOpc) && isUncondBranchOpcode(LastOpc)) {
335 TBB = SecondLastInst->getOperand(0).getMBB();
336 Cond.push_back(SecondLastInst->getOperand(1));
337 Cond.push_back(SecondLastInst->getOperand(2));
338 FBB = LastInst->getOperand(0).getMBB();
342 // If the block ends with two unconditional branches, handle it. The second
343 // one is not executed, so remove it.
344 if (isUncondBranchOpcode(SecondLastOpc) && isUncondBranchOpcode(LastOpc)) {
345 TBB = SecondLastInst->getOperand(0).getMBB();
348 I->eraseFromParent();
352 // ...likewise if it ends with a branch table followed by an unconditional
353 // branch. The branch folder can create these, and we must get rid of them for
354 // correctness of Thumb constant islands.
355 if ((isJumpTableBranchOpcode(SecondLastOpc) ||
356 isIndirectBranchOpcode(SecondLastOpc)) &&
357 isUncondBranchOpcode(LastOpc)) {
360 I->eraseFromParent();
364 // Otherwise, can't handle this.
369 unsigned ARMBaseInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
370 MachineBasicBlock::iterator I = MBB.end();
371 if (I == MBB.begin()) return 0;
373 while (I->isDebugValue()) {
374 if (I == MBB.begin())
378 if (!isUncondBranchOpcode(I->getOpcode()) &&
379 !isCondBranchOpcode(I->getOpcode()))
382 // Remove the branch.
383 I->eraseFromParent();
387 if (I == MBB.begin()) return 1;
389 if (!isCondBranchOpcode(I->getOpcode()))
392 // Remove the branch.
393 I->eraseFromParent();
398 ARMBaseInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
399 MachineBasicBlock *FBB,
400 const SmallVectorImpl<MachineOperand> &Cond,
402 ARMFunctionInfo *AFI = MBB.getParent()->getInfo<ARMFunctionInfo>();
403 int BOpc = !AFI->isThumbFunction()
404 ? ARM::B : (AFI->isThumb2Function() ? ARM::t2B : ARM::tB);
405 int BccOpc = !AFI->isThumbFunction()
406 ? ARM::Bcc : (AFI->isThumb2Function() ? ARM::t2Bcc : ARM::tBcc);
407 bool isThumb = AFI->isThumbFunction() || AFI->isThumb2Function();
409 // Shouldn't be a fall through.
410 assert(TBB && "InsertBranch must not be told to insert a fallthrough");
411 assert((Cond.size() == 2 || Cond.size() == 0) &&
412 "ARM branch conditions have two components!");
415 if (Cond.empty()) { // Unconditional branch?
417 BuildMI(&MBB, DL, get(BOpc)).addMBB(TBB).addImm(ARMCC::AL).addReg(0);
419 BuildMI(&MBB, DL, get(BOpc)).addMBB(TBB);
421 BuildMI(&MBB, DL, get(BccOpc)).addMBB(TBB)
422 .addImm(Cond[0].getImm()).addReg(Cond[1].getReg());
426 // Two-way conditional branch.
427 BuildMI(&MBB, DL, get(BccOpc)).addMBB(TBB)
428 .addImm(Cond[0].getImm()).addReg(Cond[1].getReg());
430 BuildMI(&MBB, DL, get(BOpc)).addMBB(FBB).addImm(ARMCC::AL).addReg(0);
432 BuildMI(&MBB, DL, get(BOpc)).addMBB(FBB);
436 bool ARMBaseInstrInfo::
437 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
438 ARMCC::CondCodes CC = (ARMCC::CondCodes)(int)Cond[0].getImm();
439 Cond[0].setImm(ARMCC::getOppositeCondition(CC));
443 bool ARMBaseInstrInfo::
444 PredicateInstruction(MachineInstr *MI,
445 const SmallVectorImpl<MachineOperand> &Pred) const {
446 unsigned Opc = MI->getOpcode();
447 if (isUncondBranchOpcode(Opc)) {
448 MI->setDesc(get(getMatchingCondBranchOpcode(Opc)));
449 MI->addOperand(MachineOperand::CreateImm(Pred[0].getImm()));
450 MI->addOperand(MachineOperand::CreateReg(Pred[1].getReg(), false));
454 int PIdx = MI->findFirstPredOperandIdx();
456 MachineOperand &PMO = MI->getOperand(PIdx);
457 PMO.setImm(Pred[0].getImm());
458 MI->getOperand(PIdx+1).setReg(Pred[1].getReg());
464 bool ARMBaseInstrInfo::
465 SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1,
466 const SmallVectorImpl<MachineOperand> &Pred2) const {
467 if (Pred1.size() > 2 || Pred2.size() > 2)
470 ARMCC::CondCodes CC1 = (ARMCC::CondCodes)Pred1[0].getImm();
471 ARMCC::CondCodes CC2 = (ARMCC::CondCodes)Pred2[0].getImm();
481 return CC2 == ARMCC::HI;
483 return CC2 == ARMCC::LO || CC2 == ARMCC::EQ;
485 return CC2 == ARMCC::GT;
487 return CC2 == ARMCC::LT;
491 bool ARMBaseInstrInfo::DefinesPredicate(MachineInstr *MI,
492 std::vector<MachineOperand> &Pred) const {
493 // FIXME: This confuses implicit_def with optional CPSR def.
494 const MCInstrDesc &MCID = MI->getDesc();
495 if (!MCID.getImplicitDefs() && !MCID.hasOptionalDef())
499 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
500 const MachineOperand &MO = MI->getOperand(i);
501 if (MO.isReg() && MO.getReg() == ARM::CPSR) {
510 /// isPredicable - Return true if the specified instruction can be predicated.
511 /// By default, this returns true for every instruction with a
512 /// PredicateOperand.
513 bool ARMBaseInstrInfo::isPredicable(MachineInstr *MI) const {
514 const MCInstrDesc &MCID = MI->getDesc();
515 if (!MCID.isPredicable())
518 if ((MCID.TSFlags & ARMII::DomainMask) == ARMII::DomainNEON) {
519 ARMFunctionInfo *AFI =
520 MI->getParent()->getParent()->getInfo<ARMFunctionInfo>();
521 return AFI->isThumb2Function();
526 /// FIXME: Works around a gcc miscompilation with -fstrict-aliasing.
527 LLVM_ATTRIBUTE_NOINLINE
528 static unsigned getNumJTEntries(const std::vector<MachineJumpTableEntry> &JT,
530 static unsigned getNumJTEntries(const std::vector<MachineJumpTableEntry> &JT,
532 assert(JTI < JT.size());
533 return JT[JTI].MBBs.size();
536 /// GetInstSize - Return the size of the specified MachineInstr.
538 unsigned ARMBaseInstrInfo::GetInstSizeInBytes(const MachineInstr *MI) const {
539 const MachineBasicBlock &MBB = *MI->getParent();
540 const MachineFunction *MF = MBB.getParent();
541 const MCAsmInfo *MAI = MF->getTarget().getMCAsmInfo();
543 const MCInstrDesc &MCID = MI->getDesc();
545 return MCID.getSize();
547 // If this machine instr is an inline asm, measure it.
548 if (MI->getOpcode() == ARM::INLINEASM)
549 return getInlineAsmLength(MI->getOperand(0).getSymbolName(), *MAI);
552 unsigned Opc = MI->getOpcode();
554 case TargetOpcode::IMPLICIT_DEF:
555 case TargetOpcode::KILL:
556 case TargetOpcode::PROLOG_LABEL:
557 case TargetOpcode::EH_LABEL:
558 case TargetOpcode::DBG_VALUE:
560 case ARM::MOVi16_ga_pcrel:
561 case ARM::MOVTi16_ga_pcrel:
562 case ARM::t2MOVi16_ga_pcrel:
563 case ARM::t2MOVTi16_ga_pcrel:
566 case ARM::t2MOVi32imm:
568 case ARM::CONSTPOOL_ENTRY:
569 // If this machine instr is a constant pool entry, its size is recorded as
571 return MI->getOperand(2).getImm();
572 case ARM::Int_eh_sjlj_longjmp:
574 case ARM::tInt_eh_sjlj_longjmp:
576 case ARM::Int_eh_sjlj_setjmp:
577 case ARM::Int_eh_sjlj_setjmp_nofp:
579 case ARM::tInt_eh_sjlj_setjmp:
580 case ARM::t2Int_eh_sjlj_setjmp:
581 case ARM::t2Int_eh_sjlj_setjmp_nofp:
589 case ARM::t2TBH_JT: {
590 // These are jumptable branches, i.e. a branch followed by an inlined
591 // jumptable. The size is 4 + 4 * number of entries. For TBB, each
592 // entry is one byte; TBH two byte each.
593 unsigned EntrySize = (Opc == ARM::t2TBB_JT)
594 ? 1 : ((Opc == ARM::t2TBH_JT) ? 2 : 4);
595 unsigned NumOps = MCID.getNumOperands();
596 MachineOperand JTOP =
597 MI->getOperand(NumOps - (MCID.isPredicable() ? 3 : 2));
598 unsigned JTI = JTOP.getIndex();
599 const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
601 const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
602 assert(JTI < JT.size());
603 // Thumb instructions are 2 byte aligned, but JT entries are 4 byte
604 // 4 aligned. The assembler / linker may add 2 byte padding just before
605 // the JT entries. The size does not include this padding; the
606 // constant islands pass does separate bookkeeping for it.
607 // FIXME: If we know the size of the function is less than (1 << 16) *2
608 // bytes, we can use 16-bit entries instead. Then there won't be an
610 unsigned InstSize = (Opc == ARM::tBR_JTr || Opc == ARM::t2BR_JT) ? 2 : 4;
611 unsigned NumEntries = getNumJTEntries(JT, JTI);
612 if (Opc == ARM::t2TBB_JT && (NumEntries & 1))
613 // Make sure the instruction that follows TBB is 2-byte aligned.
614 // FIXME: Constant island pass should insert an "ALIGN" instruction
617 return NumEntries * EntrySize + InstSize;
620 // Otherwise, pseudo-instruction sizes are zero.
623 return 0; // Not reached
626 void ARMBaseInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
627 MachineBasicBlock::iterator I, DebugLoc DL,
628 unsigned DestReg, unsigned SrcReg,
629 bool KillSrc) const {
630 bool GPRDest = ARM::GPRRegClass.contains(DestReg);
631 bool GPRSrc = ARM::GPRRegClass.contains(SrcReg);
633 if (GPRDest && GPRSrc) {
634 AddDefaultCC(AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::MOVr), DestReg)
635 .addReg(SrcReg, getKillRegState(KillSrc))));
639 bool SPRDest = ARM::SPRRegClass.contains(DestReg);
640 bool SPRSrc = ARM::SPRRegClass.contains(SrcReg);
643 if (SPRDest && SPRSrc)
645 else if (GPRDest && SPRSrc)
647 else if (SPRDest && GPRSrc)
649 else if (ARM::DPRRegClass.contains(DestReg, SrcReg))
651 else if (ARM::QPRRegClass.contains(DestReg, SrcReg))
655 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(Opc), DestReg);
656 MIB.addReg(SrcReg, getKillRegState(KillSrc));
657 if (Opc == ARM::VORRq)
658 MIB.addReg(SrcReg, getKillRegState(KillSrc));
663 // Generate instructions for VMOVQQ and VMOVQQQQ pseudos in place.
664 if (ARM::QQPRRegClass.contains(DestReg, SrcReg) ||
665 ARM::QQQQPRRegClass.contains(DestReg, SrcReg)) {
666 const TargetRegisterInfo *TRI = &getRegisterInfo();
667 assert(ARM::qsub_0 + 3 == ARM::qsub_3 && "Expected contiguous enum.");
668 unsigned EndSubReg = ARM::QQPRRegClass.contains(DestReg, SrcReg) ?
669 ARM::qsub_1 : ARM::qsub_3;
670 for (unsigned i = ARM::qsub_0, e = EndSubReg + 1; i != e; ++i) {
671 unsigned Dst = TRI->getSubReg(DestReg, i);
672 unsigned Src = TRI->getSubReg(SrcReg, i);
673 MachineInstrBuilder Mov =
674 AddDefaultPred(BuildMI(MBB, I, I->getDebugLoc(), get(ARM::VORRq))
675 .addReg(Dst, RegState::Define)
676 .addReg(Src, getKillRegState(KillSrc))
677 .addReg(Src, getKillRegState(KillSrc)));
678 if (i == EndSubReg) {
679 Mov->addRegisterDefined(DestReg, TRI);
681 Mov->addRegisterKilled(SrcReg, TRI);
686 llvm_unreachable("Impossible reg-to-reg copy");
690 MachineInstrBuilder &AddDReg(MachineInstrBuilder &MIB,
691 unsigned Reg, unsigned SubIdx, unsigned State,
692 const TargetRegisterInfo *TRI) {
694 return MIB.addReg(Reg, State);
696 if (TargetRegisterInfo::isPhysicalRegister(Reg))
697 return MIB.addReg(TRI->getSubReg(Reg, SubIdx), State);
698 return MIB.addReg(Reg, State, SubIdx);
701 void ARMBaseInstrInfo::
702 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
703 unsigned SrcReg, bool isKill, int FI,
704 const TargetRegisterClass *RC,
705 const TargetRegisterInfo *TRI) const {
707 if (I != MBB.end()) DL = I->getDebugLoc();
708 MachineFunction &MF = *MBB.getParent();
709 MachineFrameInfo &MFI = *MF.getFrameInfo();
710 unsigned Align = MFI.getObjectAlignment(FI);
712 MachineMemOperand *MMO =
713 MF.getMachineMemOperand(MachinePointerInfo(
714 PseudoSourceValue::getFixedStack(FI)),
715 MachineMemOperand::MOStore,
716 MFI.getObjectSize(FI),
719 switch (RC->getSize()) {
721 if (ARM::GPRRegClass.hasSubClassEq(RC)) {
722 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::STRi12))
723 .addReg(SrcReg, getKillRegState(isKill))
724 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
725 } else if (ARM::SPRRegClass.hasSubClassEq(RC)) {
726 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTRS))
727 .addReg(SrcReg, getKillRegState(isKill))
728 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
730 llvm_unreachable("Unknown reg class!");
733 if (ARM::DPRRegClass.hasSubClassEq(RC)) {
734 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTRD))
735 .addReg(SrcReg, getKillRegState(isKill))
736 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
738 llvm_unreachable("Unknown reg class!");
741 if (ARM::QPRRegClass.hasSubClassEq(RC)) {
742 if (Align >= 16 && getRegisterInfo().needsStackRealignment(MF)) {
743 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VST1q64Pseudo))
744 .addFrameIndex(FI).addImm(16)
745 .addReg(SrcReg, getKillRegState(isKill))
746 .addMemOperand(MMO));
748 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTMQIA))
749 .addReg(SrcReg, getKillRegState(isKill))
751 .addMemOperand(MMO));
754 llvm_unreachable("Unknown reg class!");
757 if (ARM::QQPRRegClass.hasSubClassEq(RC)) {
758 if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) {
759 // FIXME: It's possible to only store part of the QQ register if the
760 // spilled def has a sub-register index.
761 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VST1d64QPseudo))
762 .addFrameIndex(FI).addImm(16)
763 .addReg(SrcReg, getKillRegState(isKill))
764 .addMemOperand(MMO));
766 MachineInstrBuilder MIB =
767 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTMDIA))
770 MIB = AddDReg(MIB, SrcReg, ARM::dsub_0, getKillRegState(isKill), TRI);
771 MIB = AddDReg(MIB, SrcReg, ARM::dsub_1, 0, TRI);
772 MIB = AddDReg(MIB, SrcReg, ARM::dsub_2, 0, TRI);
773 AddDReg(MIB, SrcReg, ARM::dsub_3, 0, TRI);
776 llvm_unreachable("Unknown reg class!");
779 if (ARM::QQQQPRRegClass.hasSubClassEq(RC)) {
780 MachineInstrBuilder MIB =
781 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTMDIA))
784 MIB = AddDReg(MIB, SrcReg, ARM::dsub_0, getKillRegState(isKill), TRI);
785 MIB = AddDReg(MIB, SrcReg, ARM::dsub_1, 0, TRI);
786 MIB = AddDReg(MIB, SrcReg, ARM::dsub_2, 0, TRI);
787 MIB = AddDReg(MIB, SrcReg, ARM::dsub_3, 0, TRI);
788 MIB = AddDReg(MIB, SrcReg, ARM::dsub_4, 0, TRI);
789 MIB = AddDReg(MIB, SrcReg, ARM::dsub_5, 0, TRI);
790 MIB = AddDReg(MIB, SrcReg, ARM::dsub_6, 0, TRI);
791 AddDReg(MIB, SrcReg, ARM::dsub_7, 0, TRI);
793 llvm_unreachable("Unknown reg class!");
796 llvm_unreachable("Unknown reg class!");
801 ARMBaseInstrInfo::isStoreToStackSlot(const MachineInstr *MI,
802 int &FrameIndex) const {
803 switch (MI->getOpcode()) {
806 case ARM::t2STRs: // FIXME: don't use t2STRs to access frame.
807 if (MI->getOperand(1).isFI() &&
808 MI->getOperand(2).isReg() &&
809 MI->getOperand(3).isImm() &&
810 MI->getOperand(2).getReg() == 0 &&
811 MI->getOperand(3).getImm() == 0) {
812 FrameIndex = MI->getOperand(1).getIndex();
813 return MI->getOperand(0).getReg();
821 if (MI->getOperand(1).isFI() &&
822 MI->getOperand(2).isImm() &&
823 MI->getOperand(2).getImm() == 0) {
824 FrameIndex = MI->getOperand(1).getIndex();
825 return MI->getOperand(0).getReg();
828 case ARM::VST1q64Pseudo:
829 if (MI->getOperand(0).isFI() &&
830 MI->getOperand(2).getSubReg() == 0) {
831 FrameIndex = MI->getOperand(0).getIndex();
832 return MI->getOperand(2).getReg();
836 if (MI->getOperand(1).isFI() &&
837 MI->getOperand(0).getSubReg() == 0) {
838 FrameIndex = MI->getOperand(1).getIndex();
839 return MI->getOperand(0).getReg();
847 unsigned ARMBaseInstrInfo::isStoreToStackSlotPostFE(const MachineInstr *MI,
848 int &FrameIndex) const {
849 const MachineMemOperand *Dummy;
850 return MI->getDesc().mayStore() && hasStoreToStackSlot(MI, Dummy, FrameIndex);
853 void ARMBaseInstrInfo::
854 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
855 unsigned DestReg, int FI,
856 const TargetRegisterClass *RC,
857 const TargetRegisterInfo *TRI) const {
859 if (I != MBB.end()) DL = I->getDebugLoc();
860 MachineFunction &MF = *MBB.getParent();
861 MachineFrameInfo &MFI = *MF.getFrameInfo();
862 unsigned Align = MFI.getObjectAlignment(FI);
863 MachineMemOperand *MMO =
864 MF.getMachineMemOperand(
865 MachinePointerInfo(PseudoSourceValue::getFixedStack(FI)),
866 MachineMemOperand::MOLoad,
867 MFI.getObjectSize(FI),
870 switch (RC->getSize()) {
872 if (ARM::GPRRegClass.hasSubClassEq(RC)) {
873 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::LDRi12), DestReg)
874 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
876 } else if (ARM::SPRRegClass.hasSubClassEq(RC)) {
877 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDRS), DestReg)
878 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
880 llvm_unreachable("Unknown reg class!");
883 if (ARM::DPRRegClass.hasSubClassEq(RC)) {
884 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDRD), DestReg)
885 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
887 llvm_unreachable("Unknown reg class!");
890 if (ARM::QPRRegClass.hasSubClassEq(RC)) {
891 if (Align >= 16 && getRegisterInfo().needsStackRealignment(MF)) {
892 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLD1q64Pseudo), DestReg)
893 .addFrameIndex(FI).addImm(16)
894 .addMemOperand(MMO));
896 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDMQIA), DestReg)
898 .addMemOperand(MMO));
901 llvm_unreachable("Unknown reg class!");
904 if (ARM::QQPRRegClass.hasSubClassEq(RC)) {
905 if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) {
906 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLD1d64QPseudo), DestReg)
907 .addFrameIndex(FI).addImm(16)
908 .addMemOperand(MMO));
910 MachineInstrBuilder MIB =
911 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDMDIA))
914 MIB = AddDReg(MIB, DestReg, ARM::dsub_0, RegState::Define, TRI);
915 MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::Define, TRI);
916 MIB = AddDReg(MIB, DestReg, ARM::dsub_2, RegState::Define, TRI);
917 MIB = AddDReg(MIB, DestReg, ARM::dsub_3, RegState::Define, TRI);
918 MIB.addReg(DestReg, RegState::Define | RegState::Implicit);
921 llvm_unreachable("Unknown reg class!");
924 if (ARM::QQQQPRRegClass.hasSubClassEq(RC)) {
925 MachineInstrBuilder MIB =
926 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDMDIA))
929 MIB = AddDReg(MIB, DestReg, ARM::dsub_0, RegState::Define, TRI);
930 MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::Define, TRI);
931 MIB = AddDReg(MIB, DestReg, ARM::dsub_2, RegState::Define, TRI);
932 MIB = AddDReg(MIB, DestReg, ARM::dsub_3, RegState::Define, TRI);
933 MIB = AddDReg(MIB, DestReg, ARM::dsub_4, RegState::Define, TRI);
934 MIB = AddDReg(MIB, DestReg, ARM::dsub_5, RegState::Define, TRI);
935 MIB = AddDReg(MIB, DestReg, ARM::dsub_6, RegState::Define, TRI);
936 MIB = AddDReg(MIB, DestReg, ARM::dsub_7, RegState::Define, TRI);
937 MIB.addReg(DestReg, RegState::Define | RegState::Implicit);
939 llvm_unreachable("Unknown reg class!");
942 llvm_unreachable("Unknown regclass!");
947 ARMBaseInstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
948 int &FrameIndex) const {
949 switch (MI->getOpcode()) {
952 case ARM::t2LDRs: // FIXME: don't use t2LDRs to access frame.
953 if (MI->getOperand(1).isFI() &&
954 MI->getOperand(2).isReg() &&
955 MI->getOperand(3).isImm() &&
956 MI->getOperand(2).getReg() == 0 &&
957 MI->getOperand(3).getImm() == 0) {
958 FrameIndex = MI->getOperand(1).getIndex();
959 return MI->getOperand(0).getReg();
967 if (MI->getOperand(1).isFI() &&
968 MI->getOperand(2).isImm() &&
969 MI->getOperand(2).getImm() == 0) {
970 FrameIndex = MI->getOperand(1).getIndex();
971 return MI->getOperand(0).getReg();
974 case ARM::VLD1q64Pseudo:
975 if (MI->getOperand(1).isFI() &&
976 MI->getOperand(0).getSubReg() == 0) {
977 FrameIndex = MI->getOperand(1).getIndex();
978 return MI->getOperand(0).getReg();
982 if (MI->getOperand(1).isFI() &&
983 MI->getOperand(0).getSubReg() == 0) {
984 FrameIndex = MI->getOperand(1).getIndex();
985 return MI->getOperand(0).getReg();
993 unsigned ARMBaseInstrInfo::isLoadFromStackSlotPostFE(const MachineInstr *MI,
994 int &FrameIndex) const {
995 const MachineMemOperand *Dummy;
996 return MI->getDesc().mayLoad() && hasLoadFromStackSlot(MI, Dummy, FrameIndex);
999 bool ARMBaseInstrInfo::expandPostRAPseudo(MachineBasicBlock::iterator MI) const{
1000 // This hook gets to expand COPY instructions before they become
1001 // copyPhysReg() calls. Look for VMOVS instructions that can legally be
1002 // widened to VMOVD. We prefer the VMOVD when possible because it may be
1003 // changed into a VORR that can go down the NEON pipeline.
1004 if (!WidenVMOVS || !MI->isCopy())
1007 // Look for a copy between even S-registers. That is where we keep floats
1008 // when using NEON v2f32 instructions for f32 arithmetic.
1009 unsigned DstRegS = MI->getOperand(0).getReg();
1010 unsigned SrcRegS = MI->getOperand(1).getReg();
1011 if (!ARM::SPRRegClass.contains(DstRegS, SrcRegS))
1014 const TargetRegisterInfo *TRI = &getRegisterInfo();
1015 unsigned DstRegD = TRI->getMatchingSuperReg(DstRegS, ARM::ssub_0,
1017 unsigned SrcRegD = TRI->getMatchingSuperReg(SrcRegS, ARM::ssub_0,
1019 if (!DstRegD || !SrcRegD)
1022 // We want to widen this into a DstRegD = VMOVD SrcRegD copy. This is only
1023 // legal if the COPY already defines the full DstRegD, and it isn't a
1024 // sub-register insertion.
1025 if (!MI->definesRegister(DstRegD, TRI) || MI->readsRegister(DstRegD, TRI))
1028 // A dead copy shouldn't show up here, but reject it just in case.
1029 if (MI->getOperand(0).isDead())
1032 // All clear, widen the COPY.
1033 DEBUG(dbgs() << "widening: " << *MI);
1035 // Get rid of the old <imp-def> of DstRegD. Leave it if it defines a Q-reg
1036 // or some other super-register.
1037 int ImpDefIdx = MI->findRegisterDefOperandIdx(DstRegD);
1038 if (ImpDefIdx != -1)
1039 MI->RemoveOperand(ImpDefIdx);
1041 // Change the opcode and operands.
1042 MI->setDesc(get(ARM::VMOVD));
1043 MI->getOperand(0).setReg(DstRegD);
1044 MI->getOperand(1).setReg(SrcRegD);
1045 AddDefaultPred(MachineInstrBuilder(MI));
1047 // We are now reading SrcRegD instead of SrcRegS. This may upset the
1048 // register scavenger and machine verifier, so we need to indicate that we
1049 // are reading an undefined value from SrcRegD, but a proper value from
1051 MI->getOperand(1).setIsUndef();
1052 MachineInstrBuilder(MI).addReg(SrcRegS, RegState::Implicit);
1054 // SrcRegD may actually contain an unrelated value in the ssub_1
1055 // sub-register. Don't kill it. Only kill the ssub_0 sub-register.
1056 if (MI->getOperand(1).isKill()) {
1057 MI->getOperand(1).setIsKill(false);
1058 MI->addRegisterKilled(SrcRegS, TRI, true);
1061 DEBUG(dbgs() << "replaced by: " << *MI);
1066 ARMBaseInstrInfo::emitFrameIndexDebugValue(MachineFunction &MF,
1067 int FrameIx, uint64_t Offset,
1068 const MDNode *MDPtr,
1069 DebugLoc DL) const {
1070 MachineInstrBuilder MIB = BuildMI(MF, DL, get(ARM::DBG_VALUE))
1071 .addFrameIndex(FrameIx).addImm(0).addImm(Offset).addMetadata(MDPtr);
1075 /// Create a copy of a const pool value. Update CPI to the new index and return
1077 static unsigned duplicateCPV(MachineFunction &MF, unsigned &CPI) {
1078 MachineConstantPool *MCP = MF.getConstantPool();
1079 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1081 const MachineConstantPoolEntry &MCPE = MCP->getConstants()[CPI];
1082 assert(MCPE.isMachineConstantPoolEntry() &&
1083 "Expecting a machine constantpool entry!");
1084 ARMConstantPoolValue *ACPV =
1085 static_cast<ARMConstantPoolValue*>(MCPE.Val.MachineCPVal);
1087 unsigned PCLabelId = AFI->createPICLabelUId();
1088 ARMConstantPoolValue *NewCPV = 0;
1089 // FIXME: The below assumes PIC relocation model and that the function
1090 // is Thumb mode (t1 or t2). PCAdjustment would be 8 for ARM mode PIC, and
1091 // zero for non-PIC in ARM or Thumb. The callers are all of thumb LDR
1092 // instructions, so that's probably OK, but is PIC always correct when
1094 if (ACPV->isGlobalValue())
1095 NewCPV = ARMConstantPoolConstant::
1096 Create(cast<ARMConstantPoolConstant>(ACPV)->getGV(), PCLabelId,
1098 else if (ACPV->isExtSymbol())
1099 NewCPV = ARMConstantPoolSymbol::
1100 Create(MF.getFunction()->getContext(),
1101 cast<ARMConstantPoolSymbol>(ACPV)->getSymbol(), PCLabelId, 4);
1102 else if (ACPV->isBlockAddress())
1103 NewCPV = ARMConstantPoolConstant::
1104 Create(cast<ARMConstantPoolConstant>(ACPV)->getBlockAddress(), PCLabelId,
1105 ARMCP::CPBlockAddress, 4);
1106 else if (ACPV->isLSDA())
1107 NewCPV = ARMConstantPoolConstant::Create(MF.getFunction(), PCLabelId,
1109 else if (ACPV->isMachineBasicBlock())
1110 NewCPV = ARMConstantPoolMBB::
1111 Create(MF.getFunction()->getContext(),
1112 cast<ARMConstantPoolMBB>(ACPV)->getMBB(), PCLabelId, 4);
1114 llvm_unreachable("Unexpected ARM constantpool value type!!");
1115 CPI = MCP->getConstantPoolIndex(NewCPV, MCPE.getAlignment());
1119 void ARMBaseInstrInfo::
1120 reMaterialize(MachineBasicBlock &MBB,
1121 MachineBasicBlock::iterator I,
1122 unsigned DestReg, unsigned SubIdx,
1123 const MachineInstr *Orig,
1124 const TargetRegisterInfo &TRI) const {
1125 unsigned Opcode = Orig->getOpcode();
1128 MachineInstr *MI = MBB.getParent()->CloneMachineInstr(Orig);
1129 MI->substituteRegister(Orig->getOperand(0).getReg(), DestReg, SubIdx, TRI);
1133 case ARM::tLDRpci_pic:
1134 case ARM::t2LDRpci_pic: {
1135 MachineFunction &MF = *MBB.getParent();
1136 unsigned CPI = Orig->getOperand(1).getIndex();
1137 unsigned PCLabelId = duplicateCPV(MF, CPI);
1138 MachineInstrBuilder MIB = BuildMI(MBB, I, Orig->getDebugLoc(), get(Opcode),
1140 .addConstantPoolIndex(CPI).addImm(PCLabelId);
1141 MIB->setMemRefs(Orig->memoperands_begin(), Orig->memoperands_end());
1148 ARMBaseInstrInfo::duplicate(MachineInstr *Orig, MachineFunction &MF) const {
1149 MachineInstr *MI = TargetInstrInfoImpl::duplicate(Orig, MF);
1150 switch(Orig->getOpcode()) {
1151 case ARM::tLDRpci_pic:
1152 case ARM::t2LDRpci_pic: {
1153 unsigned CPI = Orig->getOperand(1).getIndex();
1154 unsigned PCLabelId = duplicateCPV(MF, CPI);
1155 Orig->getOperand(1).setIndex(CPI);
1156 Orig->getOperand(2).setImm(PCLabelId);
1163 bool ARMBaseInstrInfo::produceSameValue(const MachineInstr *MI0,
1164 const MachineInstr *MI1,
1165 const MachineRegisterInfo *MRI) const {
1166 int Opcode = MI0->getOpcode();
1167 if (Opcode == ARM::t2LDRpci ||
1168 Opcode == ARM::t2LDRpci_pic ||
1169 Opcode == ARM::tLDRpci ||
1170 Opcode == ARM::tLDRpci_pic ||
1171 Opcode == ARM::MOV_ga_dyn ||
1172 Opcode == ARM::MOV_ga_pcrel ||
1173 Opcode == ARM::MOV_ga_pcrel_ldr ||
1174 Opcode == ARM::t2MOV_ga_dyn ||
1175 Opcode == ARM::t2MOV_ga_pcrel) {
1176 if (MI1->getOpcode() != Opcode)
1178 if (MI0->getNumOperands() != MI1->getNumOperands())
1181 const MachineOperand &MO0 = MI0->getOperand(1);
1182 const MachineOperand &MO1 = MI1->getOperand(1);
1183 if (MO0.getOffset() != MO1.getOffset())
1186 if (Opcode == ARM::MOV_ga_dyn ||
1187 Opcode == ARM::MOV_ga_pcrel ||
1188 Opcode == ARM::MOV_ga_pcrel_ldr ||
1189 Opcode == ARM::t2MOV_ga_dyn ||
1190 Opcode == ARM::t2MOV_ga_pcrel)
1191 // Ignore the PC labels.
1192 return MO0.getGlobal() == MO1.getGlobal();
1194 const MachineFunction *MF = MI0->getParent()->getParent();
1195 const MachineConstantPool *MCP = MF->getConstantPool();
1196 int CPI0 = MO0.getIndex();
1197 int CPI1 = MO1.getIndex();
1198 const MachineConstantPoolEntry &MCPE0 = MCP->getConstants()[CPI0];
1199 const MachineConstantPoolEntry &MCPE1 = MCP->getConstants()[CPI1];
1200 bool isARMCP0 = MCPE0.isMachineConstantPoolEntry();
1201 bool isARMCP1 = MCPE1.isMachineConstantPoolEntry();
1202 if (isARMCP0 && isARMCP1) {
1203 ARMConstantPoolValue *ACPV0 =
1204 static_cast<ARMConstantPoolValue*>(MCPE0.Val.MachineCPVal);
1205 ARMConstantPoolValue *ACPV1 =
1206 static_cast<ARMConstantPoolValue*>(MCPE1.Val.MachineCPVal);
1207 return ACPV0->hasSameValue(ACPV1);
1208 } else if (!isARMCP0 && !isARMCP1) {
1209 return MCPE0.Val.ConstVal == MCPE1.Val.ConstVal;
1212 } else if (Opcode == ARM::PICLDR) {
1213 if (MI1->getOpcode() != Opcode)
1215 if (MI0->getNumOperands() != MI1->getNumOperands())
1218 unsigned Addr0 = MI0->getOperand(1).getReg();
1219 unsigned Addr1 = MI1->getOperand(1).getReg();
1220 if (Addr0 != Addr1) {
1222 !TargetRegisterInfo::isVirtualRegister(Addr0) ||
1223 !TargetRegisterInfo::isVirtualRegister(Addr1))
1226 // This assumes SSA form.
1227 MachineInstr *Def0 = MRI->getVRegDef(Addr0);
1228 MachineInstr *Def1 = MRI->getVRegDef(Addr1);
1229 // Check if the loaded value, e.g. a constantpool of a global address, are
1231 if (!produceSameValue(Def0, Def1, MRI))
1235 for (unsigned i = 3, e = MI0->getNumOperands(); i != e; ++i) {
1236 // %vreg12<def> = PICLDR %vreg11, 0, pred:14, pred:%noreg
1237 const MachineOperand &MO0 = MI0->getOperand(i);
1238 const MachineOperand &MO1 = MI1->getOperand(i);
1239 if (!MO0.isIdenticalTo(MO1))
1245 return MI0->isIdenticalTo(MI1, MachineInstr::IgnoreVRegDefs);
1248 /// areLoadsFromSameBasePtr - This is used by the pre-regalloc scheduler to
1249 /// determine if two loads are loading from the same base address. It should
1250 /// only return true if the base pointers are the same and the only differences
1251 /// between the two addresses is the offset. It also returns the offsets by
1253 bool ARMBaseInstrInfo::areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2,
1255 int64_t &Offset2) const {
1256 // Don't worry about Thumb: just ARM and Thumb2.
1257 if (Subtarget.isThumb1Only()) return false;
1259 if (!Load1->isMachineOpcode() || !Load2->isMachineOpcode())
1262 switch (Load1->getMachineOpcode()) {
1275 case ARM::t2LDRSHi8:
1277 case ARM::t2LDRSHi12:
1281 switch (Load2->getMachineOpcode()) {
1294 case ARM::t2LDRSHi8:
1296 case ARM::t2LDRSHi12:
1300 // Check if base addresses and chain operands match.
1301 if (Load1->getOperand(0) != Load2->getOperand(0) ||
1302 Load1->getOperand(4) != Load2->getOperand(4))
1305 // Index should be Reg0.
1306 if (Load1->getOperand(3) != Load2->getOperand(3))
1309 // Determine the offsets.
1310 if (isa<ConstantSDNode>(Load1->getOperand(1)) &&
1311 isa<ConstantSDNode>(Load2->getOperand(1))) {
1312 Offset1 = cast<ConstantSDNode>(Load1->getOperand(1))->getSExtValue();
1313 Offset2 = cast<ConstantSDNode>(Load2->getOperand(1))->getSExtValue();
1320 /// shouldScheduleLoadsNear - This is a used by the pre-regalloc scheduler to
1321 /// determine (in conjunction with areLoadsFromSameBasePtr) if two loads should
1322 /// be scheduled togther. On some targets if two loads are loading from
1323 /// addresses in the same cache line, it's better if they are scheduled
1324 /// together. This function takes two integers that represent the load offsets
1325 /// from the common base address. It returns true if it decides it's desirable
1326 /// to schedule the two loads together. "NumLoads" is the number of loads that
1327 /// have already been scheduled after Load1.
1328 bool ARMBaseInstrInfo::shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,
1329 int64_t Offset1, int64_t Offset2,
1330 unsigned NumLoads) const {
1331 // Don't worry about Thumb: just ARM and Thumb2.
1332 if (Subtarget.isThumb1Only()) return false;
1334 assert(Offset2 > Offset1);
1336 if ((Offset2 - Offset1) / 8 > 64)
1339 if (Load1->getMachineOpcode() != Load2->getMachineOpcode())
1340 return false; // FIXME: overly conservative?
1342 // Four loads in a row should be sufficient.
1349 bool ARMBaseInstrInfo::isSchedulingBoundary(const MachineInstr *MI,
1350 const MachineBasicBlock *MBB,
1351 const MachineFunction &MF) const {
1352 // Debug info is never a scheduling boundary. It's necessary to be explicit
1353 // due to the special treatment of IT instructions below, otherwise a
1354 // dbg_value followed by an IT will result in the IT instruction being
1355 // considered a scheduling hazard, which is wrong. It should be the actual
1356 // instruction preceding the dbg_value instruction(s), just like it is
1357 // when debug info is not present.
1358 if (MI->isDebugValue())
1361 // Terminators and labels can't be scheduled around.
1362 if (MI->getDesc().isTerminator() || MI->isLabel())
1365 // Treat the start of the IT block as a scheduling boundary, but schedule
1366 // t2IT along with all instructions following it.
1367 // FIXME: This is a big hammer. But the alternative is to add all potential
1368 // true and anti dependencies to IT block instructions as implicit operands
1369 // to the t2IT instruction. The added compile time and complexity does not
1371 MachineBasicBlock::const_iterator I = MI;
1372 // Make sure to skip any dbg_value instructions
1373 while (++I != MBB->end() && I->isDebugValue())
1375 if (I != MBB->end() && I->getOpcode() == ARM::t2IT)
1378 // Don't attempt to schedule around any instruction that defines
1379 // a stack-oriented pointer, as it's unlikely to be profitable. This
1380 // saves compile time, because it doesn't require every single
1381 // stack slot reference to depend on the instruction that does the
1383 if (MI->definesRegister(ARM::SP))
1389 bool ARMBaseInstrInfo::
1390 isProfitableToIfCvt(MachineBasicBlock &MBB,
1391 unsigned NumCycles, unsigned ExtraPredCycles,
1392 const BranchProbability &Probability) const {
1396 // Attempt to estimate the relative costs of predication versus branching.
1397 unsigned UnpredCost = Probability.getNumerator() * NumCycles;
1398 UnpredCost /= Probability.getDenominator();
1399 UnpredCost += 1; // The branch itself
1400 UnpredCost += Subtarget.getMispredictionPenalty() / 10;
1402 return (NumCycles + ExtraPredCycles) <= UnpredCost;
1405 bool ARMBaseInstrInfo::
1406 isProfitableToIfCvt(MachineBasicBlock &TMBB,
1407 unsigned TCycles, unsigned TExtra,
1408 MachineBasicBlock &FMBB,
1409 unsigned FCycles, unsigned FExtra,
1410 const BranchProbability &Probability) const {
1411 if (!TCycles || !FCycles)
1414 // Attempt to estimate the relative costs of predication versus branching.
1415 unsigned TUnpredCost = Probability.getNumerator() * TCycles;
1416 TUnpredCost /= Probability.getDenominator();
1418 uint32_t Comp = Probability.getDenominator() - Probability.getNumerator();
1419 unsigned FUnpredCost = Comp * FCycles;
1420 FUnpredCost /= Probability.getDenominator();
1422 unsigned UnpredCost = TUnpredCost + FUnpredCost;
1423 UnpredCost += 1; // The branch itself
1424 UnpredCost += Subtarget.getMispredictionPenalty() / 10;
1426 return (TCycles + FCycles + TExtra + FExtra) <= UnpredCost;
1429 /// getInstrPredicate - If instruction is predicated, returns its predicate
1430 /// condition, otherwise returns AL. It also returns the condition code
1431 /// register by reference.
1433 llvm::getInstrPredicate(const MachineInstr *MI, unsigned &PredReg) {
1434 int PIdx = MI->findFirstPredOperandIdx();
1440 PredReg = MI->getOperand(PIdx+1).getReg();
1441 return (ARMCC::CondCodes)MI->getOperand(PIdx).getImm();
1445 int llvm::getMatchingCondBranchOpcode(int Opc) {
1448 else if (Opc == ARM::tB)
1450 else if (Opc == ARM::t2B)
1453 llvm_unreachable("Unknown unconditional branch opcode!");
1458 /// Map pseudo instructions that imply an 'S' bit onto real opcodes. Whether the
1459 /// instruction is encoded with an 'S' bit is determined by the optional CPSR
1462 /// This will go away once we can teach tblgen how to set the optional CPSR def
1464 struct AddSubFlagsOpcodePair {
1466 unsigned MachineOpc;
1469 static AddSubFlagsOpcodePair AddSubFlagsOpcodeMap[] = {
1470 {ARM::ADDSri, ARM::ADDri},
1471 {ARM::ADDSrr, ARM::ADDrr},
1472 {ARM::ADDSrsi, ARM::ADDrsi},
1473 {ARM::ADDSrsr, ARM::ADDrsr},
1475 {ARM::SUBSri, ARM::SUBri},
1476 {ARM::SUBSrr, ARM::SUBrr},
1477 {ARM::SUBSrsi, ARM::SUBrsi},
1478 {ARM::SUBSrsr, ARM::SUBrsr},
1480 {ARM::RSBSri, ARM::RSBri},
1481 {ARM::RSBSrsi, ARM::RSBrsi},
1482 {ARM::RSBSrsr, ARM::RSBrsr},
1484 {ARM::t2ADDSri, ARM::t2ADDri},
1485 {ARM::t2ADDSrr, ARM::t2ADDrr},
1486 {ARM::t2ADDSrs, ARM::t2ADDrs},
1488 {ARM::t2SUBSri, ARM::t2SUBri},
1489 {ARM::t2SUBSrr, ARM::t2SUBrr},
1490 {ARM::t2SUBSrs, ARM::t2SUBrs},
1492 {ARM::t2RSBSri, ARM::t2RSBri},
1493 {ARM::t2RSBSrs, ARM::t2RSBrs},
1496 unsigned llvm::convertAddSubFlagsOpcode(unsigned OldOpc) {
1497 static const int NPairs =
1498 sizeof(AddSubFlagsOpcodeMap) / sizeof(AddSubFlagsOpcodePair);
1499 for (AddSubFlagsOpcodePair *OpcPair = &AddSubFlagsOpcodeMap[0],
1500 *End = &AddSubFlagsOpcodeMap[NPairs]; OpcPair != End; ++OpcPair) {
1501 if (OldOpc == OpcPair->PseudoOpc) {
1502 return OpcPair->MachineOpc;
1508 void llvm::emitARMRegPlusImmediate(MachineBasicBlock &MBB,
1509 MachineBasicBlock::iterator &MBBI, DebugLoc dl,
1510 unsigned DestReg, unsigned BaseReg, int NumBytes,
1511 ARMCC::CondCodes Pred, unsigned PredReg,
1512 const ARMBaseInstrInfo &TII, unsigned MIFlags) {
1513 bool isSub = NumBytes < 0;
1514 if (isSub) NumBytes = -NumBytes;
1517 unsigned RotAmt = ARM_AM::getSOImmValRotate(NumBytes);
1518 unsigned ThisVal = NumBytes & ARM_AM::rotr32(0xFF, RotAmt);
1519 assert(ThisVal && "Didn't extract field correctly");
1521 // We will handle these bits from offset, clear them.
1522 NumBytes &= ~ThisVal;
1524 assert(ARM_AM::getSOImmVal(ThisVal) != -1 && "Bit extraction didn't work?");
1526 // Build the new ADD / SUB.
1527 unsigned Opc = isSub ? ARM::SUBri : ARM::ADDri;
1528 BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg)
1529 .addReg(BaseReg, RegState::Kill).addImm(ThisVal)
1530 .addImm((unsigned)Pred).addReg(PredReg).addReg(0)
1531 .setMIFlags(MIFlags);
1536 bool llvm::rewriteARMFrameIndex(MachineInstr &MI, unsigned FrameRegIdx,
1537 unsigned FrameReg, int &Offset,
1538 const ARMBaseInstrInfo &TII) {
1539 unsigned Opcode = MI.getOpcode();
1540 const MCInstrDesc &Desc = MI.getDesc();
1541 unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
1544 // Memory operands in inline assembly always use AddrMode2.
1545 if (Opcode == ARM::INLINEASM)
1546 AddrMode = ARMII::AddrMode2;
1548 if (Opcode == ARM::ADDri) {
1549 Offset += MI.getOperand(FrameRegIdx+1).getImm();
1551 // Turn it into a move.
1552 MI.setDesc(TII.get(ARM::MOVr));
1553 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
1554 MI.RemoveOperand(FrameRegIdx+1);
1557 } else if (Offset < 0) {
1560 MI.setDesc(TII.get(ARM::SUBri));
1563 // Common case: small offset, fits into instruction.
1564 if (ARM_AM::getSOImmVal(Offset) != -1) {
1565 // Replace the FrameIndex with sp / fp
1566 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
1567 MI.getOperand(FrameRegIdx+1).ChangeToImmediate(Offset);
1572 // Otherwise, pull as much of the immedidate into this ADDri/SUBri
1574 unsigned RotAmt = ARM_AM::getSOImmValRotate(Offset);
1575 unsigned ThisImmVal = Offset & ARM_AM::rotr32(0xFF, RotAmt);
1577 // We will handle these bits from offset, clear them.
1578 Offset &= ~ThisImmVal;
1580 // Get the properly encoded SOImmVal field.
1581 assert(ARM_AM::getSOImmVal(ThisImmVal) != -1 &&
1582 "Bit extraction didn't work?");
1583 MI.getOperand(FrameRegIdx+1).ChangeToImmediate(ThisImmVal);
1585 unsigned ImmIdx = 0;
1587 unsigned NumBits = 0;
1590 case ARMII::AddrMode_i12: {
1591 ImmIdx = FrameRegIdx + 1;
1592 InstrOffs = MI.getOperand(ImmIdx).getImm();
1596 case ARMII::AddrMode2: {
1597 ImmIdx = FrameRegIdx+2;
1598 InstrOffs = ARM_AM::getAM2Offset(MI.getOperand(ImmIdx).getImm());
1599 if (ARM_AM::getAM2Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub)
1604 case ARMII::AddrMode3: {
1605 ImmIdx = FrameRegIdx+2;
1606 InstrOffs = ARM_AM::getAM3Offset(MI.getOperand(ImmIdx).getImm());
1607 if (ARM_AM::getAM3Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub)
1612 case ARMII::AddrMode4:
1613 case ARMII::AddrMode6:
1614 // Can't fold any offset even if it's zero.
1616 case ARMII::AddrMode5: {
1617 ImmIdx = FrameRegIdx+1;
1618 InstrOffs = ARM_AM::getAM5Offset(MI.getOperand(ImmIdx).getImm());
1619 if (ARM_AM::getAM5Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub)
1626 llvm_unreachable("Unsupported addressing mode!");
1630 Offset += InstrOffs * Scale;
1631 assert((Offset & (Scale-1)) == 0 && "Can't encode this offset!");
1637 // Attempt to fold address comp. if opcode has offset bits
1639 // Common case: small offset, fits into instruction.
1640 MachineOperand &ImmOp = MI.getOperand(ImmIdx);
1641 int ImmedOffset = Offset / Scale;
1642 unsigned Mask = (1 << NumBits) - 1;
1643 if ((unsigned)Offset <= Mask * Scale) {
1644 // Replace the FrameIndex with sp
1645 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
1646 // FIXME: When addrmode2 goes away, this will simplify (like the
1647 // T2 version), as the LDR.i12 versions don't need the encoding
1648 // tricks for the offset value.
1650 if (AddrMode == ARMII::AddrMode_i12)
1651 ImmedOffset = -ImmedOffset;
1653 ImmedOffset |= 1 << NumBits;
1655 ImmOp.ChangeToImmediate(ImmedOffset);
1660 // Otherwise, it didn't fit. Pull in what we can to simplify the immed.
1661 ImmedOffset = ImmedOffset & Mask;
1663 if (AddrMode == ARMII::AddrMode_i12)
1664 ImmedOffset = -ImmedOffset;
1666 ImmedOffset |= 1 << NumBits;
1668 ImmOp.ChangeToImmediate(ImmedOffset);
1669 Offset &= ~(Mask*Scale);
1673 Offset = (isSub) ? -Offset : Offset;
1677 bool ARMBaseInstrInfo::
1678 AnalyzeCompare(const MachineInstr *MI, unsigned &SrcReg, int &CmpMask,
1679 int &CmpValue) const {
1680 switch (MI->getOpcode()) {
1684 SrcReg = MI->getOperand(0).getReg();
1686 CmpValue = MI->getOperand(1).getImm();
1690 SrcReg = MI->getOperand(0).getReg();
1691 CmpMask = MI->getOperand(1).getImm();
1699 /// isSuitableForMask - Identify a suitable 'and' instruction that
1700 /// operates on the given source register and applies the same mask
1701 /// as a 'tst' instruction. Provide a limited look-through for copies.
1702 /// When successful, MI will hold the found instruction.
1703 static bool isSuitableForMask(MachineInstr *&MI, unsigned SrcReg,
1704 int CmpMask, bool CommonUse) {
1705 switch (MI->getOpcode()) {
1708 if (CmpMask != MI->getOperand(2).getImm())
1710 if (SrcReg == MI->getOperand(CommonUse ? 1 : 0).getReg())
1714 // Walk down one instruction which is potentially an 'and'.
1715 const MachineInstr &Copy = *MI;
1716 MachineBasicBlock::iterator AND(
1717 llvm::next(MachineBasicBlock::iterator(MI)));
1718 if (AND == MI->getParent()->end()) return false;
1720 return isSuitableForMask(MI, Copy.getOperand(0).getReg(),
1728 /// OptimizeCompareInstr - Convert the instruction supplying the argument to the
1729 /// comparison into one that sets the zero bit in the flags register.
1730 bool ARMBaseInstrInfo::
1731 OptimizeCompareInstr(MachineInstr *CmpInstr, unsigned SrcReg, int CmpMask,
1732 int CmpValue, const MachineRegisterInfo *MRI) const {
1736 MachineRegisterInfo::def_iterator DI = MRI->def_begin(SrcReg);
1737 if (llvm::next(DI) != MRI->def_end())
1738 // Only support one definition.
1741 MachineInstr *MI = &*DI;
1743 // Masked compares sometimes use the same register as the corresponding 'and'.
1744 if (CmpMask != ~0) {
1745 if (!isSuitableForMask(MI, SrcReg, CmpMask, false)) {
1747 for (MachineRegisterInfo::use_iterator UI = MRI->use_begin(SrcReg),
1748 UE = MRI->use_end(); UI != UE; ++UI) {
1749 if (UI->getParent() != CmpInstr->getParent()) continue;
1750 MachineInstr *PotentialAND = &*UI;
1751 if (!isSuitableForMask(PotentialAND, SrcReg, CmpMask, true))
1756 if (!MI) return false;
1760 // Conservatively refuse to convert an instruction which isn't in the same BB
1761 // as the comparison.
1762 if (MI->getParent() != CmpInstr->getParent())
1765 // Check that CPSR isn't set between the comparison instruction and the one we
1767 MachineBasicBlock::const_iterator I = CmpInstr, E = MI,
1768 B = MI->getParent()->begin();
1770 // Early exit if CmpInstr is at the beginning of the BB.
1771 if (I == B) return false;
1774 for (; I != E; --I) {
1775 const MachineInstr &Instr = *I;
1777 for (unsigned IO = 0, EO = Instr.getNumOperands(); IO != EO; ++IO) {
1778 const MachineOperand &MO = Instr.getOperand(IO);
1779 if (!MO.isReg()) continue;
1781 // This instruction modifies or uses CPSR after the one we want to
1782 // change. We can't do this transformation.
1783 if (MO.getReg() == ARM::CPSR)
1788 // The 'and' is below the comparison instruction.
1792 // Set the "zero" bit in CPSR.
1793 switch (MI->getOpcode()) {
1827 case ARM::t2EORri: {
1828 // Scan forward for the use of CPSR, if it's a conditional code requires
1829 // checking of V bit, then this is not safe to do. If we can't find the
1830 // CPSR use (i.e. used in another block), then it's not safe to perform
1831 // the optimization.
1832 bool isSafe = false;
1834 E = MI->getParent()->end();
1835 while (!isSafe && ++I != E) {
1836 const MachineInstr &Instr = *I;
1837 for (unsigned IO = 0, EO = Instr.getNumOperands();
1838 !isSafe && IO != EO; ++IO) {
1839 const MachineOperand &MO = Instr.getOperand(IO);
1840 if (!MO.isReg() || MO.getReg() != ARM::CPSR)
1846 // Condition code is after the operand before CPSR.
1847 ARMCC::CondCodes CC = (ARMCC::CondCodes)Instr.getOperand(IO-1).getImm();
1866 // Toggle the optional operand to CPSR.
1867 MI->getOperand(5).setReg(ARM::CPSR);
1868 MI->getOperand(5).setIsDef(true);
1869 CmpInstr->eraseFromParent();
1877 bool ARMBaseInstrInfo::FoldImmediate(MachineInstr *UseMI,
1878 MachineInstr *DefMI, unsigned Reg,
1879 MachineRegisterInfo *MRI) const {
1880 // Fold large immediates into add, sub, or, xor.
1881 unsigned DefOpc = DefMI->getOpcode();
1882 if (DefOpc != ARM::t2MOVi32imm && DefOpc != ARM::MOVi32imm)
1884 if (!DefMI->getOperand(1).isImm())
1885 // Could be t2MOVi32imm <ga:xx>
1888 if (!MRI->hasOneNonDBGUse(Reg))
1891 unsigned UseOpc = UseMI->getOpcode();
1892 unsigned NewUseOpc = 0;
1893 uint32_t ImmVal = (uint32_t)DefMI->getOperand(1).getImm();
1894 uint32_t SOImmValV1 = 0, SOImmValV2 = 0;
1895 bool Commute = false;
1897 default: return false;
1905 case ARM::t2EORrr: {
1906 Commute = UseMI->getOperand(2).getReg() != Reg;
1913 NewUseOpc = ARM::SUBri;
1919 if (!ARM_AM::isSOImmTwoPartVal(ImmVal))
1921 SOImmValV1 = (uint32_t)ARM_AM::getSOImmTwoPartFirst(ImmVal);
1922 SOImmValV2 = (uint32_t)ARM_AM::getSOImmTwoPartSecond(ImmVal);
1925 case ARM::ADDrr: NewUseOpc = ARM::ADDri; break;
1926 case ARM::ORRrr: NewUseOpc = ARM::ORRri; break;
1927 case ARM::EORrr: NewUseOpc = ARM::EORri; break;
1931 case ARM::t2SUBrr: {
1935 NewUseOpc = ARM::t2SUBri;
1940 case ARM::t2EORrr: {
1941 if (!ARM_AM::isT2SOImmTwoPartVal(ImmVal))
1943 SOImmValV1 = (uint32_t)ARM_AM::getT2SOImmTwoPartFirst(ImmVal);
1944 SOImmValV2 = (uint32_t)ARM_AM::getT2SOImmTwoPartSecond(ImmVal);
1947 case ARM::t2ADDrr: NewUseOpc = ARM::t2ADDri; break;
1948 case ARM::t2ORRrr: NewUseOpc = ARM::t2ORRri; break;
1949 case ARM::t2EORrr: NewUseOpc = ARM::t2EORri; break;
1957 unsigned OpIdx = Commute ? 2 : 1;
1958 unsigned Reg1 = UseMI->getOperand(OpIdx).getReg();
1959 bool isKill = UseMI->getOperand(OpIdx).isKill();
1960 unsigned NewReg = MRI->createVirtualRegister(MRI->getRegClass(Reg));
1961 AddDefaultCC(AddDefaultPred(BuildMI(*UseMI->getParent(),
1962 *UseMI, UseMI->getDebugLoc(),
1963 get(NewUseOpc), NewReg)
1964 .addReg(Reg1, getKillRegState(isKill))
1965 .addImm(SOImmValV1)));
1966 UseMI->setDesc(get(NewUseOpc));
1967 UseMI->getOperand(1).setReg(NewReg);
1968 UseMI->getOperand(1).setIsKill();
1969 UseMI->getOperand(2).ChangeToImmediate(SOImmValV2);
1970 DefMI->eraseFromParent();
1975 ARMBaseInstrInfo::getNumMicroOps(const InstrItineraryData *ItinData,
1976 const MachineInstr *MI) const {
1977 if (!ItinData || ItinData->isEmpty())
1980 const MCInstrDesc &Desc = MI->getDesc();
1981 unsigned Class = Desc.getSchedClass();
1982 unsigned UOps = ItinData->Itineraries[Class].NumMicroOps;
1986 unsigned Opc = MI->getOpcode();
1989 llvm_unreachable("Unexpected multi-uops instruction!");
1995 // The number of uOps for load / store multiple are determined by the number
1998 // On Cortex-A8, each pair of register loads / stores can be scheduled on the
1999 // same cycle. The scheduling for the first load / store must be done
2000 // separately by assuming the the address is not 64-bit aligned.
2002 // On Cortex-A9, the formula is simply (#reg / 2) + (#reg % 2). If the address
2003 // is not 64-bit aligned, then AGU would take an extra cycle. For VFP / NEON
2004 // load / store multiple, the formula is (#reg / 2) + (#reg % 2) + 1.
2006 case ARM::VLDMDIA_UPD:
2007 case ARM::VLDMDDB_UPD:
2009 case ARM::VLDMSIA_UPD:
2010 case ARM::VLDMSDB_UPD:
2012 case ARM::VSTMDIA_UPD:
2013 case ARM::VSTMDDB_UPD:
2015 case ARM::VSTMSIA_UPD:
2016 case ARM::VSTMSDB_UPD: {
2017 unsigned NumRegs = MI->getNumOperands() - Desc.getNumOperands();
2018 return (NumRegs / 2) + (NumRegs % 2) + 1;
2021 case ARM::LDMIA_RET:
2026 case ARM::LDMIA_UPD:
2027 case ARM::LDMDA_UPD:
2028 case ARM::LDMDB_UPD:
2029 case ARM::LDMIB_UPD:
2034 case ARM::STMIA_UPD:
2035 case ARM::STMDA_UPD:
2036 case ARM::STMDB_UPD:
2037 case ARM::STMIB_UPD:
2039 case ARM::tLDMIA_UPD:
2040 case ARM::tSTMIA_UPD:
2044 case ARM::t2LDMIA_RET:
2047 case ARM::t2LDMIA_UPD:
2048 case ARM::t2LDMDB_UPD:
2051 case ARM::t2STMIA_UPD:
2052 case ARM::t2STMDB_UPD: {
2053 unsigned NumRegs = MI->getNumOperands() - Desc.getNumOperands() + 1;
2054 if (Subtarget.isCortexA8()) {
2057 // 4 registers would be issued: 2, 2.
2058 // 5 registers would be issued: 2, 2, 1.
2059 UOps = (NumRegs / 2);
2063 } else if (Subtarget.isCortexA9()) {
2064 UOps = (NumRegs / 2);
2065 // If there are odd number of registers or if it's not 64-bit aligned,
2066 // then it takes an extra AGU (Address Generation Unit) cycle.
2067 if ((NumRegs % 2) ||
2068 !MI->hasOneMemOperand() ||
2069 (*MI->memoperands_begin())->getAlignment() < 8)
2073 // Assume the worst.
2081 ARMBaseInstrInfo::getVLDMDefCycle(const InstrItineraryData *ItinData,
2082 const MCInstrDesc &DefMCID,
2084 unsigned DefIdx, unsigned DefAlign) const {
2085 int RegNo = (int)(DefIdx+1) - DefMCID.getNumOperands() + 1;
2087 // Def is the address writeback.
2088 return ItinData->getOperandCycle(DefClass, DefIdx);
2091 if (Subtarget.isCortexA8()) {
2092 // (regno / 2) + (regno % 2) + 1
2093 DefCycle = RegNo / 2 + 1;
2096 } else if (Subtarget.isCortexA9()) {
2098 bool isSLoad = false;
2100 switch (DefMCID.getOpcode()) {
2103 case ARM::VLDMSIA_UPD:
2104 case ARM::VLDMSDB_UPD:
2109 // If there are odd number of 'S' registers or if it's not 64-bit aligned,
2110 // then it takes an extra cycle.
2111 if ((isSLoad && (RegNo % 2)) || DefAlign < 8)
2114 // Assume the worst.
2115 DefCycle = RegNo + 2;
2122 ARMBaseInstrInfo::getLDMDefCycle(const InstrItineraryData *ItinData,
2123 const MCInstrDesc &DefMCID,
2125 unsigned DefIdx, unsigned DefAlign) const {
2126 int RegNo = (int)(DefIdx+1) - DefMCID.getNumOperands() + 1;
2128 // Def is the address writeback.
2129 return ItinData->getOperandCycle(DefClass, DefIdx);
2132 if (Subtarget.isCortexA8()) {
2133 // 4 registers would be issued: 1, 2, 1.
2134 // 5 registers would be issued: 1, 2, 2.
2135 DefCycle = RegNo / 2;
2138 // Result latency is issue cycle + 2: E2.
2140 } else if (Subtarget.isCortexA9()) {
2141 DefCycle = (RegNo / 2);
2142 // If there are odd number of registers or if it's not 64-bit aligned,
2143 // then it takes an extra AGU (Address Generation Unit) cycle.
2144 if ((RegNo % 2) || DefAlign < 8)
2146 // Result latency is AGU cycles + 2.
2149 // Assume the worst.
2150 DefCycle = RegNo + 2;
2157 ARMBaseInstrInfo::getVSTMUseCycle(const InstrItineraryData *ItinData,
2158 const MCInstrDesc &UseMCID,
2160 unsigned UseIdx, unsigned UseAlign) const {
2161 int RegNo = (int)(UseIdx+1) - UseMCID.getNumOperands() + 1;
2163 return ItinData->getOperandCycle(UseClass, UseIdx);
2166 if (Subtarget.isCortexA8()) {
2167 // (regno / 2) + (regno % 2) + 1
2168 UseCycle = RegNo / 2 + 1;
2171 } else if (Subtarget.isCortexA9()) {
2173 bool isSStore = false;
2175 switch (UseMCID.getOpcode()) {
2178 case ARM::VSTMSIA_UPD:
2179 case ARM::VSTMSDB_UPD:
2184 // If there are odd number of 'S' registers or if it's not 64-bit aligned,
2185 // then it takes an extra cycle.
2186 if ((isSStore && (RegNo % 2)) || UseAlign < 8)
2189 // Assume the worst.
2190 UseCycle = RegNo + 2;
2197 ARMBaseInstrInfo::getSTMUseCycle(const InstrItineraryData *ItinData,
2198 const MCInstrDesc &UseMCID,
2200 unsigned UseIdx, unsigned UseAlign) const {
2201 int RegNo = (int)(UseIdx+1) - UseMCID.getNumOperands() + 1;
2203 return ItinData->getOperandCycle(UseClass, UseIdx);
2206 if (Subtarget.isCortexA8()) {
2207 UseCycle = RegNo / 2;
2212 } else if (Subtarget.isCortexA9()) {
2213 UseCycle = (RegNo / 2);
2214 // If there are odd number of registers or if it's not 64-bit aligned,
2215 // then it takes an extra AGU (Address Generation Unit) cycle.
2216 if ((RegNo % 2) || UseAlign < 8)
2219 // Assume the worst.
2226 ARMBaseInstrInfo::getOperandLatency(const InstrItineraryData *ItinData,
2227 const MCInstrDesc &DefMCID,
2228 unsigned DefIdx, unsigned DefAlign,
2229 const MCInstrDesc &UseMCID,
2230 unsigned UseIdx, unsigned UseAlign) const {
2231 unsigned DefClass = DefMCID.getSchedClass();
2232 unsigned UseClass = UseMCID.getSchedClass();
2234 if (DefIdx < DefMCID.getNumDefs() && UseIdx < UseMCID.getNumOperands())
2235 return ItinData->getOperandLatency(DefClass, DefIdx, UseClass, UseIdx);
2237 // This may be a def / use of a variable_ops instruction, the operand
2238 // latency might be determinable dynamically. Let the target try to
2241 bool LdmBypass = false;
2242 switch (DefMCID.getOpcode()) {
2244 DefCycle = ItinData->getOperandCycle(DefClass, DefIdx);
2248 case ARM::VLDMDIA_UPD:
2249 case ARM::VLDMDDB_UPD:
2251 case ARM::VLDMSIA_UPD:
2252 case ARM::VLDMSDB_UPD:
2253 DefCycle = getVLDMDefCycle(ItinData, DefMCID, DefClass, DefIdx, DefAlign);
2256 case ARM::LDMIA_RET:
2261 case ARM::LDMIA_UPD:
2262 case ARM::LDMDA_UPD:
2263 case ARM::LDMDB_UPD:
2264 case ARM::LDMIB_UPD:
2266 case ARM::tLDMIA_UPD:
2268 case ARM::t2LDMIA_RET:
2271 case ARM::t2LDMIA_UPD:
2272 case ARM::t2LDMDB_UPD:
2274 DefCycle = getLDMDefCycle(ItinData, DefMCID, DefClass, DefIdx, DefAlign);
2279 // We can't seem to determine the result latency of the def, assume it's 2.
2283 switch (UseMCID.getOpcode()) {
2285 UseCycle = ItinData->getOperandCycle(UseClass, UseIdx);
2289 case ARM::VSTMDIA_UPD:
2290 case ARM::VSTMDDB_UPD:
2292 case ARM::VSTMSIA_UPD:
2293 case ARM::VSTMSDB_UPD:
2294 UseCycle = getVSTMUseCycle(ItinData, UseMCID, UseClass, UseIdx, UseAlign);
2301 case ARM::STMIA_UPD:
2302 case ARM::STMDA_UPD:
2303 case ARM::STMDB_UPD:
2304 case ARM::STMIB_UPD:
2305 case ARM::tSTMIA_UPD:
2310 case ARM::t2STMIA_UPD:
2311 case ARM::t2STMDB_UPD:
2312 UseCycle = getSTMUseCycle(ItinData, UseMCID, UseClass, UseIdx, UseAlign);
2317 // Assume it's read in the first stage.
2320 UseCycle = DefCycle - UseCycle + 1;
2323 // It's a variable_ops instruction so we can't use DefIdx here. Just use
2324 // first def operand.
2325 if (ItinData->hasPipelineForwarding(DefClass, DefMCID.getNumOperands()-1,
2328 } else if (ItinData->hasPipelineForwarding(DefClass, DefIdx,
2329 UseClass, UseIdx)) {
2338 ARMBaseInstrInfo::getOperandLatency(const InstrItineraryData *ItinData,
2339 const MachineInstr *DefMI, unsigned DefIdx,
2340 const MachineInstr *UseMI, unsigned UseIdx) const {
2341 if (DefMI->isCopyLike() || DefMI->isInsertSubreg() ||
2342 DefMI->isRegSequence() || DefMI->isImplicitDef())
2345 const MCInstrDesc &DefMCID = DefMI->getDesc();
2346 if (!ItinData || ItinData->isEmpty())
2347 return DefMCID.mayLoad() ? 3 : 1;
2349 const MCInstrDesc &UseMCID = UseMI->getDesc();
2350 const MachineOperand &DefMO = DefMI->getOperand(DefIdx);
2351 if (DefMO.getReg() == ARM::CPSR) {
2352 if (DefMI->getOpcode() == ARM::FMSTAT) {
2353 // fpscr -> cpsr stalls over 20 cycles on A8 (and earlier?)
2354 return Subtarget.isCortexA9() ? 1 : 20;
2357 // CPSR set and branch can be paired in the same cycle.
2358 if (UseMCID.isBranch())
2362 unsigned DefAlign = DefMI->hasOneMemOperand()
2363 ? (*DefMI->memoperands_begin())->getAlignment() : 0;
2364 unsigned UseAlign = UseMI->hasOneMemOperand()
2365 ? (*UseMI->memoperands_begin())->getAlignment() : 0;
2366 int Latency = getOperandLatency(ItinData, DefMCID, DefIdx, DefAlign,
2367 UseMCID, UseIdx, UseAlign);
2370 (Subtarget.isCortexA8() || Subtarget.isCortexA9())) {
2371 // FIXME: Shifter op hack: no shift (i.e. [r +/- r]) or [r + r << 2]
2372 // variants are one cycle cheaper.
2373 switch (DefMCID.getOpcode()) {
2377 unsigned ShOpVal = DefMI->getOperand(3).getImm();
2378 unsigned ShImm = ARM_AM::getAM2Offset(ShOpVal);
2380 (ShImm == 2 && ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl))
2387 case ARM::t2LDRSHs: {
2388 // Thumb2 mode: lsl only.
2389 unsigned ShAmt = DefMI->getOperand(3).getImm();
2390 if (ShAmt == 0 || ShAmt == 2)
2397 if (DefAlign < 8 && Subtarget.isCortexA9())
2398 switch (DefMCID.getOpcode()) {
2404 case ARM::VLD1q8wb_fixed:
2405 case ARM::VLD1q16wb_fixed:
2406 case ARM::VLD1q32wb_fixed:
2407 case ARM::VLD1q64wb_fixed:
2408 case ARM::VLD1q8wb_register:
2409 case ARM::VLD1q16wb_register:
2410 case ARM::VLD1q32wb_register:
2411 case ARM::VLD1q64wb_register:
2418 case ARM::VLD2d8_UPD:
2419 case ARM::VLD2d16_UPD:
2420 case ARM::VLD2d32_UPD:
2421 case ARM::VLD2q8_UPD:
2422 case ARM::VLD2q16_UPD:
2423 case ARM::VLD2q32_UPD:
2428 case ARM::VLD3d8_UPD:
2429 case ARM::VLD3d16_UPD:
2430 case ARM::VLD3d32_UPD:
2431 case ARM::VLD1d64T_UPD:
2432 case ARM::VLD3q8_UPD:
2433 case ARM::VLD3q16_UPD:
2434 case ARM::VLD3q32_UPD:
2439 case ARM::VLD4d8_UPD:
2440 case ARM::VLD4d16_UPD:
2441 case ARM::VLD4d32_UPD:
2442 case ARM::VLD1d64Q_UPD:
2443 case ARM::VLD4q8_UPD:
2444 case ARM::VLD4q16_UPD:
2445 case ARM::VLD4q32_UPD:
2446 case ARM::VLD1DUPq8:
2447 case ARM::VLD1DUPq16:
2448 case ARM::VLD1DUPq32:
2449 case ARM::VLD1DUPq8_UPD:
2450 case ARM::VLD1DUPq16_UPD:
2451 case ARM::VLD1DUPq32_UPD:
2452 case ARM::VLD2DUPd8:
2453 case ARM::VLD2DUPd16:
2454 case ARM::VLD2DUPd32:
2455 case ARM::VLD2DUPd8_UPD:
2456 case ARM::VLD2DUPd16_UPD:
2457 case ARM::VLD2DUPd32_UPD:
2458 case ARM::VLD4DUPd8:
2459 case ARM::VLD4DUPd16:
2460 case ARM::VLD4DUPd32:
2461 case ARM::VLD4DUPd8_UPD:
2462 case ARM::VLD4DUPd16_UPD:
2463 case ARM::VLD4DUPd32_UPD:
2465 case ARM::VLD1LNd16:
2466 case ARM::VLD1LNd32:
2467 case ARM::VLD1LNd8_UPD:
2468 case ARM::VLD1LNd16_UPD:
2469 case ARM::VLD1LNd32_UPD:
2471 case ARM::VLD2LNd16:
2472 case ARM::VLD2LNd32:
2473 case ARM::VLD2LNq16:
2474 case ARM::VLD2LNq32:
2475 case ARM::VLD2LNd8_UPD:
2476 case ARM::VLD2LNd16_UPD:
2477 case ARM::VLD2LNd32_UPD:
2478 case ARM::VLD2LNq16_UPD:
2479 case ARM::VLD2LNq32_UPD:
2481 case ARM::VLD4LNd16:
2482 case ARM::VLD4LNd32:
2483 case ARM::VLD4LNq16:
2484 case ARM::VLD4LNq32:
2485 case ARM::VLD4LNd8_UPD:
2486 case ARM::VLD4LNd16_UPD:
2487 case ARM::VLD4LNd32_UPD:
2488 case ARM::VLD4LNq16_UPD:
2489 case ARM::VLD4LNq32_UPD:
2490 // If the address is not 64-bit aligned, the latencies of these
2491 // instructions increases by one.
2500 ARMBaseInstrInfo::getOperandLatency(const InstrItineraryData *ItinData,
2501 SDNode *DefNode, unsigned DefIdx,
2502 SDNode *UseNode, unsigned UseIdx) const {
2503 if (!DefNode->isMachineOpcode())
2506 const MCInstrDesc &DefMCID = get(DefNode->getMachineOpcode());
2508 if (isZeroCost(DefMCID.Opcode))
2511 if (!ItinData || ItinData->isEmpty())
2512 return DefMCID.mayLoad() ? 3 : 1;
2514 if (!UseNode->isMachineOpcode()) {
2515 int Latency = ItinData->getOperandCycle(DefMCID.getSchedClass(), DefIdx);
2516 if (Subtarget.isCortexA9())
2517 return Latency <= 2 ? 1 : Latency - 1;
2519 return Latency <= 3 ? 1 : Latency - 2;
2522 const MCInstrDesc &UseMCID = get(UseNode->getMachineOpcode());
2523 const MachineSDNode *DefMN = dyn_cast<MachineSDNode>(DefNode);
2524 unsigned DefAlign = !DefMN->memoperands_empty()
2525 ? (*DefMN->memoperands_begin())->getAlignment() : 0;
2526 const MachineSDNode *UseMN = dyn_cast<MachineSDNode>(UseNode);
2527 unsigned UseAlign = !UseMN->memoperands_empty()
2528 ? (*UseMN->memoperands_begin())->getAlignment() : 0;
2529 int Latency = getOperandLatency(ItinData, DefMCID, DefIdx, DefAlign,
2530 UseMCID, UseIdx, UseAlign);
2533 (Subtarget.isCortexA8() || Subtarget.isCortexA9())) {
2534 // FIXME: Shifter op hack: no shift (i.e. [r +/- r]) or [r + r << 2]
2535 // variants are one cycle cheaper.
2536 switch (DefMCID.getOpcode()) {
2541 cast<ConstantSDNode>(DefNode->getOperand(2))->getZExtValue();
2542 unsigned ShImm = ARM_AM::getAM2Offset(ShOpVal);
2544 (ShImm == 2 && ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl))
2551 case ARM::t2LDRSHs: {
2552 // Thumb2 mode: lsl only.
2554 cast<ConstantSDNode>(DefNode->getOperand(2))->getZExtValue();
2555 if (ShAmt == 0 || ShAmt == 2)
2562 if (DefAlign < 8 && Subtarget.isCortexA9())
2563 switch (DefMCID.getOpcode()) {
2565 case ARM::VLD1q8Pseudo:
2566 case ARM::VLD1q16Pseudo:
2567 case ARM::VLD1q32Pseudo:
2568 case ARM::VLD1q64Pseudo:
2569 case ARM::VLD1q8PseudoWB_register:
2570 case ARM::VLD1q16PseudoWB_register:
2571 case ARM::VLD1q32PseudoWB_register:
2572 case ARM::VLD1q64PseudoWB_register:
2573 case ARM::VLD1q8PseudoWB_fixed:
2574 case ARM::VLD1q16PseudoWB_fixed:
2575 case ARM::VLD1q32PseudoWB_fixed:
2576 case ARM::VLD1q64PseudoWB_fixed:
2577 case ARM::VLD2d8Pseudo:
2578 case ARM::VLD2d16Pseudo:
2579 case ARM::VLD2d32Pseudo:
2580 case ARM::VLD2q8Pseudo:
2581 case ARM::VLD2q16Pseudo:
2582 case ARM::VLD2q32Pseudo:
2583 case ARM::VLD2d8Pseudo_UPD:
2584 case ARM::VLD2d16Pseudo_UPD:
2585 case ARM::VLD2d32Pseudo_UPD:
2586 case ARM::VLD2q8Pseudo_UPD:
2587 case ARM::VLD2q16Pseudo_UPD:
2588 case ARM::VLD2q32Pseudo_UPD:
2589 case ARM::VLD3d8Pseudo:
2590 case ARM::VLD3d16Pseudo:
2591 case ARM::VLD3d32Pseudo:
2592 case ARM::VLD1d64TPseudo:
2593 case ARM::VLD3d8Pseudo_UPD:
2594 case ARM::VLD3d16Pseudo_UPD:
2595 case ARM::VLD3d32Pseudo_UPD:
2596 case ARM::VLD1d64TPseudo_UPD:
2597 case ARM::VLD3q8Pseudo_UPD:
2598 case ARM::VLD3q16Pseudo_UPD:
2599 case ARM::VLD3q32Pseudo_UPD:
2600 case ARM::VLD3q8oddPseudo:
2601 case ARM::VLD3q16oddPseudo:
2602 case ARM::VLD3q32oddPseudo:
2603 case ARM::VLD3q8oddPseudo_UPD:
2604 case ARM::VLD3q16oddPseudo_UPD:
2605 case ARM::VLD3q32oddPseudo_UPD:
2606 case ARM::VLD4d8Pseudo:
2607 case ARM::VLD4d16Pseudo:
2608 case ARM::VLD4d32Pseudo:
2609 case ARM::VLD1d64QPseudo:
2610 case ARM::VLD4d8Pseudo_UPD:
2611 case ARM::VLD4d16Pseudo_UPD:
2612 case ARM::VLD4d32Pseudo_UPD:
2613 case ARM::VLD1d64QPseudo_UPD:
2614 case ARM::VLD4q8Pseudo_UPD:
2615 case ARM::VLD4q16Pseudo_UPD:
2616 case ARM::VLD4q32Pseudo_UPD:
2617 case ARM::VLD4q8oddPseudo:
2618 case ARM::VLD4q16oddPseudo:
2619 case ARM::VLD4q32oddPseudo:
2620 case ARM::VLD4q8oddPseudo_UPD:
2621 case ARM::VLD4q16oddPseudo_UPD:
2622 case ARM::VLD4q32oddPseudo_UPD:
2623 case ARM::VLD1DUPq8Pseudo:
2624 case ARM::VLD1DUPq16Pseudo:
2625 case ARM::VLD1DUPq32Pseudo:
2626 case ARM::VLD1DUPq8Pseudo_UPD:
2627 case ARM::VLD1DUPq16Pseudo_UPD:
2628 case ARM::VLD1DUPq32Pseudo_UPD:
2629 case ARM::VLD2DUPd8Pseudo:
2630 case ARM::VLD2DUPd16Pseudo:
2631 case ARM::VLD2DUPd32Pseudo:
2632 case ARM::VLD2DUPd8Pseudo_UPD:
2633 case ARM::VLD2DUPd16Pseudo_UPD:
2634 case ARM::VLD2DUPd32Pseudo_UPD:
2635 case ARM::VLD4DUPd8Pseudo:
2636 case ARM::VLD4DUPd16Pseudo:
2637 case ARM::VLD4DUPd32Pseudo:
2638 case ARM::VLD4DUPd8Pseudo_UPD:
2639 case ARM::VLD4DUPd16Pseudo_UPD:
2640 case ARM::VLD4DUPd32Pseudo_UPD:
2641 case ARM::VLD1LNq8Pseudo:
2642 case ARM::VLD1LNq16Pseudo:
2643 case ARM::VLD1LNq32Pseudo:
2644 case ARM::VLD1LNq8Pseudo_UPD:
2645 case ARM::VLD1LNq16Pseudo_UPD:
2646 case ARM::VLD1LNq32Pseudo_UPD:
2647 case ARM::VLD2LNd8Pseudo:
2648 case ARM::VLD2LNd16Pseudo:
2649 case ARM::VLD2LNd32Pseudo:
2650 case ARM::VLD2LNq16Pseudo:
2651 case ARM::VLD2LNq32Pseudo:
2652 case ARM::VLD2LNd8Pseudo_UPD:
2653 case ARM::VLD2LNd16Pseudo_UPD:
2654 case ARM::VLD2LNd32Pseudo_UPD:
2655 case ARM::VLD2LNq16Pseudo_UPD:
2656 case ARM::VLD2LNq32Pseudo_UPD:
2657 case ARM::VLD4LNd8Pseudo:
2658 case ARM::VLD4LNd16Pseudo:
2659 case ARM::VLD4LNd32Pseudo:
2660 case ARM::VLD4LNq16Pseudo:
2661 case ARM::VLD4LNq32Pseudo:
2662 case ARM::VLD4LNd8Pseudo_UPD:
2663 case ARM::VLD4LNd16Pseudo_UPD:
2664 case ARM::VLD4LNd32Pseudo_UPD:
2665 case ARM::VLD4LNq16Pseudo_UPD:
2666 case ARM::VLD4LNq32Pseudo_UPD:
2667 // If the address is not 64-bit aligned, the latencies of these
2668 // instructions increases by one.
2676 int ARMBaseInstrInfo::getInstrLatency(const InstrItineraryData *ItinData,
2677 const MachineInstr *MI,
2678 unsigned *PredCost) const {
2679 if (MI->isCopyLike() || MI->isInsertSubreg() ||
2680 MI->isRegSequence() || MI->isImplicitDef())
2683 if (!ItinData || ItinData->isEmpty())
2686 const MCInstrDesc &MCID = MI->getDesc();
2687 unsigned Class = MCID.getSchedClass();
2688 unsigned UOps = ItinData->Itineraries[Class].NumMicroOps;
2689 if (PredCost && MCID.hasImplicitDefOfPhysReg(ARM::CPSR))
2690 // When predicated, CPSR is an additional source operand for CPSR updating
2691 // instructions, this apparently increases their latencies.
2694 return ItinData->getStageLatency(Class);
2695 return getNumMicroOps(ItinData, MI);
2698 int ARMBaseInstrInfo::getInstrLatency(const InstrItineraryData *ItinData,
2699 SDNode *Node) const {
2700 if (!Node->isMachineOpcode())
2703 if (!ItinData || ItinData->isEmpty())
2706 unsigned Opcode = Node->getMachineOpcode();
2709 return ItinData->getStageLatency(get(Opcode).getSchedClass());
2716 bool ARMBaseInstrInfo::
2717 hasHighOperandLatency(const InstrItineraryData *ItinData,
2718 const MachineRegisterInfo *MRI,
2719 const MachineInstr *DefMI, unsigned DefIdx,
2720 const MachineInstr *UseMI, unsigned UseIdx) const {
2721 unsigned DDomain = DefMI->getDesc().TSFlags & ARMII::DomainMask;
2722 unsigned UDomain = UseMI->getDesc().TSFlags & ARMII::DomainMask;
2723 if (Subtarget.isCortexA8() &&
2724 (DDomain == ARMII::DomainVFP || UDomain == ARMII::DomainVFP))
2725 // CortexA8 VFP instructions are not pipelined.
2728 // Hoist VFP / NEON instructions with 4 or higher latency.
2729 int Latency = getOperandLatency(ItinData, DefMI, DefIdx, UseMI, UseIdx);
2732 return DDomain == ARMII::DomainVFP || DDomain == ARMII::DomainNEON ||
2733 UDomain == ARMII::DomainVFP || UDomain == ARMII::DomainNEON;
2736 bool ARMBaseInstrInfo::
2737 hasLowDefLatency(const InstrItineraryData *ItinData,
2738 const MachineInstr *DefMI, unsigned DefIdx) const {
2739 if (!ItinData || ItinData->isEmpty())
2742 unsigned DDomain = DefMI->getDesc().TSFlags & ARMII::DomainMask;
2743 if (DDomain == ARMII::DomainGeneral) {
2744 unsigned DefClass = DefMI->getDesc().getSchedClass();
2745 int DefCycle = ItinData->getOperandCycle(DefClass, DefIdx);
2746 return (DefCycle != -1 && DefCycle <= 2);
2751 bool ARMBaseInstrInfo::verifyInstruction(const MachineInstr *MI,
2752 StringRef &ErrInfo) const {
2753 if (convertAddSubFlagsOpcode(MI->getOpcode())) {
2754 ErrInfo = "Pseudo flag setting opcodes only exist in Selection DAG";
2761 ARMBaseInstrInfo::isFpMLxInstruction(unsigned Opcode, unsigned &MulOpc,
2762 unsigned &AddSubOpc,
2763 bool &NegAcc, bool &HasLane) const {
2764 DenseMap<unsigned, unsigned>::const_iterator I = MLxEntryMap.find(Opcode);
2765 if (I == MLxEntryMap.end())
2768 const ARM_MLxEntry &Entry = ARM_MLxTable[I->second];
2769 MulOpc = Entry.MulOpc;
2770 AddSubOpc = Entry.AddSubOpc;
2771 NegAcc = Entry.NegAcc;
2772 HasLane = Entry.HasLane;
2776 //===----------------------------------------------------------------------===//
2777 // Execution domains.
2778 //===----------------------------------------------------------------------===//
2780 // Some instructions go down the NEON pipeline, some go down the VFP pipeline,
2781 // and some can go down both. The vmov instructions go down the VFP pipeline,
2782 // but they can be changed to vorr equivalents that are executed by the NEON
2785 // We use the following execution domain numbering:
2793 // Also see ARMInstrFormats.td and Domain* enums in ARMBaseInfo.h
2795 std::pair<uint16_t, uint16_t>
2796 ARMBaseInstrInfo::getExecutionDomain(const MachineInstr *MI) const {
2797 // VMOVD is a VFP instruction, but can be changed to NEON if it isn't
2799 if (MI->getOpcode() == ARM::VMOVD && !isPredicated(MI))
2800 return std::make_pair(ExeVFP, (1<<ExeVFP) | (1<<ExeNEON));
2802 // No other instructions can be swizzled, so just determine their domain.
2803 unsigned Domain = MI->getDesc().TSFlags & ARMII::DomainMask;
2805 if (Domain & ARMII::DomainNEON)
2806 return std::make_pair(ExeNEON, 0);
2808 // Certain instructions can go either way on Cortex-A8.
2809 // Treat them as NEON instructions.
2810 if ((Domain & ARMII::DomainNEONA8) && Subtarget.isCortexA8())
2811 return std::make_pair(ExeNEON, 0);
2813 if (Domain & ARMII::DomainVFP)
2814 return std::make_pair(ExeVFP, 0);
2816 return std::make_pair(ExeGeneric, 0);
2820 ARMBaseInstrInfo::setExecutionDomain(MachineInstr *MI, unsigned Domain) const {
2821 // We only know how to change VMOVD into VORR.
2822 assert(MI->getOpcode() == ARM::VMOVD && "Can only swizzle VMOVD");
2823 if (Domain != ExeNEON)
2826 // Zap the predicate operands.
2827 assert(!isPredicated(MI) && "Cannot predicate a VORRd");
2828 MI->RemoveOperand(3);
2829 MI->RemoveOperand(2);
2831 // Change to a VORRd which requires two identical use operands.
2832 MI->setDesc(get(ARM::VORRd));
2834 // Add the extra source operand and new predicates.
2835 // This will go before any implicit ops.
2836 AddDefaultPred(MachineInstrBuilder(MI).addOperand(MI->getOperand(1)));