1 //===-- ARMAsmPrinter.cpp - Print machine code to an ARM .s file ----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains a printer that converts from our internal representation
11 // of machine-dependent LLVM code to GAS-format ARM assembly language.
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "asm-printer"
17 #include "ARMBuildAttrs.h"
18 #include "ARMAddressingModes.h"
19 #include "ARMConstantPoolValue.h"
20 #include "InstPrinter/ARMInstPrinter.h"
21 #include "ARMMachineFunctionInfo.h"
22 #include "ARMMCInstLower.h"
23 #include "ARMTargetMachine.h"
24 #include "ARMTargetObjectFile.h"
25 #include "llvm/Analysis/DebugInfo.h"
26 #include "llvm/Constants.h"
27 #include "llvm/Module.h"
28 #include "llvm/Type.h"
29 #include "llvm/Assembly/Writer.h"
30 #include "llvm/CodeGen/AsmPrinter.h"
31 #include "llvm/CodeGen/MachineModuleInfoImpls.h"
32 #include "llvm/CodeGen/MachineFunctionPass.h"
33 #include "llvm/CodeGen/MachineJumpTableInfo.h"
34 #include "llvm/MC/MCAsmInfo.h"
35 #include "llvm/MC/MCAssembler.h"
36 #include "llvm/MC/MCContext.h"
37 #include "llvm/MC/MCExpr.h"
38 #include "llvm/MC/MCInst.h"
39 #include "llvm/MC/MCSectionMachO.h"
40 #include "llvm/MC/MCObjectStreamer.h"
41 #include "llvm/MC/MCStreamer.h"
42 #include "llvm/MC/MCSymbol.h"
43 #include "llvm/Target/Mangler.h"
44 #include "llvm/Target/TargetData.h"
45 #include "llvm/Target/TargetMachine.h"
46 #include "llvm/Target/TargetOptions.h"
47 #include "llvm/Target/TargetRegistry.h"
48 #include "llvm/ADT/SmallPtrSet.h"
49 #include "llvm/ADT/SmallString.h"
50 #include "llvm/ADT/StringExtras.h"
51 #include "llvm/Support/CommandLine.h"
52 #include "llvm/Support/Debug.h"
53 #include "llvm/Support/ErrorHandling.h"
54 #include "llvm/Support/raw_ostream.h"
69 // Per section and per symbol attributes are not supported.
70 // To implement them we would need the ability to delay this emission
71 // until the assembly file is fully parsed/generated as only then do we
72 // know the symbol and section numbers.
73 class AttributeEmitter {
75 virtual void MaybeSwitchVendor(StringRef Vendor) = 0;
76 virtual void EmitAttribute(unsigned Attribute, unsigned Value) = 0;
77 virtual void Finish() = 0;
78 virtual ~AttributeEmitter() {}
81 class AsmAttributeEmitter : public AttributeEmitter {
85 AsmAttributeEmitter(MCStreamer &Streamer_) : Streamer(Streamer_) {}
86 void MaybeSwitchVendor(StringRef Vendor) { }
88 void EmitAttribute(unsigned Attribute, unsigned Value) {
89 Streamer.EmitRawText("\t.eabi_attribute " +
90 Twine(Attribute) + ", " + Twine(Value));
96 class ObjectAttributeEmitter : public AttributeEmitter {
97 MCObjectStreamer &Streamer;
98 StringRef CurrentVendor;
99 SmallString<64> Contents;
102 ObjectAttributeEmitter(MCObjectStreamer &Streamer_) :
103 Streamer(Streamer_), CurrentVendor("") { }
105 void MaybeSwitchVendor(StringRef Vendor) {
106 assert(!Vendor.empty() && "Vendor cannot be empty.");
108 if (CurrentVendor.empty())
109 CurrentVendor = Vendor;
110 else if (CurrentVendor == Vendor)
115 CurrentVendor = Vendor;
117 assert(Contents.size() == 0);
120 void EmitAttribute(unsigned Attribute, unsigned Value) {
121 // FIXME: should be ULEB
122 Contents += Attribute;
127 const size_t ContentsSize = Contents.size();
129 // Vendor size + Vendor name + '\0'
130 const size_t VendorHeaderSize = 4 + CurrentVendor.size() + 1;
133 const size_t TagHeaderSize = 1 + 4;
135 Streamer.EmitIntValue(VendorHeaderSize + TagHeaderSize + ContentsSize, 4);
136 Streamer.EmitBytes(CurrentVendor, 0);
137 Streamer.EmitIntValue(0, 1); // '\0'
139 Streamer.EmitIntValue(ARMBuildAttrs::File, 1);
140 Streamer.EmitIntValue(TagHeaderSize + ContentsSize, 4);
142 Streamer.EmitBytes(Contents, 0);
148 class ARMAsmPrinter : public AsmPrinter {
150 /// Subtarget - Keep a pointer to the ARMSubtarget around so that we can
151 /// make the right decision when printing asm code for different targets.
152 const ARMSubtarget *Subtarget;
154 /// AFI - Keep a pointer to ARMFunctionInfo for the current
156 ARMFunctionInfo *AFI;
158 /// MCP - Keep a pointer to constantpool entries of the current
160 const MachineConstantPool *MCP;
163 explicit ARMAsmPrinter(TargetMachine &TM, MCStreamer &Streamer)
164 : AsmPrinter(TM, Streamer), AFI(NULL), MCP(NULL) {
165 Subtarget = &TM.getSubtarget<ARMSubtarget>();
168 virtual const char *getPassName() const {
169 return "ARM Assembly Printer";
172 void printOperand(const MachineInstr *MI, int OpNum, raw_ostream &O,
173 const char *Modifier = 0);
175 virtual bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
176 unsigned AsmVariant, const char *ExtraCode,
178 virtual bool PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNum,
180 const char *ExtraCode, raw_ostream &O);
182 void EmitJumpTable(const MachineInstr *MI);
183 void EmitJump2Table(const MachineInstr *MI);
184 virtual void EmitInstruction(const MachineInstr *MI);
185 bool runOnMachineFunction(MachineFunction &F);
187 virtual void EmitConstantPool() {} // we emit constant pools customly!
188 virtual void EmitFunctionEntryLabel();
189 void EmitStartOfAsmFile(Module &M);
190 void EmitEndOfAsmFile(Module &M);
193 // Helpers for EmitStartOfAsmFile() and EmitEndOfAsmFile()
194 void emitAttributes();
196 // Helper for ELF .o only
197 void emitARMAttributeSection();
200 void PrintDebugValueComment(const MachineInstr *MI, raw_ostream &OS);
202 MachineLocation getDebugValueLocation(const MachineInstr *MI) const {
203 MachineLocation Location;
204 assert (MI->getNumOperands() == 4 && "Invalid no. of machine operands!");
205 // Frame address. Currently handles register +- offset only.
206 if (MI->getOperand(0).isReg() && MI->getOperand(1).isImm())
207 Location.set(MI->getOperand(0).getReg(), MI->getOperand(1).getImm());
209 DEBUG(dbgs() << "DBG_VALUE instruction ignored! " << *MI << "\n");
214 virtual unsigned getISAEncoding() {
215 // ARM/Darwin adds ISA to the DWARF info for each function.
216 if (!Subtarget->isTargetDarwin())
218 return Subtarget->isThumb() ?
219 llvm::ARM::DW_ISA_ARM_thumb : llvm::ARM::DW_ISA_ARM_arm;
222 MCSymbol *GetARMSetPICJumpTableLabel2(unsigned uid, unsigned uid2,
223 const MachineBasicBlock *MBB) const;
224 MCSymbol *GetARMJTIPICJumpTableLabel2(unsigned uid, unsigned uid2) const;
226 MCSymbol *GetARMSJLJEHLabel(void) const;
228 /// EmitMachineConstantPoolValue - Print a machine constantpool value to
230 virtual void EmitMachineConstantPoolValue(MachineConstantPoolValue *MCPV);
232 } // end of anonymous namespace
234 void ARMAsmPrinter::EmitFunctionEntryLabel() {
235 if (AFI->isThumbFunction()) {
236 OutStreamer.EmitAssemblerFlag(MCAF_Code16);
237 OutStreamer.EmitThumbFunc(Subtarget->isTargetDarwin()? CurrentFnSym : 0);
240 OutStreamer.EmitLabel(CurrentFnSym);
243 /// runOnMachineFunction - This uses the EmitInstruction()
244 /// method to print assembly for each instruction.
246 bool ARMAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
247 AFI = MF.getInfo<ARMFunctionInfo>();
248 MCP = MF.getConstantPool();
250 return AsmPrinter::runOnMachineFunction(MF);
253 void ARMAsmPrinter::printOperand(const MachineInstr *MI, int OpNum,
254 raw_ostream &O, const char *Modifier) {
255 const MachineOperand &MO = MI->getOperand(OpNum);
256 unsigned TF = MO.getTargetFlags();
258 switch (MO.getType()) {
260 assert(0 && "<unknown operand type>");
261 case MachineOperand::MO_Register: {
262 unsigned Reg = MO.getReg();
263 assert(TargetRegisterInfo::isPhysicalRegister(Reg));
264 assert(!MO.getSubReg() && "Subregs should be eliminated!");
265 O << ARMInstPrinter::getRegisterName(Reg);
268 case MachineOperand::MO_Immediate: {
269 int64_t Imm = MO.getImm();
271 if ((Modifier && strcmp(Modifier, "lo16") == 0) ||
272 (TF == ARMII::MO_LO16))
274 else if ((Modifier && strcmp(Modifier, "hi16") == 0) ||
275 (TF == ARMII::MO_HI16))
280 case MachineOperand::MO_MachineBasicBlock:
281 O << *MO.getMBB()->getSymbol();
283 case MachineOperand::MO_GlobalAddress: {
284 const GlobalValue *GV = MO.getGlobal();
285 if ((Modifier && strcmp(Modifier, "lo16") == 0) ||
286 (TF & ARMII::MO_LO16))
288 else if ((Modifier && strcmp(Modifier, "hi16") == 0) ||
289 (TF & ARMII::MO_HI16))
291 O << *Mang->getSymbol(GV);
293 printOffset(MO.getOffset(), O);
294 if (TF == ARMII::MO_PLT)
298 case MachineOperand::MO_ExternalSymbol: {
299 O << *GetExternalSymbolSymbol(MO.getSymbolName());
300 if (TF == ARMII::MO_PLT)
304 case MachineOperand::MO_ConstantPoolIndex:
305 O << *GetCPISymbol(MO.getIndex());
307 case MachineOperand::MO_JumpTableIndex:
308 O << *GetJTISymbol(MO.getIndex());
313 //===--------------------------------------------------------------------===//
315 MCSymbol *ARMAsmPrinter::
316 GetARMSetPICJumpTableLabel2(unsigned uid, unsigned uid2,
317 const MachineBasicBlock *MBB) const {
318 SmallString<60> Name;
319 raw_svector_ostream(Name) << MAI->getPrivateGlobalPrefix()
320 << getFunctionNumber() << '_' << uid << '_' << uid2
321 << "_set_" << MBB->getNumber();
322 return OutContext.GetOrCreateSymbol(Name.str());
325 MCSymbol *ARMAsmPrinter::
326 GetARMJTIPICJumpTableLabel2(unsigned uid, unsigned uid2) const {
327 SmallString<60> Name;
328 raw_svector_ostream(Name) << MAI->getPrivateGlobalPrefix() << "JTI"
329 << getFunctionNumber() << '_' << uid << '_' << uid2;
330 return OutContext.GetOrCreateSymbol(Name.str());
334 MCSymbol *ARMAsmPrinter::GetARMSJLJEHLabel(void) const {
335 SmallString<60> Name;
336 raw_svector_ostream(Name) << MAI->getPrivateGlobalPrefix() << "SJLJEH"
337 << getFunctionNumber();
338 return OutContext.GetOrCreateSymbol(Name.str());
341 bool ARMAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
342 unsigned AsmVariant, const char *ExtraCode,
344 // Does this asm operand have a single letter operand modifier?
345 if (ExtraCode && ExtraCode[0]) {
346 if (ExtraCode[1] != 0) return true; // Unknown modifier.
348 switch (ExtraCode[0]) {
349 default: return true; // Unknown modifier.
350 case 'a': // Print as a memory address.
351 if (MI->getOperand(OpNum).isReg()) {
353 << ARMInstPrinter::getRegisterName(MI->getOperand(OpNum).getReg())
358 case 'c': // Don't print "#" before an immediate operand.
359 if (!MI->getOperand(OpNum).isImm())
361 O << MI->getOperand(OpNum).getImm();
363 case 'P': // Print a VFP double precision register.
364 case 'q': // Print a NEON quad precision register.
365 printOperand(MI, OpNum, O);
370 report_fatal_error("llvm does not support 'Q', 'R', and 'H' modifiers!");
375 printOperand(MI, OpNum, O);
379 bool ARMAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI,
380 unsigned OpNum, unsigned AsmVariant,
381 const char *ExtraCode,
383 if (ExtraCode && ExtraCode[0])
384 return true; // Unknown modifier.
386 const MachineOperand &MO = MI->getOperand(OpNum);
387 assert(MO.isReg() && "unexpected inline asm memory operand");
388 O << "[" << ARMInstPrinter::getRegisterName(MO.getReg()) << "]";
392 void ARMAsmPrinter::EmitStartOfAsmFile(Module &M) {
393 if (Subtarget->isTargetDarwin()) {
394 Reloc::Model RelocM = TM.getRelocationModel();
395 if (RelocM == Reloc::PIC_ || RelocM == Reloc::DynamicNoPIC) {
396 // Declare all the text sections up front (before the DWARF sections
397 // emitted by AsmPrinter::doInitialization) so the assembler will keep
398 // them together at the beginning of the object file. This helps
399 // avoid out-of-range branches that are due a fundamental limitation of
400 // the way symbol offsets are encoded with the current Darwin ARM
402 const TargetLoweringObjectFileMachO &TLOFMacho =
403 static_cast<const TargetLoweringObjectFileMachO &>(
404 getObjFileLowering());
405 OutStreamer.SwitchSection(TLOFMacho.getTextSection());
406 OutStreamer.SwitchSection(TLOFMacho.getTextCoalSection());
407 OutStreamer.SwitchSection(TLOFMacho.getConstTextCoalSection());
408 if (RelocM == Reloc::DynamicNoPIC) {
409 const MCSection *sect =
410 OutContext.getMachOSection("__TEXT", "__symbol_stub4",
411 MCSectionMachO::S_SYMBOL_STUBS,
412 12, SectionKind::getText());
413 OutStreamer.SwitchSection(sect);
415 const MCSection *sect =
416 OutContext.getMachOSection("__TEXT", "__picsymbolstub4",
417 MCSectionMachO::S_SYMBOL_STUBS,
418 16, SectionKind::getText());
419 OutStreamer.SwitchSection(sect);
421 const MCSection *StaticInitSect =
422 OutContext.getMachOSection("__TEXT", "__StaticInit",
423 MCSectionMachO::S_REGULAR |
424 MCSectionMachO::S_ATTR_PURE_INSTRUCTIONS,
425 SectionKind::getText());
426 OutStreamer.SwitchSection(StaticInitSect);
430 // Use unified assembler syntax.
431 OutStreamer.EmitAssemblerFlag(MCAF_SyntaxUnified);
433 // Emit ARM Build Attributes
434 if (Subtarget->isTargetELF()) {
441 void ARMAsmPrinter::EmitEndOfAsmFile(Module &M) {
442 if (Subtarget->isTargetDarwin()) {
443 // All darwin targets use mach-o.
444 const TargetLoweringObjectFileMachO &TLOFMacho =
445 static_cast<const TargetLoweringObjectFileMachO &>(getObjFileLowering());
446 MachineModuleInfoMachO &MMIMacho =
447 MMI->getObjFileInfo<MachineModuleInfoMachO>();
449 // Output non-lazy-pointers for external and common global variables.
450 MachineModuleInfoMachO::SymbolListTy Stubs = MMIMacho.GetGVStubList();
452 if (!Stubs.empty()) {
453 // Switch with ".non_lazy_symbol_pointer" directive.
454 OutStreamer.SwitchSection(TLOFMacho.getNonLazySymbolPointerSection());
456 for (unsigned i = 0, e = Stubs.size(); i != e; ++i) {
458 OutStreamer.EmitLabel(Stubs[i].first);
459 // .indirect_symbol _foo
460 MachineModuleInfoImpl::StubValueTy &MCSym = Stubs[i].second;
461 OutStreamer.EmitSymbolAttribute(MCSym.getPointer(),MCSA_IndirectSymbol);
464 // External to current translation unit.
465 OutStreamer.EmitIntValue(0, 4/*size*/, 0/*addrspace*/);
467 // Internal to current translation unit.
469 // When we place the LSDA into the TEXT section, the type info
470 // pointers need to be indirect and pc-rel. We accomplish this by
471 // using NLPs; however, sometimes the types are local to the file.
472 // We need to fill in the value for the NLP in those cases.
473 OutStreamer.EmitValue(MCSymbolRefExpr::Create(MCSym.getPointer(),
475 4/*size*/, 0/*addrspace*/);
479 OutStreamer.AddBlankLine();
482 Stubs = MMIMacho.GetHiddenGVStubList();
483 if (!Stubs.empty()) {
484 OutStreamer.SwitchSection(getObjFileLowering().getDataSection());
486 for (unsigned i = 0, e = Stubs.size(); i != e; ++i) {
488 OutStreamer.EmitLabel(Stubs[i].first);
490 OutStreamer.EmitValue(MCSymbolRefExpr::
491 Create(Stubs[i].second.getPointer(),
493 4/*size*/, 0/*addrspace*/);
497 OutStreamer.AddBlankLine();
500 // Funny Darwin hack: This flag tells the linker that no global symbols
501 // contain code that falls through to other global symbols (e.g. the obvious
502 // implementation of multiple entry points). If this doesn't occur, the
503 // linker can safely perform dead code stripping. Since LLVM never
504 // generates code that does this, it is always safe to set.
505 OutStreamer.EmitAssemblerFlag(MCAF_SubsectionsViaSymbols);
509 //===----------------------------------------------------------------------===//
510 // Helper routines for EmitStartOfAsmFile() and EmitEndOfAsmFile()
512 // The following seem like one-off assembler flags, but they actually need
513 // to appear in the .ARM.attributes section in ELF.
514 // Instead of subclassing the MCELFStreamer, we do the work here.
516 void ARMAsmPrinter::emitAttributes() {
518 emitARMAttributeSection();
520 AttributeEmitter *AttrEmitter;
521 if (OutStreamer.hasRawTextSupport())
522 AttrEmitter = new AsmAttributeEmitter(OutStreamer);
524 MCObjectStreamer &O = static_cast<MCObjectStreamer&>(OutStreamer);
525 AttrEmitter = new ObjectAttributeEmitter(O);
528 AttrEmitter->MaybeSwitchVendor("aeabi");
530 std::string CPUString = Subtarget->getCPUString();
531 if (OutStreamer.hasRawTextSupport()) {
532 if (CPUString != "generic")
533 OutStreamer.EmitRawText(StringRef("\t.cpu ") + CPUString);
535 assert(CPUString == "generic" && "Unsupported .cpu attribute for ELF/.o");
536 // FIXME: Why these defaults?
537 AttrEmitter->EmitAttribute(ARMBuildAttrs::CPU_arch, ARMBuildAttrs::v4T);
538 AttrEmitter->EmitAttribute(ARMBuildAttrs::ARM_ISA_use, 1);
539 AttrEmitter->EmitAttribute(ARMBuildAttrs::THUMB_ISA_use, 1);
542 // FIXME: Emit FPU type
543 if (Subtarget->hasVFP2())
544 AttrEmitter->EmitAttribute(ARMBuildAttrs::VFP_arch, 2);
546 // Signal various FP modes.
548 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_FP_denormal, 1);
549 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_FP_exceptions, 1);
552 if (NoInfsFPMath && NoNaNsFPMath)
553 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_FP_number_model, 1);
555 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_FP_number_model, 3);
557 // 8-bytes alignment stuff.
558 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_align8_needed, 1);
559 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_align8_preserved, 1);
561 // Hard float. Use both S and D registers and conform to AAPCS-VFP.
562 if (Subtarget->isAAPCS_ABI() && FloatABIType == FloatABI::Hard) {
563 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_HardFP_use, 3);
564 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_VFP_args, 1);
566 // FIXME: Should we signal R9 usage?
568 AttrEmitter->EmitAttribute(ARMBuildAttrs::DIV_use, 1);
570 AttrEmitter->Finish();
574 void ARMAsmPrinter::emitARMAttributeSection() {
576 // [ <section-length> "vendor-name"
577 // [ <file-tag> <size> <attribute>*
578 // | <section-tag> <size> <section-number>* 0 <attribute>*
579 // | <symbol-tag> <size> <symbol-number>* 0 <attribute>*
583 if (OutStreamer.hasRawTextSupport())
586 const ARMElfTargetObjectFile &TLOFELF =
587 static_cast<const ARMElfTargetObjectFile &>
588 (getObjFileLowering());
590 OutStreamer.SwitchSection(TLOFELF.getAttributesSection());
593 OutStreamer.EmitIntValue(0x41, 1);
596 //===----------------------------------------------------------------------===//
598 static MCSymbol *getPICLabel(const char *Prefix, unsigned FunctionNumber,
599 unsigned LabelId, MCContext &Ctx) {
601 MCSymbol *Label = Ctx.GetOrCreateSymbol(Twine(Prefix)
602 + "PC" + Twine(FunctionNumber) + "_" + Twine(LabelId));
606 static MCSymbolRefExpr::VariantKind
607 getModifierVariantKind(ARMCP::ARMCPModifier Modifier) {
609 default: llvm_unreachable("Unknown modifier!");
610 case ARMCP::no_modifier: return MCSymbolRefExpr::VK_None;
611 case ARMCP::TLSGD: return MCSymbolRefExpr::VK_ARM_TLSGD;
612 case ARMCP::TPOFF: return MCSymbolRefExpr::VK_ARM_TPOFF;
613 case ARMCP::GOTTPOFF: return MCSymbolRefExpr::VK_ARM_GOTTPOFF;
614 case ARMCP::GOT: return MCSymbolRefExpr::VK_ARM_GOT;
615 case ARMCP::GOTOFF: return MCSymbolRefExpr::VK_ARM_GOTOFF;
617 return MCSymbolRefExpr::VK_None;
621 EmitMachineConstantPoolValue(MachineConstantPoolValue *MCPV) {
622 int Size = TM.getTargetData()->getTypeAllocSize(MCPV->getType());
624 ARMConstantPoolValue *ACPV = static_cast<ARMConstantPoolValue*>(MCPV);
627 if (ACPV->isLSDA()) {
628 SmallString<128> Str;
629 raw_svector_ostream OS(Str);
630 OS << MAI->getPrivateGlobalPrefix() << "_LSDA_" << getFunctionNumber();
631 MCSym = OutContext.GetOrCreateSymbol(OS.str());
632 } else if (ACPV->isBlockAddress()) {
633 MCSym = GetBlockAddressSymbol(ACPV->getBlockAddress());
634 } else if (ACPV->isGlobalValue()) {
635 const GlobalValue *GV = ACPV->getGV();
636 bool isIndirect = Subtarget->isTargetDarwin() &&
637 Subtarget->GVIsIndirectSymbol(GV, TM.getRelocationModel());
639 MCSym = Mang->getSymbol(GV);
641 // FIXME: Remove this when Darwin transition to @GOT like syntax.
642 MCSym = GetSymbolWithGlobalValueBase(GV, "$non_lazy_ptr");
644 MachineModuleInfoMachO &MMIMachO =
645 MMI->getObjFileInfo<MachineModuleInfoMachO>();
646 MachineModuleInfoImpl::StubValueTy &StubSym =
647 GV->hasHiddenVisibility() ? MMIMachO.getHiddenGVStubEntry(MCSym) :
648 MMIMachO.getGVStubEntry(MCSym);
649 if (StubSym.getPointer() == 0)
650 StubSym = MachineModuleInfoImpl::
651 StubValueTy(Mang->getSymbol(GV), !GV->hasInternalLinkage());
654 assert(ACPV->isExtSymbol() && "unrecognized constant pool value");
655 MCSym = GetExternalSymbolSymbol(ACPV->getSymbol());
658 // Create an MCSymbol for the reference.
660 MCSymbolRefExpr::Create(MCSym, getModifierVariantKind(ACPV->getModifier()),
663 if (ACPV->getPCAdjustment()) {
664 MCSymbol *PCLabel = getPICLabel(MAI->getPrivateGlobalPrefix(),
668 const MCExpr *PCRelExpr = MCSymbolRefExpr::Create(PCLabel, OutContext);
670 MCBinaryExpr::CreateAdd(PCRelExpr,
671 MCConstantExpr::Create(ACPV->getPCAdjustment(),
674 if (ACPV->mustAddCurrentAddress()) {
675 // We want "(<expr> - .)", but MC doesn't have a concept of the '.'
676 // label, so just emit a local label end reference that instead.
677 MCSymbol *DotSym = OutContext.CreateTempSymbol();
678 OutStreamer.EmitLabel(DotSym);
679 const MCExpr *DotExpr = MCSymbolRefExpr::Create(DotSym, OutContext);
680 PCRelExpr = MCBinaryExpr::CreateSub(PCRelExpr, DotExpr, OutContext);
682 Expr = MCBinaryExpr::CreateSub(Expr, PCRelExpr, OutContext);
684 OutStreamer.EmitValue(Expr, Size);
687 void ARMAsmPrinter::EmitJumpTable(const MachineInstr *MI) {
688 unsigned Opcode = MI->getOpcode();
690 if (Opcode == ARM::BR_JTadd)
692 else if (Opcode == ARM::BR_JTm)
695 const MachineOperand &MO1 = MI->getOperand(OpNum);
696 const MachineOperand &MO2 = MI->getOperand(OpNum+1); // Unique Id
697 unsigned JTI = MO1.getIndex();
699 // Emit a label for the jump table.
700 MCSymbol *JTISymbol = GetARMJTIPICJumpTableLabel2(JTI, MO2.getImm());
701 OutStreamer.EmitLabel(JTISymbol);
703 // Emit each entry of the table.
704 const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
705 const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
706 const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
708 for (unsigned i = 0, e = JTBBs.size(); i != e; ++i) {
709 MachineBasicBlock *MBB = JTBBs[i];
710 // Construct an MCExpr for the entry. We want a value of the form:
711 // (BasicBlockAddr - TableBeginAddr)
713 // For example, a table with entries jumping to basic blocks BB0 and BB1
716 // .word (LBB0 - LJTI_0_0)
717 // .word (LBB1 - LJTI_0_0)
718 const MCExpr *Expr = MCSymbolRefExpr::Create(MBB->getSymbol(), OutContext);
720 if (TM.getRelocationModel() == Reloc::PIC_)
721 Expr = MCBinaryExpr::CreateSub(Expr, MCSymbolRefExpr::Create(JTISymbol,
724 OutStreamer.EmitValue(Expr, 4);
728 void ARMAsmPrinter::EmitJump2Table(const MachineInstr *MI) {
729 unsigned Opcode = MI->getOpcode();
730 int OpNum = (Opcode == ARM::t2BR_JT) ? 2 : 1;
731 const MachineOperand &MO1 = MI->getOperand(OpNum);
732 const MachineOperand &MO2 = MI->getOperand(OpNum+1); // Unique Id
733 unsigned JTI = MO1.getIndex();
735 // Emit a label for the jump table.
736 MCSymbol *JTISymbol = GetARMJTIPICJumpTableLabel2(JTI, MO2.getImm());
737 OutStreamer.EmitLabel(JTISymbol);
739 // Emit each entry of the table.
740 const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
741 const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
742 const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
743 unsigned OffsetWidth = 4;
744 if (MI->getOpcode() == ARM::t2TBB)
746 else if (MI->getOpcode() == ARM::t2TBH)
749 for (unsigned i = 0, e = JTBBs.size(); i != e; ++i) {
750 MachineBasicBlock *MBB = JTBBs[i];
751 const MCExpr *MBBSymbolExpr = MCSymbolRefExpr::Create(MBB->getSymbol(),
753 // If this isn't a TBB or TBH, the entries are direct branch instructions.
754 if (OffsetWidth == 4) {
756 BrInst.setOpcode(ARM::t2B);
757 BrInst.addOperand(MCOperand::CreateExpr(MBBSymbolExpr));
758 OutStreamer.EmitInstruction(BrInst);
761 // Otherwise it's an offset from the dispatch instruction. Construct an
762 // MCExpr for the entry. We want a value of the form:
763 // (BasicBlockAddr - TableBeginAddr) / 2
765 // For example, a TBB table with entries jumping to basic blocks BB0 and BB1
768 // .byte (LBB0 - LJTI_0_0) / 2
769 // .byte (LBB1 - LJTI_0_0) / 2
771 MCBinaryExpr::CreateSub(MBBSymbolExpr,
772 MCSymbolRefExpr::Create(JTISymbol, OutContext),
774 Expr = MCBinaryExpr::CreateDiv(Expr, MCConstantExpr::Create(2, OutContext),
776 OutStreamer.EmitValue(Expr, OffsetWidth);
779 // Make sure the instruction that follows TBB is 2-byte aligned.
780 // FIXME: Constant island pass should insert an "ALIGN" instruction instead.
781 if (MI->getOpcode() == ARM::t2TBB)
785 void ARMAsmPrinter::PrintDebugValueComment(const MachineInstr *MI,
787 unsigned NOps = MI->getNumOperands();
789 OS << '\t' << MAI->getCommentString() << "DEBUG_VALUE: ";
790 // cast away const; DIetc do not take const operands for some reason.
791 DIVariable V(const_cast<MDNode *>(MI->getOperand(NOps-1).getMetadata()));
794 // Frame address. Currently handles register +- offset only.
795 assert(MI->getOperand(0).isReg() && MI->getOperand(1).isImm());
796 OS << '['; printOperand(MI, 0, OS); OS << '+'; printOperand(MI, 1, OS);
799 printOperand(MI, NOps-2, OS);
802 void ARMAsmPrinter::EmitInstruction(const MachineInstr *MI) {
803 ARMMCInstLower MCInstLowering(OutContext, *Mang, *this);
804 switch (MI->getOpcode()) {
805 case ARM::t2MOVi32imm:
806 assert(0 && "Should be lowered by thumb2it pass");
808 case ARM::DBG_VALUE: {
809 if (isVerbose() && OutStreamer.hasRawTextSupport()) {
810 SmallString<128> TmpStr;
811 raw_svector_ostream OS(TmpStr);
812 PrintDebugValueComment(MI, OS);
813 OutStreamer.EmitRawText(StringRef(OS.str()));
818 // This is a pseudo op for a label + instruction sequence, which looks like:
821 // This adds the address of LPC0 to r0.
824 OutStreamer.EmitLabel(getPICLabel(MAI->getPrivateGlobalPrefix(),
825 getFunctionNumber(), MI->getOperand(2).getImm(),
828 // Form and emit the add.
830 AddInst.setOpcode(ARM::tADDhirr);
831 AddInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
832 AddInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
833 AddInst.addOperand(MCOperand::CreateReg(ARM::PC));
834 // Add predicate operands.
835 AddInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
836 AddInst.addOperand(MCOperand::CreateReg(0));
837 OutStreamer.EmitInstruction(AddInst);
841 // This is a pseudo op for a label + instruction sequence, which looks like:
844 // This adds the address of LPC0 to r0.
847 OutStreamer.EmitLabel(getPICLabel(MAI->getPrivateGlobalPrefix(),
848 getFunctionNumber(), MI->getOperand(2).getImm(),
851 // Form and emit the add.
853 AddInst.setOpcode(ARM::ADDrr);
854 AddInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
855 AddInst.addOperand(MCOperand::CreateReg(ARM::PC));
856 AddInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg()));
857 // Add predicate operands.
858 AddInst.addOperand(MCOperand::CreateImm(MI->getOperand(3).getImm()));
859 AddInst.addOperand(MCOperand::CreateReg(MI->getOperand(4).getReg()));
860 // Add 's' bit operand (always reg0 for this)
861 AddInst.addOperand(MCOperand::CreateReg(0));
862 OutStreamer.EmitInstruction(AddInst);
872 case ARM::PICLDRSH: {
873 // This is a pseudo op for a label + instruction sequence, which looks like:
876 // The LCP0 label is referenced by a constant pool entry in order to get
877 // a PC-relative address at the ldr instruction.
880 OutStreamer.EmitLabel(getPICLabel(MAI->getPrivateGlobalPrefix(),
881 getFunctionNumber(), MI->getOperand(2).getImm(),
884 // Form and emit the load
886 switch (MI->getOpcode()) {
888 llvm_unreachable("Unexpected opcode!");
889 case ARM::PICSTR: Opcode = ARM::STRrs; break;
890 case ARM::PICSTRB: Opcode = ARM::STRBrs; break;
891 case ARM::PICSTRH: Opcode = ARM::STRH; break;
892 case ARM::PICLDR: Opcode = ARM::LDRrs; break;
893 case ARM::PICLDRB: Opcode = ARM::LDRBrs; break;
894 case ARM::PICLDRH: Opcode = ARM::LDRH; break;
895 case ARM::PICLDRSB: Opcode = ARM::LDRSB; break;
896 case ARM::PICLDRSH: Opcode = ARM::LDRSH; break;
899 LdStInst.setOpcode(Opcode);
900 LdStInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
901 LdStInst.addOperand(MCOperand::CreateReg(ARM::PC));
902 LdStInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg()));
903 LdStInst.addOperand(MCOperand::CreateImm(0));
904 // Add predicate operands.
905 LdStInst.addOperand(MCOperand::CreateImm(MI->getOperand(3).getImm()));
906 LdStInst.addOperand(MCOperand::CreateReg(MI->getOperand(4).getReg()));
907 OutStreamer.EmitInstruction(LdStInst);
911 case ARM::CONSTPOOL_ENTRY: {
912 /// CONSTPOOL_ENTRY - This instruction represents a floating constant pool
913 /// in the function. The first operand is the ID# for this instruction, the
914 /// second is the index into the MachineConstantPool that this is, the third
915 /// is the size in bytes of this constant pool entry.
916 unsigned LabelId = (unsigned)MI->getOperand(0).getImm();
917 unsigned CPIdx = (unsigned)MI->getOperand(1).getIndex();
920 OutStreamer.EmitLabel(GetCPISymbol(LabelId));
922 const MachineConstantPoolEntry &MCPE = MCP->getConstants()[CPIdx];
923 if (MCPE.isMachineConstantPoolEntry())
924 EmitMachineConstantPoolValue(MCPE.Val.MachineCPVal);
926 EmitGlobalConstant(MCPE.Val.ConstVal);
933 // Lower and emit the instruction itself, then the jump table following it.
935 MCInstLowering.Lower(MI, TmpInst);
936 OutStreamer.EmitInstruction(TmpInst);
943 case ARM::BR_JTadd: {
944 // Lower and emit the instruction itself, then the jump table following it.
946 MCInstLowering.Lower(MI, TmpInst);
947 OutStreamer.EmitInstruction(TmpInst);
952 // Non-Darwin binutils don't yet support the "trap" mnemonic.
953 // FIXME: Remove this special case when they do.
954 if (!Subtarget->isTargetDarwin()) {
955 //.long 0xe7ffdefe @ trap
956 uint32_t Val = 0xe7ffdefeUL;
957 OutStreamer.AddComment("trap");
958 OutStreamer.EmitIntValue(Val, 4);
964 // Non-Darwin binutils don't yet support the "trap" mnemonic.
965 // FIXME: Remove this special case when they do.
966 if (!Subtarget->isTargetDarwin()) {
967 //.short 57086 @ trap
968 uint16_t Val = 0xdefe;
969 OutStreamer.AddComment("trap");
970 OutStreamer.EmitIntValue(Val, 2);
975 case ARM::t2Int_eh_sjlj_setjmp:
976 case ARM::t2Int_eh_sjlj_setjmp_nofp:
977 case ARM::tInt_eh_sjlj_setjmp: {
978 // Two incoming args: GPR:$src, GPR:$val
981 // str $val, [$src, #4]
986 unsigned SrcReg = MI->getOperand(0).getReg();
987 unsigned ValReg = MI->getOperand(1).getReg();
988 MCSymbol *Label = GetARMSJLJEHLabel();
991 TmpInst.setOpcode(ARM::tMOVgpr2tgpr);
992 TmpInst.addOperand(MCOperand::CreateReg(ValReg));
993 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
995 TmpInst.addOperand(MCOperand::CreateReg(ARM::CPSR));
996 OutStreamer.AddComment("eh_setjmp begin");
997 OutStreamer.EmitInstruction(TmpInst);
1001 TmpInst.setOpcode(ARM::tADDi3);
1002 TmpInst.addOperand(MCOperand::CreateReg(ValReg));
1004 TmpInst.addOperand(MCOperand::CreateReg(ARM::CPSR));
1005 TmpInst.addOperand(MCOperand::CreateReg(ValReg));
1006 TmpInst.addOperand(MCOperand::CreateImm(7));
1008 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1009 TmpInst.addOperand(MCOperand::CreateReg(0));
1010 OutStreamer.EmitInstruction(TmpInst);
1014 TmpInst.setOpcode(ARM::tSTR);
1015 TmpInst.addOperand(MCOperand::CreateReg(ValReg));
1016 TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
1017 // The offset immediate is #4. The operand value is scaled by 4 for the
1018 // tSTR instruction.
1019 TmpInst.addOperand(MCOperand::CreateImm(1));
1020 TmpInst.addOperand(MCOperand::CreateReg(0));
1022 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1023 TmpInst.addOperand(MCOperand::CreateReg(0));
1024 OutStreamer.EmitInstruction(TmpInst);
1028 TmpInst.setOpcode(ARM::tMOVi8);
1029 TmpInst.addOperand(MCOperand::CreateReg(ARM::R0));
1030 TmpInst.addOperand(MCOperand::CreateReg(ARM::CPSR));
1031 TmpInst.addOperand(MCOperand::CreateImm(0));
1033 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1034 TmpInst.addOperand(MCOperand::CreateReg(0));
1035 OutStreamer.EmitInstruction(TmpInst);
1038 const MCExpr *SymbolExpr = MCSymbolRefExpr::Create(Label, OutContext);
1040 TmpInst.setOpcode(ARM::tB);
1041 TmpInst.addOperand(MCOperand::CreateExpr(SymbolExpr));
1042 OutStreamer.EmitInstruction(TmpInst);
1046 TmpInst.setOpcode(ARM::tMOVi8);
1047 TmpInst.addOperand(MCOperand::CreateReg(ARM::R0));
1048 TmpInst.addOperand(MCOperand::CreateReg(ARM::CPSR));
1049 TmpInst.addOperand(MCOperand::CreateImm(1));
1051 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1052 TmpInst.addOperand(MCOperand::CreateReg(0));
1053 OutStreamer.AddComment("eh_setjmp end");
1054 OutStreamer.EmitInstruction(TmpInst);
1056 OutStreamer.EmitLabel(Label);
1060 case ARM::Int_eh_sjlj_setjmp_nofp:
1061 case ARM::Int_eh_sjlj_setjmp: {
1062 // Two incoming args: GPR:$src, GPR:$val
1064 // str $val, [$src, #+4]
1068 unsigned SrcReg = MI->getOperand(0).getReg();
1069 unsigned ValReg = MI->getOperand(1).getReg();
1073 TmpInst.setOpcode(ARM::ADDri);
1074 TmpInst.addOperand(MCOperand::CreateReg(ValReg));
1075 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1076 TmpInst.addOperand(MCOperand::CreateImm(8));
1078 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1079 TmpInst.addOperand(MCOperand::CreateReg(0));
1080 // 's' bit operand (always reg0 for this).
1081 TmpInst.addOperand(MCOperand::CreateReg(0));
1082 OutStreamer.AddComment("eh_setjmp begin");
1083 OutStreamer.EmitInstruction(TmpInst);
1087 TmpInst.setOpcode(ARM::STRi12);
1088 TmpInst.addOperand(MCOperand::CreateReg(ValReg));
1089 TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
1090 TmpInst.addOperand(MCOperand::CreateImm(4));
1092 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1093 TmpInst.addOperand(MCOperand::CreateReg(0));
1094 OutStreamer.EmitInstruction(TmpInst);
1098 TmpInst.setOpcode(ARM::MOVi);
1099 TmpInst.addOperand(MCOperand::CreateReg(ARM::R0));
1100 TmpInst.addOperand(MCOperand::CreateImm(0));
1102 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1103 TmpInst.addOperand(MCOperand::CreateReg(0));
1104 // 's' bit operand (always reg0 for this).
1105 TmpInst.addOperand(MCOperand::CreateReg(0));
1106 OutStreamer.EmitInstruction(TmpInst);
1110 TmpInst.setOpcode(ARM::ADDri);
1111 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1112 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1113 TmpInst.addOperand(MCOperand::CreateImm(0));
1115 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1116 TmpInst.addOperand(MCOperand::CreateReg(0));
1117 // 's' bit operand (always reg0 for this).
1118 TmpInst.addOperand(MCOperand::CreateReg(0));
1119 OutStreamer.EmitInstruction(TmpInst);
1123 TmpInst.setOpcode(ARM::MOVi);
1124 TmpInst.addOperand(MCOperand::CreateReg(ARM::R0));
1125 TmpInst.addOperand(MCOperand::CreateImm(1));
1127 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1128 TmpInst.addOperand(MCOperand::CreateReg(0));
1129 // 's' bit operand (always reg0 for this).
1130 TmpInst.addOperand(MCOperand::CreateReg(0));
1131 OutStreamer.AddComment("eh_setjmp end");
1132 OutStreamer.EmitInstruction(TmpInst);
1136 case ARM::Int_eh_sjlj_longjmp: {
1137 // ldr sp, [$src, #8]
1138 // ldr $scratch, [$src, #4]
1141 unsigned SrcReg = MI->getOperand(0).getReg();
1142 unsigned ScratchReg = MI->getOperand(1).getReg();
1145 TmpInst.setOpcode(ARM::LDRi12);
1146 TmpInst.addOperand(MCOperand::CreateReg(ARM::SP));
1147 TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
1148 TmpInst.addOperand(MCOperand::CreateImm(8));
1150 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1151 TmpInst.addOperand(MCOperand::CreateReg(0));
1152 OutStreamer.EmitInstruction(TmpInst);
1156 TmpInst.setOpcode(ARM::LDRi12);
1157 TmpInst.addOperand(MCOperand::CreateReg(ScratchReg));
1158 TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
1159 TmpInst.addOperand(MCOperand::CreateImm(4));
1161 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1162 TmpInst.addOperand(MCOperand::CreateReg(0));
1163 OutStreamer.EmitInstruction(TmpInst);
1167 TmpInst.setOpcode(ARM::LDRi12);
1168 TmpInst.addOperand(MCOperand::CreateReg(ARM::R7));
1169 TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
1170 TmpInst.addOperand(MCOperand::CreateImm(0));
1172 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1173 TmpInst.addOperand(MCOperand::CreateReg(0));
1174 OutStreamer.EmitInstruction(TmpInst);
1178 TmpInst.setOpcode(ARM::BRIND);
1179 TmpInst.addOperand(MCOperand::CreateReg(ScratchReg));
1181 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1182 TmpInst.addOperand(MCOperand::CreateReg(0));
1183 OutStreamer.EmitInstruction(TmpInst);
1187 case ARM::tInt_eh_sjlj_longjmp: {
1188 // ldr $scratch, [$src, #8]
1190 // ldr $scratch, [$src, #4]
1193 unsigned SrcReg = MI->getOperand(0).getReg();
1194 unsigned ScratchReg = MI->getOperand(1).getReg();
1197 TmpInst.setOpcode(ARM::tLDR);
1198 TmpInst.addOperand(MCOperand::CreateReg(ScratchReg));
1199 TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
1200 // The offset immediate is #8. The operand value is scaled by 4 for the
1201 // tSTR instruction.
1202 TmpInst.addOperand(MCOperand::CreateImm(2));
1203 TmpInst.addOperand(MCOperand::CreateReg(0));
1205 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1206 TmpInst.addOperand(MCOperand::CreateReg(0));
1207 OutStreamer.EmitInstruction(TmpInst);
1211 TmpInst.setOpcode(ARM::tMOVtgpr2gpr);
1212 TmpInst.addOperand(MCOperand::CreateReg(ARM::SP));
1213 TmpInst.addOperand(MCOperand::CreateReg(ScratchReg));
1215 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1216 TmpInst.addOperand(MCOperand::CreateReg(0));
1217 OutStreamer.EmitInstruction(TmpInst);
1221 TmpInst.setOpcode(ARM::tLDR);
1222 TmpInst.addOperand(MCOperand::CreateReg(ScratchReg));
1223 TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
1224 TmpInst.addOperand(MCOperand::CreateImm(1));
1225 TmpInst.addOperand(MCOperand::CreateReg(0));
1227 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1228 TmpInst.addOperand(MCOperand::CreateReg(0));
1229 OutStreamer.EmitInstruction(TmpInst);
1233 TmpInst.setOpcode(ARM::tLDR);
1234 TmpInst.addOperand(MCOperand::CreateReg(ARM::R7));
1235 TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
1236 TmpInst.addOperand(MCOperand::CreateImm(0));
1237 TmpInst.addOperand(MCOperand::CreateReg(0));
1239 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1240 TmpInst.addOperand(MCOperand::CreateReg(0));
1241 OutStreamer.EmitInstruction(TmpInst);
1245 TmpInst.setOpcode(ARM::tBX_RET_vararg);
1246 TmpInst.addOperand(MCOperand::CreateReg(ScratchReg));
1248 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1249 TmpInst.addOperand(MCOperand::CreateReg(0));
1250 OutStreamer.EmitInstruction(TmpInst);
1257 MCInstLowering.Lower(MI, TmpInst);
1258 OutStreamer.EmitInstruction(TmpInst);
1261 //===----------------------------------------------------------------------===//
1262 // Target Registry Stuff
1263 //===----------------------------------------------------------------------===//
1265 static MCInstPrinter *createARMMCInstPrinter(const Target &T,
1266 unsigned SyntaxVariant,
1267 const MCAsmInfo &MAI) {
1268 if (SyntaxVariant == 0)
1269 return new ARMInstPrinter(MAI);
1273 // Force static initialization.
1274 extern "C" void LLVMInitializeARMAsmPrinter() {
1275 RegisterAsmPrinter<ARMAsmPrinter> X(TheARMTarget);
1276 RegisterAsmPrinter<ARMAsmPrinter> Y(TheThumbTarget);
1278 TargetRegistry::RegisterMCInstPrinter(TheARMTarget, createARMMCInstPrinter);
1279 TargetRegistry::RegisterMCInstPrinter(TheThumbTarget, createARMMCInstPrinter);