1 //===-- ARMAsmPrinter.cpp - Print machine code to an ARM .s file ----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains a printer that converts from our internal representation
11 // of machine-dependent LLVM code to GAS-format ARM assembly language.
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "asm-printer"
17 #include "ARMBuildAttrs.h"
18 #include "ARMAddressingModes.h"
19 #include "ARMConstantPoolValue.h"
20 #include "InstPrinter/ARMInstPrinter.h"
21 #include "ARMAsmPrinter.h"
22 #include "ARMMachineFunctionInfo.h"
23 #include "ARMTargetMachine.h"
24 #include "ARMTargetObjectFile.h"
25 #include "llvm/Analysis/DebugInfo.h"
26 #include "llvm/Constants.h"
27 #include "llvm/Module.h"
28 #include "llvm/Type.h"
29 #include "llvm/Assembly/Writer.h"
30 #include "llvm/CodeGen/MachineModuleInfoImpls.h"
31 #include "llvm/CodeGen/MachineFunctionPass.h"
32 #include "llvm/CodeGen/MachineJumpTableInfo.h"
33 #include "llvm/MC/MCAsmInfo.h"
34 #include "llvm/MC/MCAssembler.h"
35 #include "llvm/MC/MCContext.h"
36 #include "llvm/MC/MCExpr.h"
37 #include "llvm/MC/MCInst.h"
38 #include "llvm/MC/MCSectionMachO.h"
39 #include "llvm/MC/MCObjectStreamer.h"
40 #include "llvm/MC/MCStreamer.h"
41 #include "llvm/MC/MCSymbol.h"
42 #include "llvm/Target/Mangler.h"
43 #include "llvm/Target/TargetData.h"
44 #include "llvm/Target/TargetMachine.h"
45 #include "llvm/Target/TargetOptions.h"
46 #include "llvm/Target/TargetRegistry.h"
47 #include "llvm/ADT/SmallPtrSet.h"
48 #include "llvm/ADT/SmallString.h"
49 #include "llvm/ADT/StringExtras.h"
50 #include "llvm/Support/CommandLine.h"
51 #include "llvm/Support/Debug.h"
52 #include "llvm/Support/ErrorHandling.h"
53 #include "llvm/Support/raw_ostream.h"
59 // Per section and per symbol attributes are not supported.
60 // To implement them we would need the ability to delay this emission
61 // until the assembly file is fully parsed/generated as only then do we
62 // know the symbol and section numbers.
63 class AttributeEmitter {
65 virtual void MaybeSwitchVendor(StringRef Vendor) = 0;
66 virtual void EmitAttribute(unsigned Attribute, unsigned Value) = 0;
67 virtual void Finish() = 0;
68 virtual ~AttributeEmitter() {}
71 class AsmAttributeEmitter : public AttributeEmitter {
75 AsmAttributeEmitter(MCStreamer &Streamer_) : Streamer(Streamer_) {}
76 void MaybeSwitchVendor(StringRef Vendor) { }
78 void EmitAttribute(unsigned Attribute, unsigned Value) {
79 Streamer.EmitRawText("\t.eabi_attribute " +
80 Twine(Attribute) + ", " + Twine(Value));
86 class ObjectAttributeEmitter : public AttributeEmitter {
87 MCObjectStreamer &Streamer;
88 StringRef CurrentVendor;
89 SmallString<64> Contents;
92 ObjectAttributeEmitter(MCObjectStreamer &Streamer_) :
93 Streamer(Streamer_), CurrentVendor("") { }
95 void MaybeSwitchVendor(StringRef Vendor) {
96 assert(!Vendor.empty() && "Vendor cannot be empty.");
98 if (CurrentVendor.empty())
99 CurrentVendor = Vendor;
100 else if (CurrentVendor == Vendor)
105 CurrentVendor = Vendor;
107 assert(Contents.size() == 0);
110 void EmitAttribute(unsigned Attribute, unsigned Value) {
111 // FIXME: should be ULEB
112 Contents += Attribute;
117 const size_t ContentsSize = Contents.size();
119 // Vendor size + Vendor name + '\0'
120 const size_t VendorHeaderSize = 4 + CurrentVendor.size() + 1;
123 const size_t TagHeaderSize = 1 + 4;
125 Streamer.EmitIntValue(VendorHeaderSize + TagHeaderSize + ContentsSize, 4);
126 Streamer.EmitBytes(CurrentVendor, 0);
127 Streamer.EmitIntValue(0, 1); // '\0'
129 Streamer.EmitIntValue(ARMBuildAttrs::File, 1);
130 Streamer.EmitIntValue(TagHeaderSize + ContentsSize, 4);
132 Streamer.EmitBytes(Contents, 0);
138 } // end of anonymous namespace
140 MachineLocation ARMAsmPrinter::
141 getDebugValueLocation(const MachineInstr *MI) const {
142 MachineLocation Location;
143 assert(MI->getNumOperands() == 4 && "Invalid no. of machine operands!");
144 // Frame address. Currently handles register +- offset only.
145 if (MI->getOperand(0).isReg() && MI->getOperand(1).isImm())
146 Location.set(MI->getOperand(0).getReg(), MI->getOperand(1).getImm());
148 DEBUG(dbgs() << "DBG_VALUE instruction ignored! " << *MI << "\n");
153 void ARMAsmPrinter::EmitFunctionEntryLabel() {
154 if (AFI->isThumbFunction()) {
155 OutStreamer.EmitAssemblerFlag(MCAF_Code16);
156 OutStreamer.EmitThumbFunc(Subtarget->isTargetDarwin()? CurrentFnSym : 0);
159 OutStreamer.EmitLabel(CurrentFnSym);
162 /// runOnMachineFunction - This uses the EmitInstruction()
163 /// method to print assembly for each instruction.
165 bool ARMAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
166 AFI = MF.getInfo<ARMFunctionInfo>();
167 MCP = MF.getConstantPool();
169 return AsmPrinter::runOnMachineFunction(MF);
172 void ARMAsmPrinter::printOperand(const MachineInstr *MI, int OpNum,
173 raw_ostream &O, const char *Modifier) {
174 const MachineOperand &MO = MI->getOperand(OpNum);
175 unsigned TF = MO.getTargetFlags();
177 switch (MO.getType()) {
179 assert(0 && "<unknown operand type>");
180 case MachineOperand::MO_Register: {
181 unsigned Reg = MO.getReg();
182 assert(TargetRegisterInfo::isPhysicalRegister(Reg));
183 assert(!MO.getSubReg() && "Subregs should be eliminated!");
184 O << ARMInstPrinter::getRegisterName(Reg);
187 case MachineOperand::MO_Immediate: {
188 int64_t Imm = MO.getImm();
190 if ((Modifier && strcmp(Modifier, "lo16") == 0) ||
191 (TF == ARMII::MO_LO16))
193 else if ((Modifier && strcmp(Modifier, "hi16") == 0) ||
194 (TF == ARMII::MO_HI16))
199 case MachineOperand::MO_MachineBasicBlock:
200 O << *MO.getMBB()->getSymbol();
202 case MachineOperand::MO_GlobalAddress: {
203 const GlobalValue *GV = MO.getGlobal();
204 if ((Modifier && strcmp(Modifier, "lo16") == 0) ||
205 (TF & ARMII::MO_LO16))
207 else if ((Modifier && strcmp(Modifier, "hi16") == 0) ||
208 (TF & ARMII::MO_HI16))
210 O << *Mang->getSymbol(GV);
212 printOffset(MO.getOffset(), O);
213 if (TF == ARMII::MO_PLT)
217 case MachineOperand::MO_ExternalSymbol: {
218 O << *GetExternalSymbolSymbol(MO.getSymbolName());
219 if (TF == ARMII::MO_PLT)
223 case MachineOperand::MO_ConstantPoolIndex:
224 O << *GetCPISymbol(MO.getIndex());
226 case MachineOperand::MO_JumpTableIndex:
227 O << *GetJTISymbol(MO.getIndex());
232 //===--------------------------------------------------------------------===//
234 MCSymbol *ARMAsmPrinter::
235 GetARMSetPICJumpTableLabel2(unsigned uid, unsigned uid2,
236 const MachineBasicBlock *MBB) const {
237 SmallString<60> Name;
238 raw_svector_ostream(Name) << MAI->getPrivateGlobalPrefix()
239 << getFunctionNumber() << '_' << uid << '_' << uid2
240 << "_set_" << MBB->getNumber();
241 return OutContext.GetOrCreateSymbol(Name.str());
244 MCSymbol *ARMAsmPrinter::
245 GetARMJTIPICJumpTableLabel2(unsigned uid, unsigned uid2) const {
246 SmallString<60> Name;
247 raw_svector_ostream(Name) << MAI->getPrivateGlobalPrefix() << "JTI"
248 << getFunctionNumber() << '_' << uid << '_' << uid2;
249 return OutContext.GetOrCreateSymbol(Name.str());
253 MCSymbol *ARMAsmPrinter::GetARMSJLJEHLabel(void) const {
254 SmallString<60> Name;
255 raw_svector_ostream(Name) << MAI->getPrivateGlobalPrefix() << "SJLJEH"
256 << getFunctionNumber();
257 return OutContext.GetOrCreateSymbol(Name.str());
260 bool ARMAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
261 unsigned AsmVariant, const char *ExtraCode,
263 // Does this asm operand have a single letter operand modifier?
264 if (ExtraCode && ExtraCode[0]) {
265 if (ExtraCode[1] != 0) return true; // Unknown modifier.
267 switch (ExtraCode[0]) {
268 default: return true; // Unknown modifier.
269 case 'a': // Print as a memory address.
270 if (MI->getOperand(OpNum).isReg()) {
272 << ARMInstPrinter::getRegisterName(MI->getOperand(OpNum).getReg())
277 case 'c': // Don't print "#" before an immediate operand.
278 if (!MI->getOperand(OpNum).isImm())
280 O << MI->getOperand(OpNum).getImm();
282 case 'P': // Print a VFP double precision register.
283 case 'q': // Print a NEON quad precision register.
284 printOperand(MI, OpNum, O);
289 report_fatal_error("llvm does not support 'Q', 'R', and 'H' modifiers!");
294 printOperand(MI, OpNum, O);
298 bool ARMAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI,
299 unsigned OpNum, unsigned AsmVariant,
300 const char *ExtraCode,
302 if (ExtraCode && ExtraCode[0])
303 return true; // Unknown modifier.
305 const MachineOperand &MO = MI->getOperand(OpNum);
306 assert(MO.isReg() && "unexpected inline asm memory operand");
307 O << "[" << ARMInstPrinter::getRegisterName(MO.getReg()) << "]";
311 void ARMAsmPrinter::EmitStartOfAsmFile(Module &M) {
312 if (Subtarget->isTargetDarwin()) {
313 Reloc::Model RelocM = TM.getRelocationModel();
314 if (RelocM == Reloc::PIC_ || RelocM == Reloc::DynamicNoPIC) {
315 // Declare all the text sections up front (before the DWARF sections
316 // emitted by AsmPrinter::doInitialization) so the assembler will keep
317 // them together at the beginning of the object file. This helps
318 // avoid out-of-range branches that are due a fundamental limitation of
319 // the way symbol offsets are encoded with the current Darwin ARM
321 const TargetLoweringObjectFileMachO &TLOFMacho =
322 static_cast<const TargetLoweringObjectFileMachO &>(
323 getObjFileLowering());
324 OutStreamer.SwitchSection(TLOFMacho.getTextSection());
325 OutStreamer.SwitchSection(TLOFMacho.getTextCoalSection());
326 OutStreamer.SwitchSection(TLOFMacho.getConstTextCoalSection());
327 if (RelocM == Reloc::DynamicNoPIC) {
328 const MCSection *sect =
329 OutContext.getMachOSection("__TEXT", "__symbol_stub4",
330 MCSectionMachO::S_SYMBOL_STUBS,
331 12, SectionKind::getText());
332 OutStreamer.SwitchSection(sect);
334 const MCSection *sect =
335 OutContext.getMachOSection("__TEXT", "__picsymbolstub4",
336 MCSectionMachO::S_SYMBOL_STUBS,
337 16, SectionKind::getText());
338 OutStreamer.SwitchSection(sect);
340 const MCSection *StaticInitSect =
341 OutContext.getMachOSection("__TEXT", "__StaticInit",
342 MCSectionMachO::S_REGULAR |
343 MCSectionMachO::S_ATTR_PURE_INSTRUCTIONS,
344 SectionKind::getText());
345 OutStreamer.SwitchSection(StaticInitSect);
349 // Use unified assembler syntax.
350 OutStreamer.EmitAssemblerFlag(MCAF_SyntaxUnified);
352 // Emit ARM Build Attributes
353 if (Subtarget->isTargetELF()) {
360 void ARMAsmPrinter::EmitEndOfAsmFile(Module &M) {
361 if (Subtarget->isTargetDarwin()) {
362 // All darwin targets use mach-o.
363 const TargetLoweringObjectFileMachO &TLOFMacho =
364 static_cast<const TargetLoweringObjectFileMachO &>(getObjFileLowering());
365 MachineModuleInfoMachO &MMIMacho =
366 MMI->getObjFileInfo<MachineModuleInfoMachO>();
368 // Output non-lazy-pointers for external and common global variables.
369 MachineModuleInfoMachO::SymbolListTy Stubs = MMIMacho.GetGVStubList();
371 if (!Stubs.empty()) {
372 // Switch with ".non_lazy_symbol_pointer" directive.
373 OutStreamer.SwitchSection(TLOFMacho.getNonLazySymbolPointerSection());
375 for (unsigned i = 0, e = Stubs.size(); i != e; ++i) {
377 OutStreamer.EmitLabel(Stubs[i].first);
378 // .indirect_symbol _foo
379 MachineModuleInfoImpl::StubValueTy &MCSym = Stubs[i].second;
380 OutStreamer.EmitSymbolAttribute(MCSym.getPointer(),MCSA_IndirectSymbol);
383 // External to current translation unit.
384 OutStreamer.EmitIntValue(0, 4/*size*/, 0/*addrspace*/);
386 // Internal to current translation unit.
388 // When we place the LSDA into the TEXT section, the type info
389 // pointers need to be indirect and pc-rel. We accomplish this by
390 // using NLPs; however, sometimes the types are local to the file.
391 // We need to fill in the value for the NLP in those cases.
392 OutStreamer.EmitValue(MCSymbolRefExpr::Create(MCSym.getPointer(),
394 4/*size*/, 0/*addrspace*/);
398 OutStreamer.AddBlankLine();
401 Stubs = MMIMacho.GetHiddenGVStubList();
402 if (!Stubs.empty()) {
403 OutStreamer.SwitchSection(getObjFileLowering().getDataSection());
405 for (unsigned i = 0, e = Stubs.size(); i != e; ++i) {
407 OutStreamer.EmitLabel(Stubs[i].first);
409 OutStreamer.EmitValue(MCSymbolRefExpr::
410 Create(Stubs[i].second.getPointer(),
412 4/*size*/, 0/*addrspace*/);
416 OutStreamer.AddBlankLine();
419 // Funny Darwin hack: This flag tells the linker that no global symbols
420 // contain code that falls through to other global symbols (e.g. the obvious
421 // implementation of multiple entry points). If this doesn't occur, the
422 // linker can safely perform dead code stripping. Since LLVM never
423 // generates code that does this, it is always safe to set.
424 OutStreamer.EmitAssemblerFlag(MCAF_SubsectionsViaSymbols);
428 //===----------------------------------------------------------------------===//
429 // Helper routines for EmitStartOfAsmFile() and EmitEndOfAsmFile()
431 // The following seem like one-off assembler flags, but they actually need
432 // to appear in the .ARM.attributes section in ELF.
433 // Instead of subclassing the MCELFStreamer, we do the work here.
435 void ARMAsmPrinter::emitAttributes() {
437 emitARMAttributeSection();
439 AttributeEmitter *AttrEmitter;
440 if (OutStreamer.hasRawTextSupport())
441 AttrEmitter = new AsmAttributeEmitter(OutStreamer);
443 MCObjectStreamer &O = static_cast<MCObjectStreamer&>(OutStreamer);
444 AttrEmitter = new ObjectAttributeEmitter(O);
447 AttrEmitter->MaybeSwitchVendor("aeabi");
449 std::string CPUString = Subtarget->getCPUString();
450 if (OutStreamer.hasRawTextSupport()) {
451 if (CPUString != "generic")
452 OutStreamer.EmitRawText(StringRef("\t.cpu ") + CPUString);
454 assert(CPUString == "generic" && "Unsupported .cpu attribute for ELF/.o");
455 // FIXME: Why these defaults?
456 AttrEmitter->EmitAttribute(ARMBuildAttrs::CPU_arch, ARMBuildAttrs::v4T);
457 AttrEmitter->EmitAttribute(ARMBuildAttrs::ARM_ISA_use, 1);
458 AttrEmitter->EmitAttribute(ARMBuildAttrs::THUMB_ISA_use, 1);
461 // FIXME: Emit FPU type
462 if (Subtarget->hasVFP2())
463 AttrEmitter->EmitAttribute(ARMBuildAttrs::VFP_arch, 2);
465 // Signal various FP modes.
467 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_FP_denormal, 1);
468 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_FP_exceptions, 1);
471 if (NoInfsFPMath && NoNaNsFPMath)
472 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_FP_number_model, 1);
474 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_FP_number_model, 3);
476 // 8-bytes alignment stuff.
477 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_align8_needed, 1);
478 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_align8_preserved, 1);
480 // Hard float. Use both S and D registers and conform to AAPCS-VFP.
481 if (Subtarget->isAAPCS_ABI() && FloatABIType == FloatABI::Hard) {
482 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_HardFP_use, 3);
483 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_VFP_args, 1);
485 // FIXME: Should we signal R9 usage?
487 AttrEmitter->EmitAttribute(ARMBuildAttrs::DIV_use, 1);
489 AttrEmitter->Finish();
493 void ARMAsmPrinter::emitARMAttributeSection() {
495 // [ <section-length> "vendor-name"
496 // [ <file-tag> <size> <attribute>*
497 // | <section-tag> <size> <section-number>* 0 <attribute>*
498 // | <symbol-tag> <size> <symbol-number>* 0 <attribute>*
502 if (OutStreamer.hasRawTextSupport())
505 const ARMElfTargetObjectFile &TLOFELF =
506 static_cast<const ARMElfTargetObjectFile &>
507 (getObjFileLowering());
509 OutStreamer.SwitchSection(TLOFELF.getAttributesSection());
512 OutStreamer.EmitIntValue(0x41, 1);
515 //===----------------------------------------------------------------------===//
517 static MCSymbol *getPICLabel(const char *Prefix, unsigned FunctionNumber,
518 unsigned LabelId, MCContext &Ctx) {
520 MCSymbol *Label = Ctx.GetOrCreateSymbol(Twine(Prefix)
521 + "PC" + Twine(FunctionNumber) + "_" + Twine(LabelId));
525 static MCSymbolRefExpr::VariantKind
526 getModifierVariantKind(ARMCP::ARMCPModifier Modifier) {
528 default: llvm_unreachable("Unknown modifier!");
529 case ARMCP::no_modifier: return MCSymbolRefExpr::VK_None;
530 case ARMCP::TLSGD: return MCSymbolRefExpr::VK_ARM_TLSGD;
531 case ARMCP::TPOFF: return MCSymbolRefExpr::VK_ARM_TPOFF;
532 case ARMCP::GOTTPOFF: return MCSymbolRefExpr::VK_ARM_GOTTPOFF;
533 case ARMCP::GOT: return MCSymbolRefExpr::VK_ARM_GOT;
534 case ARMCP::GOTOFF: return MCSymbolRefExpr::VK_ARM_GOTOFF;
536 return MCSymbolRefExpr::VK_None;
540 EmitMachineConstantPoolValue(MachineConstantPoolValue *MCPV) {
541 int Size = TM.getTargetData()->getTypeAllocSize(MCPV->getType());
543 ARMConstantPoolValue *ACPV = static_cast<ARMConstantPoolValue*>(MCPV);
546 if (ACPV->isLSDA()) {
547 SmallString<128> Str;
548 raw_svector_ostream OS(Str);
549 OS << MAI->getPrivateGlobalPrefix() << "_LSDA_" << getFunctionNumber();
550 MCSym = OutContext.GetOrCreateSymbol(OS.str());
551 } else if (ACPV->isBlockAddress()) {
552 MCSym = GetBlockAddressSymbol(ACPV->getBlockAddress());
553 } else if (ACPV->isGlobalValue()) {
554 const GlobalValue *GV = ACPV->getGV();
555 bool isIndirect = Subtarget->isTargetDarwin() &&
556 Subtarget->GVIsIndirectSymbol(GV, TM.getRelocationModel());
558 MCSym = Mang->getSymbol(GV);
560 // FIXME: Remove this when Darwin transition to @GOT like syntax.
561 MCSym = GetSymbolWithGlobalValueBase(GV, "$non_lazy_ptr");
563 MachineModuleInfoMachO &MMIMachO =
564 MMI->getObjFileInfo<MachineModuleInfoMachO>();
565 MachineModuleInfoImpl::StubValueTy &StubSym =
566 GV->hasHiddenVisibility() ? MMIMachO.getHiddenGVStubEntry(MCSym) :
567 MMIMachO.getGVStubEntry(MCSym);
568 if (StubSym.getPointer() == 0)
569 StubSym = MachineModuleInfoImpl::
570 StubValueTy(Mang->getSymbol(GV), !GV->hasInternalLinkage());
573 assert(ACPV->isExtSymbol() && "unrecognized constant pool value");
574 MCSym = GetExternalSymbolSymbol(ACPV->getSymbol());
577 // Create an MCSymbol for the reference.
579 MCSymbolRefExpr::Create(MCSym, getModifierVariantKind(ACPV->getModifier()),
582 if (ACPV->getPCAdjustment()) {
583 MCSymbol *PCLabel = getPICLabel(MAI->getPrivateGlobalPrefix(),
587 const MCExpr *PCRelExpr = MCSymbolRefExpr::Create(PCLabel, OutContext);
589 MCBinaryExpr::CreateAdd(PCRelExpr,
590 MCConstantExpr::Create(ACPV->getPCAdjustment(),
593 if (ACPV->mustAddCurrentAddress()) {
594 // We want "(<expr> - .)", but MC doesn't have a concept of the '.'
595 // label, so just emit a local label end reference that instead.
596 MCSymbol *DotSym = OutContext.CreateTempSymbol();
597 OutStreamer.EmitLabel(DotSym);
598 const MCExpr *DotExpr = MCSymbolRefExpr::Create(DotSym, OutContext);
599 PCRelExpr = MCBinaryExpr::CreateSub(PCRelExpr, DotExpr, OutContext);
601 Expr = MCBinaryExpr::CreateSub(Expr, PCRelExpr, OutContext);
603 OutStreamer.EmitValue(Expr, Size);
606 void ARMAsmPrinter::EmitJumpTable(const MachineInstr *MI) {
607 unsigned Opcode = MI->getOpcode();
609 if (Opcode == ARM::BR_JTadd)
611 else if (Opcode == ARM::BR_JTm)
614 const MachineOperand &MO1 = MI->getOperand(OpNum);
615 const MachineOperand &MO2 = MI->getOperand(OpNum+1); // Unique Id
616 unsigned JTI = MO1.getIndex();
618 // Emit a label for the jump table.
619 MCSymbol *JTISymbol = GetARMJTIPICJumpTableLabel2(JTI, MO2.getImm());
620 OutStreamer.EmitLabel(JTISymbol);
622 // Emit each entry of the table.
623 const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
624 const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
625 const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
627 for (unsigned i = 0, e = JTBBs.size(); i != e; ++i) {
628 MachineBasicBlock *MBB = JTBBs[i];
629 // Construct an MCExpr for the entry. We want a value of the form:
630 // (BasicBlockAddr - TableBeginAddr)
632 // For example, a table with entries jumping to basic blocks BB0 and BB1
635 // .word (LBB0 - LJTI_0_0)
636 // .word (LBB1 - LJTI_0_0)
637 const MCExpr *Expr = MCSymbolRefExpr::Create(MBB->getSymbol(), OutContext);
639 if (TM.getRelocationModel() == Reloc::PIC_)
640 Expr = MCBinaryExpr::CreateSub(Expr, MCSymbolRefExpr::Create(JTISymbol,
643 OutStreamer.EmitValue(Expr, 4);
647 void ARMAsmPrinter::EmitJump2Table(const MachineInstr *MI) {
648 unsigned Opcode = MI->getOpcode();
649 int OpNum = (Opcode == ARM::t2BR_JT) ? 2 : 1;
650 const MachineOperand &MO1 = MI->getOperand(OpNum);
651 const MachineOperand &MO2 = MI->getOperand(OpNum+1); // Unique Id
652 unsigned JTI = MO1.getIndex();
654 // Emit a label for the jump table.
655 MCSymbol *JTISymbol = GetARMJTIPICJumpTableLabel2(JTI, MO2.getImm());
656 OutStreamer.EmitLabel(JTISymbol);
658 // Emit each entry of the table.
659 const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
660 const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
661 const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
662 unsigned OffsetWidth = 4;
663 if (MI->getOpcode() == ARM::t2TBB_JT)
665 else if (MI->getOpcode() == ARM::t2TBH_JT)
668 for (unsigned i = 0, e = JTBBs.size(); i != e; ++i) {
669 MachineBasicBlock *MBB = JTBBs[i];
670 const MCExpr *MBBSymbolExpr = MCSymbolRefExpr::Create(MBB->getSymbol(),
672 // If this isn't a TBB or TBH, the entries are direct branch instructions.
673 if (OffsetWidth == 4) {
675 BrInst.setOpcode(ARM::t2B);
676 BrInst.addOperand(MCOperand::CreateExpr(MBBSymbolExpr));
677 OutStreamer.EmitInstruction(BrInst);
680 // Otherwise it's an offset from the dispatch instruction. Construct an
681 // MCExpr for the entry. We want a value of the form:
682 // (BasicBlockAddr - TableBeginAddr) / 2
684 // For example, a TBB table with entries jumping to basic blocks BB0 and BB1
687 // .byte (LBB0 - LJTI_0_0) / 2
688 // .byte (LBB1 - LJTI_0_0) / 2
690 MCBinaryExpr::CreateSub(MBBSymbolExpr,
691 MCSymbolRefExpr::Create(JTISymbol, OutContext),
693 Expr = MCBinaryExpr::CreateDiv(Expr, MCConstantExpr::Create(2, OutContext),
695 OutStreamer.EmitValue(Expr, OffsetWidth);
699 void ARMAsmPrinter::PrintDebugValueComment(const MachineInstr *MI,
701 unsigned NOps = MI->getNumOperands();
703 OS << '\t' << MAI->getCommentString() << "DEBUG_VALUE: ";
704 // cast away const; DIetc do not take const operands for some reason.
705 DIVariable V(const_cast<MDNode *>(MI->getOperand(NOps-1).getMetadata()));
708 // Frame address. Currently handles register +- offset only.
709 assert(MI->getOperand(0).isReg() && MI->getOperand(1).isImm());
710 OS << '['; printOperand(MI, 0, OS); OS << '+'; printOperand(MI, 1, OS);
713 printOperand(MI, NOps-2, OS);
716 void ARMAsmPrinter::EmitInstruction(const MachineInstr *MI) {
717 switch (MI->getOpcode()) {
719 case ARM::t2MOVi32imm: assert(0 && "Should be lowered by thumb2it pass");
720 case ARM::DBG_VALUE: {
721 if (isVerbose() && OutStreamer.hasRawTextSupport()) {
722 SmallString<128> TmpStr;
723 raw_svector_ostream OS(TmpStr);
724 PrintDebugValueComment(MI, OS);
725 OutStreamer.EmitRawText(StringRef(OS.str()));
729 case ARM::LEApcrelJT: {
730 unsigned JTI = MI->getOperand(1).getIndex();
731 unsigned Id = MI->getOperand(2).getImm();
732 MCSymbol *JTISymbol = GetARMJTIPICJumpTableLabel2(JTI, Id);
733 const MCExpr *SymbolExpr = MCSymbolRefExpr::Create(JTISymbol, OutContext);
735 TmpInst.setOpcode(ARM::ADRadd);
736 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
737 TmpInst.addOperand(MCOperand::CreateExpr(SymbolExpr));
738 // Add predicate operands.
739 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
740 TmpInst.addOperand(MCOperand::CreateReg(0));
741 OutStreamer.EmitInstruction(TmpInst);
746 TmpInst.setOpcode(ARM::MOVr);
747 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
748 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
749 // Add predicate operands.
750 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
751 TmpInst.addOperand(MCOperand::CreateReg(0));
752 // Add 's' bit operand (always reg0 for this)
753 TmpInst.addOperand(MCOperand::CreateReg(0));
754 OutStreamer.EmitInstruction(TmpInst);
761 TmpInst.setOpcode(ARM::MOVr);
762 TmpInst.addOperand(MCOperand::CreateReg(ARM::LR));
763 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
764 // Add predicate operands.
765 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
766 TmpInst.addOperand(MCOperand::CreateReg(0));
767 // Add 's' bit operand (always reg0 for this)
768 TmpInst.addOperand(MCOperand::CreateReg(0));
769 OutStreamer.EmitInstruction(TmpInst);
773 TmpInst.setOpcode(ARM::BX);
774 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
775 OutStreamer.EmitInstruction(TmpInst);
779 case ARM::BMOVPCRXr9_CALL:
780 case ARM::BMOVPCRX_CALL: {
783 TmpInst.setOpcode(ARM::MOVr);
784 TmpInst.addOperand(MCOperand::CreateReg(ARM::LR));
785 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
786 // Add predicate operands.
787 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
788 TmpInst.addOperand(MCOperand::CreateReg(0));
789 // Add 's' bit operand (always reg0 for this)
790 TmpInst.addOperand(MCOperand::CreateReg(0));
791 OutStreamer.EmitInstruction(TmpInst);
795 TmpInst.setOpcode(ARM::MOVr);
796 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
797 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
798 // Add predicate operands.
799 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
800 TmpInst.addOperand(MCOperand::CreateReg(0));
801 // Add 's' bit operand (always reg0 for this)
802 TmpInst.addOperand(MCOperand::CreateReg(0));
803 OutStreamer.EmitInstruction(TmpInst);
808 // This is a pseudo op for a label + instruction sequence, which looks like:
811 // This adds the address of LPC0 to r0.
814 OutStreamer.EmitLabel(getPICLabel(MAI->getPrivateGlobalPrefix(),
815 getFunctionNumber(), MI->getOperand(2).getImm(),
818 // Form and emit the add.
820 AddInst.setOpcode(ARM::tADDhirr);
821 AddInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
822 AddInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
823 AddInst.addOperand(MCOperand::CreateReg(ARM::PC));
824 // Add predicate operands.
825 AddInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
826 AddInst.addOperand(MCOperand::CreateReg(0));
827 OutStreamer.EmitInstruction(AddInst);
831 // This is a pseudo op for a label + instruction sequence, which looks like:
834 // This adds the address of LPC0 to r0.
837 OutStreamer.EmitLabel(getPICLabel(MAI->getPrivateGlobalPrefix(),
838 getFunctionNumber(), MI->getOperand(2).getImm(),
841 // Form and emit the add.
843 AddInst.setOpcode(ARM::ADDrr);
844 AddInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
845 AddInst.addOperand(MCOperand::CreateReg(ARM::PC));
846 AddInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg()));
847 // Add predicate operands.
848 AddInst.addOperand(MCOperand::CreateImm(MI->getOperand(3).getImm()));
849 AddInst.addOperand(MCOperand::CreateReg(MI->getOperand(4).getReg()));
850 // Add 's' bit operand (always reg0 for this)
851 AddInst.addOperand(MCOperand::CreateReg(0));
852 OutStreamer.EmitInstruction(AddInst);
862 case ARM::PICLDRSH: {
863 // This is a pseudo op for a label + instruction sequence, which looks like:
866 // The LCP0 label is referenced by a constant pool entry in order to get
867 // a PC-relative address at the ldr instruction.
870 OutStreamer.EmitLabel(getPICLabel(MAI->getPrivateGlobalPrefix(),
871 getFunctionNumber(), MI->getOperand(2).getImm(),
874 // Form and emit the load
876 switch (MI->getOpcode()) {
878 llvm_unreachable("Unexpected opcode!");
879 case ARM::PICSTR: Opcode = ARM::STRrs; break;
880 case ARM::PICSTRB: Opcode = ARM::STRBrs; break;
881 case ARM::PICSTRH: Opcode = ARM::STRH; break;
882 case ARM::PICLDR: Opcode = ARM::LDRrs; break;
883 case ARM::PICLDRB: Opcode = ARM::LDRBrs; break;
884 case ARM::PICLDRH: Opcode = ARM::LDRH; break;
885 case ARM::PICLDRSB: Opcode = ARM::LDRSB; break;
886 case ARM::PICLDRSH: Opcode = ARM::LDRSH; break;
889 LdStInst.setOpcode(Opcode);
890 LdStInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
891 LdStInst.addOperand(MCOperand::CreateReg(ARM::PC));
892 LdStInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg()));
893 LdStInst.addOperand(MCOperand::CreateImm(0));
894 // Add predicate operands.
895 LdStInst.addOperand(MCOperand::CreateImm(MI->getOperand(3).getImm()));
896 LdStInst.addOperand(MCOperand::CreateReg(MI->getOperand(4).getReg()));
897 OutStreamer.EmitInstruction(LdStInst);
901 case ARM::CONSTPOOL_ENTRY: {
902 /// CONSTPOOL_ENTRY - This instruction represents a floating constant pool
903 /// in the function. The first operand is the ID# for this instruction, the
904 /// second is the index into the MachineConstantPool that this is, the third
905 /// is the size in bytes of this constant pool entry.
906 unsigned LabelId = (unsigned)MI->getOperand(0).getImm();
907 unsigned CPIdx = (unsigned)MI->getOperand(1).getIndex();
910 OutStreamer.EmitLabel(GetCPISymbol(LabelId));
912 const MachineConstantPoolEntry &MCPE = MCP->getConstants()[CPIdx];
913 if (MCPE.isMachineConstantPoolEntry())
914 EmitMachineConstantPoolValue(MCPE.Val.MachineCPVal);
916 EmitGlobalConstant(MCPE.Val.ConstVal);
921 // Lower and emit the instruction itself, then the jump table following it.
923 TmpInst.setOpcode(ARM::tMOVgpr2gpr);
924 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
925 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
926 // Add predicate operands.
927 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
928 TmpInst.addOperand(MCOperand::CreateReg(0));
929 OutStreamer.EmitInstruction(TmpInst);
930 // Output the data for the jump table itself
934 case ARM::t2TBB_JT: {
935 // Lower and emit the instruction itself, then the jump table following it.
938 TmpInst.setOpcode(ARM::t2TBB);
939 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
940 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
941 // Add predicate operands.
942 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
943 TmpInst.addOperand(MCOperand::CreateReg(0));
944 OutStreamer.EmitInstruction(TmpInst);
945 // Output the data for the jump table itself
947 // Make sure the next instruction is 2-byte aligned.
951 case ARM::t2TBH_JT: {
952 // Lower and emit the instruction itself, then the jump table following it.
955 TmpInst.setOpcode(ARM::t2TBH);
956 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
957 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
958 // Add predicate operands.
959 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
960 TmpInst.addOperand(MCOperand::CreateReg(0));
961 OutStreamer.EmitInstruction(TmpInst);
962 // Output the data for the jump table itself
968 // Lower and emit the instruction itself, then the jump table following it.
971 unsigned Opc = MI->getOpcode() == ARM::BR_JTr ?
972 ARM::MOVr : ARM::tMOVgpr2gpr;
973 TmpInst.setOpcode(Opc);
974 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
975 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
976 // Add predicate operands.
977 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
978 TmpInst.addOperand(MCOperand::CreateReg(0));
979 // Add 's' bit operand (always reg0 for this)
980 if (Opc == ARM::MOVr)
981 TmpInst.addOperand(MCOperand::CreateReg(0));
982 OutStreamer.EmitInstruction(TmpInst);
984 // Make sure the Thumb jump table is 4-byte aligned.
985 if (Opc == ARM::tMOVr)
988 // Output the data for the jump table itself
993 // Lower and emit the instruction itself, then the jump table following it.
996 if (MI->getOperand(1).getReg() == 0) {
998 TmpInst.setOpcode(ARM::LDRi12);
999 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1000 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1001 TmpInst.addOperand(MCOperand::CreateImm(MI->getOperand(2).getImm()));
1003 TmpInst.setOpcode(ARM::LDRrs);
1004 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1005 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1006 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg()));
1007 TmpInst.addOperand(MCOperand::CreateImm(0));
1009 // Add predicate operands.
1010 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1011 TmpInst.addOperand(MCOperand::CreateReg(0));
1012 OutStreamer.EmitInstruction(TmpInst);
1014 // Output the data for the jump table itself
1018 case ARM::BR_JTadd: {
1019 // Lower and emit the instruction itself, then the jump table following it.
1020 // add pc, target, idx
1022 TmpInst.setOpcode(ARM::ADDrr);
1023 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1024 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1025 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg()));
1026 // Add predicate operands.
1027 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1028 TmpInst.addOperand(MCOperand::CreateReg(0));
1029 // Add 's' bit operand (always reg0 for this)
1030 TmpInst.addOperand(MCOperand::CreateReg(0));
1031 OutStreamer.EmitInstruction(TmpInst);
1033 // Output the data for the jump table itself
1038 // Non-Darwin binutils don't yet support the "trap" mnemonic.
1039 // FIXME: Remove this special case when they do.
1040 if (!Subtarget->isTargetDarwin()) {
1041 //.long 0xe7ffdefe @ trap
1042 uint32_t Val = 0xe7ffdefeUL;
1043 OutStreamer.AddComment("trap");
1044 OutStreamer.EmitIntValue(Val, 4);
1050 // Non-Darwin binutils don't yet support the "trap" mnemonic.
1051 // FIXME: Remove this special case when they do.
1052 if (!Subtarget->isTargetDarwin()) {
1053 //.short 57086 @ trap
1054 uint16_t Val = 0xdefe;
1055 OutStreamer.AddComment("trap");
1056 OutStreamer.EmitIntValue(Val, 2);
1061 case ARM::t2Int_eh_sjlj_setjmp:
1062 case ARM::t2Int_eh_sjlj_setjmp_nofp:
1063 case ARM::tInt_eh_sjlj_setjmp: {
1064 // Two incoming args: GPR:$src, GPR:$val
1067 // str $val, [$src, #4]
1072 unsigned SrcReg = MI->getOperand(0).getReg();
1073 unsigned ValReg = MI->getOperand(1).getReg();
1074 MCSymbol *Label = GetARMSJLJEHLabel();
1077 TmpInst.setOpcode(ARM::tMOVgpr2tgpr);
1078 TmpInst.addOperand(MCOperand::CreateReg(ValReg));
1079 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1081 TmpInst.addOperand(MCOperand::CreateReg(ARM::CPSR));
1082 OutStreamer.AddComment("eh_setjmp begin");
1083 OutStreamer.EmitInstruction(TmpInst);
1087 TmpInst.setOpcode(ARM::tADDi3);
1088 TmpInst.addOperand(MCOperand::CreateReg(ValReg));
1090 TmpInst.addOperand(MCOperand::CreateReg(ARM::CPSR));
1091 TmpInst.addOperand(MCOperand::CreateReg(ValReg));
1092 TmpInst.addOperand(MCOperand::CreateImm(7));
1094 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1095 TmpInst.addOperand(MCOperand::CreateReg(0));
1096 OutStreamer.EmitInstruction(TmpInst);
1100 TmpInst.setOpcode(ARM::tSTR);
1101 TmpInst.addOperand(MCOperand::CreateReg(ValReg));
1102 TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
1103 // The offset immediate is #4. The operand value is scaled by 4 for the
1104 // tSTR instruction.
1105 TmpInst.addOperand(MCOperand::CreateImm(1));
1106 TmpInst.addOperand(MCOperand::CreateReg(0));
1108 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1109 TmpInst.addOperand(MCOperand::CreateReg(0));
1110 OutStreamer.EmitInstruction(TmpInst);
1114 TmpInst.setOpcode(ARM::tMOVi8);
1115 TmpInst.addOperand(MCOperand::CreateReg(ARM::R0));
1116 TmpInst.addOperand(MCOperand::CreateReg(ARM::CPSR));
1117 TmpInst.addOperand(MCOperand::CreateImm(0));
1119 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1120 TmpInst.addOperand(MCOperand::CreateReg(0));
1121 OutStreamer.EmitInstruction(TmpInst);
1124 const MCExpr *SymbolExpr = MCSymbolRefExpr::Create(Label, OutContext);
1126 TmpInst.setOpcode(ARM::tB);
1127 TmpInst.addOperand(MCOperand::CreateExpr(SymbolExpr));
1128 OutStreamer.EmitInstruction(TmpInst);
1132 TmpInst.setOpcode(ARM::tMOVi8);
1133 TmpInst.addOperand(MCOperand::CreateReg(ARM::R0));
1134 TmpInst.addOperand(MCOperand::CreateReg(ARM::CPSR));
1135 TmpInst.addOperand(MCOperand::CreateImm(1));
1137 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1138 TmpInst.addOperand(MCOperand::CreateReg(0));
1139 OutStreamer.AddComment("eh_setjmp end");
1140 OutStreamer.EmitInstruction(TmpInst);
1142 OutStreamer.EmitLabel(Label);
1146 case ARM::Int_eh_sjlj_setjmp_nofp:
1147 case ARM::Int_eh_sjlj_setjmp: {
1148 // Two incoming args: GPR:$src, GPR:$val
1150 // str $val, [$src, #+4]
1154 unsigned SrcReg = MI->getOperand(0).getReg();
1155 unsigned ValReg = MI->getOperand(1).getReg();
1159 TmpInst.setOpcode(ARM::ADDri);
1160 TmpInst.addOperand(MCOperand::CreateReg(ValReg));
1161 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1162 TmpInst.addOperand(MCOperand::CreateImm(8));
1164 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1165 TmpInst.addOperand(MCOperand::CreateReg(0));
1166 // 's' bit operand (always reg0 for this).
1167 TmpInst.addOperand(MCOperand::CreateReg(0));
1168 OutStreamer.AddComment("eh_setjmp begin");
1169 OutStreamer.EmitInstruction(TmpInst);
1173 TmpInst.setOpcode(ARM::STRi12);
1174 TmpInst.addOperand(MCOperand::CreateReg(ValReg));
1175 TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
1176 TmpInst.addOperand(MCOperand::CreateImm(4));
1178 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1179 TmpInst.addOperand(MCOperand::CreateReg(0));
1180 OutStreamer.EmitInstruction(TmpInst);
1184 TmpInst.setOpcode(ARM::MOVi);
1185 TmpInst.addOperand(MCOperand::CreateReg(ARM::R0));
1186 TmpInst.addOperand(MCOperand::CreateImm(0));
1188 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1189 TmpInst.addOperand(MCOperand::CreateReg(0));
1190 // 's' bit operand (always reg0 for this).
1191 TmpInst.addOperand(MCOperand::CreateReg(0));
1192 OutStreamer.EmitInstruction(TmpInst);
1196 TmpInst.setOpcode(ARM::ADDri);
1197 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1198 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1199 TmpInst.addOperand(MCOperand::CreateImm(0));
1201 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1202 TmpInst.addOperand(MCOperand::CreateReg(0));
1203 // 's' bit operand (always reg0 for this).
1204 TmpInst.addOperand(MCOperand::CreateReg(0));
1205 OutStreamer.EmitInstruction(TmpInst);
1209 TmpInst.setOpcode(ARM::MOVi);
1210 TmpInst.addOperand(MCOperand::CreateReg(ARM::R0));
1211 TmpInst.addOperand(MCOperand::CreateImm(1));
1213 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1214 TmpInst.addOperand(MCOperand::CreateReg(0));
1215 // 's' bit operand (always reg0 for this).
1216 TmpInst.addOperand(MCOperand::CreateReg(0));
1217 OutStreamer.AddComment("eh_setjmp end");
1218 OutStreamer.EmitInstruction(TmpInst);
1222 case ARM::Int_eh_sjlj_longjmp: {
1223 // ldr sp, [$src, #8]
1224 // ldr $scratch, [$src, #4]
1227 unsigned SrcReg = MI->getOperand(0).getReg();
1228 unsigned ScratchReg = MI->getOperand(1).getReg();
1231 TmpInst.setOpcode(ARM::LDRi12);
1232 TmpInst.addOperand(MCOperand::CreateReg(ARM::SP));
1233 TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
1234 TmpInst.addOperand(MCOperand::CreateImm(8));
1236 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1237 TmpInst.addOperand(MCOperand::CreateReg(0));
1238 OutStreamer.EmitInstruction(TmpInst);
1242 TmpInst.setOpcode(ARM::LDRi12);
1243 TmpInst.addOperand(MCOperand::CreateReg(ScratchReg));
1244 TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
1245 TmpInst.addOperand(MCOperand::CreateImm(4));
1247 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1248 TmpInst.addOperand(MCOperand::CreateReg(0));
1249 OutStreamer.EmitInstruction(TmpInst);
1253 TmpInst.setOpcode(ARM::LDRi12);
1254 TmpInst.addOperand(MCOperand::CreateReg(ARM::R7));
1255 TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
1256 TmpInst.addOperand(MCOperand::CreateImm(0));
1258 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1259 TmpInst.addOperand(MCOperand::CreateReg(0));
1260 OutStreamer.EmitInstruction(TmpInst);
1264 TmpInst.setOpcode(ARM::BX);
1265 TmpInst.addOperand(MCOperand::CreateReg(ScratchReg));
1267 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1268 TmpInst.addOperand(MCOperand::CreateReg(0));
1269 OutStreamer.EmitInstruction(TmpInst);
1273 case ARM::tInt_eh_sjlj_longjmp: {
1274 // ldr $scratch, [$src, #8]
1276 // ldr $scratch, [$src, #4]
1279 unsigned SrcReg = MI->getOperand(0).getReg();
1280 unsigned ScratchReg = MI->getOperand(1).getReg();
1283 TmpInst.setOpcode(ARM::tLDR);
1284 TmpInst.addOperand(MCOperand::CreateReg(ScratchReg));
1285 TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
1286 // The offset immediate is #8. The operand value is scaled by 4 for the
1287 // tSTR instruction.
1288 TmpInst.addOperand(MCOperand::CreateImm(2));
1289 TmpInst.addOperand(MCOperand::CreateReg(0));
1291 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1292 TmpInst.addOperand(MCOperand::CreateReg(0));
1293 OutStreamer.EmitInstruction(TmpInst);
1297 TmpInst.setOpcode(ARM::tMOVtgpr2gpr);
1298 TmpInst.addOperand(MCOperand::CreateReg(ARM::SP));
1299 TmpInst.addOperand(MCOperand::CreateReg(ScratchReg));
1301 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1302 TmpInst.addOperand(MCOperand::CreateReg(0));
1303 OutStreamer.EmitInstruction(TmpInst);
1307 TmpInst.setOpcode(ARM::tLDR);
1308 TmpInst.addOperand(MCOperand::CreateReg(ScratchReg));
1309 TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
1310 TmpInst.addOperand(MCOperand::CreateImm(1));
1311 TmpInst.addOperand(MCOperand::CreateReg(0));
1313 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1314 TmpInst.addOperand(MCOperand::CreateReg(0));
1315 OutStreamer.EmitInstruction(TmpInst);
1319 TmpInst.setOpcode(ARM::tLDR);
1320 TmpInst.addOperand(MCOperand::CreateReg(ARM::R7));
1321 TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
1322 TmpInst.addOperand(MCOperand::CreateImm(0));
1323 TmpInst.addOperand(MCOperand::CreateReg(0));
1325 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1326 TmpInst.addOperand(MCOperand::CreateReg(0));
1327 OutStreamer.EmitInstruction(TmpInst);
1331 TmpInst.setOpcode(ARM::tBX_RET_vararg);
1332 TmpInst.addOperand(MCOperand::CreateReg(ScratchReg));
1334 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1335 TmpInst.addOperand(MCOperand::CreateReg(0));
1336 OutStreamer.EmitInstruction(TmpInst);
1343 LowerARMMachineInstrToMCInst(MI, TmpInst, *this);
1344 OutStreamer.EmitInstruction(TmpInst);
1347 //===----------------------------------------------------------------------===//
1348 // Target Registry Stuff
1349 //===----------------------------------------------------------------------===//
1351 static MCInstPrinter *createARMMCInstPrinter(const Target &T,
1352 unsigned SyntaxVariant,
1353 const MCAsmInfo &MAI) {
1354 if (SyntaxVariant == 0)
1355 return new ARMInstPrinter(MAI);
1359 // Force static initialization.
1360 extern "C" void LLVMInitializeARMAsmPrinter() {
1361 RegisterAsmPrinter<ARMAsmPrinter> X(TheARMTarget);
1362 RegisterAsmPrinter<ARMAsmPrinter> Y(TheThumbTarget);
1364 TargetRegistry::RegisterMCInstPrinter(TheARMTarget, createARMMCInstPrinter);
1365 TargetRegistry::RegisterMCInstPrinter(TheThumbTarget, createARMMCInstPrinter);