1 //===-- ARMAsmPrinter.cpp - Print machine code to an ARM .s file ----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains a printer that converts from our internal representation
11 // of machine-dependent LLVM code to GAS-format ARM assembly language.
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "asm-printer"
17 #include "ARMBuildAttrs.h"
18 #include "ARMAddressingModes.h"
19 #include "ARMConstantPoolValue.h"
20 #include "InstPrinter/ARMInstPrinter.h"
21 #include "ARMMachineFunctionInfo.h"
22 #include "ARMMCInstLower.h"
23 #include "ARMTargetMachine.h"
24 #include "ARMTargetObjectFile.h"
25 #include "llvm/Analysis/DebugInfo.h"
26 #include "llvm/Constants.h"
27 #include "llvm/Module.h"
28 #include "llvm/Type.h"
29 #include "llvm/Assembly/Writer.h"
30 #include "llvm/CodeGen/AsmPrinter.h"
31 #include "llvm/CodeGen/MachineModuleInfoImpls.h"
32 #include "llvm/CodeGen/MachineFunctionPass.h"
33 #include "llvm/CodeGen/MachineJumpTableInfo.h"
34 #include "llvm/MC/MCAsmInfo.h"
35 #include "llvm/MC/MCAssembler.h"
36 #include "llvm/MC/MCContext.h"
37 #include "llvm/MC/MCExpr.h"
38 #include "llvm/MC/MCInst.h"
39 #include "llvm/MC/MCSectionMachO.h"
40 #include "llvm/MC/MCObjectStreamer.h"
41 #include "llvm/MC/MCStreamer.h"
42 #include "llvm/MC/MCSymbol.h"
43 #include "llvm/Target/Mangler.h"
44 #include "llvm/Target/TargetData.h"
45 #include "llvm/Target/TargetMachine.h"
46 #include "llvm/Target/TargetOptions.h"
47 #include "llvm/Target/TargetRegistry.h"
48 #include "llvm/ADT/SmallPtrSet.h"
49 #include "llvm/ADT/SmallString.h"
50 #include "llvm/ADT/StringExtras.h"
51 #include "llvm/Support/CommandLine.h"
52 #include "llvm/Support/Debug.h"
53 #include "llvm/Support/ErrorHandling.h"
54 #include "llvm/Support/raw_ostream.h"
69 // Per section and per symbol attributes are not supported.
70 // To implement them we would need the ability to delay this emission
71 // until the assembly file is fully parsed/generated as only then do we
72 // know the symbol and section numbers.
73 class AttributeEmitter {
75 virtual void MaybeSwitchVendor(StringRef Vendor) = 0;
76 virtual void EmitAttribute(unsigned Attribute, unsigned Value) = 0;
77 virtual void Finish() = 0;
78 virtual ~AttributeEmitter() {}
81 class AsmAttributeEmitter : public AttributeEmitter {
85 AsmAttributeEmitter(MCStreamer &Streamer_) : Streamer(Streamer_) {}
86 void MaybeSwitchVendor(StringRef Vendor) { }
88 void EmitAttribute(unsigned Attribute, unsigned Value) {
89 Streamer.EmitRawText("\t.eabi_attribute " +
90 Twine(Attribute) + ", " + Twine(Value));
96 class ObjectAttributeEmitter : public AttributeEmitter {
97 MCObjectStreamer &Streamer;
100 StringRef CurrentVendor;
101 SmallString<64> Contents;
104 ObjectAttributeEmitter(MCObjectStreamer &Streamer_) :
105 Streamer(Streamer_), CurrentVendor("") { }
107 void MaybeSwitchVendor(StringRef Vendor) {
108 assert(!Vendor.empty() && "Vendor cannot be empty.");
110 if (CurrentVendor.empty())
111 CurrentVendor = Vendor;
112 else if (CurrentVendor == Vendor)
117 CurrentVendor = Vendor;
119 SectionStart = Contents.size();
121 // Length of the data for this vendor.
122 Contents.append(4, (char)0);
124 Contents.append(Vendor.begin(), Vendor.end());
127 Contents += ARMBuildAttrs::File;
129 TagStart = Contents.size();
131 // Length of the data for this tag.
132 Contents.append(4, (char)0);
135 void EmitAttribute(unsigned Attribute, unsigned Value) {
136 // FIXME: should be ULEB
137 Contents += Attribute;
142 size_t EndPos = Contents.size();
145 *((uint32_t*)&Contents[SectionStart]) = EndPos - SectionStart;
147 // +1 since it includes the tag that came before it.
148 *((uint32_t*)&Contents[TagStart]) = EndPos - TagStart + 1;
150 Streamer.EmitBytes(Contents, 0);
154 class ARMAsmPrinter : public AsmPrinter {
156 /// Subtarget - Keep a pointer to the ARMSubtarget around so that we can
157 /// make the right decision when printing asm code for different targets.
158 const ARMSubtarget *Subtarget;
160 /// AFI - Keep a pointer to ARMFunctionInfo for the current
162 ARMFunctionInfo *AFI;
164 /// MCP - Keep a pointer to constantpool entries of the current
166 const MachineConstantPool *MCP;
169 explicit ARMAsmPrinter(TargetMachine &TM, MCStreamer &Streamer)
170 : AsmPrinter(TM, Streamer), AFI(NULL), MCP(NULL) {
171 Subtarget = &TM.getSubtarget<ARMSubtarget>();
174 virtual const char *getPassName() const {
175 return "ARM Assembly Printer";
178 void printOperand(const MachineInstr *MI, int OpNum, raw_ostream &O,
179 const char *Modifier = 0);
181 virtual bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
182 unsigned AsmVariant, const char *ExtraCode,
184 virtual bool PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNum,
186 const char *ExtraCode, raw_ostream &O);
188 void EmitJumpTable(const MachineInstr *MI);
189 void EmitJump2Table(const MachineInstr *MI);
190 virtual void EmitInstruction(const MachineInstr *MI);
191 bool runOnMachineFunction(MachineFunction &F);
193 virtual void EmitConstantPool() {} // we emit constant pools customly!
194 virtual void EmitFunctionEntryLabel();
195 void EmitStartOfAsmFile(Module &M);
196 void EmitEndOfAsmFile(Module &M);
199 // Helpers for EmitStartOfAsmFile() and EmitEndOfAsmFile()
200 void emitAttributes();
202 // Helper for ELF .o only
203 void emitARMAttributeSection();
206 void PrintDebugValueComment(const MachineInstr *MI, raw_ostream &OS);
208 MachineLocation getDebugValueLocation(const MachineInstr *MI) const {
209 MachineLocation Location;
210 assert (MI->getNumOperands() == 4 && "Invalid no. of machine operands!");
211 // Frame address. Currently handles register +- offset only.
212 if (MI->getOperand(0).isReg() && MI->getOperand(1).isImm())
213 Location.set(MI->getOperand(0).getReg(), MI->getOperand(1).getImm());
215 DEBUG(dbgs() << "DBG_VALUE instruction ignored! " << *MI << "\n");
220 virtual unsigned getISAEncoding() {
221 // ARM/Darwin adds ISA to the DWARF info for each function.
222 if (!Subtarget->isTargetDarwin())
224 return Subtarget->isThumb() ?
225 llvm::ARM::DW_ISA_ARM_thumb : llvm::ARM::DW_ISA_ARM_arm;
228 MCSymbol *GetARMSetPICJumpTableLabel2(unsigned uid, unsigned uid2,
229 const MachineBasicBlock *MBB) const;
230 MCSymbol *GetARMJTIPICJumpTableLabel2(unsigned uid, unsigned uid2) const;
232 MCSymbol *GetARMSJLJEHLabel(void) const;
234 /// EmitMachineConstantPoolValue - Print a machine constantpool value to
236 virtual void EmitMachineConstantPoolValue(MachineConstantPoolValue *MCPV) {
237 SmallString<128> Str;
238 raw_svector_ostream OS(Str);
239 EmitMachineConstantPoolValue(MCPV, OS);
240 OutStreamer.EmitRawText(OS.str());
243 void EmitMachineConstantPoolValue(MachineConstantPoolValue *MCPV,
245 switch (TM.getTargetData()->getTypeAllocSize(MCPV->getType())) {
246 case 1: O << MAI->getData8bitsDirective(0); break;
247 case 2: O << MAI->getData16bitsDirective(0); break;
248 case 4: O << MAI->getData32bitsDirective(0); break;
249 default: assert(0 && "Unknown CPV size");
252 ARMConstantPoolValue *ACPV = static_cast<ARMConstantPoolValue*>(MCPV);
254 if (ACPV->isLSDA()) {
255 O << MAI->getPrivateGlobalPrefix() << "_LSDA_" << getFunctionNumber();
256 } else if (ACPV->isBlockAddress()) {
257 O << *GetBlockAddressSymbol(ACPV->getBlockAddress());
258 } else if (ACPV->isGlobalValue()) {
259 const GlobalValue *GV = ACPV->getGV();
260 bool isIndirect = Subtarget->isTargetDarwin() &&
261 Subtarget->GVIsIndirectSymbol(GV, TM.getRelocationModel());
263 O << *Mang->getSymbol(GV);
265 // FIXME: Remove this when Darwin transition to @GOT like syntax.
266 MCSymbol *Sym = GetSymbolWithGlobalValueBase(GV, "$non_lazy_ptr");
269 MachineModuleInfoMachO &MMIMachO =
270 MMI->getObjFileInfo<MachineModuleInfoMachO>();
271 MachineModuleInfoImpl::StubValueTy &StubSym =
272 GV->hasHiddenVisibility() ? MMIMachO.getHiddenGVStubEntry(Sym) :
273 MMIMachO.getGVStubEntry(Sym);
274 if (StubSym.getPointer() == 0)
275 StubSym = MachineModuleInfoImpl::
276 StubValueTy(Mang->getSymbol(GV), !GV->hasInternalLinkage());
279 assert(ACPV->isExtSymbol() && "unrecognized constant pool value");
280 O << *GetExternalSymbolSymbol(ACPV->getSymbol());
283 if (ACPV->hasModifier()) O << "(" << ACPV->getModifier() << ")";
284 if (ACPV->getPCAdjustment() != 0) {
285 O << "-(" << MAI->getPrivateGlobalPrefix() << "PC"
286 << getFunctionNumber() << "_" << ACPV->getLabelId()
287 << "+" << (unsigned)ACPV->getPCAdjustment();
288 if (ACPV->mustAddCurrentAddress())
294 } // end of anonymous namespace
296 void ARMAsmPrinter::EmitFunctionEntryLabel() {
297 if (AFI->isThumbFunction()) {
298 OutStreamer.EmitRawText(StringRef("\t.code\t16"));
299 if (!Subtarget->isTargetDarwin())
300 OutStreamer.EmitRawText(StringRef("\t.thumb_func"));
302 // This needs to emit to a temporary string to get properly quoted
303 // MCSymbols when they have spaces in them.
304 SmallString<128> Tmp;
305 raw_svector_ostream OS(Tmp);
306 OS << "\t.thumb_func\t" << *CurrentFnSym;
307 OutStreamer.EmitRawText(OS.str());
311 OutStreamer.EmitLabel(CurrentFnSym);
314 /// runOnMachineFunction - This uses the EmitInstruction()
315 /// method to print assembly for each instruction.
317 bool ARMAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
318 AFI = MF.getInfo<ARMFunctionInfo>();
319 MCP = MF.getConstantPool();
321 return AsmPrinter::runOnMachineFunction(MF);
324 void ARMAsmPrinter::printOperand(const MachineInstr *MI, int OpNum,
325 raw_ostream &O, const char *Modifier) {
326 const MachineOperand &MO = MI->getOperand(OpNum);
327 unsigned TF = MO.getTargetFlags();
329 switch (MO.getType()) {
331 assert(0 && "<unknown operand type>");
332 case MachineOperand::MO_Register: {
333 unsigned Reg = MO.getReg();
334 assert(TargetRegisterInfo::isPhysicalRegister(Reg));
335 assert(!MO.getSubReg() && "Subregs should be eliminated!");
336 O << ARMInstPrinter::getRegisterName(Reg);
339 case MachineOperand::MO_Immediate: {
340 int64_t Imm = MO.getImm();
342 if ((Modifier && strcmp(Modifier, "lo16") == 0) ||
343 (TF == ARMII::MO_LO16))
345 else if ((Modifier && strcmp(Modifier, "hi16") == 0) ||
346 (TF == ARMII::MO_HI16))
351 case MachineOperand::MO_MachineBasicBlock:
352 O << *MO.getMBB()->getSymbol();
354 case MachineOperand::MO_GlobalAddress: {
355 const GlobalValue *GV = MO.getGlobal();
356 if ((Modifier && strcmp(Modifier, "lo16") == 0) ||
357 (TF & ARMII::MO_LO16))
359 else if ((Modifier && strcmp(Modifier, "hi16") == 0) ||
360 (TF & ARMII::MO_HI16))
362 O << *Mang->getSymbol(GV);
364 printOffset(MO.getOffset(), O);
365 if (TF == ARMII::MO_PLT)
369 case MachineOperand::MO_ExternalSymbol: {
370 O << *GetExternalSymbolSymbol(MO.getSymbolName());
371 if (TF == ARMII::MO_PLT)
375 case MachineOperand::MO_ConstantPoolIndex:
376 O << *GetCPISymbol(MO.getIndex());
378 case MachineOperand::MO_JumpTableIndex:
379 O << *GetJTISymbol(MO.getIndex());
384 //===--------------------------------------------------------------------===//
386 MCSymbol *ARMAsmPrinter::
387 GetARMSetPICJumpTableLabel2(unsigned uid, unsigned uid2,
388 const MachineBasicBlock *MBB) const {
389 SmallString<60> Name;
390 raw_svector_ostream(Name) << MAI->getPrivateGlobalPrefix()
391 << getFunctionNumber() << '_' << uid << '_' << uid2
392 << "_set_" << MBB->getNumber();
393 return OutContext.GetOrCreateSymbol(Name.str());
396 MCSymbol *ARMAsmPrinter::
397 GetARMJTIPICJumpTableLabel2(unsigned uid, unsigned uid2) const {
398 SmallString<60> Name;
399 raw_svector_ostream(Name) << MAI->getPrivateGlobalPrefix() << "JTI"
400 << getFunctionNumber() << '_' << uid << '_' << uid2;
401 return OutContext.GetOrCreateSymbol(Name.str());
405 MCSymbol *ARMAsmPrinter::GetARMSJLJEHLabel(void) const {
406 SmallString<60> Name;
407 raw_svector_ostream(Name) << MAI->getPrivateGlobalPrefix() << "SJLJEH"
408 << getFunctionNumber();
409 return OutContext.GetOrCreateSymbol(Name.str());
412 bool ARMAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
413 unsigned AsmVariant, const char *ExtraCode,
415 // Does this asm operand have a single letter operand modifier?
416 if (ExtraCode && ExtraCode[0]) {
417 if (ExtraCode[1] != 0) return true; // Unknown modifier.
419 switch (ExtraCode[0]) {
420 default: return true; // Unknown modifier.
421 case 'a': // Print as a memory address.
422 if (MI->getOperand(OpNum).isReg()) {
424 << ARMInstPrinter::getRegisterName(MI->getOperand(OpNum).getReg())
429 case 'c': // Don't print "#" before an immediate operand.
430 if (!MI->getOperand(OpNum).isImm())
432 O << MI->getOperand(OpNum).getImm();
434 case 'P': // Print a VFP double precision register.
435 case 'q': // Print a NEON quad precision register.
436 printOperand(MI, OpNum, O);
441 report_fatal_error("llvm does not support 'Q', 'R', and 'H' modifiers!");
446 printOperand(MI, OpNum, O);
450 bool ARMAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI,
451 unsigned OpNum, unsigned AsmVariant,
452 const char *ExtraCode,
454 if (ExtraCode && ExtraCode[0])
455 return true; // Unknown modifier.
457 const MachineOperand &MO = MI->getOperand(OpNum);
458 assert(MO.isReg() && "unexpected inline asm memory operand");
459 O << "[" << ARMInstPrinter::getRegisterName(MO.getReg()) << "]";
463 void ARMAsmPrinter::EmitStartOfAsmFile(Module &M) {
464 if (Subtarget->isTargetDarwin()) {
465 Reloc::Model RelocM = TM.getRelocationModel();
466 if (RelocM == Reloc::PIC_ || RelocM == Reloc::DynamicNoPIC) {
467 // Declare all the text sections up front (before the DWARF sections
468 // emitted by AsmPrinter::doInitialization) so the assembler will keep
469 // them together at the beginning of the object file. This helps
470 // avoid out-of-range branches that are due a fundamental limitation of
471 // the way symbol offsets are encoded with the current Darwin ARM
473 const TargetLoweringObjectFileMachO &TLOFMacho =
474 static_cast<const TargetLoweringObjectFileMachO &>(
475 getObjFileLowering());
476 OutStreamer.SwitchSection(TLOFMacho.getTextSection());
477 OutStreamer.SwitchSection(TLOFMacho.getTextCoalSection());
478 OutStreamer.SwitchSection(TLOFMacho.getConstTextCoalSection());
479 if (RelocM == Reloc::DynamicNoPIC) {
480 const MCSection *sect =
481 OutContext.getMachOSection("__TEXT", "__symbol_stub4",
482 MCSectionMachO::S_SYMBOL_STUBS,
483 12, SectionKind::getText());
484 OutStreamer.SwitchSection(sect);
486 const MCSection *sect =
487 OutContext.getMachOSection("__TEXT", "__picsymbolstub4",
488 MCSectionMachO::S_SYMBOL_STUBS,
489 16, SectionKind::getText());
490 OutStreamer.SwitchSection(sect);
492 const MCSection *StaticInitSect =
493 OutContext.getMachOSection("__TEXT", "__StaticInit",
494 MCSectionMachO::S_REGULAR |
495 MCSectionMachO::S_ATTR_PURE_INSTRUCTIONS,
496 SectionKind::getText());
497 OutStreamer.SwitchSection(StaticInitSect);
501 // Use unified assembler syntax.
502 OutStreamer.EmitAssemblerFlag(MCAF_SyntaxUnified);
504 // Emit ARM Build Attributes
505 if (Subtarget->isTargetELF()) {
512 void ARMAsmPrinter::EmitEndOfAsmFile(Module &M) {
513 if (Subtarget->isTargetDarwin()) {
514 // All darwin targets use mach-o.
515 const TargetLoweringObjectFileMachO &TLOFMacho =
516 static_cast<const TargetLoweringObjectFileMachO &>(getObjFileLowering());
517 MachineModuleInfoMachO &MMIMacho =
518 MMI->getObjFileInfo<MachineModuleInfoMachO>();
520 // Output non-lazy-pointers for external and common global variables.
521 MachineModuleInfoMachO::SymbolListTy Stubs = MMIMacho.GetGVStubList();
523 if (!Stubs.empty()) {
524 // Switch with ".non_lazy_symbol_pointer" directive.
525 OutStreamer.SwitchSection(TLOFMacho.getNonLazySymbolPointerSection());
527 for (unsigned i = 0, e = Stubs.size(); i != e; ++i) {
529 OutStreamer.EmitLabel(Stubs[i].first);
530 // .indirect_symbol _foo
531 MachineModuleInfoImpl::StubValueTy &MCSym = Stubs[i].second;
532 OutStreamer.EmitSymbolAttribute(MCSym.getPointer(),MCSA_IndirectSymbol);
535 // External to current translation unit.
536 OutStreamer.EmitIntValue(0, 4/*size*/, 0/*addrspace*/);
538 // Internal to current translation unit.
540 // When we place the LSDA into the TEXT section, the type info
541 // pointers need to be indirect and pc-rel. We accomplish this by
542 // using NLPs; however, sometimes the types are local to the file.
543 // We need to fill in the value for the NLP in those cases.
544 OutStreamer.EmitValue(MCSymbolRefExpr::Create(MCSym.getPointer(),
546 4/*size*/, 0/*addrspace*/);
550 OutStreamer.AddBlankLine();
553 Stubs = MMIMacho.GetHiddenGVStubList();
554 if (!Stubs.empty()) {
555 OutStreamer.SwitchSection(getObjFileLowering().getDataSection());
557 for (unsigned i = 0, e = Stubs.size(); i != e; ++i) {
559 OutStreamer.EmitLabel(Stubs[i].first);
561 OutStreamer.EmitValue(MCSymbolRefExpr::
562 Create(Stubs[i].second.getPointer(),
564 4/*size*/, 0/*addrspace*/);
568 OutStreamer.AddBlankLine();
571 // Funny Darwin hack: This flag tells the linker that no global symbols
572 // contain code that falls through to other global symbols (e.g. the obvious
573 // implementation of multiple entry points). If this doesn't occur, the
574 // linker can safely perform dead code stripping. Since LLVM never
575 // generates code that does this, it is always safe to set.
576 OutStreamer.EmitAssemblerFlag(MCAF_SubsectionsViaSymbols);
580 //===----------------------------------------------------------------------===//
581 // Helper routines for EmitStartOfAsmFile() and EmitEndOfAsmFile()
583 // The following seem like one-off assembler flags, but they actually need
584 // to appear in the .ARM.attributes section in ELF.
585 // Instead of subclassing the MCELFStreamer, we do the work here.
587 void ARMAsmPrinter::emitAttributes() {
589 emitARMAttributeSection();
591 AttributeEmitter *AttrEmitter;
592 if (OutStreamer.hasRawTextSupport())
593 AttrEmitter = new AsmAttributeEmitter(OutStreamer);
595 MCObjectStreamer &O = static_cast<MCObjectStreamer&>(OutStreamer);
596 AttrEmitter = new ObjectAttributeEmitter(O);
599 AttrEmitter->MaybeSwitchVendor("aeabi");
601 std::string CPUString = Subtarget->getCPUString();
602 if (OutStreamer.hasRawTextSupport()) {
603 if (CPUString != "generic")
604 OutStreamer.EmitRawText(StringRef("\t.cpu ") + CPUString);
606 assert(CPUString == "generic" && "Unsupported .cpu attribute for ELF/.o");
607 // FIXME: Why these defaults?
608 AttrEmitter->EmitAttribute(ARMBuildAttrs::CPU_arch, ARMBuildAttrs::v4T);
609 AttrEmitter->EmitAttribute(ARMBuildAttrs::ARM_ISA_use, 1);
610 AttrEmitter->EmitAttribute(ARMBuildAttrs::THUMB_ISA_use, 1);
613 // FIXME: Emit FPU type
614 if (Subtarget->hasVFP2())
615 AttrEmitter->EmitAttribute(ARMBuildAttrs::VFP_arch, 2);
617 // Signal various FP modes.
619 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_FP_denormal, 1);
620 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_FP_exceptions, 1);
623 if (NoInfsFPMath && NoNaNsFPMath)
624 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_FP_number_model, 1);
626 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_FP_number_model, 3);
628 // 8-bytes alignment stuff.
629 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_align8_needed, 1);
630 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_align8_preserved, 1);
632 // Hard float. Use both S and D registers and conform to AAPCS-VFP.
633 if (Subtarget->isAAPCS_ABI() && FloatABIType == FloatABI::Hard) {
634 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_HardFP_use, 3);
635 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_VFP_args, 1);
637 // FIXME: Should we signal R9 usage?
639 AttrEmitter->EmitAttribute(ARMBuildAttrs::DIV_use, 1);
641 AttrEmitter->Finish();
645 void ARMAsmPrinter::emitARMAttributeSection() {
647 // [ <section-length> "vendor-name"
648 // [ <file-tag> <size> <attribute>*
649 // | <section-tag> <size> <section-number>* 0 <attribute>*
650 // | <symbol-tag> <size> <symbol-number>* 0 <attribute>*
654 if (OutStreamer.hasRawTextSupport())
657 const ARMElfTargetObjectFile &TLOFELF =
658 static_cast<const ARMElfTargetObjectFile &>
659 (getObjFileLowering());
661 OutStreamer.SwitchSection(TLOFELF.getAttributesSection());
664 OutStreamer.EmitIntValue(0x41, 1);
667 //===----------------------------------------------------------------------===//
669 static MCSymbol *getPICLabel(const char *Prefix, unsigned FunctionNumber,
670 unsigned LabelId, MCContext &Ctx) {
672 MCSymbol *Label = Ctx.GetOrCreateSymbol(Twine(Prefix)
673 + "PC" + Twine(FunctionNumber) + "_" + Twine(LabelId));
677 void ARMAsmPrinter::EmitJumpTable(const MachineInstr *MI) {
678 unsigned Opcode = MI->getOpcode();
680 if (Opcode == ARM::BR_JTadd)
682 else if (Opcode == ARM::BR_JTm)
685 const MachineOperand &MO1 = MI->getOperand(OpNum);
686 const MachineOperand &MO2 = MI->getOperand(OpNum+1); // Unique Id
687 unsigned JTI = MO1.getIndex();
689 // Emit a label for the jump table.
690 MCSymbol *JTISymbol = GetARMJTIPICJumpTableLabel2(JTI, MO2.getImm());
691 OutStreamer.EmitLabel(JTISymbol);
693 // Emit each entry of the table.
694 const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
695 const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
696 const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
698 for (unsigned i = 0, e = JTBBs.size(); i != e; ++i) {
699 MachineBasicBlock *MBB = JTBBs[i];
700 // Construct an MCExpr for the entry. We want a value of the form:
701 // (BasicBlockAddr - TableBeginAddr)
703 // For example, a table with entries jumping to basic blocks BB0 and BB1
706 // .word (LBB0 - LJTI_0_0)
707 // .word (LBB1 - LJTI_0_0)
708 const MCExpr *Expr = MCSymbolRefExpr::Create(MBB->getSymbol(), OutContext);
710 if (TM.getRelocationModel() == Reloc::PIC_)
711 Expr = MCBinaryExpr::CreateSub(Expr, MCSymbolRefExpr::Create(JTISymbol,
714 OutStreamer.EmitValue(Expr, 4);
718 void ARMAsmPrinter::EmitJump2Table(const MachineInstr *MI) {
719 unsigned Opcode = MI->getOpcode();
720 int OpNum = (Opcode == ARM::t2BR_JT) ? 2 : 1;
721 const MachineOperand &MO1 = MI->getOperand(OpNum);
722 const MachineOperand &MO2 = MI->getOperand(OpNum+1); // Unique Id
723 unsigned JTI = MO1.getIndex();
725 // Emit a label for the jump table.
726 MCSymbol *JTISymbol = GetARMJTIPICJumpTableLabel2(JTI, MO2.getImm());
727 OutStreamer.EmitLabel(JTISymbol);
729 // Emit each entry of the table.
730 const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
731 const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
732 const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
733 unsigned OffsetWidth = 4;
734 if (MI->getOpcode() == ARM::t2TBB)
736 else if (MI->getOpcode() == ARM::t2TBH)
739 for (unsigned i = 0, e = JTBBs.size(); i != e; ++i) {
740 MachineBasicBlock *MBB = JTBBs[i];
741 const MCExpr *MBBSymbolExpr = MCSymbolRefExpr::Create(MBB->getSymbol(),
743 // If this isn't a TBB or TBH, the entries are direct branch instructions.
744 if (OffsetWidth == 4) {
746 BrInst.setOpcode(ARM::t2B);
747 BrInst.addOperand(MCOperand::CreateExpr(MBBSymbolExpr));
748 OutStreamer.EmitInstruction(BrInst);
751 // Otherwise it's an offset from the dispatch instruction. Construct an
752 // MCExpr for the entry. We want a value of the form:
753 // (BasicBlockAddr - TableBeginAddr) / 2
755 // For example, a TBB table with entries jumping to basic blocks BB0 and BB1
758 // .byte (LBB0 - LJTI_0_0) / 2
759 // .byte (LBB1 - LJTI_0_0) / 2
761 MCBinaryExpr::CreateSub(MBBSymbolExpr,
762 MCSymbolRefExpr::Create(JTISymbol, OutContext),
764 Expr = MCBinaryExpr::CreateDiv(Expr, MCConstantExpr::Create(2, OutContext),
766 OutStreamer.EmitValue(Expr, OffsetWidth);
769 // Make sure the instruction that follows TBB is 2-byte aligned.
770 // FIXME: Constant island pass should insert an "ALIGN" instruction instead.
771 if (MI->getOpcode() == ARM::t2TBB)
775 void ARMAsmPrinter::PrintDebugValueComment(const MachineInstr *MI,
777 unsigned NOps = MI->getNumOperands();
779 OS << '\t' << MAI->getCommentString() << "DEBUG_VALUE: ";
780 // cast away const; DIetc do not take const operands for some reason.
781 DIVariable V(const_cast<MDNode *>(MI->getOperand(NOps-1).getMetadata()));
784 // Frame address. Currently handles register +- offset only.
785 assert(MI->getOperand(0).isReg() && MI->getOperand(1).isImm());
786 OS << '['; printOperand(MI, 0, OS); OS << '+'; printOperand(MI, 1, OS);
789 printOperand(MI, NOps-2, OS);
792 void ARMAsmPrinter::EmitInstruction(const MachineInstr *MI) {
793 ARMMCInstLower MCInstLowering(OutContext, *Mang, *this);
794 switch (MI->getOpcode()) {
795 case ARM::t2MOVi32imm:
796 assert(0 && "Should be lowered by thumb2it pass");
798 case ARM::DBG_VALUE: {
799 if (isVerbose() && OutStreamer.hasRawTextSupport()) {
800 SmallString<128> TmpStr;
801 raw_svector_ostream OS(TmpStr);
802 PrintDebugValueComment(MI, OS);
803 OutStreamer.EmitRawText(StringRef(OS.str()));
808 // This is a pseudo op for a label + instruction sequence, which looks like:
811 // This adds the address of LPC0 to r0.
814 OutStreamer.EmitLabel(getPICLabel(MAI->getPrivateGlobalPrefix(),
815 getFunctionNumber(), MI->getOperand(2).getImm(),
818 // Form and emit the add.
820 AddInst.setOpcode(ARM::tADDhirr);
821 AddInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
822 AddInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
823 AddInst.addOperand(MCOperand::CreateReg(ARM::PC));
824 // Add predicate operands.
825 AddInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
826 AddInst.addOperand(MCOperand::CreateReg(0));
827 OutStreamer.EmitInstruction(AddInst);
831 // This is a pseudo op for a label + instruction sequence, which looks like:
834 // This adds the address of LPC0 to r0.
837 OutStreamer.EmitLabel(getPICLabel(MAI->getPrivateGlobalPrefix(),
838 getFunctionNumber(), MI->getOperand(2).getImm(),
841 // Form and emit the add.
843 AddInst.setOpcode(ARM::ADDrr);
844 AddInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
845 AddInst.addOperand(MCOperand::CreateReg(ARM::PC));
846 AddInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg()));
847 // Add predicate operands.
848 AddInst.addOperand(MCOperand::CreateImm(MI->getOperand(3).getImm()));
849 AddInst.addOperand(MCOperand::CreateReg(MI->getOperand(4).getReg()));
850 // Add 's' bit operand (always reg0 for this)
851 AddInst.addOperand(MCOperand::CreateReg(0));
852 OutStreamer.EmitInstruction(AddInst);
862 case ARM::PICLDRSH: {
863 // This is a pseudo op for a label + instruction sequence, which looks like:
866 // The LCP0 label is referenced by a constant pool entry in order to get
867 // a PC-relative address at the ldr instruction.
870 OutStreamer.EmitLabel(getPICLabel(MAI->getPrivateGlobalPrefix(),
871 getFunctionNumber(), MI->getOperand(2).getImm(),
874 // Form and emit the load
876 switch (MI->getOpcode()) {
878 llvm_unreachable("Unexpected opcode!");
879 case ARM::PICSTR: Opcode = ARM::STR; break;
880 case ARM::PICSTRB: Opcode = ARM::STRB; break;
881 case ARM::PICSTRH: Opcode = ARM::STRH; break;
882 case ARM::PICLDR: Opcode = ARM::LDR; break;
883 case ARM::PICLDRB: Opcode = ARM::LDRB; break;
884 case ARM::PICLDRH: Opcode = ARM::LDRH; break;
885 case ARM::PICLDRSB: Opcode = ARM::LDRSB; break;
886 case ARM::PICLDRSH: Opcode = ARM::LDRSH; break;
889 LdStInst.setOpcode(Opcode);
890 LdStInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
891 LdStInst.addOperand(MCOperand::CreateReg(ARM::PC));
892 LdStInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg()));
893 LdStInst.addOperand(MCOperand::CreateImm(0));
894 // Add predicate operands.
895 LdStInst.addOperand(MCOperand::CreateImm(MI->getOperand(3).getImm()));
896 LdStInst.addOperand(MCOperand::CreateReg(MI->getOperand(4).getReg()));
897 OutStreamer.EmitInstruction(LdStInst);
901 case ARM::CONSTPOOL_ENTRY: {
902 /// CONSTPOOL_ENTRY - This instruction represents a floating constant pool
903 /// in the function. The first operand is the ID# for this instruction, the
904 /// second is the index into the MachineConstantPool that this is, the third
905 /// is the size in bytes of this constant pool entry.
906 unsigned LabelId = (unsigned)MI->getOperand(0).getImm();
907 unsigned CPIdx = (unsigned)MI->getOperand(1).getIndex();
910 OutStreamer.EmitLabel(GetCPISymbol(LabelId));
912 const MachineConstantPoolEntry &MCPE = MCP->getConstants()[CPIdx];
913 if (MCPE.isMachineConstantPoolEntry())
914 EmitMachineConstantPoolValue(MCPE.Val.MachineCPVal);
916 EmitGlobalConstant(MCPE.Val.ConstVal);
920 case ARM::MOVi2pieces: {
921 // FIXME: We'd like to remove the asm string in the .td file, but the
922 // This is a hack that lowers as a two instruction sequence.
923 unsigned DstReg = MI->getOperand(0).getReg();
924 unsigned ImmVal = (unsigned)MI->getOperand(1).getImm();
926 unsigned SOImmValV1 = ARM_AM::getSOImmTwoPartFirst(ImmVal);
927 unsigned SOImmValV2 = ARM_AM::getSOImmTwoPartSecond(ImmVal);
931 TmpInst.setOpcode(ARM::MOVi);
932 TmpInst.addOperand(MCOperand::CreateReg(DstReg));
933 TmpInst.addOperand(MCOperand::CreateImm(SOImmValV1));
936 TmpInst.addOperand(MCOperand::CreateImm(MI->getOperand(2).getImm()));
937 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(3).getReg()));
939 TmpInst.addOperand(MCOperand::CreateReg(0)); // cc_out
940 OutStreamer.EmitInstruction(TmpInst);
945 TmpInst.setOpcode(ARM::ORRri);
946 TmpInst.addOperand(MCOperand::CreateReg(DstReg)); // dstreg
947 TmpInst.addOperand(MCOperand::CreateReg(DstReg)); // inreg
948 TmpInst.addOperand(MCOperand::CreateImm(SOImmValV2)); // so_imm
950 TmpInst.addOperand(MCOperand::CreateImm(MI->getOperand(2).getImm()));
951 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(3).getReg()));
953 TmpInst.addOperand(MCOperand::CreateReg(0)); // cc_out
954 OutStreamer.EmitInstruction(TmpInst);
958 case ARM::MOVi32imm: {
959 // FIXME: We'd like to remove the asm string in the .td file, but the
960 // This is a hack that lowers as a two instruction sequence.
961 unsigned DstReg = MI->getOperand(0).getReg();
962 const MachineOperand &MO = MI->getOperand(1);
965 unsigned ImmVal = (unsigned)MI->getOperand(1).getImm();
966 V1 = MCOperand::CreateImm(ImmVal & 65535);
967 V2 = MCOperand::CreateImm(ImmVal >> 16);
968 } else if (MO.isGlobal()) {
969 MCSymbol *Symbol = MCInstLowering.GetGlobalAddressSymbol(MO.getGlobal());
970 const MCSymbolRefExpr *SymRef1 =
971 MCSymbolRefExpr::Create(Symbol,
972 MCSymbolRefExpr::VK_ARM_LO16, OutContext);
973 const MCSymbolRefExpr *SymRef2 =
974 MCSymbolRefExpr::Create(Symbol,
975 MCSymbolRefExpr::VK_ARM_HI16, OutContext);
976 V1 = MCOperand::CreateExpr(SymRef1);
977 V2 = MCOperand::CreateExpr(SymRef2);
979 // FIXME: External symbol?
981 llvm_unreachable("cannot handle this operand");
986 TmpInst.setOpcode(ARM::MOVi16);
987 TmpInst.addOperand(MCOperand::CreateReg(DstReg)); // dstreg
988 TmpInst.addOperand(V1); // lower16(imm)
991 TmpInst.addOperand(MCOperand::CreateImm(MI->getOperand(2).getImm()));
992 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(3).getReg()));
994 OutStreamer.EmitInstruction(TmpInst);
999 TmpInst.setOpcode(ARM::MOVTi16);
1000 TmpInst.addOperand(MCOperand::CreateReg(DstReg)); // dstreg
1001 TmpInst.addOperand(MCOperand::CreateReg(DstReg)); // srcreg
1002 TmpInst.addOperand(V2); // upper16(imm)
1005 TmpInst.addOperand(MCOperand::CreateImm(MI->getOperand(2).getImm()));
1006 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(3).getReg()));
1008 OutStreamer.EmitInstruction(TmpInst);
1015 case ARM::t2BR_JT: {
1016 // Lower and emit the instruction itself, then the jump table following it.
1018 MCInstLowering.Lower(MI, TmpInst);
1019 OutStreamer.EmitInstruction(TmpInst);
1026 case ARM::BR_JTadd: {
1027 // Lower and emit the instruction itself, then the jump table following it.
1029 MCInstLowering.Lower(MI, TmpInst);
1030 OutStreamer.EmitInstruction(TmpInst);
1035 // Non-Darwin binutils don't yet support the "trap" mnemonic.
1036 // FIXME: Remove this special case when they do.
1037 if (!Subtarget->isTargetDarwin()) {
1038 //.long 0xe7ffdefe @ trap
1039 uint32_t Val = 0xe7ffdefeUL;
1040 OutStreamer.AddComment("trap");
1041 OutStreamer.EmitIntValue(Val, 4);
1047 // Non-Darwin binutils don't yet support the "trap" mnemonic.
1048 // FIXME: Remove this special case when they do.
1049 if (!Subtarget->isTargetDarwin()) {
1050 //.short 57086 @ trap
1051 uint16_t Val = 0xdefe;
1052 OutStreamer.AddComment("trap");
1053 OutStreamer.EmitIntValue(Val, 2);
1058 case ARM::t2Int_eh_sjlj_setjmp:
1059 case ARM::t2Int_eh_sjlj_setjmp_nofp:
1060 case ARM::tInt_eh_sjlj_setjmp: {
1061 // Two incoming args: GPR:$src, GPR:$val
1064 // str $val, [$src, #4]
1069 unsigned SrcReg = MI->getOperand(0).getReg();
1070 unsigned ValReg = MI->getOperand(1).getReg();
1071 MCSymbol *Label = GetARMSJLJEHLabel();
1074 TmpInst.setOpcode(ARM::tMOVgpr2tgpr);
1075 TmpInst.addOperand(MCOperand::CreateReg(ValReg));
1076 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1078 TmpInst.addOperand(MCOperand::CreateReg(ARM::CPSR));
1079 OutStreamer.AddComment("eh_setjmp begin");
1080 OutStreamer.EmitInstruction(TmpInst);
1084 TmpInst.setOpcode(ARM::tADDi3);
1085 TmpInst.addOperand(MCOperand::CreateReg(ValReg));
1087 TmpInst.addOperand(MCOperand::CreateReg(ARM::CPSR));
1088 TmpInst.addOperand(MCOperand::CreateReg(ValReg));
1089 TmpInst.addOperand(MCOperand::CreateImm(7));
1091 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1092 TmpInst.addOperand(MCOperand::CreateReg(0));
1093 OutStreamer.EmitInstruction(TmpInst);
1097 TmpInst.setOpcode(ARM::tSTR);
1098 TmpInst.addOperand(MCOperand::CreateReg(ValReg));
1099 TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
1100 // The offset immediate is #4. The operand value is scaled by 4 for the
1101 // tSTR instruction.
1102 TmpInst.addOperand(MCOperand::CreateImm(1));
1103 TmpInst.addOperand(MCOperand::CreateReg(0));
1105 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1106 TmpInst.addOperand(MCOperand::CreateReg(0));
1107 OutStreamer.EmitInstruction(TmpInst);
1111 TmpInst.setOpcode(ARM::tMOVi8);
1112 TmpInst.addOperand(MCOperand::CreateReg(ARM::R0));
1113 TmpInst.addOperand(MCOperand::CreateReg(ARM::CPSR));
1114 TmpInst.addOperand(MCOperand::CreateImm(0));
1116 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1117 TmpInst.addOperand(MCOperand::CreateReg(0));
1118 OutStreamer.EmitInstruction(TmpInst);
1121 const MCExpr *SymbolExpr = MCSymbolRefExpr::Create(Label, OutContext);
1123 TmpInst.setOpcode(ARM::tB);
1124 TmpInst.addOperand(MCOperand::CreateExpr(SymbolExpr));
1125 OutStreamer.EmitInstruction(TmpInst);
1129 TmpInst.setOpcode(ARM::tMOVi8);
1130 TmpInst.addOperand(MCOperand::CreateReg(ARM::R0));
1131 TmpInst.addOperand(MCOperand::CreateReg(ARM::CPSR));
1132 TmpInst.addOperand(MCOperand::CreateImm(1));
1134 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1135 TmpInst.addOperand(MCOperand::CreateReg(0));
1136 OutStreamer.AddComment("eh_setjmp end");
1137 OutStreamer.EmitInstruction(TmpInst);
1139 OutStreamer.EmitLabel(Label);
1143 case ARM::Int_eh_sjlj_setjmp_nofp:
1144 case ARM::Int_eh_sjlj_setjmp: {
1145 // Two incoming args: GPR:$src, GPR:$val
1147 // str $val, [$src, #+4]
1151 unsigned SrcReg = MI->getOperand(0).getReg();
1152 unsigned ValReg = MI->getOperand(1).getReg();
1156 TmpInst.setOpcode(ARM::ADDri);
1157 TmpInst.addOperand(MCOperand::CreateReg(ValReg));
1158 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1159 TmpInst.addOperand(MCOperand::CreateImm(8));
1161 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1162 TmpInst.addOperand(MCOperand::CreateReg(0));
1163 // 's' bit operand (always reg0 for this).
1164 TmpInst.addOperand(MCOperand::CreateReg(0));
1165 OutStreamer.AddComment("eh_setjmp begin");
1166 OutStreamer.EmitInstruction(TmpInst);
1170 TmpInst.setOpcode(ARM::STR);
1171 TmpInst.addOperand(MCOperand::CreateReg(ValReg));
1172 TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
1173 TmpInst.addOperand(MCOperand::CreateReg(0));
1174 TmpInst.addOperand(MCOperand::CreateImm(4));
1176 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1177 TmpInst.addOperand(MCOperand::CreateReg(0));
1178 OutStreamer.EmitInstruction(TmpInst);
1182 TmpInst.setOpcode(ARM::MOVi);
1183 TmpInst.addOperand(MCOperand::CreateReg(ARM::R0));
1184 TmpInst.addOperand(MCOperand::CreateImm(0));
1186 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1187 TmpInst.addOperand(MCOperand::CreateReg(0));
1188 // 's' bit operand (always reg0 for this).
1189 TmpInst.addOperand(MCOperand::CreateReg(0));
1190 OutStreamer.EmitInstruction(TmpInst);
1194 TmpInst.setOpcode(ARM::ADDri);
1195 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1196 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1197 TmpInst.addOperand(MCOperand::CreateImm(0));
1199 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1200 TmpInst.addOperand(MCOperand::CreateReg(0));
1201 // 's' bit operand (always reg0 for this).
1202 TmpInst.addOperand(MCOperand::CreateReg(0));
1203 OutStreamer.EmitInstruction(TmpInst);
1207 TmpInst.setOpcode(ARM::MOVi);
1208 TmpInst.addOperand(MCOperand::CreateReg(ARM::R0));
1209 TmpInst.addOperand(MCOperand::CreateImm(1));
1211 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1212 TmpInst.addOperand(MCOperand::CreateReg(0));
1213 // 's' bit operand (always reg0 for this).
1214 TmpInst.addOperand(MCOperand::CreateReg(0));
1215 OutStreamer.AddComment("eh_setjmp end");
1216 OutStreamer.EmitInstruction(TmpInst);
1220 case ARM::Int_eh_sjlj_longjmp: {
1221 // ldr sp, [$src, #8]
1222 // ldr $scratch, [$src, #4]
1225 unsigned SrcReg = MI->getOperand(0).getReg();
1226 unsigned ScratchReg = MI->getOperand(1).getReg();
1229 TmpInst.setOpcode(ARM::LDR);
1230 TmpInst.addOperand(MCOperand::CreateReg(ARM::SP));
1231 TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
1232 TmpInst.addOperand(MCOperand::CreateReg(0));
1233 TmpInst.addOperand(MCOperand::CreateImm(8));
1235 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1236 TmpInst.addOperand(MCOperand::CreateReg(0));
1237 OutStreamer.EmitInstruction(TmpInst);
1241 TmpInst.setOpcode(ARM::LDR);
1242 TmpInst.addOperand(MCOperand::CreateReg(ScratchReg));
1243 TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
1244 TmpInst.addOperand(MCOperand::CreateReg(0));
1245 TmpInst.addOperand(MCOperand::CreateImm(4));
1247 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1248 TmpInst.addOperand(MCOperand::CreateReg(0));
1249 OutStreamer.EmitInstruction(TmpInst);
1253 TmpInst.setOpcode(ARM::LDR);
1254 TmpInst.addOperand(MCOperand::CreateReg(ARM::R7));
1255 TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
1256 TmpInst.addOperand(MCOperand::CreateReg(0));
1257 TmpInst.addOperand(MCOperand::CreateImm(0));
1259 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1260 TmpInst.addOperand(MCOperand::CreateReg(0));
1261 OutStreamer.EmitInstruction(TmpInst);
1265 TmpInst.setOpcode(ARM::BRIND);
1266 TmpInst.addOperand(MCOperand::CreateReg(ScratchReg));
1268 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1269 TmpInst.addOperand(MCOperand::CreateReg(0));
1270 OutStreamer.EmitInstruction(TmpInst);
1274 case ARM::tInt_eh_sjlj_longjmp: {
1275 // ldr $scratch, [$src, #8]
1277 // ldr $scratch, [$src, #4]
1280 unsigned SrcReg = MI->getOperand(0).getReg();
1281 unsigned ScratchReg = MI->getOperand(1).getReg();
1284 TmpInst.setOpcode(ARM::tLDR);
1285 TmpInst.addOperand(MCOperand::CreateReg(ScratchReg));
1286 TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
1287 // The offset immediate is #8. The operand value is scaled by 4 for the
1288 // tSTR instruction.
1289 TmpInst.addOperand(MCOperand::CreateImm(2));
1290 TmpInst.addOperand(MCOperand::CreateReg(0));
1292 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1293 TmpInst.addOperand(MCOperand::CreateReg(0));
1294 OutStreamer.EmitInstruction(TmpInst);
1298 TmpInst.setOpcode(ARM::tMOVtgpr2gpr);
1299 TmpInst.addOperand(MCOperand::CreateReg(ARM::SP));
1300 TmpInst.addOperand(MCOperand::CreateReg(ScratchReg));
1302 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1303 TmpInst.addOperand(MCOperand::CreateReg(0));
1304 OutStreamer.EmitInstruction(TmpInst);
1308 TmpInst.setOpcode(ARM::tLDR);
1309 TmpInst.addOperand(MCOperand::CreateReg(ScratchReg));
1310 TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
1311 TmpInst.addOperand(MCOperand::CreateImm(1));
1312 TmpInst.addOperand(MCOperand::CreateReg(0));
1314 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1315 TmpInst.addOperand(MCOperand::CreateReg(0));
1316 OutStreamer.EmitInstruction(TmpInst);
1320 TmpInst.setOpcode(ARM::tLDR);
1321 TmpInst.addOperand(MCOperand::CreateReg(ARM::R7));
1322 TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
1323 TmpInst.addOperand(MCOperand::CreateImm(0));
1324 TmpInst.addOperand(MCOperand::CreateReg(0));
1326 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1327 TmpInst.addOperand(MCOperand::CreateReg(0));
1328 OutStreamer.EmitInstruction(TmpInst);
1332 TmpInst.setOpcode(ARM::tBX_RET_vararg);
1333 TmpInst.addOperand(MCOperand::CreateReg(ScratchReg));
1335 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1336 TmpInst.addOperand(MCOperand::CreateReg(0));
1337 OutStreamer.EmitInstruction(TmpInst);
1344 MCInstLowering.Lower(MI, TmpInst);
1345 OutStreamer.EmitInstruction(TmpInst);
1348 //===----------------------------------------------------------------------===//
1349 // Target Registry Stuff
1350 //===----------------------------------------------------------------------===//
1352 static MCInstPrinter *createARMMCInstPrinter(const Target &T,
1353 unsigned SyntaxVariant,
1354 const MCAsmInfo &MAI) {
1355 if (SyntaxVariant == 0)
1356 return new ARMInstPrinter(MAI);
1360 // Force static initialization.
1361 extern "C" void LLVMInitializeARMAsmPrinter() {
1362 RegisterAsmPrinter<ARMAsmPrinter> X(TheARMTarget);
1363 RegisterAsmPrinter<ARMAsmPrinter> Y(TheThumbTarget);
1365 TargetRegistry::RegisterMCInstPrinter(TheARMTarget, createARMMCInstPrinter);
1366 TargetRegistry::RegisterMCInstPrinter(TheThumbTarget, createARMMCInstPrinter);