1 //===-- ARMAsmPrinter.cpp - Print machine code to an ARM .s file ----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains a printer that converts from our internal representation
11 // of machine-dependent LLVM code to GAS-format ARM assembly language.
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "asm-printer"
17 #include "ARMBuildAttrs.h"
18 #include "ARMAddressingModes.h"
19 #include "ARMConstantPoolValue.h"
20 #include "InstPrinter/ARMInstPrinter.h"
21 #include "ARMMachineFunctionInfo.h"
22 #include "ARMMCInstLower.h"
23 #include "ARMTargetMachine.h"
24 #include "ARMTargetObjectFile.h"
25 #include "llvm/Analysis/DebugInfo.h"
26 #include "llvm/Constants.h"
27 #include "llvm/Module.h"
28 #include "llvm/Type.h"
29 #include "llvm/Assembly/Writer.h"
30 #include "llvm/CodeGen/AsmPrinter.h"
31 #include "llvm/CodeGen/MachineModuleInfoImpls.h"
32 #include "llvm/CodeGen/MachineFunctionPass.h"
33 #include "llvm/CodeGen/MachineJumpTableInfo.h"
34 #include "llvm/MC/MCAsmInfo.h"
35 #include "llvm/MC/MCAssembler.h"
36 #include "llvm/MC/MCContext.h"
37 #include "llvm/MC/MCExpr.h"
38 #include "llvm/MC/MCInst.h"
39 #include "llvm/MC/MCSectionMachO.h"
40 #include "llvm/MC/MCObjectStreamer.h"
41 #include "llvm/MC/MCStreamer.h"
42 #include "llvm/MC/MCSymbol.h"
43 #include "llvm/Target/Mangler.h"
44 #include "llvm/Target/TargetData.h"
45 #include "llvm/Target/TargetMachine.h"
46 #include "llvm/Target/TargetOptions.h"
47 #include "llvm/Target/TargetRegistry.h"
48 #include "llvm/ADT/SmallPtrSet.h"
49 #include "llvm/ADT/SmallString.h"
50 #include "llvm/ADT/StringExtras.h"
51 #include "llvm/Support/CommandLine.h"
52 #include "llvm/Support/Debug.h"
53 #include "llvm/Support/ErrorHandling.h"
54 #include "llvm/Support/raw_ostream.h"
69 // Per section and per symbol attributes are not supported.
70 // To implement them we would need the ability to delay this emission
71 // until the assembly file is fully parsed/generated as only then do we
72 // know the symbol and section numbers.
73 class AttributeEmitter {
75 virtual void MaybeSwitchVendor(StringRef Vendor) = 0;
76 virtual void EmitAttribute(unsigned Attribute, unsigned Value) = 0;
77 virtual void Finish() = 0;
78 virtual ~AttributeEmitter() {}
81 class AsmAttributeEmitter : public AttributeEmitter {
85 AsmAttributeEmitter(MCStreamer &Streamer_) : Streamer(Streamer_) {}
86 void MaybeSwitchVendor(StringRef Vendor) { }
88 void EmitAttribute(unsigned Attribute, unsigned Value) {
89 Streamer.EmitRawText("\t.eabi_attribute " +
90 Twine(Attribute) + ", " + Twine(Value));
96 class ObjectAttributeEmitter : public AttributeEmitter {
97 MCObjectStreamer &Streamer;
98 StringRef CurrentVendor;
99 SmallString<64> Contents;
102 ObjectAttributeEmitter(MCObjectStreamer &Streamer_) :
103 Streamer(Streamer_), CurrentVendor("") { }
105 void MaybeSwitchVendor(StringRef Vendor) {
106 assert(!Vendor.empty() && "Vendor cannot be empty.");
108 if (CurrentVendor.empty())
109 CurrentVendor = Vendor;
110 else if (CurrentVendor == Vendor)
115 CurrentVendor = Vendor;
117 assert(Contents.size() == 0);
120 void EmitAttribute(unsigned Attribute, unsigned Value) {
121 // FIXME: should be ULEB
122 Contents += Attribute;
127 const size_t ContentsSize = Contents.size();
129 // Vendor size + Vendor name + '\0'
130 const size_t VendorHeaderSize = 4 + CurrentVendor.size() + 1;
133 const size_t TagHeaderSize = 1 + 4;
135 Streamer.EmitIntValue(VendorHeaderSize + TagHeaderSize + ContentsSize, 4);
136 Streamer.EmitBytes(CurrentVendor, 0);
137 Streamer.EmitIntValue(0, 1); // '\0'
139 Streamer.EmitIntValue(ARMBuildAttrs::File, 1);
140 Streamer.EmitIntValue(TagHeaderSize + ContentsSize, 4);
142 Streamer.EmitBytes(Contents, 0);
148 class ARMAsmPrinter : public AsmPrinter {
150 /// Subtarget - Keep a pointer to the ARMSubtarget around so that we can
151 /// make the right decision when printing asm code for different targets.
152 const ARMSubtarget *Subtarget;
154 /// AFI - Keep a pointer to ARMFunctionInfo for the current
156 ARMFunctionInfo *AFI;
158 /// MCP - Keep a pointer to constantpool entries of the current
160 const MachineConstantPool *MCP;
163 explicit ARMAsmPrinter(TargetMachine &TM, MCStreamer &Streamer)
164 : AsmPrinter(TM, Streamer), AFI(NULL), MCP(NULL) {
165 Subtarget = &TM.getSubtarget<ARMSubtarget>();
168 virtual const char *getPassName() const {
169 return "ARM Assembly Printer";
172 void printOperand(const MachineInstr *MI, int OpNum, raw_ostream &O,
173 const char *Modifier = 0);
175 virtual bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
176 unsigned AsmVariant, const char *ExtraCode,
178 virtual bool PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNum,
180 const char *ExtraCode, raw_ostream &O);
182 void EmitJumpTable(const MachineInstr *MI);
183 void EmitJump2Table(const MachineInstr *MI);
184 virtual void EmitInstruction(const MachineInstr *MI);
185 bool runOnMachineFunction(MachineFunction &F);
187 virtual void EmitConstantPool() {} // we emit constant pools customly!
188 virtual void EmitFunctionEntryLabel();
189 void EmitStartOfAsmFile(Module &M);
190 void EmitEndOfAsmFile(Module &M);
193 // Helpers for EmitStartOfAsmFile() and EmitEndOfAsmFile()
194 void emitAttributes();
196 // Helper for ELF .o only
197 void emitARMAttributeSection();
200 void PrintDebugValueComment(const MachineInstr *MI, raw_ostream &OS);
202 MachineLocation getDebugValueLocation(const MachineInstr *MI) const {
203 MachineLocation Location;
204 assert (MI->getNumOperands() == 4 && "Invalid no. of machine operands!");
205 // Frame address. Currently handles register +- offset only.
206 if (MI->getOperand(0).isReg() && MI->getOperand(1).isImm())
207 Location.set(MI->getOperand(0).getReg(), MI->getOperand(1).getImm());
209 DEBUG(dbgs() << "DBG_VALUE instruction ignored! " << *MI << "\n");
214 virtual unsigned getISAEncoding() {
215 // ARM/Darwin adds ISA to the DWARF info for each function.
216 if (!Subtarget->isTargetDarwin())
218 return Subtarget->isThumb() ?
219 llvm::ARM::DW_ISA_ARM_thumb : llvm::ARM::DW_ISA_ARM_arm;
222 MCSymbol *GetARMSetPICJumpTableLabel2(unsigned uid, unsigned uid2,
223 const MachineBasicBlock *MBB) const;
224 MCSymbol *GetARMJTIPICJumpTableLabel2(unsigned uid, unsigned uid2) const;
226 MCSymbol *GetARMSJLJEHLabel(void) const;
228 /// EmitMachineConstantPoolValue - Print a machine constantpool value to
230 virtual void EmitMachineConstantPoolValue(MachineConstantPoolValue *MCPV);
232 } // end of anonymous namespace
234 void ARMAsmPrinter::EmitFunctionEntryLabel() {
235 if (AFI->isThumbFunction()) {
236 OutStreamer.EmitAssemblerFlag(MCAF_Code16);
237 OutStreamer.EmitThumbFunc(Subtarget->isTargetDarwin()? CurrentFnSym : 0);
240 OutStreamer.EmitLabel(CurrentFnSym);
243 /// runOnMachineFunction - This uses the EmitInstruction()
244 /// method to print assembly for each instruction.
246 bool ARMAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
247 AFI = MF.getInfo<ARMFunctionInfo>();
248 MCP = MF.getConstantPool();
250 return AsmPrinter::runOnMachineFunction(MF);
253 void ARMAsmPrinter::printOperand(const MachineInstr *MI, int OpNum,
254 raw_ostream &O, const char *Modifier) {
255 const MachineOperand &MO = MI->getOperand(OpNum);
256 unsigned TF = MO.getTargetFlags();
258 switch (MO.getType()) {
260 assert(0 && "<unknown operand type>");
261 case MachineOperand::MO_Register: {
262 unsigned Reg = MO.getReg();
263 assert(TargetRegisterInfo::isPhysicalRegister(Reg));
264 assert(!MO.getSubReg() && "Subregs should be eliminated!");
265 O << ARMInstPrinter::getRegisterName(Reg);
268 case MachineOperand::MO_Immediate: {
269 int64_t Imm = MO.getImm();
271 if ((Modifier && strcmp(Modifier, "lo16") == 0) ||
272 (TF == ARMII::MO_LO16))
274 else if ((Modifier && strcmp(Modifier, "hi16") == 0) ||
275 (TF == ARMII::MO_HI16))
280 case MachineOperand::MO_MachineBasicBlock:
281 O << *MO.getMBB()->getSymbol();
283 case MachineOperand::MO_GlobalAddress: {
284 const GlobalValue *GV = MO.getGlobal();
285 if ((Modifier && strcmp(Modifier, "lo16") == 0) ||
286 (TF & ARMII::MO_LO16))
288 else if ((Modifier && strcmp(Modifier, "hi16") == 0) ||
289 (TF & ARMII::MO_HI16))
291 O << *Mang->getSymbol(GV);
293 printOffset(MO.getOffset(), O);
294 if (TF == ARMII::MO_PLT)
298 case MachineOperand::MO_ExternalSymbol: {
299 O << *GetExternalSymbolSymbol(MO.getSymbolName());
300 if (TF == ARMII::MO_PLT)
304 case MachineOperand::MO_ConstantPoolIndex:
305 O << *GetCPISymbol(MO.getIndex());
307 case MachineOperand::MO_JumpTableIndex:
308 O << *GetJTISymbol(MO.getIndex());
313 //===--------------------------------------------------------------------===//
315 MCSymbol *ARMAsmPrinter::
316 GetARMSetPICJumpTableLabel2(unsigned uid, unsigned uid2,
317 const MachineBasicBlock *MBB) const {
318 SmallString<60> Name;
319 raw_svector_ostream(Name) << MAI->getPrivateGlobalPrefix()
320 << getFunctionNumber() << '_' << uid << '_' << uid2
321 << "_set_" << MBB->getNumber();
322 return OutContext.GetOrCreateSymbol(Name.str());
325 MCSymbol *ARMAsmPrinter::
326 GetARMJTIPICJumpTableLabel2(unsigned uid, unsigned uid2) const {
327 SmallString<60> Name;
328 raw_svector_ostream(Name) << MAI->getPrivateGlobalPrefix() << "JTI"
329 << getFunctionNumber() << '_' << uid << '_' << uid2;
330 return OutContext.GetOrCreateSymbol(Name.str());
334 MCSymbol *ARMAsmPrinter::GetARMSJLJEHLabel(void) const {
335 SmallString<60> Name;
336 raw_svector_ostream(Name) << MAI->getPrivateGlobalPrefix() << "SJLJEH"
337 << getFunctionNumber();
338 return OutContext.GetOrCreateSymbol(Name.str());
341 bool ARMAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
342 unsigned AsmVariant, const char *ExtraCode,
344 // Does this asm operand have a single letter operand modifier?
345 if (ExtraCode && ExtraCode[0]) {
346 if (ExtraCode[1] != 0) return true; // Unknown modifier.
348 switch (ExtraCode[0]) {
349 default: return true; // Unknown modifier.
350 case 'a': // Print as a memory address.
351 if (MI->getOperand(OpNum).isReg()) {
353 << ARMInstPrinter::getRegisterName(MI->getOperand(OpNum).getReg())
358 case 'c': // Don't print "#" before an immediate operand.
359 if (!MI->getOperand(OpNum).isImm())
361 O << MI->getOperand(OpNum).getImm();
363 case 'P': // Print a VFP double precision register.
364 case 'q': // Print a NEON quad precision register.
365 printOperand(MI, OpNum, O);
370 report_fatal_error("llvm does not support 'Q', 'R', and 'H' modifiers!");
375 printOperand(MI, OpNum, O);
379 bool ARMAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI,
380 unsigned OpNum, unsigned AsmVariant,
381 const char *ExtraCode,
383 if (ExtraCode && ExtraCode[0])
384 return true; // Unknown modifier.
386 const MachineOperand &MO = MI->getOperand(OpNum);
387 assert(MO.isReg() && "unexpected inline asm memory operand");
388 O << "[" << ARMInstPrinter::getRegisterName(MO.getReg()) << "]";
392 void ARMAsmPrinter::EmitStartOfAsmFile(Module &M) {
393 if (Subtarget->isTargetDarwin()) {
394 Reloc::Model RelocM = TM.getRelocationModel();
395 if (RelocM == Reloc::PIC_ || RelocM == Reloc::DynamicNoPIC) {
396 // Declare all the text sections up front (before the DWARF sections
397 // emitted by AsmPrinter::doInitialization) so the assembler will keep
398 // them together at the beginning of the object file. This helps
399 // avoid out-of-range branches that are due a fundamental limitation of
400 // the way symbol offsets are encoded with the current Darwin ARM
402 const TargetLoweringObjectFileMachO &TLOFMacho =
403 static_cast<const TargetLoweringObjectFileMachO &>(
404 getObjFileLowering());
405 OutStreamer.SwitchSection(TLOFMacho.getTextSection());
406 OutStreamer.SwitchSection(TLOFMacho.getTextCoalSection());
407 OutStreamer.SwitchSection(TLOFMacho.getConstTextCoalSection());
408 if (RelocM == Reloc::DynamicNoPIC) {
409 const MCSection *sect =
410 OutContext.getMachOSection("__TEXT", "__symbol_stub4",
411 MCSectionMachO::S_SYMBOL_STUBS,
412 12, SectionKind::getText());
413 OutStreamer.SwitchSection(sect);
415 const MCSection *sect =
416 OutContext.getMachOSection("__TEXT", "__picsymbolstub4",
417 MCSectionMachO::S_SYMBOL_STUBS,
418 16, SectionKind::getText());
419 OutStreamer.SwitchSection(sect);
421 const MCSection *StaticInitSect =
422 OutContext.getMachOSection("__TEXT", "__StaticInit",
423 MCSectionMachO::S_REGULAR |
424 MCSectionMachO::S_ATTR_PURE_INSTRUCTIONS,
425 SectionKind::getText());
426 OutStreamer.SwitchSection(StaticInitSect);
430 // Use unified assembler syntax.
431 OutStreamer.EmitAssemblerFlag(MCAF_SyntaxUnified);
433 // Emit ARM Build Attributes
434 if (Subtarget->isTargetELF()) {
441 void ARMAsmPrinter::EmitEndOfAsmFile(Module &M) {
442 if (Subtarget->isTargetDarwin()) {
443 // All darwin targets use mach-o.
444 const TargetLoweringObjectFileMachO &TLOFMacho =
445 static_cast<const TargetLoweringObjectFileMachO &>(getObjFileLowering());
446 MachineModuleInfoMachO &MMIMacho =
447 MMI->getObjFileInfo<MachineModuleInfoMachO>();
449 // Output non-lazy-pointers for external and common global variables.
450 MachineModuleInfoMachO::SymbolListTy Stubs = MMIMacho.GetGVStubList();
452 if (!Stubs.empty()) {
453 // Switch with ".non_lazy_symbol_pointer" directive.
454 OutStreamer.SwitchSection(TLOFMacho.getNonLazySymbolPointerSection());
456 for (unsigned i = 0, e = Stubs.size(); i != e; ++i) {
458 OutStreamer.EmitLabel(Stubs[i].first);
459 // .indirect_symbol _foo
460 MachineModuleInfoImpl::StubValueTy &MCSym = Stubs[i].second;
461 OutStreamer.EmitSymbolAttribute(MCSym.getPointer(),MCSA_IndirectSymbol);
464 // External to current translation unit.
465 OutStreamer.EmitIntValue(0, 4/*size*/, 0/*addrspace*/);
467 // Internal to current translation unit.
469 // When we place the LSDA into the TEXT section, the type info
470 // pointers need to be indirect and pc-rel. We accomplish this by
471 // using NLPs; however, sometimes the types are local to the file.
472 // We need to fill in the value for the NLP in those cases.
473 OutStreamer.EmitValue(MCSymbolRefExpr::Create(MCSym.getPointer(),
475 4/*size*/, 0/*addrspace*/);
479 OutStreamer.AddBlankLine();
482 Stubs = MMIMacho.GetHiddenGVStubList();
483 if (!Stubs.empty()) {
484 OutStreamer.SwitchSection(getObjFileLowering().getDataSection());
486 for (unsigned i = 0, e = Stubs.size(); i != e; ++i) {
488 OutStreamer.EmitLabel(Stubs[i].first);
490 OutStreamer.EmitValue(MCSymbolRefExpr::
491 Create(Stubs[i].second.getPointer(),
493 4/*size*/, 0/*addrspace*/);
497 OutStreamer.AddBlankLine();
500 // Funny Darwin hack: This flag tells the linker that no global symbols
501 // contain code that falls through to other global symbols (e.g. the obvious
502 // implementation of multiple entry points). If this doesn't occur, the
503 // linker can safely perform dead code stripping. Since LLVM never
504 // generates code that does this, it is always safe to set.
505 OutStreamer.EmitAssemblerFlag(MCAF_SubsectionsViaSymbols);
509 //===----------------------------------------------------------------------===//
510 // Helper routines for EmitStartOfAsmFile() and EmitEndOfAsmFile()
512 // The following seem like one-off assembler flags, but they actually need
513 // to appear in the .ARM.attributes section in ELF.
514 // Instead of subclassing the MCELFStreamer, we do the work here.
516 void ARMAsmPrinter::emitAttributes() {
518 emitARMAttributeSection();
520 AttributeEmitter *AttrEmitter;
521 if (OutStreamer.hasRawTextSupport())
522 AttrEmitter = new AsmAttributeEmitter(OutStreamer);
524 MCObjectStreamer &O = static_cast<MCObjectStreamer&>(OutStreamer);
525 AttrEmitter = new ObjectAttributeEmitter(O);
528 AttrEmitter->MaybeSwitchVendor("aeabi");
530 std::string CPUString = Subtarget->getCPUString();
531 if (OutStreamer.hasRawTextSupport()) {
532 if (CPUString != "generic")
533 OutStreamer.EmitRawText(StringRef("\t.cpu ") + CPUString);
535 assert(CPUString == "generic" && "Unsupported .cpu attribute for ELF/.o");
536 // FIXME: Why these defaults?
537 AttrEmitter->EmitAttribute(ARMBuildAttrs::CPU_arch, ARMBuildAttrs::v4T);
538 AttrEmitter->EmitAttribute(ARMBuildAttrs::ARM_ISA_use, 1);
539 AttrEmitter->EmitAttribute(ARMBuildAttrs::THUMB_ISA_use, 1);
542 // FIXME: Emit FPU type
543 if (Subtarget->hasVFP2())
544 AttrEmitter->EmitAttribute(ARMBuildAttrs::VFP_arch, 2);
546 // Signal various FP modes.
548 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_FP_denormal, 1);
549 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_FP_exceptions, 1);
552 if (NoInfsFPMath && NoNaNsFPMath)
553 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_FP_number_model, 1);
555 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_FP_number_model, 3);
557 // 8-bytes alignment stuff.
558 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_align8_needed, 1);
559 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_align8_preserved, 1);
561 // Hard float. Use both S and D registers and conform to AAPCS-VFP.
562 if (Subtarget->isAAPCS_ABI() && FloatABIType == FloatABI::Hard) {
563 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_HardFP_use, 3);
564 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_VFP_args, 1);
566 // FIXME: Should we signal R9 usage?
568 AttrEmitter->EmitAttribute(ARMBuildAttrs::DIV_use, 1);
570 AttrEmitter->Finish();
574 void ARMAsmPrinter::emitARMAttributeSection() {
576 // [ <section-length> "vendor-name"
577 // [ <file-tag> <size> <attribute>*
578 // | <section-tag> <size> <section-number>* 0 <attribute>*
579 // | <symbol-tag> <size> <symbol-number>* 0 <attribute>*
583 if (OutStreamer.hasRawTextSupport())
586 const ARMElfTargetObjectFile &TLOFELF =
587 static_cast<const ARMElfTargetObjectFile &>
588 (getObjFileLowering());
590 OutStreamer.SwitchSection(TLOFELF.getAttributesSection());
593 OutStreamer.EmitIntValue(0x41, 1);
596 //===----------------------------------------------------------------------===//
598 static MCSymbol *getPICLabel(const char *Prefix, unsigned FunctionNumber,
599 unsigned LabelId, MCContext &Ctx) {
601 MCSymbol *Label = Ctx.GetOrCreateSymbol(Twine(Prefix)
602 + "PC" + Twine(FunctionNumber) + "_" + Twine(LabelId));
607 EmitMachineConstantPoolValue(MachineConstantPoolValue *MCPV) {
608 int Size = TM.getTargetData()->getTypeAllocSize(MCPV->getType());
610 ARMConstantPoolValue *ACPV = static_cast<ARMConstantPoolValue*>(MCPV);
611 SmallString<128> Str;
612 raw_svector_ostream OS(Str);
614 if (ACPV->isLSDA()) {
615 OS << MAI->getPrivateGlobalPrefix() << "_LSDA_" << getFunctionNumber();
616 } else if (ACPV->isBlockAddress()) {
617 OS << *GetBlockAddressSymbol(ACPV->getBlockAddress());
618 } else if (ACPV->isGlobalValue()) {
619 const GlobalValue *GV = ACPV->getGV();
620 bool isIndirect = Subtarget->isTargetDarwin() &&
621 Subtarget->GVIsIndirectSymbol(GV, TM.getRelocationModel());
623 OS << *Mang->getSymbol(GV);
625 // FIXME: Remove this when Darwin transition to @GOT like syntax.
626 MCSymbol *Sym = GetSymbolWithGlobalValueBase(GV, "$non_lazy_ptr");
629 MachineModuleInfoMachO &MMIMachO =
630 MMI->getObjFileInfo<MachineModuleInfoMachO>();
631 MachineModuleInfoImpl::StubValueTy &StubSym =
632 GV->hasHiddenVisibility() ? MMIMachO.getHiddenGVStubEntry(Sym) :
633 MMIMachO.getGVStubEntry(Sym);
634 if (StubSym.getPointer() == 0)
635 StubSym = MachineModuleInfoImpl::
636 StubValueTy(Mang->getSymbol(GV), !GV->hasInternalLinkage());
639 assert(ACPV->isExtSymbol() && "unrecognized constant pool value");
640 OS << *GetExternalSymbolSymbol(ACPV->getSymbol());
643 // Create an MCSymbol for the reference.
644 MCSymbol *MCSym = OutContext.GetOrCreateSymbol(OS.str());
645 const MCExpr *Expr = MCSymbolRefExpr::Create(MCSym, OutContext);
647 // FIXME: Model the whole expression an an MCExpr and we can get rid
648 // of this hasRawTextSupport() clause and just do an EmitValue().
649 if (OutStreamer.hasRawTextSupport()) {
650 if (ACPV->hasModifier()) OS << "(" << ACPV->getModifierText() << ")";
651 if (ACPV->getPCAdjustment() != 0) {
652 OS << "-(" << MAI->getPrivateGlobalPrefix() << "PC"
653 << getFunctionNumber() << "_" << ACPV->getLabelId()
654 << "+" << (unsigned)ACPV->getPCAdjustment();
655 if (ACPV->mustAddCurrentAddress())
659 const char *DataDirective = 0;
661 case 1: DataDirective = MAI->getData8bitsDirective(0); break;
662 case 2: DataDirective = MAI->getData16bitsDirective(0); break;
663 case 4: DataDirective = MAI->getData32bitsDirective(0); break;
664 default: assert(0 && "Unknown CPV size");
666 Twine Text(DataDirective, OS.str());
667 OutStreamer.EmitRawText(Text);
669 assert(!ACPV->hasModifier() &&
670 "ARM binary streamer of non-trivial constant pool value!");
671 if (ACPV->getPCAdjustment()) {
672 MCSymbol *PCLabel = getPICLabel(MAI->getPrivateGlobalPrefix(),
676 const MCExpr *PCRelExpr = MCSymbolRefExpr::Create(PCLabel, OutContext);
678 MCBinaryExpr::CreateAdd(PCRelExpr,
679 MCConstantExpr::Create(ACPV->getPCAdjustment(),
682 if (ACPV->mustAddCurrentAddress()) {
683 // We want "(<expr> - .)", but MC doesn't have a concept of the '.'
684 // label, so just emit a local label end reference that instead.
685 MCSymbol *DotSym = OutContext.CreateTempSymbol();
686 OutStreamer.EmitLabel(DotSym);
687 const MCExpr *DotExpr = MCSymbolRefExpr::Create(DotSym, OutContext);
688 Expr = MCBinaryExpr::CreateSub(Expr, DotExpr, OutContext);
690 Expr = MCBinaryExpr::CreateSub(Expr, PCRelExpr, OutContext);
692 OutStreamer.EmitValue(Expr, Size);
696 void ARMAsmPrinter::EmitJumpTable(const MachineInstr *MI) {
697 unsigned Opcode = MI->getOpcode();
699 if (Opcode == ARM::BR_JTadd)
701 else if (Opcode == ARM::BR_JTm)
704 const MachineOperand &MO1 = MI->getOperand(OpNum);
705 const MachineOperand &MO2 = MI->getOperand(OpNum+1); // Unique Id
706 unsigned JTI = MO1.getIndex();
708 // Emit a label for the jump table.
709 MCSymbol *JTISymbol = GetARMJTIPICJumpTableLabel2(JTI, MO2.getImm());
710 OutStreamer.EmitLabel(JTISymbol);
712 // Emit each entry of the table.
713 const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
714 const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
715 const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
717 for (unsigned i = 0, e = JTBBs.size(); i != e; ++i) {
718 MachineBasicBlock *MBB = JTBBs[i];
719 // Construct an MCExpr for the entry. We want a value of the form:
720 // (BasicBlockAddr - TableBeginAddr)
722 // For example, a table with entries jumping to basic blocks BB0 and BB1
725 // .word (LBB0 - LJTI_0_0)
726 // .word (LBB1 - LJTI_0_0)
727 const MCExpr *Expr = MCSymbolRefExpr::Create(MBB->getSymbol(), OutContext);
729 if (TM.getRelocationModel() == Reloc::PIC_)
730 Expr = MCBinaryExpr::CreateSub(Expr, MCSymbolRefExpr::Create(JTISymbol,
733 OutStreamer.EmitValue(Expr, 4);
737 void ARMAsmPrinter::EmitJump2Table(const MachineInstr *MI) {
738 unsigned Opcode = MI->getOpcode();
739 int OpNum = (Opcode == ARM::t2BR_JT) ? 2 : 1;
740 const MachineOperand &MO1 = MI->getOperand(OpNum);
741 const MachineOperand &MO2 = MI->getOperand(OpNum+1); // Unique Id
742 unsigned JTI = MO1.getIndex();
744 // Emit a label for the jump table.
745 MCSymbol *JTISymbol = GetARMJTIPICJumpTableLabel2(JTI, MO2.getImm());
746 OutStreamer.EmitLabel(JTISymbol);
748 // Emit each entry of the table.
749 const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
750 const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
751 const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
752 unsigned OffsetWidth = 4;
753 if (MI->getOpcode() == ARM::t2TBB)
755 else if (MI->getOpcode() == ARM::t2TBH)
758 for (unsigned i = 0, e = JTBBs.size(); i != e; ++i) {
759 MachineBasicBlock *MBB = JTBBs[i];
760 const MCExpr *MBBSymbolExpr = MCSymbolRefExpr::Create(MBB->getSymbol(),
762 // If this isn't a TBB or TBH, the entries are direct branch instructions.
763 if (OffsetWidth == 4) {
765 BrInst.setOpcode(ARM::t2B);
766 BrInst.addOperand(MCOperand::CreateExpr(MBBSymbolExpr));
767 OutStreamer.EmitInstruction(BrInst);
770 // Otherwise it's an offset from the dispatch instruction. Construct an
771 // MCExpr for the entry. We want a value of the form:
772 // (BasicBlockAddr - TableBeginAddr) / 2
774 // For example, a TBB table with entries jumping to basic blocks BB0 and BB1
777 // .byte (LBB0 - LJTI_0_0) / 2
778 // .byte (LBB1 - LJTI_0_0) / 2
780 MCBinaryExpr::CreateSub(MBBSymbolExpr,
781 MCSymbolRefExpr::Create(JTISymbol, OutContext),
783 Expr = MCBinaryExpr::CreateDiv(Expr, MCConstantExpr::Create(2, OutContext),
785 OutStreamer.EmitValue(Expr, OffsetWidth);
788 // Make sure the instruction that follows TBB is 2-byte aligned.
789 // FIXME: Constant island pass should insert an "ALIGN" instruction instead.
790 if (MI->getOpcode() == ARM::t2TBB)
794 void ARMAsmPrinter::PrintDebugValueComment(const MachineInstr *MI,
796 unsigned NOps = MI->getNumOperands();
798 OS << '\t' << MAI->getCommentString() << "DEBUG_VALUE: ";
799 // cast away const; DIetc do not take const operands for some reason.
800 DIVariable V(const_cast<MDNode *>(MI->getOperand(NOps-1).getMetadata()));
803 // Frame address. Currently handles register +- offset only.
804 assert(MI->getOperand(0).isReg() && MI->getOperand(1).isImm());
805 OS << '['; printOperand(MI, 0, OS); OS << '+'; printOperand(MI, 1, OS);
808 printOperand(MI, NOps-2, OS);
811 void ARMAsmPrinter::EmitInstruction(const MachineInstr *MI) {
812 ARMMCInstLower MCInstLowering(OutContext, *Mang, *this);
813 switch (MI->getOpcode()) {
814 case ARM::t2MOVi32imm:
815 assert(0 && "Should be lowered by thumb2it pass");
817 case ARM::DBG_VALUE: {
818 if (isVerbose() && OutStreamer.hasRawTextSupport()) {
819 SmallString<128> TmpStr;
820 raw_svector_ostream OS(TmpStr);
821 PrintDebugValueComment(MI, OS);
822 OutStreamer.EmitRawText(StringRef(OS.str()));
827 // This is a pseudo op for a label + instruction sequence, which looks like:
830 // This adds the address of LPC0 to r0.
833 OutStreamer.EmitLabel(getPICLabel(MAI->getPrivateGlobalPrefix(),
834 getFunctionNumber(), MI->getOperand(2).getImm(),
837 // Form and emit the add.
839 AddInst.setOpcode(ARM::tADDhirr);
840 AddInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
841 AddInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
842 AddInst.addOperand(MCOperand::CreateReg(ARM::PC));
843 // Add predicate operands.
844 AddInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
845 AddInst.addOperand(MCOperand::CreateReg(0));
846 OutStreamer.EmitInstruction(AddInst);
850 // This is a pseudo op for a label + instruction sequence, which looks like:
853 // This adds the address of LPC0 to r0.
856 OutStreamer.EmitLabel(getPICLabel(MAI->getPrivateGlobalPrefix(),
857 getFunctionNumber(), MI->getOperand(2).getImm(),
860 // Form and emit the add.
862 AddInst.setOpcode(ARM::ADDrr);
863 AddInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
864 AddInst.addOperand(MCOperand::CreateReg(ARM::PC));
865 AddInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg()));
866 // Add predicate operands.
867 AddInst.addOperand(MCOperand::CreateImm(MI->getOperand(3).getImm()));
868 AddInst.addOperand(MCOperand::CreateReg(MI->getOperand(4).getReg()));
869 // Add 's' bit operand (always reg0 for this)
870 AddInst.addOperand(MCOperand::CreateReg(0));
871 OutStreamer.EmitInstruction(AddInst);
881 case ARM::PICLDRSH: {
882 // This is a pseudo op for a label + instruction sequence, which looks like:
885 // The LCP0 label is referenced by a constant pool entry in order to get
886 // a PC-relative address at the ldr instruction.
889 OutStreamer.EmitLabel(getPICLabel(MAI->getPrivateGlobalPrefix(),
890 getFunctionNumber(), MI->getOperand(2).getImm(),
893 // Form and emit the load
895 switch (MI->getOpcode()) {
897 llvm_unreachable("Unexpected opcode!");
898 case ARM::PICSTR: Opcode = ARM::STRrs; break;
899 case ARM::PICSTRB: Opcode = ARM::STRBrs; break;
900 case ARM::PICSTRH: Opcode = ARM::STRH; break;
901 case ARM::PICLDR: Opcode = ARM::LDRrs; break;
902 case ARM::PICLDRB: Opcode = ARM::LDRBrs; break;
903 case ARM::PICLDRH: Opcode = ARM::LDRH; break;
904 case ARM::PICLDRSB: Opcode = ARM::LDRSB; break;
905 case ARM::PICLDRSH: Opcode = ARM::LDRSH; break;
908 LdStInst.setOpcode(Opcode);
909 LdStInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
910 LdStInst.addOperand(MCOperand::CreateReg(ARM::PC));
911 LdStInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg()));
912 LdStInst.addOperand(MCOperand::CreateImm(0));
913 // Add predicate operands.
914 LdStInst.addOperand(MCOperand::CreateImm(MI->getOperand(3).getImm()));
915 LdStInst.addOperand(MCOperand::CreateReg(MI->getOperand(4).getReg()));
916 OutStreamer.EmitInstruction(LdStInst);
920 case ARM::CONSTPOOL_ENTRY: {
921 /// CONSTPOOL_ENTRY - This instruction represents a floating constant pool
922 /// in the function. The first operand is the ID# for this instruction, the
923 /// second is the index into the MachineConstantPool that this is, the third
924 /// is the size in bytes of this constant pool entry.
925 unsigned LabelId = (unsigned)MI->getOperand(0).getImm();
926 unsigned CPIdx = (unsigned)MI->getOperand(1).getIndex();
929 OutStreamer.EmitLabel(GetCPISymbol(LabelId));
931 const MachineConstantPoolEntry &MCPE = MCP->getConstants()[CPIdx];
932 if (MCPE.isMachineConstantPoolEntry())
933 EmitMachineConstantPoolValue(MCPE.Val.MachineCPVal);
935 EmitGlobalConstant(MCPE.Val.ConstVal);
942 // Lower and emit the instruction itself, then the jump table following it.
944 MCInstLowering.Lower(MI, TmpInst);
945 OutStreamer.EmitInstruction(TmpInst);
952 case ARM::BR_JTadd: {
953 // Lower and emit the instruction itself, then the jump table following it.
955 MCInstLowering.Lower(MI, TmpInst);
956 OutStreamer.EmitInstruction(TmpInst);
961 // Non-Darwin binutils don't yet support the "trap" mnemonic.
962 // FIXME: Remove this special case when they do.
963 if (!Subtarget->isTargetDarwin()) {
964 //.long 0xe7ffdefe @ trap
965 uint32_t Val = 0xe7ffdefeUL;
966 OutStreamer.AddComment("trap");
967 OutStreamer.EmitIntValue(Val, 4);
973 // Non-Darwin binutils don't yet support the "trap" mnemonic.
974 // FIXME: Remove this special case when they do.
975 if (!Subtarget->isTargetDarwin()) {
976 //.short 57086 @ trap
977 uint16_t Val = 0xdefe;
978 OutStreamer.AddComment("trap");
979 OutStreamer.EmitIntValue(Val, 2);
984 case ARM::t2Int_eh_sjlj_setjmp:
985 case ARM::t2Int_eh_sjlj_setjmp_nofp:
986 case ARM::tInt_eh_sjlj_setjmp: {
987 // Two incoming args: GPR:$src, GPR:$val
990 // str $val, [$src, #4]
995 unsigned SrcReg = MI->getOperand(0).getReg();
996 unsigned ValReg = MI->getOperand(1).getReg();
997 MCSymbol *Label = GetARMSJLJEHLabel();
1000 TmpInst.setOpcode(ARM::tMOVgpr2tgpr);
1001 TmpInst.addOperand(MCOperand::CreateReg(ValReg));
1002 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1004 TmpInst.addOperand(MCOperand::CreateReg(ARM::CPSR));
1005 OutStreamer.AddComment("eh_setjmp begin");
1006 OutStreamer.EmitInstruction(TmpInst);
1010 TmpInst.setOpcode(ARM::tADDi3);
1011 TmpInst.addOperand(MCOperand::CreateReg(ValReg));
1013 TmpInst.addOperand(MCOperand::CreateReg(ARM::CPSR));
1014 TmpInst.addOperand(MCOperand::CreateReg(ValReg));
1015 TmpInst.addOperand(MCOperand::CreateImm(7));
1017 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1018 TmpInst.addOperand(MCOperand::CreateReg(0));
1019 OutStreamer.EmitInstruction(TmpInst);
1023 TmpInst.setOpcode(ARM::tSTR);
1024 TmpInst.addOperand(MCOperand::CreateReg(ValReg));
1025 TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
1026 // The offset immediate is #4. The operand value is scaled by 4 for the
1027 // tSTR instruction.
1028 TmpInst.addOperand(MCOperand::CreateImm(1));
1029 TmpInst.addOperand(MCOperand::CreateReg(0));
1031 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1032 TmpInst.addOperand(MCOperand::CreateReg(0));
1033 OutStreamer.EmitInstruction(TmpInst);
1037 TmpInst.setOpcode(ARM::tMOVi8);
1038 TmpInst.addOperand(MCOperand::CreateReg(ARM::R0));
1039 TmpInst.addOperand(MCOperand::CreateReg(ARM::CPSR));
1040 TmpInst.addOperand(MCOperand::CreateImm(0));
1042 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1043 TmpInst.addOperand(MCOperand::CreateReg(0));
1044 OutStreamer.EmitInstruction(TmpInst);
1047 const MCExpr *SymbolExpr = MCSymbolRefExpr::Create(Label, OutContext);
1049 TmpInst.setOpcode(ARM::tB);
1050 TmpInst.addOperand(MCOperand::CreateExpr(SymbolExpr));
1051 OutStreamer.EmitInstruction(TmpInst);
1055 TmpInst.setOpcode(ARM::tMOVi8);
1056 TmpInst.addOperand(MCOperand::CreateReg(ARM::R0));
1057 TmpInst.addOperand(MCOperand::CreateReg(ARM::CPSR));
1058 TmpInst.addOperand(MCOperand::CreateImm(1));
1060 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1061 TmpInst.addOperand(MCOperand::CreateReg(0));
1062 OutStreamer.AddComment("eh_setjmp end");
1063 OutStreamer.EmitInstruction(TmpInst);
1065 OutStreamer.EmitLabel(Label);
1069 case ARM::Int_eh_sjlj_setjmp_nofp:
1070 case ARM::Int_eh_sjlj_setjmp: {
1071 // Two incoming args: GPR:$src, GPR:$val
1073 // str $val, [$src, #+4]
1077 unsigned SrcReg = MI->getOperand(0).getReg();
1078 unsigned ValReg = MI->getOperand(1).getReg();
1082 TmpInst.setOpcode(ARM::ADDri);
1083 TmpInst.addOperand(MCOperand::CreateReg(ValReg));
1084 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1085 TmpInst.addOperand(MCOperand::CreateImm(8));
1087 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1088 TmpInst.addOperand(MCOperand::CreateReg(0));
1089 // 's' bit operand (always reg0 for this).
1090 TmpInst.addOperand(MCOperand::CreateReg(0));
1091 OutStreamer.AddComment("eh_setjmp begin");
1092 OutStreamer.EmitInstruction(TmpInst);
1096 TmpInst.setOpcode(ARM::STRi12);
1097 TmpInst.addOperand(MCOperand::CreateReg(ValReg));
1098 TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
1099 TmpInst.addOperand(MCOperand::CreateImm(4));
1101 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1102 TmpInst.addOperand(MCOperand::CreateReg(0));
1103 OutStreamer.EmitInstruction(TmpInst);
1107 TmpInst.setOpcode(ARM::MOVi);
1108 TmpInst.addOperand(MCOperand::CreateReg(ARM::R0));
1109 TmpInst.addOperand(MCOperand::CreateImm(0));
1111 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1112 TmpInst.addOperand(MCOperand::CreateReg(0));
1113 // 's' bit operand (always reg0 for this).
1114 TmpInst.addOperand(MCOperand::CreateReg(0));
1115 OutStreamer.EmitInstruction(TmpInst);
1119 TmpInst.setOpcode(ARM::ADDri);
1120 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1121 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1122 TmpInst.addOperand(MCOperand::CreateImm(0));
1124 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1125 TmpInst.addOperand(MCOperand::CreateReg(0));
1126 // 's' bit operand (always reg0 for this).
1127 TmpInst.addOperand(MCOperand::CreateReg(0));
1128 OutStreamer.EmitInstruction(TmpInst);
1132 TmpInst.setOpcode(ARM::MOVi);
1133 TmpInst.addOperand(MCOperand::CreateReg(ARM::R0));
1134 TmpInst.addOperand(MCOperand::CreateImm(1));
1136 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1137 TmpInst.addOperand(MCOperand::CreateReg(0));
1138 // 's' bit operand (always reg0 for this).
1139 TmpInst.addOperand(MCOperand::CreateReg(0));
1140 OutStreamer.AddComment("eh_setjmp end");
1141 OutStreamer.EmitInstruction(TmpInst);
1145 case ARM::Int_eh_sjlj_longjmp: {
1146 // ldr sp, [$src, #8]
1147 // ldr $scratch, [$src, #4]
1150 unsigned SrcReg = MI->getOperand(0).getReg();
1151 unsigned ScratchReg = MI->getOperand(1).getReg();
1154 TmpInst.setOpcode(ARM::LDRi12);
1155 TmpInst.addOperand(MCOperand::CreateReg(ARM::SP));
1156 TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
1157 TmpInst.addOperand(MCOperand::CreateImm(8));
1159 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1160 TmpInst.addOperand(MCOperand::CreateReg(0));
1161 OutStreamer.EmitInstruction(TmpInst);
1165 TmpInst.setOpcode(ARM::LDRi12);
1166 TmpInst.addOperand(MCOperand::CreateReg(ScratchReg));
1167 TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
1168 TmpInst.addOperand(MCOperand::CreateImm(4));
1170 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1171 TmpInst.addOperand(MCOperand::CreateReg(0));
1172 OutStreamer.EmitInstruction(TmpInst);
1176 TmpInst.setOpcode(ARM::LDRi12);
1177 TmpInst.addOperand(MCOperand::CreateReg(ARM::R7));
1178 TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
1179 TmpInst.addOperand(MCOperand::CreateImm(0));
1181 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1182 TmpInst.addOperand(MCOperand::CreateReg(0));
1183 OutStreamer.EmitInstruction(TmpInst);
1187 TmpInst.setOpcode(ARM::BRIND);
1188 TmpInst.addOperand(MCOperand::CreateReg(ScratchReg));
1190 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1191 TmpInst.addOperand(MCOperand::CreateReg(0));
1192 OutStreamer.EmitInstruction(TmpInst);
1196 case ARM::tInt_eh_sjlj_longjmp: {
1197 // ldr $scratch, [$src, #8]
1199 // ldr $scratch, [$src, #4]
1202 unsigned SrcReg = MI->getOperand(0).getReg();
1203 unsigned ScratchReg = MI->getOperand(1).getReg();
1206 TmpInst.setOpcode(ARM::tLDR);
1207 TmpInst.addOperand(MCOperand::CreateReg(ScratchReg));
1208 TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
1209 // The offset immediate is #8. The operand value is scaled by 4 for the
1210 // tSTR instruction.
1211 TmpInst.addOperand(MCOperand::CreateImm(2));
1212 TmpInst.addOperand(MCOperand::CreateReg(0));
1214 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1215 TmpInst.addOperand(MCOperand::CreateReg(0));
1216 OutStreamer.EmitInstruction(TmpInst);
1220 TmpInst.setOpcode(ARM::tMOVtgpr2gpr);
1221 TmpInst.addOperand(MCOperand::CreateReg(ARM::SP));
1222 TmpInst.addOperand(MCOperand::CreateReg(ScratchReg));
1224 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1225 TmpInst.addOperand(MCOperand::CreateReg(0));
1226 OutStreamer.EmitInstruction(TmpInst);
1230 TmpInst.setOpcode(ARM::tLDR);
1231 TmpInst.addOperand(MCOperand::CreateReg(ScratchReg));
1232 TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
1233 TmpInst.addOperand(MCOperand::CreateImm(1));
1234 TmpInst.addOperand(MCOperand::CreateReg(0));
1236 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1237 TmpInst.addOperand(MCOperand::CreateReg(0));
1238 OutStreamer.EmitInstruction(TmpInst);
1242 TmpInst.setOpcode(ARM::tLDR);
1243 TmpInst.addOperand(MCOperand::CreateReg(ARM::R7));
1244 TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
1245 TmpInst.addOperand(MCOperand::CreateImm(0));
1246 TmpInst.addOperand(MCOperand::CreateReg(0));
1248 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1249 TmpInst.addOperand(MCOperand::CreateReg(0));
1250 OutStreamer.EmitInstruction(TmpInst);
1254 TmpInst.setOpcode(ARM::tBX_RET_vararg);
1255 TmpInst.addOperand(MCOperand::CreateReg(ScratchReg));
1257 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1258 TmpInst.addOperand(MCOperand::CreateReg(0));
1259 OutStreamer.EmitInstruction(TmpInst);
1266 MCInstLowering.Lower(MI, TmpInst);
1267 OutStreamer.EmitInstruction(TmpInst);
1270 //===----------------------------------------------------------------------===//
1271 // Target Registry Stuff
1272 //===----------------------------------------------------------------------===//
1274 static MCInstPrinter *createARMMCInstPrinter(const Target &T,
1275 unsigned SyntaxVariant,
1276 const MCAsmInfo &MAI) {
1277 if (SyntaxVariant == 0)
1278 return new ARMInstPrinter(MAI);
1282 // Force static initialization.
1283 extern "C" void LLVMInitializeARMAsmPrinter() {
1284 RegisterAsmPrinter<ARMAsmPrinter> X(TheARMTarget);
1285 RegisterAsmPrinter<ARMAsmPrinter> Y(TheThumbTarget);
1287 TargetRegistry::RegisterMCInstPrinter(TheARMTarget, createARMMCInstPrinter);
1288 TargetRegistry::RegisterMCInstPrinter(TheThumbTarget, createARMMCInstPrinter);