1 //===-- ARMAsmPrinter.cpp - Print machine code to an ARM .s file ----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains a printer that converts from our internal representation
11 // of machine-dependent LLVM code to GAS-format ARM assembly language.
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "asm-printer"
17 #include "ARMBuildAttrs.h"
18 #include "ARMAddressingModes.h"
19 #include "ARMConstantPoolValue.h"
20 #include "InstPrinter/ARMInstPrinter.h"
21 #include "ARMMachineFunctionInfo.h"
22 #include "ARMMCInstLower.h"
23 #include "ARMTargetMachine.h"
24 #include "ARMTargetObjectFile.h"
25 #include "llvm/Analysis/DebugInfo.h"
26 #include "llvm/Constants.h"
27 #include "llvm/Module.h"
28 #include "llvm/Type.h"
29 #include "llvm/Assembly/Writer.h"
30 #include "llvm/CodeGen/AsmPrinter.h"
31 #include "llvm/CodeGen/MachineModuleInfoImpls.h"
32 #include "llvm/CodeGen/MachineFunctionPass.h"
33 #include "llvm/CodeGen/MachineJumpTableInfo.h"
34 #include "llvm/MC/MCAsmInfo.h"
35 #include "llvm/MC/MCContext.h"
36 #include "llvm/MC/MCExpr.h"
37 #include "llvm/MC/MCInst.h"
38 #include "llvm/MC/MCSectionMachO.h"
39 #include "llvm/MC/MCStreamer.h"
40 #include "llvm/MC/MCSymbol.h"
41 #include "llvm/Target/Mangler.h"
42 #include "llvm/Target/TargetData.h"
43 #include "llvm/Target/TargetMachine.h"
44 #include "llvm/Target/TargetOptions.h"
45 #include "llvm/Target/TargetRegistry.h"
46 #include "llvm/ADT/SmallPtrSet.h"
47 #include "llvm/ADT/SmallString.h"
48 #include "llvm/ADT/StringExtras.h"
49 #include "llvm/Support/CommandLine.h"
50 #include "llvm/Support/Debug.h"
51 #include "llvm/Support/ErrorHandling.h"
52 #include "llvm/Support/raw_ostream.h"
66 class ARMAsmPrinter : public AsmPrinter {
68 /// Subtarget - Keep a pointer to the ARMSubtarget around so that we can
69 /// make the right decision when printing asm code for different targets.
70 const ARMSubtarget *Subtarget;
72 /// AFI - Keep a pointer to ARMFunctionInfo for the current
76 /// MCP - Keep a pointer to constantpool entries of the current
78 const MachineConstantPool *MCP;
81 explicit ARMAsmPrinter(TargetMachine &TM, MCStreamer &Streamer)
82 : AsmPrinter(TM, Streamer), AFI(NULL), MCP(NULL) {
83 Subtarget = &TM.getSubtarget<ARMSubtarget>();
86 virtual const char *getPassName() const {
87 return "ARM Assembly Printer";
90 void printOperand(const MachineInstr *MI, int OpNum, raw_ostream &O,
91 const char *Modifier = 0);
93 virtual bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
94 unsigned AsmVariant, const char *ExtraCode,
96 virtual bool PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNum,
98 const char *ExtraCode, raw_ostream &O);
100 void EmitJumpTable(const MachineInstr *MI);
101 void EmitJump2Table(const MachineInstr *MI);
102 virtual void EmitInstruction(const MachineInstr *MI);
103 bool runOnMachineFunction(MachineFunction &F);
105 virtual void EmitConstantPool() {} // we emit constant pools customly!
106 virtual void EmitFunctionEntryLabel();
107 void EmitStartOfAsmFile(Module &M);
108 void EmitEndOfAsmFile(Module &M);
111 // Helpers for EmitStartOfAsmFile() and EmitEndOfAsmFile()
112 void emitAttributes();
113 void emitTextAttribute(ARMBuildAttrs::SpecialAttr attr, StringRef v);
114 void emitAttribute(ARMBuildAttrs::AttrType attr, int v);
116 // Helper for ELF .o only
117 void emitARMAttributeSection();
120 void PrintDebugValueComment(const MachineInstr *MI, raw_ostream &OS);
122 MachineLocation getDebugValueLocation(const MachineInstr *MI) const {
123 MachineLocation Location;
124 assert (MI->getNumOperands() == 4 && "Invalid no. of machine operands!");
125 // Frame address. Currently handles register +- offset only.
126 if (MI->getOperand(0).isReg() && MI->getOperand(1).isImm())
127 Location.set(MI->getOperand(0).getReg(), MI->getOperand(1).getImm());
129 DEBUG(dbgs() << "DBG_VALUE instruction ignored! " << *MI << "\n");
134 virtual unsigned getISAEncoding() {
135 // ARM/Darwin adds ISA to the DWARF info for each function.
136 if (!Subtarget->isTargetDarwin())
138 return Subtarget->isThumb() ?
139 llvm::ARM::DW_ISA_ARM_thumb : llvm::ARM::DW_ISA_ARM_arm;
142 MCSymbol *GetARMSetPICJumpTableLabel2(unsigned uid, unsigned uid2,
143 const MachineBasicBlock *MBB) const;
144 MCSymbol *GetARMJTIPICJumpTableLabel2(unsigned uid, unsigned uid2) const;
146 MCSymbol *GetARMSJLJEHLabel(void) const;
148 /// EmitMachineConstantPoolValue - Print a machine constantpool value to
150 virtual void EmitMachineConstantPoolValue(MachineConstantPoolValue *MCPV) {
151 SmallString<128> Str;
152 raw_svector_ostream OS(Str);
153 EmitMachineConstantPoolValue(MCPV, OS);
154 OutStreamer.EmitRawText(OS.str());
157 void EmitMachineConstantPoolValue(MachineConstantPoolValue *MCPV,
159 switch (TM.getTargetData()->getTypeAllocSize(MCPV->getType())) {
160 case 1: O << MAI->getData8bitsDirective(0); break;
161 case 2: O << MAI->getData16bitsDirective(0); break;
162 case 4: O << MAI->getData32bitsDirective(0); break;
163 default: assert(0 && "Unknown CPV size");
166 ARMConstantPoolValue *ACPV = static_cast<ARMConstantPoolValue*>(MCPV);
168 if (ACPV->isLSDA()) {
169 O << MAI->getPrivateGlobalPrefix() << "_LSDA_" << getFunctionNumber();
170 } else if (ACPV->isBlockAddress()) {
171 O << *GetBlockAddressSymbol(ACPV->getBlockAddress());
172 } else if (ACPV->isGlobalValue()) {
173 const GlobalValue *GV = ACPV->getGV();
174 bool isIndirect = Subtarget->isTargetDarwin() &&
175 Subtarget->GVIsIndirectSymbol(GV, TM.getRelocationModel());
177 O << *Mang->getSymbol(GV);
179 // FIXME: Remove this when Darwin transition to @GOT like syntax.
180 MCSymbol *Sym = GetSymbolWithGlobalValueBase(GV, "$non_lazy_ptr");
183 MachineModuleInfoMachO &MMIMachO =
184 MMI->getObjFileInfo<MachineModuleInfoMachO>();
185 MachineModuleInfoImpl::StubValueTy &StubSym =
186 GV->hasHiddenVisibility() ? MMIMachO.getHiddenGVStubEntry(Sym) :
187 MMIMachO.getGVStubEntry(Sym);
188 if (StubSym.getPointer() == 0)
189 StubSym = MachineModuleInfoImpl::
190 StubValueTy(Mang->getSymbol(GV), !GV->hasInternalLinkage());
193 assert(ACPV->isExtSymbol() && "unrecognized constant pool value");
194 O << *GetExternalSymbolSymbol(ACPV->getSymbol());
197 if (ACPV->hasModifier()) O << "(" << ACPV->getModifier() << ")";
198 if (ACPV->getPCAdjustment() != 0) {
199 O << "-(" << MAI->getPrivateGlobalPrefix() << "PC"
200 << getFunctionNumber() << "_" << ACPV->getLabelId()
201 << "+" << (unsigned)ACPV->getPCAdjustment();
202 if (ACPV->mustAddCurrentAddress())
208 } // end of anonymous namespace
210 void ARMAsmPrinter::EmitFunctionEntryLabel() {
211 if (AFI->isThumbFunction()) {
212 OutStreamer.EmitRawText(StringRef("\t.code\t16"));
213 if (!Subtarget->isTargetDarwin())
214 OutStreamer.EmitRawText(StringRef("\t.thumb_func"));
216 // This needs to emit to a temporary string to get properly quoted
217 // MCSymbols when they have spaces in them.
218 SmallString<128> Tmp;
219 raw_svector_ostream OS(Tmp);
220 OS << "\t.thumb_func\t" << *CurrentFnSym;
221 OutStreamer.EmitRawText(OS.str());
225 OutStreamer.EmitLabel(CurrentFnSym);
228 /// runOnMachineFunction - This uses the EmitInstruction()
229 /// method to print assembly for each instruction.
231 bool ARMAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
232 AFI = MF.getInfo<ARMFunctionInfo>();
233 MCP = MF.getConstantPool();
235 return AsmPrinter::runOnMachineFunction(MF);
238 void ARMAsmPrinter::printOperand(const MachineInstr *MI, int OpNum,
239 raw_ostream &O, const char *Modifier) {
240 const MachineOperand &MO = MI->getOperand(OpNum);
241 unsigned TF = MO.getTargetFlags();
243 switch (MO.getType()) {
245 assert(0 && "<unknown operand type>");
246 case MachineOperand::MO_Register: {
247 unsigned Reg = MO.getReg();
248 assert(TargetRegisterInfo::isPhysicalRegister(Reg));
249 assert(!MO.getSubReg() && "Subregs should be eliminated!");
250 O << ARMInstPrinter::getRegisterName(Reg);
253 case MachineOperand::MO_Immediate: {
254 int64_t Imm = MO.getImm();
256 if ((Modifier && strcmp(Modifier, "lo16") == 0) ||
257 (TF == ARMII::MO_LO16))
259 else if ((Modifier && strcmp(Modifier, "hi16") == 0) ||
260 (TF == ARMII::MO_HI16))
265 case MachineOperand::MO_MachineBasicBlock:
266 O << *MO.getMBB()->getSymbol();
268 case MachineOperand::MO_GlobalAddress: {
269 const GlobalValue *GV = MO.getGlobal();
270 if ((Modifier && strcmp(Modifier, "lo16") == 0) ||
271 (TF & ARMII::MO_LO16))
273 else if ((Modifier && strcmp(Modifier, "hi16") == 0) ||
274 (TF & ARMII::MO_HI16))
276 O << *Mang->getSymbol(GV);
278 printOffset(MO.getOffset(), O);
279 if (TF == ARMII::MO_PLT)
283 case MachineOperand::MO_ExternalSymbol: {
284 O << *GetExternalSymbolSymbol(MO.getSymbolName());
285 if (TF == ARMII::MO_PLT)
289 case MachineOperand::MO_ConstantPoolIndex:
290 O << *GetCPISymbol(MO.getIndex());
292 case MachineOperand::MO_JumpTableIndex:
293 O << *GetJTISymbol(MO.getIndex());
298 //===--------------------------------------------------------------------===//
300 MCSymbol *ARMAsmPrinter::
301 GetARMSetPICJumpTableLabel2(unsigned uid, unsigned uid2,
302 const MachineBasicBlock *MBB) const {
303 SmallString<60> Name;
304 raw_svector_ostream(Name) << MAI->getPrivateGlobalPrefix()
305 << getFunctionNumber() << '_' << uid << '_' << uid2
306 << "_set_" << MBB->getNumber();
307 return OutContext.GetOrCreateSymbol(Name.str());
310 MCSymbol *ARMAsmPrinter::
311 GetARMJTIPICJumpTableLabel2(unsigned uid, unsigned uid2) const {
312 SmallString<60> Name;
313 raw_svector_ostream(Name) << MAI->getPrivateGlobalPrefix() << "JTI"
314 << getFunctionNumber() << '_' << uid << '_' << uid2;
315 return OutContext.GetOrCreateSymbol(Name.str());
319 MCSymbol *ARMAsmPrinter::GetARMSJLJEHLabel(void) const {
320 SmallString<60> Name;
321 raw_svector_ostream(Name) << MAI->getPrivateGlobalPrefix() << "SJLJEH"
322 << getFunctionNumber();
323 return OutContext.GetOrCreateSymbol(Name.str());
326 bool ARMAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
327 unsigned AsmVariant, const char *ExtraCode,
329 // Does this asm operand have a single letter operand modifier?
330 if (ExtraCode && ExtraCode[0]) {
331 if (ExtraCode[1] != 0) return true; // Unknown modifier.
333 switch (ExtraCode[0]) {
334 default: return true; // Unknown modifier.
335 case 'a': // Print as a memory address.
336 if (MI->getOperand(OpNum).isReg()) {
338 << ARMInstPrinter::getRegisterName(MI->getOperand(OpNum).getReg())
343 case 'c': // Don't print "#" before an immediate operand.
344 if (!MI->getOperand(OpNum).isImm())
346 O << MI->getOperand(OpNum).getImm();
348 case 'P': // Print a VFP double precision register.
349 case 'q': // Print a NEON quad precision register.
350 printOperand(MI, OpNum, O);
355 report_fatal_error("llvm does not support 'Q', 'R', and 'H' modifiers!");
360 printOperand(MI, OpNum, O);
364 bool ARMAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI,
365 unsigned OpNum, unsigned AsmVariant,
366 const char *ExtraCode,
368 if (ExtraCode && ExtraCode[0])
369 return true; // Unknown modifier.
371 const MachineOperand &MO = MI->getOperand(OpNum);
372 assert(MO.isReg() && "unexpected inline asm memory operand");
373 O << "[" << ARMInstPrinter::getRegisterName(MO.getReg()) << "]";
377 void ARMAsmPrinter::EmitStartOfAsmFile(Module &M) {
378 if (Subtarget->isTargetDarwin()) {
379 Reloc::Model RelocM = TM.getRelocationModel();
380 if (RelocM == Reloc::PIC_ || RelocM == Reloc::DynamicNoPIC) {
381 // Declare all the text sections up front (before the DWARF sections
382 // emitted by AsmPrinter::doInitialization) so the assembler will keep
383 // them together at the beginning of the object file. This helps
384 // avoid out-of-range branches that are due a fundamental limitation of
385 // the way symbol offsets are encoded with the current Darwin ARM
387 const TargetLoweringObjectFileMachO &TLOFMacho =
388 static_cast<const TargetLoweringObjectFileMachO &>(
389 getObjFileLowering());
390 OutStreamer.SwitchSection(TLOFMacho.getTextSection());
391 OutStreamer.SwitchSection(TLOFMacho.getTextCoalSection());
392 OutStreamer.SwitchSection(TLOFMacho.getConstTextCoalSection());
393 if (RelocM == Reloc::DynamicNoPIC) {
394 const MCSection *sect =
395 OutContext.getMachOSection("__TEXT", "__symbol_stub4",
396 MCSectionMachO::S_SYMBOL_STUBS,
397 12, SectionKind::getText());
398 OutStreamer.SwitchSection(sect);
400 const MCSection *sect =
401 OutContext.getMachOSection("__TEXT", "__picsymbolstub4",
402 MCSectionMachO::S_SYMBOL_STUBS,
403 16, SectionKind::getText());
404 OutStreamer.SwitchSection(sect);
406 const MCSection *StaticInitSect =
407 OutContext.getMachOSection("__TEXT", "__StaticInit",
408 MCSectionMachO::S_REGULAR |
409 MCSectionMachO::S_ATTR_PURE_INSTRUCTIONS,
410 SectionKind::getText());
411 OutStreamer.SwitchSection(StaticInitSect);
415 // Use unified assembler syntax.
416 OutStreamer.EmitAssemblerFlag(MCAF_SyntaxUnified);
418 // Emit ARM Build Attributes
419 if (Subtarget->isTargetELF()) {
426 void ARMAsmPrinter::EmitEndOfAsmFile(Module &M) {
427 if (Subtarget->isTargetDarwin()) {
428 // All darwin targets use mach-o.
429 const TargetLoweringObjectFileMachO &TLOFMacho =
430 static_cast<const TargetLoweringObjectFileMachO &>(getObjFileLowering());
431 MachineModuleInfoMachO &MMIMacho =
432 MMI->getObjFileInfo<MachineModuleInfoMachO>();
434 // Output non-lazy-pointers for external and common global variables.
435 MachineModuleInfoMachO::SymbolListTy Stubs = MMIMacho.GetGVStubList();
437 if (!Stubs.empty()) {
438 // Switch with ".non_lazy_symbol_pointer" directive.
439 OutStreamer.SwitchSection(TLOFMacho.getNonLazySymbolPointerSection());
441 for (unsigned i = 0, e = Stubs.size(); i != e; ++i) {
443 OutStreamer.EmitLabel(Stubs[i].first);
444 // .indirect_symbol _foo
445 MachineModuleInfoImpl::StubValueTy &MCSym = Stubs[i].second;
446 OutStreamer.EmitSymbolAttribute(MCSym.getPointer(),MCSA_IndirectSymbol);
449 // External to current translation unit.
450 OutStreamer.EmitIntValue(0, 4/*size*/, 0/*addrspace*/);
452 // Internal to current translation unit.
454 // When we place the LSDA into the TEXT section, the type info
455 // pointers need to be indirect and pc-rel. We accomplish this by
456 // using NLPs; however, sometimes the types are local to the file.
457 // We need to fill in the value for the NLP in those cases.
458 OutStreamer.EmitValue(MCSymbolRefExpr::Create(MCSym.getPointer(),
460 4/*size*/, 0/*addrspace*/);
464 OutStreamer.AddBlankLine();
467 Stubs = MMIMacho.GetHiddenGVStubList();
468 if (!Stubs.empty()) {
469 OutStreamer.SwitchSection(getObjFileLowering().getDataSection());
471 for (unsigned i = 0, e = Stubs.size(); i != e; ++i) {
473 OutStreamer.EmitLabel(Stubs[i].first);
475 OutStreamer.EmitValue(MCSymbolRefExpr::
476 Create(Stubs[i].second.getPointer(),
478 4/*size*/, 0/*addrspace*/);
482 OutStreamer.AddBlankLine();
485 // Funny Darwin hack: This flag tells the linker that no global symbols
486 // contain code that falls through to other global symbols (e.g. the obvious
487 // implementation of multiple entry points). If this doesn't occur, the
488 // linker can safely perform dead code stripping. Since LLVM never
489 // generates code that does this, it is always safe to set.
490 OutStreamer.EmitAssemblerFlag(MCAF_SubsectionsViaSymbols);
494 //===----------------------------------------------------------------------===//
495 // Helper routines for EmitStartOfAsmFile() and EmitEndOfAsmFile()
497 // The following seem like one-off assembler flags, but they actually need
498 // to appear in the .ARM.attributes section in ELF.
499 // Instead of subclassing the MCELFStreamer, we do the work here.
501 void ARMAsmPrinter::emitAttributes() {
503 emitARMAttributeSection();
505 std::string CPUString = Subtarget->getCPUString();
506 emitTextAttribute(ARMBuildAttrs::SEL_CPU, CPUString);
508 // FIXME: Emit FPU type
509 if (Subtarget->hasVFP2())
510 emitAttribute(ARMBuildAttrs::VFP_arch, 2);
512 // Signal various FP modes.
514 emitAttribute(ARMBuildAttrs::ABI_FP_denormal, 1);
515 emitAttribute(ARMBuildAttrs::ABI_FP_exceptions, 1);
518 if (NoInfsFPMath && NoNaNsFPMath)
519 emitAttribute(ARMBuildAttrs::ABI_FP_number_model, 1);
521 emitAttribute(ARMBuildAttrs::ABI_FP_number_model, 3);
523 // 8-bytes alignment stuff.
524 emitAttribute(ARMBuildAttrs::ABI_align8_needed, 1);
525 emitAttribute(ARMBuildAttrs::ABI_align8_preserved, 1);
527 // Hard float. Use both S and D registers and conform to AAPCS-VFP.
528 if (Subtarget->isAAPCS_ABI() && FloatABIType == FloatABI::Hard) {
529 emitAttribute(ARMBuildAttrs::ABI_HardFP_use, 3);
530 emitAttribute(ARMBuildAttrs::ABI_VFP_args, 1);
532 // FIXME: Should we signal R9 usage?
535 void ARMAsmPrinter::emitARMAttributeSection() {
537 // [ <section-length> "vendor-name"
538 // [ <file-tag> <size> <attribute>*
539 // | <section-tag> <size> <section-number>* 0 <attribute>*
540 // | <symbol-tag> <size> <symbol-number>* 0 <attribute>*
544 if (OutStreamer.hasRawTextSupport())
547 const ARMElfTargetObjectFile &TLOFELF =
548 static_cast<const ARMElfTargetObjectFile &>
549 (getObjFileLowering());
551 OutStreamer.SwitchSection(TLOFELF.getAttributesSection());
552 // Fixme: Still more to do here.
555 void ARMAsmPrinter::emitAttribute(ARMBuildAttrs::AttrType attr, int v) {
556 if (OutStreamer.hasRawTextSupport()) {
557 OutStreamer.EmitRawText("\t.eabi_attribute " +
558 Twine(attr) + ", " + Twine(v));
561 assert(0 && "ELF .ARM.attributes unimplemented");
565 void ARMAsmPrinter::emitTextAttribute(ARMBuildAttrs::SpecialAttr attr,
568 default: assert(0 && "Unimplemented ARMBuildAttrs::SpecialAttr"); break;
569 case ARMBuildAttrs::SEL_CPU:
570 if (OutStreamer.hasRawTextSupport()) {
571 if (val != "generic") {
572 OutStreamer.EmitRawText("\t.cpu " + val);
580 //===----------------------------------------------------------------------===//
582 static MCSymbol *getPICLabel(const char *Prefix, unsigned FunctionNumber,
583 unsigned LabelId, MCContext &Ctx) {
585 MCSymbol *Label = Ctx.GetOrCreateSymbol(Twine(Prefix)
586 + "PC" + Twine(FunctionNumber) + "_" + Twine(LabelId));
590 void ARMAsmPrinter::EmitJumpTable(const MachineInstr *MI) {
591 unsigned Opcode = MI->getOpcode();
593 if (Opcode == ARM::BR_JTadd)
595 else if (Opcode == ARM::BR_JTm)
598 const MachineOperand &MO1 = MI->getOperand(OpNum);
599 const MachineOperand &MO2 = MI->getOperand(OpNum+1); // Unique Id
600 unsigned JTI = MO1.getIndex();
602 // Emit a label for the jump table.
603 MCSymbol *JTISymbol = GetARMJTIPICJumpTableLabel2(JTI, MO2.getImm());
604 OutStreamer.EmitLabel(JTISymbol);
606 // Emit each entry of the table.
607 const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
608 const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
609 const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
611 for (unsigned i = 0, e = JTBBs.size(); i != e; ++i) {
612 MachineBasicBlock *MBB = JTBBs[i];
613 // Construct an MCExpr for the entry. We want a value of the form:
614 // (BasicBlockAddr - TableBeginAddr)
616 // For example, a table with entries jumping to basic blocks BB0 and BB1
619 // .word (LBB0 - LJTI_0_0)
620 // .word (LBB1 - LJTI_0_0)
621 const MCExpr *Expr = MCSymbolRefExpr::Create(MBB->getSymbol(), OutContext);
623 if (TM.getRelocationModel() == Reloc::PIC_)
624 Expr = MCBinaryExpr::CreateSub(Expr, MCSymbolRefExpr::Create(JTISymbol,
627 OutStreamer.EmitValue(Expr, 4);
631 void ARMAsmPrinter::EmitJump2Table(const MachineInstr *MI) {
632 unsigned Opcode = MI->getOpcode();
633 int OpNum = (Opcode == ARM::t2BR_JT) ? 2 : 1;
634 const MachineOperand &MO1 = MI->getOperand(OpNum);
635 const MachineOperand &MO2 = MI->getOperand(OpNum+1); // Unique Id
636 unsigned JTI = MO1.getIndex();
638 // Emit a label for the jump table.
639 MCSymbol *JTISymbol = GetARMJTIPICJumpTableLabel2(JTI, MO2.getImm());
640 OutStreamer.EmitLabel(JTISymbol);
642 // Emit each entry of the table.
643 const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
644 const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
645 const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
646 unsigned OffsetWidth = 4;
647 if (MI->getOpcode() == ARM::t2TBB)
649 else if (MI->getOpcode() == ARM::t2TBH)
652 for (unsigned i = 0, e = JTBBs.size(); i != e; ++i) {
653 MachineBasicBlock *MBB = JTBBs[i];
654 const MCExpr *MBBSymbolExpr = MCSymbolRefExpr::Create(MBB->getSymbol(),
656 // If this isn't a TBB or TBH, the entries are direct branch instructions.
657 if (OffsetWidth == 4) {
659 BrInst.setOpcode(ARM::t2B);
660 BrInst.addOperand(MCOperand::CreateExpr(MBBSymbolExpr));
661 OutStreamer.EmitInstruction(BrInst);
664 // Otherwise it's an offset from the dispatch instruction. Construct an
665 // MCExpr for the entry. We want a value of the form:
666 // (BasicBlockAddr - TableBeginAddr) / 2
668 // For example, a TBB table with entries jumping to basic blocks BB0 and BB1
671 // .byte (LBB0 - LJTI_0_0) / 2
672 // .byte (LBB1 - LJTI_0_0) / 2
674 MCBinaryExpr::CreateSub(MBBSymbolExpr,
675 MCSymbolRefExpr::Create(JTISymbol, OutContext),
677 Expr = MCBinaryExpr::CreateDiv(Expr, MCConstantExpr::Create(2, OutContext),
679 OutStreamer.EmitValue(Expr, OffsetWidth);
682 // Make sure the instruction that follows TBB is 2-byte aligned.
683 // FIXME: Constant island pass should insert an "ALIGN" instruction instead.
684 if (MI->getOpcode() == ARM::t2TBB)
688 void ARMAsmPrinter::PrintDebugValueComment(const MachineInstr *MI,
690 unsigned NOps = MI->getNumOperands();
692 OS << '\t' << MAI->getCommentString() << "DEBUG_VALUE: ";
693 // cast away const; DIetc do not take const operands for some reason.
694 DIVariable V(const_cast<MDNode *>(MI->getOperand(NOps-1).getMetadata()));
697 // Frame address. Currently handles register +- offset only.
698 assert(MI->getOperand(0).isReg() && MI->getOperand(1).isImm());
699 OS << '['; printOperand(MI, 0, OS); OS << '+'; printOperand(MI, 1, OS);
702 printOperand(MI, NOps-2, OS);
705 void ARMAsmPrinter::EmitInstruction(const MachineInstr *MI) {
706 ARMMCInstLower MCInstLowering(OutContext, *Mang, *this);
707 switch (MI->getOpcode()) {
708 case ARM::t2MOVi32imm:
709 assert(0 && "Should be lowered by thumb2it pass");
711 case ARM::DBG_VALUE: {
712 if (isVerbose() && OutStreamer.hasRawTextSupport()) {
713 SmallString<128> TmpStr;
714 raw_svector_ostream OS(TmpStr);
715 PrintDebugValueComment(MI, OS);
716 OutStreamer.EmitRawText(StringRef(OS.str()));
721 // This is a pseudo op for a label + instruction sequence, which looks like:
724 // This adds the address of LPC0 to r0.
727 OutStreamer.EmitLabel(getPICLabel(MAI->getPrivateGlobalPrefix(),
728 getFunctionNumber(), MI->getOperand(2).getImm(),
731 // Form and emit the add.
733 AddInst.setOpcode(ARM::tADDhirr);
734 AddInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
735 AddInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
736 AddInst.addOperand(MCOperand::CreateReg(ARM::PC));
737 // Add predicate operands.
738 AddInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
739 AddInst.addOperand(MCOperand::CreateReg(0));
740 OutStreamer.EmitInstruction(AddInst);
744 // This is a pseudo op for a label + instruction sequence, which looks like:
747 // This adds the address of LPC0 to r0.
750 OutStreamer.EmitLabel(getPICLabel(MAI->getPrivateGlobalPrefix(),
751 getFunctionNumber(), MI->getOperand(2).getImm(),
754 // Form and emit the add.
756 AddInst.setOpcode(ARM::ADDrr);
757 AddInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
758 AddInst.addOperand(MCOperand::CreateReg(ARM::PC));
759 AddInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg()));
760 // Add predicate operands.
761 AddInst.addOperand(MCOperand::CreateImm(MI->getOperand(3).getImm()));
762 AddInst.addOperand(MCOperand::CreateReg(MI->getOperand(4).getReg()));
763 // Add 's' bit operand (always reg0 for this)
764 AddInst.addOperand(MCOperand::CreateReg(0));
765 OutStreamer.EmitInstruction(AddInst);
775 case ARM::PICLDRSH: {
776 // This is a pseudo op for a label + instruction sequence, which looks like:
779 // The LCP0 label is referenced by a constant pool entry in order to get
780 // a PC-relative address at the ldr instruction.
783 OutStreamer.EmitLabel(getPICLabel(MAI->getPrivateGlobalPrefix(),
784 getFunctionNumber(), MI->getOperand(2).getImm(),
787 // Form and emit the load
789 switch (MI->getOpcode()) {
791 llvm_unreachable("Unexpected opcode!");
792 case ARM::PICSTR: Opcode = ARM::STR; break;
793 case ARM::PICSTRB: Opcode = ARM::STRB; break;
794 case ARM::PICSTRH: Opcode = ARM::STRH; break;
795 case ARM::PICLDR: Opcode = ARM::LDR; break;
796 case ARM::PICLDRB: Opcode = ARM::LDRB; break;
797 case ARM::PICLDRH: Opcode = ARM::LDRH; break;
798 case ARM::PICLDRSB: Opcode = ARM::LDRSB; break;
799 case ARM::PICLDRSH: Opcode = ARM::LDRSH; break;
802 LdStInst.setOpcode(Opcode);
803 LdStInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
804 LdStInst.addOperand(MCOperand::CreateReg(ARM::PC));
805 LdStInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg()));
806 LdStInst.addOperand(MCOperand::CreateImm(0));
807 // Add predicate operands.
808 LdStInst.addOperand(MCOperand::CreateImm(MI->getOperand(3).getImm()));
809 LdStInst.addOperand(MCOperand::CreateReg(MI->getOperand(4).getReg()));
810 OutStreamer.EmitInstruction(LdStInst);
814 case ARM::CONSTPOOL_ENTRY: {
815 /// CONSTPOOL_ENTRY - This instruction represents a floating constant pool
816 /// in the function. The first operand is the ID# for this instruction, the
817 /// second is the index into the MachineConstantPool that this is, the third
818 /// is the size in bytes of this constant pool entry.
819 unsigned LabelId = (unsigned)MI->getOperand(0).getImm();
820 unsigned CPIdx = (unsigned)MI->getOperand(1).getIndex();
823 OutStreamer.EmitLabel(GetCPISymbol(LabelId));
825 const MachineConstantPoolEntry &MCPE = MCP->getConstants()[CPIdx];
826 if (MCPE.isMachineConstantPoolEntry())
827 EmitMachineConstantPoolValue(MCPE.Val.MachineCPVal);
829 EmitGlobalConstant(MCPE.Val.ConstVal);
833 case ARM::MOVi2pieces: {
834 // FIXME: We'd like to remove the asm string in the .td file, but the
835 // This is a hack that lowers as a two instruction sequence.
836 unsigned DstReg = MI->getOperand(0).getReg();
837 unsigned ImmVal = (unsigned)MI->getOperand(1).getImm();
839 unsigned SOImmValV1 = ARM_AM::getSOImmTwoPartFirst(ImmVal);
840 unsigned SOImmValV2 = ARM_AM::getSOImmTwoPartSecond(ImmVal);
844 TmpInst.setOpcode(ARM::MOVi);
845 TmpInst.addOperand(MCOperand::CreateReg(DstReg));
846 TmpInst.addOperand(MCOperand::CreateImm(SOImmValV1));
849 TmpInst.addOperand(MCOperand::CreateImm(MI->getOperand(2).getImm()));
850 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(3).getReg()));
852 TmpInst.addOperand(MCOperand::CreateReg(0)); // cc_out
853 OutStreamer.EmitInstruction(TmpInst);
858 TmpInst.setOpcode(ARM::ORRri);
859 TmpInst.addOperand(MCOperand::CreateReg(DstReg)); // dstreg
860 TmpInst.addOperand(MCOperand::CreateReg(DstReg)); // inreg
861 TmpInst.addOperand(MCOperand::CreateImm(SOImmValV2)); // so_imm
863 TmpInst.addOperand(MCOperand::CreateImm(MI->getOperand(2).getImm()));
864 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(3).getReg()));
866 TmpInst.addOperand(MCOperand::CreateReg(0)); // cc_out
867 OutStreamer.EmitInstruction(TmpInst);
871 case ARM::MOVi32imm: {
872 // FIXME: We'd like to remove the asm string in the .td file, but the
873 // This is a hack that lowers as a two instruction sequence.
874 unsigned DstReg = MI->getOperand(0).getReg();
875 const MachineOperand &MO = MI->getOperand(1);
878 unsigned ImmVal = (unsigned)MI->getOperand(1).getImm();
879 V1 = MCOperand::CreateImm(ImmVal & 65535);
880 V2 = MCOperand::CreateImm(ImmVal >> 16);
881 } else if (MO.isGlobal()) {
882 MCSymbol *Symbol = MCInstLowering.GetGlobalAddressSymbol(MO.getGlobal());
883 const MCSymbolRefExpr *SymRef1 =
884 MCSymbolRefExpr::Create(Symbol,
885 MCSymbolRefExpr::VK_ARM_LO16, OutContext);
886 const MCSymbolRefExpr *SymRef2 =
887 MCSymbolRefExpr::Create(Symbol,
888 MCSymbolRefExpr::VK_ARM_HI16, OutContext);
889 V1 = MCOperand::CreateExpr(SymRef1);
890 V2 = MCOperand::CreateExpr(SymRef2);
892 // FIXME: External symbol?
894 llvm_unreachable("cannot handle this operand");
899 TmpInst.setOpcode(ARM::MOVi16);
900 TmpInst.addOperand(MCOperand::CreateReg(DstReg)); // dstreg
901 TmpInst.addOperand(V1); // lower16(imm)
904 TmpInst.addOperand(MCOperand::CreateImm(MI->getOperand(2).getImm()));
905 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(3).getReg()));
907 OutStreamer.EmitInstruction(TmpInst);
912 TmpInst.setOpcode(ARM::MOVTi16);
913 TmpInst.addOperand(MCOperand::CreateReg(DstReg)); // dstreg
914 TmpInst.addOperand(MCOperand::CreateReg(DstReg)); // srcreg
915 TmpInst.addOperand(V2); // upper16(imm)
918 TmpInst.addOperand(MCOperand::CreateImm(MI->getOperand(2).getImm()));
919 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(3).getReg()));
921 OutStreamer.EmitInstruction(TmpInst);
929 // Lower and emit the instruction itself, then the jump table following it.
931 MCInstLowering.Lower(MI, TmpInst);
932 OutStreamer.EmitInstruction(TmpInst);
939 case ARM::BR_JTadd: {
940 // Lower and emit the instruction itself, then the jump table following it.
942 MCInstLowering.Lower(MI, TmpInst);
943 OutStreamer.EmitInstruction(TmpInst);
948 // Non-Darwin binutils don't yet support the "trap" mnemonic.
949 // FIXME: Remove this special case when they do.
950 if (!Subtarget->isTargetDarwin()) {
951 //.long 0xe7ffdefe @ trap
952 uint32_t Val = 0xe7ffdefeUL;
953 OutStreamer.AddComment("trap");
954 OutStreamer.EmitIntValue(Val, 4);
960 // Non-Darwin binutils don't yet support the "trap" mnemonic.
961 // FIXME: Remove this special case when they do.
962 if (!Subtarget->isTargetDarwin()) {
963 //.short 57086 @ trap
964 uint16_t Val = 0xdefe;
965 OutStreamer.AddComment("trap");
966 OutStreamer.EmitIntValue(Val, 2);
971 case ARM::t2Int_eh_sjlj_setjmp:
972 case ARM::t2Int_eh_sjlj_setjmp_nofp:
973 case ARM::tInt_eh_sjlj_setjmp: {
974 // Two incoming args: GPR:$src, GPR:$val
977 // str $val, [$src, #4]
982 unsigned SrcReg = MI->getOperand(0).getReg();
983 unsigned ValReg = MI->getOperand(1).getReg();
984 MCSymbol *Label = GetARMSJLJEHLabel();
987 TmpInst.setOpcode(ARM::tMOVgpr2tgpr);
988 TmpInst.addOperand(MCOperand::CreateReg(ValReg));
989 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
991 TmpInst.addOperand(MCOperand::CreateReg(ARM::CPSR));
992 OutStreamer.AddComment("eh_setjmp begin");
993 OutStreamer.EmitInstruction(TmpInst);
997 TmpInst.setOpcode(ARM::tADDi3);
998 TmpInst.addOperand(MCOperand::CreateReg(ValReg));
1000 TmpInst.addOperand(MCOperand::CreateReg(ARM::CPSR));
1001 TmpInst.addOperand(MCOperand::CreateReg(ValReg));
1002 TmpInst.addOperand(MCOperand::CreateImm(7));
1004 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1005 TmpInst.addOperand(MCOperand::CreateReg(0));
1006 OutStreamer.EmitInstruction(TmpInst);
1010 TmpInst.setOpcode(ARM::tSTR);
1011 TmpInst.addOperand(MCOperand::CreateReg(ValReg));
1012 TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
1013 // The offset immediate is #4. The operand value is scaled by 4 for the
1014 // tSTR instruction.
1015 TmpInst.addOperand(MCOperand::CreateImm(1));
1016 TmpInst.addOperand(MCOperand::CreateReg(0));
1018 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1019 TmpInst.addOperand(MCOperand::CreateReg(0));
1020 OutStreamer.EmitInstruction(TmpInst);
1024 TmpInst.setOpcode(ARM::tMOVi8);
1025 TmpInst.addOperand(MCOperand::CreateReg(ARM::R0));
1026 TmpInst.addOperand(MCOperand::CreateReg(ARM::CPSR));
1027 TmpInst.addOperand(MCOperand::CreateImm(0));
1029 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1030 TmpInst.addOperand(MCOperand::CreateReg(0));
1031 OutStreamer.EmitInstruction(TmpInst);
1034 const MCExpr *SymbolExpr = MCSymbolRefExpr::Create(Label, OutContext);
1036 TmpInst.setOpcode(ARM::tB);
1037 TmpInst.addOperand(MCOperand::CreateExpr(SymbolExpr));
1038 OutStreamer.EmitInstruction(TmpInst);
1042 TmpInst.setOpcode(ARM::tMOVi8);
1043 TmpInst.addOperand(MCOperand::CreateReg(ARM::R0));
1044 TmpInst.addOperand(MCOperand::CreateReg(ARM::CPSR));
1045 TmpInst.addOperand(MCOperand::CreateImm(1));
1047 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1048 TmpInst.addOperand(MCOperand::CreateReg(0));
1049 OutStreamer.AddComment("eh_setjmp end");
1050 OutStreamer.EmitInstruction(TmpInst);
1052 OutStreamer.EmitLabel(Label);
1056 case ARM::Int_eh_sjlj_setjmp_nofp:
1057 case ARM::Int_eh_sjlj_setjmp: {
1058 // Two incoming args: GPR:$src, GPR:$val
1060 // str $val, [$src, #+4]
1064 unsigned SrcReg = MI->getOperand(0).getReg();
1065 unsigned ValReg = MI->getOperand(1).getReg();
1069 TmpInst.setOpcode(ARM::ADDri);
1070 TmpInst.addOperand(MCOperand::CreateReg(ValReg));
1071 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1072 TmpInst.addOperand(MCOperand::CreateImm(8));
1074 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1075 TmpInst.addOperand(MCOperand::CreateReg(0));
1076 // 's' bit operand (always reg0 for this).
1077 TmpInst.addOperand(MCOperand::CreateReg(0));
1078 OutStreamer.AddComment("eh_setjmp begin");
1079 OutStreamer.EmitInstruction(TmpInst);
1083 TmpInst.setOpcode(ARM::STR);
1084 TmpInst.addOperand(MCOperand::CreateReg(ValReg));
1085 TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
1086 TmpInst.addOperand(MCOperand::CreateReg(0));
1087 TmpInst.addOperand(MCOperand::CreateImm(4));
1089 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1090 TmpInst.addOperand(MCOperand::CreateReg(0));
1091 OutStreamer.EmitInstruction(TmpInst);
1095 TmpInst.setOpcode(ARM::MOVi);
1096 TmpInst.addOperand(MCOperand::CreateReg(ARM::R0));
1097 TmpInst.addOperand(MCOperand::CreateImm(0));
1099 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1100 TmpInst.addOperand(MCOperand::CreateReg(0));
1101 // 's' bit operand (always reg0 for this).
1102 TmpInst.addOperand(MCOperand::CreateReg(0));
1103 OutStreamer.EmitInstruction(TmpInst);
1107 TmpInst.setOpcode(ARM::ADDri);
1108 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1109 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1110 TmpInst.addOperand(MCOperand::CreateImm(0));
1112 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1113 TmpInst.addOperand(MCOperand::CreateReg(0));
1114 // 's' bit operand (always reg0 for this).
1115 TmpInst.addOperand(MCOperand::CreateReg(0));
1116 OutStreamer.EmitInstruction(TmpInst);
1120 TmpInst.setOpcode(ARM::MOVi);
1121 TmpInst.addOperand(MCOperand::CreateReg(ARM::R0));
1122 TmpInst.addOperand(MCOperand::CreateImm(1));
1124 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1125 TmpInst.addOperand(MCOperand::CreateReg(0));
1126 // 's' bit operand (always reg0 for this).
1127 TmpInst.addOperand(MCOperand::CreateReg(0));
1128 OutStreamer.AddComment("eh_setjmp end");
1129 OutStreamer.EmitInstruction(TmpInst);
1133 case ARM::Int_eh_sjlj_longjmp: {
1134 // ldr sp, [$src, #8]
1135 // ldr $scratch, [$src, #4]
1138 unsigned SrcReg = MI->getOperand(0).getReg();
1139 unsigned ScratchReg = MI->getOperand(1).getReg();
1142 TmpInst.setOpcode(ARM::LDR);
1143 TmpInst.addOperand(MCOperand::CreateReg(ARM::SP));
1144 TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
1145 TmpInst.addOperand(MCOperand::CreateReg(0));
1146 TmpInst.addOperand(MCOperand::CreateImm(8));
1148 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1149 TmpInst.addOperand(MCOperand::CreateReg(0));
1150 OutStreamer.EmitInstruction(TmpInst);
1154 TmpInst.setOpcode(ARM::LDR);
1155 TmpInst.addOperand(MCOperand::CreateReg(ScratchReg));
1156 TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
1157 TmpInst.addOperand(MCOperand::CreateReg(0));
1158 TmpInst.addOperand(MCOperand::CreateImm(4));
1160 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1161 TmpInst.addOperand(MCOperand::CreateReg(0));
1162 OutStreamer.EmitInstruction(TmpInst);
1166 TmpInst.setOpcode(ARM::LDR);
1167 TmpInst.addOperand(MCOperand::CreateReg(ARM::R7));
1168 TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
1169 TmpInst.addOperand(MCOperand::CreateReg(0));
1170 TmpInst.addOperand(MCOperand::CreateImm(0));
1172 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1173 TmpInst.addOperand(MCOperand::CreateReg(0));
1174 OutStreamer.EmitInstruction(TmpInst);
1178 TmpInst.setOpcode(ARM::BRIND);
1179 TmpInst.addOperand(MCOperand::CreateReg(ScratchReg));
1181 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1182 TmpInst.addOperand(MCOperand::CreateReg(0));
1183 OutStreamer.EmitInstruction(TmpInst);
1187 case ARM::tInt_eh_sjlj_longjmp: {
1188 // ldr $scratch, [$src, #8]
1190 // ldr $scratch, [$src, #4]
1193 unsigned SrcReg = MI->getOperand(0).getReg();
1194 unsigned ScratchReg = MI->getOperand(1).getReg();
1197 TmpInst.setOpcode(ARM::tLDR);
1198 TmpInst.addOperand(MCOperand::CreateReg(ScratchReg));
1199 TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
1200 // The offset immediate is #8. The operand value is scaled by 4 for the
1201 // tSTR instruction.
1202 TmpInst.addOperand(MCOperand::CreateImm(2));
1203 TmpInst.addOperand(MCOperand::CreateReg(0));
1205 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1206 TmpInst.addOperand(MCOperand::CreateReg(0));
1207 OutStreamer.EmitInstruction(TmpInst);
1211 TmpInst.setOpcode(ARM::tMOVtgpr2gpr);
1212 TmpInst.addOperand(MCOperand::CreateReg(ARM::SP));
1213 TmpInst.addOperand(MCOperand::CreateReg(ScratchReg));
1215 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1216 TmpInst.addOperand(MCOperand::CreateReg(0));
1217 OutStreamer.EmitInstruction(TmpInst);
1221 TmpInst.setOpcode(ARM::tLDR);
1222 TmpInst.addOperand(MCOperand::CreateReg(ScratchReg));
1223 TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
1224 TmpInst.addOperand(MCOperand::CreateImm(1));
1225 TmpInst.addOperand(MCOperand::CreateReg(0));
1227 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1228 TmpInst.addOperand(MCOperand::CreateReg(0));
1229 OutStreamer.EmitInstruction(TmpInst);
1233 TmpInst.setOpcode(ARM::tLDR);
1234 TmpInst.addOperand(MCOperand::CreateReg(ARM::R7));
1235 TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
1236 TmpInst.addOperand(MCOperand::CreateImm(0));
1237 TmpInst.addOperand(MCOperand::CreateReg(0));
1239 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1240 TmpInst.addOperand(MCOperand::CreateReg(0));
1241 OutStreamer.EmitInstruction(TmpInst);
1245 TmpInst.setOpcode(ARM::tBX_RET_vararg);
1246 TmpInst.addOperand(MCOperand::CreateReg(ScratchReg));
1248 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1249 TmpInst.addOperand(MCOperand::CreateReg(0));
1250 OutStreamer.EmitInstruction(TmpInst);
1257 MCInstLowering.Lower(MI, TmpInst);
1258 OutStreamer.EmitInstruction(TmpInst);
1261 //===----------------------------------------------------------------------===//
1262 // Target Registry Stuff
1263 //===----------------------------------------------------------------------===//
1265 static MCInstPrinter *createARMMCInstPrinter(const Target &T,
1266 unsigned SyntaxVariant,
1267 const MCAsmInfo &MAI) {
1268 if (SyntaxVariant == 0)
1269 return new ARMInstPrinter(MAI);
1273 // Force static initialization.
1274 extern "C" void LLVMInitializeARMAsmPrinter() {
1275 RegisterAsmPrinter<ARMAsmPrinter> X(TheARMTarget);
1276 RegisterAsmPrinter<ARMAsmPrinter> Y(TheThumbTarget);
1278 TargetRegistry::RegisterMCInstPrinter(TheARMTarget, createARMMCInstPrinter);
1279 TargetRegistry::RegisterMCInstPrinter(TheThumbTarget, createARMMCInstPrinter);